1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
30 */
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/rman.h>
39 #include <sys/socket.h>
40 #include <sys/sysctl.h>
41 #include <sys/systm.h>
42
43 #include <net/if.h>
44 #include <net/if_media.h>
45
46 #include <dev/mii/mii.h>
47 #include <dev/mii/miivar.h>
48
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51
52 #include "xgbe.h"
53 #include "xgbe-common.h"
54
55 #include "miibus_if.h"
56 #include "ifdi_if.h"
57 #include "opt_inet.h"
58 #include "opt_inet6.h"
59 #include "opt_rss.h"
60
61 #ifdef RSS
62 #include <net/rss_config.h>
63 #include <netinet/in_rss.h>
64 #endif
65
66 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
67
68 extern struct if_txrx axgbe_txrx;
69 static int axgbe_sph_enable;
70
71 /* Function prototypes */
72 static void *axgbe_register(device_t);
73 static int axgbe_if_attach_pre(if_ctx_t);
74 static int axgbe_if_attach_post(if_ctx_t);
75 static int axgbe_if_detach(if_ctx_t);
76 static void axgbe_if_stop(if_ctx_t);
77 static void axgbe_if_init(if_ctx_t);
78
79 /* Queue related routines */
80 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
81 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
82 static int axgbe_alloc_channels(if_ctx_t);
83 static void axgbe_free_channels(struct axgbe_if_softc *);
84 static void axgbe_if_queues_free(if_ctx_t);
85 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
86 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
87
88 /* Interrupt related routines */
89 static void axgbe_if_disable_intr(if_ctx_t);
90 static void axgbe_if_enable_intr(if_ctx_t);
91 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
92 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
93
94 /* Init and Iflib routines */
95 static void axgbe_pci_init(struct xgbe_prv_data *);
96 static void axgbe_pci_stop(if_ctx_t);
97 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
98 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
99 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
100 static void axgbe_if_update_admin_status(if_ctx_t);
101 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
102 static int axgbe_if_media_change(if_ctx_t);
103 static int axgbe_if_promisc_set(if_ctx_t, int);
104 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
105 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
106 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
107 #if __FreeBSD_version >= 1300000
108 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
109 #endif
110 static void axgbe_set_counts(if_ctx_t);
111 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
112 static void axgbe_initialize_rss_mapping(struct xgbe_prv_data *);
113
114 /* MII interface registered functions */
115 static int axgbe_miibus_readreg(device_t, int, int);
116 static int axgbe_miibus_writereg(device_t, int, int, int);
117 static void axgbe_miibus_statchg(device_t);
118
119 /* ISR routines */
120 static int axgbe_dev_isr(void *);
121 static void axgbe_ecc_isr(void *);
122 static void axgbe_i2c_isr(void *);
123 static void axgbe_an_isr(void *);
124 static int axgbe_msix_que(void *);
125
126 /* Timer routines */
127 static void xgbe_service(void *, int);
128 static void xgbe_service_timer(void *);
129 static void xgbe_init_timers(struct xgbe_prv_data *);
130 static void xgbe_stop_timers(struct xgbe_prv_data *);
131
132 /* Dump routines */
133 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
134
135 /*
136 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
137 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
138 * table.
139 */
140 static struct resource_spec axgbe_pci_mac_spec[] = {
141 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
142 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
143 { -1, 0 }
144 };
145
146 static const pci_vendor_info_t axgbe_vendor_info_array[] =
147 {
148 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
149 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
150 PVID_END
151 };
152
153 static struct xgbe_version_data xgbe_v2a = {
154 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
155 .xpcs_access = XGBE_XPCS_ACCESS_V2,
156 .mmc_64bit = 1,
157 .tx_max_fifo_size = 229376,
158 .rx_max_fifo_size = 229376,
159 .tx_tstamp_workaround = 1,
160 .ecc_support = 1,
161 .i2c_support = 1,
162 .irq_reissue_support = 1,
163 .tx_desc_prefetch = 5,
164 .rx_desc_prefetch = 5,
165 .an_cdr_workaround = 1,
166 };
167
168 static struct xgbe_version_data xgbe_v2b = {
169 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
170 .xpcs_access = XGBE_XPCS_ACCESS_V2,
171 .mmc_64bit = 1,
172 .tx_max_fifo_size = 65536,
173 .rx_max_fifo_size = 65536,
174 .tx_tstamp_workaround = 1,
175 .ecc_support = 1,
176 .i2c_support = 1,
177 .irq_reissue_support = 1,
178 .tx_desc_prefetch = 5,
179 .rx_desc_prefetch = 5,
180 .an_cdr_workaround = 1,
181 };
182
183 /* Device Interface */
184 static device_method_t ax_methods[] = {
185 DEVMETHOD(device_register, axgbe_register),
186 DEVMETHOD(device_probe, iflib_device_probe),
187 DEVMETHOD(device_attach, iflib_device_attach),
188 DEVMETHOD(device_detach, iflib_device_detach),
189
190 /* MII interface */
191 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
192 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
193 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
194
195 DEVMETHOD_END
196 };
197
198 static driver_t ax_driver = {
199 "ax", ax_methods, sizeof(struct axgbe_if_softc),
200 };
201
202 DRIVER_MODULE(axp, pci, ax_driver, 0, 0);
203 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0);
204 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
205
206 MODULE_DEPEND(ax, pci, 1, 1, 1);
207 MODULE_DEPEND(ax, ether, 1, 1, 1);
208 MODULE_DEPEND(ax, iflib, 1, 1, 1);
209 MODULE_DEPEND(ax, miibus, 1, 1, 1);
210
211 /* Iflib Interface */
212 static device_method_t axgbe_if_methods[] = {
213 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
214 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
215 DEVMETHOD(ifdi_detach, axgbe_if_detach),
216 DEVMETHOD(ifdi_init, axgbe_if_init),
217 DEVMETHOD(ifdi_stop, axgbe_if_stop),
218 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
219 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
220 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
221 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
222 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
223 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
224 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
225 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
226 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
227 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
228 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
229 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
230 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
231 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
232 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
233 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
234 #if __FreeBSD_version >= 1300000
235 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
236 #endif
237 DEVMETHOD_END
238 };
239
240 static driver_t axgbe_if_driver = {
241 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
242 };
243
244 /* Iflib Shared Context */
245 static struct if_shared_ctx axgbe_sctx_init = {
246 .isc_magic = IFLIB_MAGIC,
247 .isc_driver = &axgbe_if_driver,
248 .isc_q_align = PAGE_SIZE,
249 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
250 .isc_tx_maxsegsize = PAGE_SIZE,
251 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
252 .isc_tso_maxsegsize = PAGE_SIZE,
253 .isc_rx_maxsize = MJUM9BYTES,
254 .isc_rx_maxsegsize = MJUM9BYTES,
255 .isc_rx_nsegments = 1,
256 .isc_admin_intrcnt = 4,
257
258 .isc_vendor_info = axgbe_vendor_info_array,
259 .isc_driver_version = XGBE_DRV_VERSION,
260
261 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
262 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
263 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
264
265 .isc_ntxqs = 1,
266 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
267 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
268 };
269
270 static void *
axgbe_register(device_t dev)271 axgbe_register(device_t dev)
272 {
273 int axgbe_nfl;
274 int axgbe_nrxqs;
275 int error, i;
276 char *value = NULL;
277
278 value = kern_getenv("dev.ax.sph_enable");
279 if (value) {
280 axgbe_sph_enable = strtol(value, NULL, 10);
281 freeenv(value);
282 } else {
283 /*
284 * No tunable found, generate one with default values
285 * Note: only a reboot will reveal the new kenv
286 */
287 error = kern_setenv("dev.ax.sph_enable", "0");
288 if (error) {
289 printf("Error setting tunable, using default driver values\n");
290 }
291 axgbe_sph_enable = 0;
292 }
293
294 if (!axgbe_sph_enable) {
295 axgbe_nfl = 1;
296 axgbe_nrxqs = 1;
297 } else {
298 axgbe_nfl = 2;
299 axgbe_nrxqs = 2;
300 }
301
302 axgbe_sctx_init.isc_nfl = axgbe_nfl;
303 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
304
305 for (i = 0 ; i < axgbe_nrxqs ; i++) {
306 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
307 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
308 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
309 }
310
311 return (&axgbe_sctx_init);
312 }
313
314 /* MII Interface Functions */
315 static int
axgbe_miibus_readreg(device_t dev,int phy,int reg)316 axgbe_miibus_readreg(device_t dev, int phy, int reg)
317 {
318 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
319 struct xgbe_prv_data *pdata = &sc->pdata;
320 int val;
321
322 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
323
324 val = xgbe_phy_mii_read(pdata, phy, reg);
325
326 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
327 return (val & 0xFFFF);
328 }
329
330 static int
axgbe_miibus_writereg(device_t dev,int phy,int reg,int val)331 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
332 {
333 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
334 struct xgbe_prv_data *pdata = &sc->pdata;
335
336 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
337
338 xgbe_phy_mii_write(pdata, phy, reg, val);
339
340 return(0);
341 }
342
343 static void
axgbe_miibus_statchg(device_t dev)344 axgbe_miibus_statchg(device_t dev)
345 {
346 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
347 struct xgbe_prv_data *pdata = &sc->pdata;
348 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
349 if_t ifp = pdata->netdev;
350 int bmsr;
351
352 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
353 pdata->phy_link);
354
355 if (mii == NULL || ifp == NULL ||
356 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
357 return;
358
359 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
360 (IFM_ACTIVE | IFM_AVALID)) {
361
362 switch (IFM_SUBTYPE(mii->mii_media_active)) {
363 case IFM_10_T:
364 case IFM_100_TX:
365 pdata->phy.link = 1;
366 break;
367 case IFM_1000_T:
368 case IFM_1000_SX:
369 case IFM_2500_SX:
370 pdata->phy.link = 1;
371 break;
372 default:
373 pdata->phy.link = 0;
374 break;
375 }
376 } else
377 pdata->phy_link = 0;
378
379 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
380 if (bmsr & BMSR_ANEG) {
381
382 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
383
384 /* Raise AN Interrupt */
385 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
386 XGBE_AN_CL73_INT_MASK);
387 }
388 }
389
390 static int
axgbe_if_attach_pre(if_ctx_t ctx)391 axgbe_if_attach_pre(if_ctx_t ctx)
392 {
393 struct axgbe_if_softc *sc;
394 struct xgbe_prv_data *pdata;
395 struct resource *mac_res[2];
396 if_softc_ctx_t scctx;
397 if_shared_ctx_t sctx;
398 device_t dev;
399 device_t rdev;
400 unsigned int ma_lo, ma_hi;
401 unsigned int reg;
402 int ret;
403
404 sc = iflib_get_softc(ctx);
405 sc->pdata.dev = dev = iflib_get_dev(ctx);
406 sc->sctx = sctx = iflib_get_sctx(ctx);
407 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
408 sc->media = iflib_get_media(ctx);
409 sc->ctx = ctx;
410 sc->link_status = LINK_STATE_DOWN;
411 pdata = &sc->pdata;
412 pdata->netdev = iflib_get_ifp(ctx);
413
414 spin_lock_init(&pdata->xpcs_lock);
415
416 /* Initialize locks */
417 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
418 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
419
420 /* Allocate VLAN bitmap */
421 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
422 pdata->num_active_vlans = 0;
423
424 /* Get the version data */
425 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
426 if (pci_get_device(dev) == 0x1458)
427 sc->pdata.vdata = &xgbe_v2a;
428 else if (pci_get_device(dev) == 0x1459)
429 sc->pdata.vdata = &xgbe_v2b;
430
431 /* PCI setup */
432 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
433 axgbe_error("Unable to allocate bus resources\n");
434 ret = ENXIO;
435 goto free_vlans;
436 }
437
438 sc->pdata.xgmac_res = mac_res[0];
439 sc->pdata.xpcs_res = mac_res[1];
440
441 /*
442 * Set the PCS indirect addressing definition registers.
443 * A newer version of the hardware is using the same PCI ids
444 * for the network device but has altered register definitions
445 * for determining the window settings for the indirect PCS access.
446 * This code checks hardware usage and uses the register values
447 * accordingly.
448 */
449 rdev = pci_find_dbsf(0, 0, 0, 0);
450 if (rdev && pci_get_device(rdev) == 0x15d0
451 && pci_get_vendor(rdev) == 0x1022) {
452 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
453 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
454 } else {
455 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
456 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
457 }
458
459 /* Configure the PCS indirect addressing support */
460 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
461 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
462 pdata->xpcs_window <<= 6;
463 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
464 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
465 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
466 DBGPR("xpcs window def : %#010x\n",
467 pdata->xpcs_window_def_reg);
468 DBGPR("xpcs window sel : %#010x\n",
469 pdata->xpcs_window_sel_reg);
470 DBGPR("xpcs window : %#010x\n",
471 pdata->xpcs_window);
472 DBGPR("xpcs window size : %#010x\n",
473 pdata->xpcs_window_size);
474 DBGPR("xpcs window mask : %#010x\n",
475 pdata->xpcs_window_mask);
476
477 /* Enable all interrupts in the hardware */
478 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
479
480 /* Retrieve the MAC address */
481 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
482 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
483 pdata->mac_addr[0] = ma_lo & 0xff;
484 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
485 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
486 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
487 pdata->mac_addr[4] = ma_hi & 0xff;
488 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
489 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
490 axgbe_error("Invalid mac address\n");
491 ret = EINVAL;
492 goto release_bus_resource;
493 }
494 iflib_set_mac(ctx, pdata->mac_addr);
495
496 /* Clock settings */
497 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
498 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
499
500 /* Set the DMA coherency values */
501 pdata->coherent = 1;
502 pdata->arcr = XGBE_DMA_PCI_ARCR;
503 pdata->awcr = XGBE_DMA_PCI_AWCR;
504 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
505
506 /* Read the port property registers */
507 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
508 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
509 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
510 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
511 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
512 DBGPR("port property 0 = %#010x\n", pdata->pp0);
513 DBGPR("port property 1 = %#010x\n", pdata->pp1);
514 DBGPR("port property 2 = %#010x\n", pdata->pp2);
515 DBGPR("port property 3 = %#010x\n", pdata->pp3);
516 DBGPR("port property 4 = %#010x\n", pdata->pp4);
517
518 /* Set the maximum channels and queues */
519 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
520 MAX_TX_DMA);
521 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
522 MAX_RX_DMA);
523 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
524 MAX_TX_QUEUES);
525 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
526 MAX_RX_QUEUES);
527 DBGPR("max tx/rx channel count = %u/%u\n",
528 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
529 DBGPR("max tx/rx hw queue count = %u/%u\n",
530 pdata->tx_max_q_count, pdata->rx_max_q_count);
531
532 axgbe_set_counts(ctx);
533
534 /* Set the maximum fifo amounts */
535 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
536 TX_FIFO_SIZE);
537 pdata->tx_max_fifo_size *= 16384;
538 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
539 pdata->vdata->tx_max_fifo_size);
540 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
541 RX_FIFO_SIZE);
542 pdata->rx_max_fifo_size *= 16384;
543 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
544 pdata->vdata->rx_max_fifo_size);
545 DBGPR("max tx/rx max fifo size = %u/%u\n",
546 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
547
548 /* Initialize IFLIB if_softc_ctx_t */
549 axgbe_init_iflib_softc_ctx(sc);
550
551 /* Alloc channels */
552 if (axgbe_alloc_channels(ctx)) {
553 axgbe_error("Unable to allocate channel memory\n");
554 ret = ENOMEM;
555 goto release_bus_resource;
556 }
557
558 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
559
560 /* create the workqueue */
561 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
562 taskqueue_thread_enqueue, &pdata->dev_workqueue);
563 if (pdata->dev_workqueue == NULL) {
564 axgbe_error("Unable to allocate workqueue\n");
565 ret = ENOMEM;
566 goto free_channels;
567 }
568 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
569 "axgbe dev taskq");
570 if (ret) {
571 axgbe_error("Unable to start taskqueue\n");
572 ret = ENOMEM;
573 goto free_task_queue;
574 }
575
576 /* Init timers */
577 xgbe_init_timers(pdata);
578
579 return (0);
580
581 free_task_queue:
582 taskqueue_free(pdata->dev_workqueue);
583
584 free_channels:
585 axgbe_free_channels(sc);
586
587 release_bus_resource:
588 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
589
590 free_vlans:
591 free(pdata->active_vlans, M_AXGBE);
592
593 return (ret);
594 } /* axgbe_if_attach_pre */
595
596 static void
xgbe_init_all_fptrs(struct xgbe_prv_data * pdata)597 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
598 {
599 xgbe_init_function_ptrs_dev(&pdata->hw_if);
600 xgbe_init_function_ptrs_phy(&pdata->phy_if);
601 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
602 xgbe_init_function_ptrs_desc(&pdata->desc_if);
603
604 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
605 }
606
607 static void
axgbe_set_counts(if_ctx_t ctx)608 axgbe_set_counts(if_ctx_t ctx)
609 {
610 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
611 struct xgbe_prv_data *pdata = &sc->pdata;
612 cpuset_t lcpus;
613 int cpu_count, err;
614 size_t len;
615
616 /* Set all function pointers */
617 xgbe_init_all_fptrs(pdata);
618
619 /* Populate the hardware features */
620 xgbe_get_all_hw_features(pdata);
621
622 if (!pdata->tx_max_channel_count)
623 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
624 if (!pdata->rx_max_channel_count)
625 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
626
627 if (!pdata->tx_max_q_count)
628 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
629 if (!pdata->rx_max_q_count)
630 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
631
632 /*
633 * Calculate the number of Tx and Rx rings to be created
634 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
635 * the number of Tx queues to the number of Tx channels
636 * enabled
637 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
638 * number of Rx queues or maximum allowed
639 */
640
641 /* Get cpu count from sysctl */
642 len = sizeof(cpu_count);
643 err = kernel_sysctlbyname(curthread, "hw.ncpu", &cpu_count, &len, NULL,
644 0, NULL, 0);
645 if (err) {
646 axgbe_error("Unable to fetch number of cpus\n");
647 cpu_count = 1;
648 }
649
650 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
651 axgbe_error("Unable to fetch CPU list\n");
652 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
653 }
654
655 DBGPR("ncpu %d intrcpu %d\n", cpu_count, CPU_COUNT(&lcpus));
656
657 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
658 pdata->tx_ring_count = min(pdata->tx_ring_count,
659 pdata->tx_max_channel_count);
660 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
661
662 pdata->tx_q_count = pdata->tx_ring_count;
663
664 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
665 pdata->rx_ring_count = min(pdata->rx_ring_count,
666 pdata->rx_max_channel_count);
667
668 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
669
670 DBGPR("TX/RX max channel count = %u/%u\n",
671 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
672 DBGPR("TX/RX max queue count = %u/%u\n",
673 pdata->tx_max_q_count, pdata->rx_max_q_count);
674 DBGPR("TX/RX DMA ring count = %u/%u\n",
675 pdata->tx_ring_count, pdata->rx_ring_count);
676 DBGPR("TX/RX hardware queue count = %u/%u\n",
677 pdata->tx_q_count, pdata->rx_q_count);
678 } /* axgbe_set_counts */
679
680 static void
axgbe_init_iflib_softc_ctx(struct axgbe_if_softc * sc)681 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
682 {
683 struct xgbe_prv_data *pdata = &sc->pdata;
684 if_softc_ctx_t scctx = sc->scctx;
685 if_shared_ctx_t sctx = sc->sctx;
686 int i;
687
688 scctx->isc_nrxqsets = pdata->rx_q_count;
689 scctx->isc_ntxqsets = pdata->tx_q_count;
690 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
691 scctx->isc_tx_nsegments = 32;
692
693 for (i = 0; i < sctx->isc_ntxqs; i++) {
694 scctx->isc_txqsizes[i] =
695 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
696 128);
697 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
698 }
699
700 for (i = 0; i < sctx->isc_nrxqs; i++) {
701 scctx->isc_rxqsizes[i] =
702 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
703 128);
704 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
705 }
706
707 scctx->isc_tx_tso_segments_max = 32;
708 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
709 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
710
711 /*
712 * Set capabilities
713 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
714 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
715 * IFCAP_HWCSUM) is set
716 */
717 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
718 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
719 CSUM_TSO);
720 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
721 IFCAP_JUMBO_MTU |
722 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
723 IFCAP_VLAN_HWCSUM |
724 IFCAP_TSO | IFCAP_VLAN_HWTSO);
725 scctx->isc_capabilities = scctx->isc_capenable;
726
727 /*
728 * Set rss_table_size alone when adding RSS support. rss_table_mask
729 * will be set by IFLIB based on rss_table_size
730 */
731 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
732
733 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
734 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
735
736 scctx->isc_txrx = &axgbe_txrx;
737 }
738
739 static void
axgbe_initialize_rss_mapping(struct xgbe_prv_data * pdata)740 axgbe_initialize_rss_mapping(struct xgbe_prv_data *pdata)
741 {
742 int i;
743
744 /* Get RSS key */
745 #ifdef RSS
746 int qid;
747 uint32_t rss_hash_config = 0;
748
749 rss_getkey((uint8_t *)&pdata->rss_key);
750
751 rss_hash_config = rss_gethashconfig();
752
753 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
754 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
755 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
756 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
757 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
758 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
759 #else
760 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
761
762 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
763 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
764 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
765 #endif
766
767 /* Setup RSS lookup table */
768 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) {
769 #ifdef RSS
770 qid = rss_get_indirection_to_bucket(i) % pdata->rx_ring_count;
771 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
772 #else
773 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
774 i % pdata->rx_ring_count);
775 #endif
776 }
777
778 }
779
780 static int
axgbe_alloc_channels(if_ctx_t ctx)781 axgbe_alloc_channels(if_ctx_t ctx)
782 {
783 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
784 struct xgbe_prv_data *pdata = &sc->pdata;
785 struct xgbe_channel *channel;
786 int i, j, count;
787
788 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
789 pdata->rx_ring_count);
790
791 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
792 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
793
794 /* Allocate channel memory */
795 for (i = 0; i < count ; i++) {
796 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
797 M_AXGBE, M_NOWAIT | M_ZERO);
798
799 if (channel == NULL) {
800 for (j = 0; j < i; j++) {
801 free(pdata->channel[j], M_AXGBE);
802 pdata->channel[j] = NULL;
803 }
804 return (ENOMEM);
805 }
806
807 pdata->channel[i] = channel;
808 }
809
810 pdata->total_channel_count = count;
811 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
812
813 for (i = 0; i < count; i++) {
814
815 channel = pdata->channel[i];
816 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
817
818 channel->pdata = pdata;
819 channel->queue_index = i;
820 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
821 bus_space_subregion(channel->dma_tag,
822 rman_get_bushandle(pdata->xgmac_res),
823 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
824 &channel->dma_handle);
825 channel->tx_ring = NULL;
826 channel->rx_ring = NULL;
827 }
828
829 return (0);
830 } /* axgbe_alloc_channels */
831
832 static void
axgbe_free_channels(struct axgbe_if_softc * sc)833 axgbe_free_channels(struct axgbe_if_softc *sc)
834 {
835 struct xgbe_prv_data *pdata = &sc->pdata;
836 int i;
837
838 for (i = 0; i < pdata->total_channel_count ; i++) {
839 free(pdata->channel[i], M_AXGBE);
840 pdata->channel[i] = NULL;
841 }
842
843 pdata->total_channel_count = 0;
844 pdata->channel_count = 0;
845 }
846
847 static void
xgbe_service(void * ctx,int pending)848 xgbe_service(void *ctx, int pending)
849 {
850 struct xgbe_prv_data *pdata = ctx;
851 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
852 bool prev_state = false;
853
854 /* Get previous link status */
855 prev_state = pdata->phy.link;
856
857 pdata->phy_if.phy_status(pdata);
858
859 if (prev_state != pdata->phy.link) {
860 pdata->phy_link = pdata->phy.link;
861 axgbe_if_update_admin_status(sc->ctx);
862 }
863
864 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
865 }
866
867 static void
xgbe_service_timer(void * data)868 xgbe_service_timer(void *data)
869 {
870 struct xgbe_prv_data *pdata = data;
871
872 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
873 }
874
875 static void
xgbe_init_timers(struct xgbe_prv_data * pdata)876 xgbe_init_timers(struct xgbe_prv_data *pdata)
877 {
878 callout_init(&pdata->service_timer, 1);
879 }
880
881 static void
xgbe_start_timers(struct xgbe_prv_data * pdata)882 xgbe_start_timers(struct xgbe_prv_data *pdata)
883 {
884 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
885 }
886
887 static void
xgbe_stop_timers(struct xgbe_prv_data * pdata)888 xgbe_stop_timers(struct xgbe_prv_data *pdata)
889 {
890 callout_drain(&pdata->service_timer);
891 callout_stop(&pdata->service_timer);
892 }
893
894 static void
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)895 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
896 {
897 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
898
899 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
900 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
901 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
902 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
903 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
904 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
905 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
906 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
907 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
908 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
909 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
910 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
911 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
912 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
913 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
914 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
915 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
916 MDIO_AN_ADVERTISE,
917 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
918 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
919 MDIO_AN_ADVERTISE + 1,
920 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
921 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
922 MDIO_AN_ADVERTISE + 2,
923 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
924 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
925 MDIO_AN_COMP_STAT,
926 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
927
928 axgbe_printf(1, "\n************************************************\n");
929 }
930
931 static void
xgbe_dump_prop_registers(struct xgbe_prv_data * pdata)932 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
933 {
934 int i;
935
936 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
937
938 for (i = 0 ; i < 38 ; i++) {
939 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
940 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
941 (XP_PROP_0 + (i * 4))));
942 }
943 }
944
945 static void
xgbe_dump_dma_registers(struct xgbe_prv_data * pdata,int ch)946 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
947 {
948 struct xgbe_channel *channel;
949 int i;
950
951 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
952
953 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
954 XGMAC_IOREAD(pdata, DMA_MR));
955 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
956 XGMAC_IOREAD(pdata, DMA_SBMR));
957 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
958 XGMAC_IOREAD(pdata, DMA_ISR));
959 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
960 XGMAC_IOREAD(pdata, DMA_AXIARCR));
961 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
962 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
963 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
964 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
965 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
966 XGMAC_IOREAD(pdata, DMA_DSR0));
967 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
968 XGMAC_IOREAD(pdata, DMA_DSR1));
969 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
970 XGMAC_IOREAD(pdata, DMA_DSR2));
971 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
972 XGMAC_IOREAD(pdata, DMA_DSR3));
973 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
974 XGMAC_IOREAD(pdata, DMA_DSR4));
975 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
976 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
977 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
978 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
979
980 for (i = 0 ; i < 8 ; i++ ) {
981
982 if (ch >= 0) {
983 if (i != ch)
984 continue;
985 }
986
987 channel = pdata->channel[i];
988
989 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
990
991 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
992 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
993 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
994 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
995 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
996 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
997 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
998 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
999 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
1000 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
1001 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
1002 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
1003 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
1004 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
1005 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
1006 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
1007 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
1008 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
1009 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
1010 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
1011 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
1012 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
1013 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
1014 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
1015 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
1016 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
1017 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
1018 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
1019 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
1020 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
1021 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
1022 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
1023 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
1024 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
1025 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
1026 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
1027 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
1028 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
1029 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
1030 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
1031 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
1032 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
1033 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
1034 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
1035 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
1036 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
1037 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
1038 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
1039 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
1040 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
1041 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
1042 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
1043 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
1044 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
1045 }
1046 }
1047
1048 static void
xgbe_dump_mtl_registers(struct xgbe_prv_data * pdata)1049 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
1050 {
1051 int i;
1052
1053 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
1054
1055 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
1056 XGMAC_IOREAD(pdata, MTL_OMR));
1057 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
1058 XGMAC_IOREAD(pdata, MTL_FDCR));
1059 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
1060 XGMAC_IOREAD(pdata, MTL_FDSR));
1061 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
1062 XGMAC_IOREAD(pdata, MTL_FDDR));
1063 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
1064 XGMAC_IOREAD(pdata, MTL_ISR));
1065 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
1066 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
1067 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
1068 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1069 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
1070 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1071 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
1072 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1073 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
1074 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1075
1076 for (i = 0 ; i < 8 ; i++ ) {
1077
1078 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1079
1080 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1081 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1082 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1083 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1084 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1085 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1086 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1087 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1088 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1089 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1090 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1091 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1092
1093 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1094 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1095 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1096 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1097 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1098 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1099 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1100 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1101 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1102 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1103 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1104 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1105 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1106 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1107 }
1108 }
1109
1110 static void
xgbe_dump_mac_registers(struct xgbe_prv_data * pdata)1111 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1112 {
1113 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1114
1115 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1116 XGMAC_IOREAD(pdata, MAC_TCR));
1117 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1118 XGMAC_IOREAD(pdata, MAC_RCR));
1119 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1120 XGMAC_IOREAD(pdata, MAC_PFR));
1121 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1122 XGMAC_IOREAD(pdata, MAC_WTR));
1123 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1124 XGMAC_IOREAD(pdata, MAC_HTR0));
1125 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1126 XGMAC_IOREAD(pdata, MAC_HTR1));
1127 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1128 XGMAC_IOREAD(pdata, MAC_HTR2));
1129 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1130 XGMAC_IOREAD(pdata, MAC_HTR3));
1131 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1132 XGMAC_IOREAD(pdata, MAC_HTR4));
1133 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1134 XGMAC_IOREAD(pdata, MAC_HTR5));
1135 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1136 XGMAC_IOREAD(pdata, MAC_HTR6));
1137 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1138 XGMAC_IOREAD(pdata, MAC_HTR7));
1139 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1140 XGMAC_IOREAD(pdata, MAC_VLANTR));
1141 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1142 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1143 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1144 XGMAC_IOREAD(pdata, MAC_VLANIR));
1145 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1146 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1147 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1148 XGMAC_IOREAD(pdata, MAC_RETMR));
1149 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1150 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1151 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1152 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1153 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1154 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1155 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1156 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1157 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1158 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1159 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1160 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1161 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1162 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1163 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1164 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1165 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1166 XGMAC_IOREAD(pdata, MAC_RFCR));
1167 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1168 XGMAC_IOREAD(pdata, MAC_RQC0R));
1169 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1170 XGMAC_IOREAD(pdata, MAC_RQC1R));
1171 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1172 XGMAC_IOREAD(pdata, MAC_RQC2R));
1173 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1174 XGMAC_IOREAD(pdata, MAC_RQC3R));
1175 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1176 XGMAC_IOREAD(pdata, MAC_ISR));
1177 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1178 XGMAC_IOREAD(pdata, MAC_IER));
1179 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1180 XGMAC_IOREAD(pdata, MAC_RTSR));
1181 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1182 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1183 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1184 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1185 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1186 XGMAC_IOREAD(pdata, MAC_LPICSR));
1187 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1188 XGMAC_IOREAD(pdata, MAC_LPITCR));
1189 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1190 XGMAC_IOREAD(pdata, MAC_TIR));
1191 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1192 XGMAC_IOREAD(pdata, MAC_VR));
1193 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1194 XGMAC_IOREAD(pdata, MAC_DR));
1195 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1196 XGMAC_IOREAD(pdata, MAC_HWF0R));
1197 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1198 XGMAC_IOREAD(pdata, MAC_HWF1R));
1199 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1200 XGMAC_IOREAD(pdata, MAC_HWF2R));
1201 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1202 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1203 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1204 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1205 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1206 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1207 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1208 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1209 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1210 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1211 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1212 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1213 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1214 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1215 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1216 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1217 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1218 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1219 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1220 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1221 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1222 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1223 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1224 XGMAC_IOREAD(pdata, MAC_RSSCR));
1225 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1226 XGMAC_IOREAD(pdata, MAC_RSSDR));
1227 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1228 XGMAC_IOREAD(pdata, MAC_RSSAR));
1229 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1230 XGMAC_IOREAD(pdata, MAC_TSCR));
1231 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1232 XGMAC_IOREAD(pdata, MAC_SSIR));
1233 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1234 XGMAC_IOREAD(pdata, MAC_STSR));
1235 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1236 XGMAC_IOREAD(pdata, MAC_STNR));
1237 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1238 XGMAC_IOREAD(pdata, MAC_STSUR));
1239 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1240 XGMAC_IOREAD(pdata, MAC_STNUR));
1241 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1242 XGMAC_IOREAD(pdata, MAC_TSAR));
1243 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1244 XGMAC_IOREAD(pdata, MAC_TSSR));
1245 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1246 XGMAC_IOREAD(pdata, MAC_TXSNR));
1247 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1248 XGMAC_IOREAD(pdata, MAC_TXSSR));
1249 }
1250
1251 static void
xgbe_dump_rmon_counters(struct xgbe_prv_data * pdata)1252 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1253 {
1254 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1255
1256 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1257
1258 pdata->hw_if.read_mmc_stats(pdata);
1259
1260 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1261 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1262 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1263 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1264 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1265 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1266 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1267 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1268 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1269 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1270 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1271 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1272 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1273 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1274 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1275 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1276 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1277 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1278 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1279 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1280 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1281 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1282 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1283 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1284 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1285 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1286 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1287 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1288 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1289 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1290 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1291 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1292 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1293 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1294 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1295 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1296 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1297 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1298 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1299 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1300 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1301 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1302 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1303 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1304 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1305 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1306 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1307 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1308 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1309 MMC_RXRUNTERROR, stats->rxrunterror);
1310 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1311 MMC_RXJABBERERROR, stats->rxjabbererror);
1312 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1313 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1314 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1315 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1316 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1317 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1318 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1319 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1320 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1321 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1322 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1323 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1324 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1325 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1326 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1327 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1328 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1329 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1330 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1331 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1332 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1333 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1334 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1335 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1336 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1337 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1338 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1339 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1340 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1341 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1342 }
1343
1344 void
xgbe_dump_i2c_registers(struct xgbe_prv_data * pdata)1345 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1346 {
1347 axgbe_printf(1, "*************** I2C Registers **************\n");
1348 axgbe_printf(1, " IC_CON : %010x\n",
1349 XI2C_IOREAD(pdata, 0x00));
1350 axgbe_printf(1, " IC_TAR : %010x\n",
1351 XI2C_IOREAD(pdata, 0x04));
1352 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1353 XI2C_IOREAD(pdata, 0x0c));
1354 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1355 XI2C_IOREAD(pdata, 0x2c));
1356 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1357 XI2C_IOREAD(pdata, 0x30));
1358 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1359 XI2C_IOREAD(pdata, 0x34));
1360 axgbe_printf(1, " IC_RX_TL : %010x\n",
1361 XI2C_IOREAD(pdata, 0x38));
1362 axgbe_printf(1, " IC_TX_TL : %010x\n",
1363 XI2C_IOREAD(pdata, 0x3c));
1364 axgbe_printf(1, " IC_ENABLE : %010x\n",
1365 XI2C_IOREAD(pdata, 0x6c));
1366 axgbe_printf(1, " IC_STATUS : %010x\n",
1367 XI2C_IOREAD(pdata, 0x70));
1368 axgbe_printf(1, " IC_TXFLR : %010x\n",
1369 XI2C_IOREAD(pdata, 0x74));
1370 axgbe_printf(1, " IC_RXFLR : %010x\n",
1371 XI2C_IOREAD(pdata, 0x78));
1372 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1373 XI2C_IOREAD(pdata, 0x9c));
1374 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1375 XI2C_IOREAD(pdata, 0xf4));
1376 }
1377
1378 static void
xgbe_dump_active_vlans(struct xgbe_prv_data * pdata)1379 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1380 {
1381 int i;
1382
1383 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1384 if (i && (i%8 == 0))
1385 axgbe_printf(1, "\n");
1386 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1387 }
1388 axgbe_printf(1, "\n");
1389 }
1390
1391 static void
xgbe_default_config(struct xgbe_prv_data * pdata)1392 xgbe_default_config(struct xgbe_prv_data *pdata)
1393 {
1394 pdata->blen = DMA_SBMR_BLEN_64;
1395 pdata->pbl = DMA_PBL_128;
1396 pdata->aal = 1;
1397 pdata->rd_osr_limit = 8;
1398 pdata->wr_osr_limit = 8;
1399 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1400 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1401 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1402 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1403 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1404 pdata->pause_autoneg = 1;
1405 pdata->phy_speed = SPEED_UNKNOWN;
1406 pdata->power_down = 0;
1407 pdata->enable_rss = 1;
1408 }
1409
1410 static int
axgbe_if_attach_post(if_ctx_t ctx)1411 axgbe_if_attach_post(if_ctx_t ctx)
1412 {
1413 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1414 struct xgbe_prv_data *pdata = &sc->pdata;
1415 if_t ifp = pdata->netdev;
1416 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1417 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1418 if_softc_ctx_t scctx = sc->scctx;
1419 int ret;
1420
1421 /* set split header support based on tunable */
1422 pdata->sph_enable = axgbe_sph_enable;
1423
1424 /* Initialize ECC timestamps */
1425 pdata->tx_sec_period = ticks;
1426 pdata->tx_ded_period = ticks;
1427 pdata->rx_sec_period = ticks;
1428 pdata->rx_ded_period = ticks;
1429 pdata->desc_sec_period = ticks;
1430 pdata->desc_ded_period = ticks;
1431
1432 /* Reset the hardware */
1433 ret = hw_if->exit(&sc->pdata);
1434 if (ret)
1435 axgbe_error("%s: exit error %d\n", __func__, ret);
1436
1437 axgbe_sysctl_init(pdata);
1438
1439 /* Configure the defaults */
1440 xgbe_default_config(pdata);
1441
1442 /* Set default max values if not provided */
1443 if (!pdata->tx_max_fifo_size)
1444 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1445 if (!pdata->rx_max_fifo_size)
1446 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1447
1448 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1449 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1450
1451 /* Set and validate the number of descriptors for a ring */
1452 MPASS(powerof2(XGBE_TX_DESC_CNT));
1453 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1454 MPASS(powerof2(XGBE_RX_DESC_CNT));
1455 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1456
1457 /* Adjust the number of queues based on interrupts assigned */
1458 if (pdata->channel_irq_count) {
1459 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1460 pdata->channel_irq_count);
1461 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1462 pdata->channel_irq_count);
1463
1464 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1465 pdata->tx_ring_count, pdata->tx_q_count,
1466 pdata->rx_ring_count, pdata->rx_q_count);
1467 }
1468
1469 /* Set channel count based on interrupts assigned */
1470 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1471 scctx->isc_nrxqsets);
1472 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1473
1474 axgbe_initialize_rss_mapping(pdata);
1475
1476 /* Initialize the PHY device */
1477 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1478 phy_if->phy_init(pdata);
1479
1480 /* Set the coalescing */
1481 xgbe_init_rx_coalesce(&sc->pdata);
1482 xgbe_init_tx_coalesce(&sc->pdata);
1483
1484 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1485 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1486 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1487 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1488 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1489 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1490 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1491 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1492 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1493 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1494 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1495 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1496 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1497
1498 /* Initialize the phy */
1499 pdata->phy_link = -1;
1500 pdata->phy_speed = SPEED_UNKNOWN;
1501 ret = phy_if->phy_reset(pdata);
1502 if (ret)
1503 return (ret);
1504
1505 /* Calculate the Rx buffer size before allocating rings */
1506 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1507 pdata->rx_buf_size = ret;
1508 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1509
1510 /*
1511 * Mark the device down until it is initialized, which happens
1512 * when the device is accessed first (for configuring the iface,
1513 * eg: setting IP)
1514 */
1515 set_bit(XGBE_DOWN, &pdata->dev_state);
1516
1517 DBGPR("mtu %d\n", if_getmtu(ifp));
1518 scctx->isc_max_frame_size = if_getmtu(ifp) + 18;
1519 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1520
1521 axgbe_pci_init(pdata);
1522
1523 return (0);
1524 } /* axgbe_if_attach_post */
1525
1526 static void
xgbe_free_intr(struct xgbe_prv_data * pdata,struct resource * res,void * tag,int rid)1527 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1528 int rid)
1529 {
1530 if (tag)
1531 bus_teardown_intr(pdata->dev, res, tag);
1532
1533 if (res)
1534 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1535 }
1536
1537 static void
axgbe_interrupts_free(if_ctx_t ctx)1538 axgbe_interrupts_free(if_ctx_t ctx)
1539 {
1540 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1541 struct xgbe_prv_data *pdata = &sc->pdata;
1542 if_softc_ctx_t scctx = sc->scctx;
1543 struct xgbe_channel *channel;
1544 struct if_irq irq;
1545 int i;
1546
1547 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1548
1549 /* Free dev_irq */
1550 iflib_irq_free(ctx, &pdata->dev_irq);
1551
1552 /* Free ecc_irq */
1553 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1554 pdata->ecc_rid);
1555
1556 /* Free i2c_irq */
1557 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1558 pdata->i2c_rid);
1559
1560 /* Free an_irq */
1561 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1562 pdata->an_rid);
1563
1564 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1565
1566 channel = pdata->channel[i];
1567 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1568 irq.ii_res = channel->dma_irq_res;
1569 irq.ii_tag = channel->dma_irq_tag;
1570 iflib_irq_free(ctx, &irq);
1571 }
1572 }
1573
1574 static int
axgbe_if_detach(if_ctx_t ctx)1575 axgbe_if_detach(if_ctx_t ctx)
1576 {
1577 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1578 struct xgbe_prv_data *pdata = &sc->pdata;
1579 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1580 struct resource *mac_res[2];
1581
1582 mac_res[0] = pdata->xgmac_res;
1583 mac_res[1] = pdata->xpcs_res;
1584
1585 phy_if->phy_stop(pdata);
1586 phy_if->phy_exit(pdata);
1587
1588 /* Free Interrupts */
1589 axgbe_interrupts_free(ctx);
1590
1591 /* Free workqueues */
1592 taskqueue_free(pdata->dev_workqueue);
1593
1594 /* Release bus resources */
1595 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1596
1597 /* Free VLAN bitmap */
1598 free(pdata->active_vlans, M_AXGBE);
1599
1600 axgbe_sysctl_exit(pdata);
1601
1602 return (0);
1603 } /* axgbe_if_detach */
1604
1605 static void
axgbe_pci_init(struct xgbe_prv_data * pdata)1606 axgbe_pci_init(struct xgbe_prv_data *pdata)
1607 {
1608 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1609 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1610 int ret = 0;
1611
1612 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1613 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1614 return;
1615 }
1616
1617 hw_if->init(pdata);
1618
1619 ret = phy_if->phy_start(pdata);
1620 if (ret) {
1621 axgbe_error("%s: phy start %d\n", __func__, ret);
1622 ret = hw_if->exit(pdata);
1623 if (ret)
1624 axgbe_error("%s: exit error %d\n", __func__, ret);
1625 return;
1626 }
1627
1628 hw_if->enable_tx(pdata);
1629 hw_if->enable_rx(pdata);
1630
1631 xgbe_start_timers(pdata);
1632
1633 clear_bit(XGBE_DOWN, &pdata->dev_state);
1634
1635 xgbe_dump_phy_registers(pdata);
1636 xgbe_dump_prop_registers(pdata);
1637 xgbe_dump_dma_registers(pdata, -1);
1638 xgbe_dump_mtl_registers(pdata);
1639 xgbe_dump_mac_registers(pdata);
1640 xgbe_dump_rmon_counters(pdata);
1641 }
1642
1643 static void
axgbe_if_init(if_ctx_t ctx)1644 axgbe_if_init(if_ctx_t ctx)
1645 {
1646 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1647 struct xgbe_prv_data *pdata = &sc->pdata;
1648
1649 axgbe_pci_init(pdata);
1650 }
1651
1652 static void
axgbe_pci_stop(if_ctx_t ctx)1653 axgbe_pci_stop(if_ctx_t ctx)
1654 {
1655 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1656 struct xgbe_prv_data *pdata = &sc->pdata;
1657 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1658 int ret;
1659
1660 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1661 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1662 return;
1663 }
1664
1665 xgbe_stop_timers(pdata);
1666 taskqueue_drain_all(pdata->dev_workqueue);
1667
1668 hw_if->disable_tx(pdata);
1669 hw_if->disable_rx(pdata);
1670
1671 ret = hw_if->exit(pdata);
1672 if (ret)
1673 axgbe_error("%s: exit error %d\n", __func__, ret);
1674
1675 set_bit(XGBE_DOWN, &pdata->dev_state);
1676 }
1677
1678 static void
axgbe_if_stop(if_ctx_t ctx)1679 axgbe_if_stop(if_ctx_t ctx)
1680 {
1681 axgbe_pci_stop(ctx);
1682 }
1683
1684 static void
axgbe_if_disable_intr(if_ctx_t ctx)1685 axgbe_if_disable_intr(if_ctx_t ctx)
1686 {
1687 /* TODO - implement */
1688 }
1689
1690 static void
axgbe_if_enable_intr(if_ctx_t ctx)1691 axgbe_if_enable_intr(if_ctx_t ctx)
1692 {
1693 /* TODO - implement */
1694 }
1695
1696 static int
axgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int ntxqs,int ntxqsets)1697 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1698 int ntxqsets)
1699 {
1700 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1701 struct xgbe_prv_data *pdata = &sc->pdata;
1702 if_softc_ctx_t scctx = sc->scctx;
1703 struct xgbe_channel *channel;
1704 struct xgbe_ring *tx_ring;
1705 int i, j, k;
1706
1707 MPASS(scctx->isc_ntxqsets > 0);
1708 MPASS(scctx->isc_ntxqsets == ntxqsets);
1709 MPASS(ntxqs == 1);
1710
1711 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1712 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1713
1714 for (i = 0 ; i < ntxqsets; i++) {
1715
1716 channel = pdata->channel[i];
1717
1718 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1719 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1720
1721 if (tx_ring == NULL) {
1722 axgbe_error("Unable to allocate TX ring memory\n");
1723 goto tx_ring_fail;
1724 }
1725
1726 channel->tx_ring = tx_ring;
1727
1728 for (j = 0; j < ntxqs; j++, tx_ring++) {
1729 tx_ring->rdata =
1730 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1731 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1732
1733 /* Get the virtual & physical address of hw queues */
1734 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1735 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1736 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1737 spin_lock_init(&tx_ring->lock);
1738 }
1739 }
1740
1741 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1742
1743 return (0);
1744
1745 tx_ring_fail:
1746
1747 for (j = 0; j < i ; j++) {
1748
1749 channel = pdata->channel[j];
1750
1751 tx_ring = channel->tx_ring;
1752 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1753 if (tx_ring && tx_ring->rdata)
1754 free(tx_ring->rdata, M_AXGBE);
1755 }
1756 free(channel->tx_ring, M_AXGBE);
1757
1758 channel->tx_ring = NULL;
1759 }
1760
1761 return (ENOMEM);
1762
1763 } /* axgbe_if_tx_queues_alloc */
1764
1765 static int
axgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int nrxqs,int nrxqsets)1766 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1767 int nrxqsets)
1768 {
1769 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1770 struct xgbe_prv_data *pdata = &sc->pdata;
1771 if_softc_ctx_t scctx = sc->scctx;
1772 struct xgbe_channel *channel;
1773 struct xgbe_ring *rx_ring;
1774 int i, j, k;
1775
1776 MPASS(scctx->isc_nrxqsets > 0);
1777 MPASS(scctx->isc_nrxqsets == nrxqsets);
1778 if (!pdata->sph_enable) {
1779 MPASS(nrxqs == 1);
1780 } else {
1781 MPASS(nrxqs == 2);
1782 }
1783
1784 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1785 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1786
1787 for (i = 0 ; i < nrxqsets; i++) {
1788
1789 channel = pdata->channel[i];
1790
1791 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1792 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1793
1794 if (rx_ring == NULL) {
1795 axgbe_error("Unable to allocate RX ring memory\n");
1796 goto rx_ring_fail;
1797 }
1798
1799 channel->rx_ring = rx_ring;
1800
1801 for (j = 0; j < nrxqs; j++, rx_ring++) {
1802 rx_ring->rdata =
1803 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1804 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1805
1806 /* Get the virtual and physical address of the hw queues */
1807 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1808 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1809 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1810 spin_lock_init(&rx_ring->lock);
1811 }
1812 }
1813
1814 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1815
1816 return (0);
1817
1818 rx_ring_fail:
1819
1820 for (j = 0 ; j < i ; j++) {
1821
1822 channel = pdata->channel[j];
1823
1824 rx_ring = channel->rx_ring;
1825 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1826 if (rx_ring && rx_ring->rdata)
1827 free(rx_ring->rdata, M_AXGBE);
1828 }
1829 free(channel->rx_ring, M_AXGBE);
1830
1831 channel->rx_ring = NULL;
1832 }
1833
1834 return (ENOMEM);
1835
1836 } /* axgbe_if_rx_queues_alloc */
1837
1838 static void
axgbe_if_queues_free(if_ctx_t ctx)1839 axgbe_if_queues_free(if_ctx_t ctx)
1840 {
1841 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1842 struct xgbe_prv_data *pdata = &sc->pdata;
1843 if_softc_ctx_t scctx = sc->scctx;
1844 if_shared_ctx_t sctx = sc->sctx;
1845 struct xgbe_channel *channel;
1846 struct xgbe_ring *tx_ring;
1847 struct xgbe_ring *rx_ring;
1848 int i, j;
1849
1850 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1851
1852 channel = pdata->channel[i];
1853
1854 tx_ring = channel->tx_ring;
1855 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1856 if (tx_ring && tx_ring->rdata)
1857 free(tx_ring->rdata, M_AXGBE);
1858 }
1859 free(channel->tx_ring, M_AXGBE);
1860 channel->tx_ring = NULL;
1861 }
1862
1863 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1864
1865 channel = pdata->channel[i];
1866
1867 rx_ring = channel->rx_ring;
1868 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1869 if (rx_ring && rx_ring->rdata)
1870 free(rx_ring->rdata, M_AXGBE);
1871 }
1872 free(channel->rx_ring, M_AXGBE);
1873 channel->rx_ring = NULL;
1874 }
1875
1876 axgbe_free_channels(sc);
1877 } /* axgbe_if_queues_free */
1878
1879 static void
axgbe_if_vlan_register(if_ctx_t ctx,uint16_t vtag)1880 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1881 {
1882 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1883 struct xgbe_prv_data *pdata = &sc->pdata;
1884 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1885
1886 if (!bit_test(pdata->active_vlans, vtag)) {
1887 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1888
1889 bit_set(pdata->active_vlans, vtag);
1890 hw_if->update_vlan_hash_table(pdata);
1891 pdata->num_active_vlans++;
1892
1893 axgbe_printf(1, "Total active vlans: %d\n",
1894 pdata->num_active_vlans);
1895 } else
1896 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1897
1898 xgbe_dump_active_vlans(pdata);
1899 }
1900
1901 static void
axgbe_if_vlan_unregister(if_ctx_t ctx,uint16_t vtag)1902 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1903 {
1904 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1905 struct xgbe_prv_data *pdata = &sc->pdata;
1906 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1907
1908 if (pdata->num_active_vlans == 0) {
1909 axgbe_printf(1, "No active VLANs to unregister\n");
1910 return;
1911 }
1912
1913 if (bit_test(pdata->active_vlans, vtag)){
1914 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1915
1916 bit_clear(pdata->active_vlans, vtag);
1917 hw_if->update_vlan_hash_table(pdata);
1918 pdata->num_active_vlans--;
1919
1920 axgbe_printf(1, "Total active vlans: %d\n",
1921 pdata->num_active_vlans);
1922 } else
1923 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1924
1925 xgbe_dump_active_vlans(pdata);
1926 }
1927
1928 #if __FreeBSD_version >= 1300000
1929 static bool
axgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1930 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1931 {
1932 switch (event) {
1933 case IFLIB_RESTART_VLAN_CONFIG:
1934 default:
1935 return (true);
1936 }
1937 }
1938 #endif
1939
1940 static int
axgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)1941 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1942 {
1943 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1944 struct xgbe_prv_data *pdata = &sc->pdata;
1945 if_softc_ctx_t scctx = sc->scctx;
1946 struct xgbe_channel *channel;
1947 struct if_irq irq;
1948 int i, error, rid = 0, flags;
1949 char buf[16];
1950
1951 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1952
1953 pdata->isr_as_tasklet = 1;
1954
1955 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1956 pdata->irq_count = 1;
1957 pdata->channel_irq_count = 1;
1958 return (0);
1959 }
1960
1961 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1962 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1963
1964 flags = RF_ACTIVE;
1965
1966 /* DEV INTR SETUP */
1967 rid++;
1968 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1969 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1970 if (error) {
1971 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1972 rid, "dev_irq");
1973 return (error);
1974 }
1975
1976 /* ECC INTR SETUP */
1977 rid++;
1978 pdata->ecc_rid = rid;
1979 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1980 &rid, flags);
1981 if (!pdata->ecc_irq_res) {
1982 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1983 rid, "ecc_irq");
1984 return (ENOMEM);
1985 }
1986
1987 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1988 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1989 if (error) {
1990 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1991 rid, "ecc_irq", error);
1992 return (error);
1993 }
1994
1995 /* I2C INTR SETUP */
1996 rid++;
1997 pdata->i2c_rid = rid;
1998 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1999 &rid, flags);
2000 if (!pdata->i2c_irq_res) {
2001 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
2002 rid, "i2c_irq");
2003 return (ENOMEM);
2004 }
2005
2006 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
2007 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
2008 if (error) {
2009 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2010 rid, "i2c_irq", error);
2011 return (error);
2012 }
2013
2014 /* AN INTR SETUP */
2015 rid++;
2016 pdata->an_rid = rid;
2017 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
2018 &rid, flags);
2019 if (!pdata->an_irq_res) {
2020 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
2021 rid, "an_irq");
2022 return (ENOMEM);
2023 }
2024
2025 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
2026 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
2027 if (error) {
2028 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2029 rid, "an_irq", error);
2030 return (error);
2031 }
2032
2033 pdata->per_channel_irq = 1;
2034 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
2035 rid++;
2036 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
2037
2038 channel = pdata->channel[i];
2039
2040 snprintf(buf, sizeof(buf), "rxq%d", i);
2041 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
2042 axgbe_msix_que, channel, channel->queue_index, buf);
2043
2044 if (error) {
2045 axgbe_error("Failed to allocated que int %d err: %d\n",
2046 i, error);
2047 return (error);
2048 }
2049
2050 channel->dma_irq_rid = rid;
2051 channel->dma_irq_res = irq.ii_res;
2052 channel->dma_irq_tag = irq.ii_tag;
2053 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2054 __func__, scctx->isc_nrxqsets, i, rid);
2055 }
2056 pdata->irq_count = msix;
2057 pdata->channel_irq_count = scctx->isc_nrxqsets;
2058
2059 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2060
2061 channel = pdata->channel[i];
2062
2063 snprintf(buf, sizeof(buf), "txq%d", i);
2064 irq.ii_res = channel->dma_irq_res;
2065 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2066 channel->queue_index, buf);
2067 }
2068
2069 return (0);
2070 } /* axgbe_if_msix_intr_assign */
2071
2072 static int
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2073 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2074 {
2075 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2076 enum xgbe_int int_id;
2077
2078 if (channel->tx_ring && channel->rx_ring)
2079 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2080 else if (channel->tx_ring)
2081 int_id = XGMAC_INT_DMA_CH_SR_TI;
2082 else if (channel->rx_ring)
2083 int_id = XGMAC_INT_DMA_CH_SR_RI;
2084 else
2085 return (-1);
2086
2087 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2088 __func__, channel->queue_index, int_id);
2089 return (hw_if->enable_int(channel, int_id));
2090 }
2091
2092 static void
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2093 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2094 {
2095 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2096 enum xgbe_int int_id;
2097
2098 if (channel->tx_ring && channel->rx_ring)
2099 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2100 else if (channel->tx_ring)
2101 int_id = XGMAC_INT_DMA_CH_SR_TI;
2102 else if (channel->rx_ring)
2103 int_id = XGMAC_INT_DMA_CH_SR_RI;
2104 else
2105 return;
2106
2107 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2108 __func__, channel->queue_index, int_id);
2109 hw_if->disable_int(channel, int_id);
2110 }
2111
2112 static void
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)2113 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2114 {
2115 unsigned int i;
2116
2117 for (i = 0; i < pdata->channel_count; i++)
2118 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2119 }
2120
2121 static int
axgbe_msix_que(void * arg)2122 axgbe_msix_que(void *arg)
2123 {
2124 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2125 struct xgbe_prv_data *pdata = channel->pdata;
2126 unsigned int dma_status;
2127
2128 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2129 __func__, channel->queue_index,
2130 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2131 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2132 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2133 XGMAC_IOREAD(pdata, DMA_ISR),
2134 XGMAC_IOREAD(pdata, MAC_ISR));
2135
2136 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2137
2138 /* Disable Tx and Rx channel interrupts */
2139 xgbe_disable_rx_tx_int(pdata, channel);
2140
2141 /* Clear the interrupts */
2142 dma_status = 0;
2143 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2144 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2145 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2146
2147 return (FILTER_SCHEDULE_THREAD);
2148 }
2149
2150 static int
axgbe_dev_isr(void * arg)2151 axgbe_dev_isr(void *arg)
2152 {
2153 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2154 struct xgbe_prv_data *pdata = &sc->pdata;
2155 struct xgbe_channel *channel;
2156 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2157 unsigned int i, dma_isr, dma_ch_isr;
2158 unsigned int mac_isr, mac_mdioisr;
2159 int ret = FILTER_HANDLED;
2160
2161 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2162 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2163
2164 if (!dma_isr)
2165 return (FILTER_HANDLED);
2166
2167 for (i = 0; i < pdata->channel_count; i++) {
2168
2169 if (!(dma_isr & (1 << i)))
2170 continue;
2171
2172 channel = pdata->channel[i];
2173
2174 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2175 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2176 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2177 DMA_CH_DSR));
2178
2179 /*
2180 * The TI or RI interrupt bits may still be set even if using
2181 * per channel DMA interrupts. Check to be sure those are not
2182 * enabled before using the private data napi structure.
2183 */
2184 if (!pdata->per_channel_irq &&
2185 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2186 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2187
2188 /* Disable Tx and Rx interrupts */
2189 xgbe_disable_rx_tx_ints(pdata);
2190 } else {
2191
2192 /*
2193 * Don't clear Rx/Tx status if doing per channel DMA
2194 * interrupts, these will be cleared by the ISR for
2195 * per channel DMA interrupts
2196 */
2197 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2198 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2199 }
2200
2201 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2202 pdata->ext_stats.rx_buffer_unavailable++;
2203
2204 /* Restart the device on a Fatal Bus Error */
2205 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2206 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2207 __func__, dma_ch_isr);
2208
2209 /* Clear all interrupt signals */
2210 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2211
2212 ret = FILTER_SCHEDULE_THREAD;
2213 }
2214
2215 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2216
2217 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2218 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2219
2220 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2221 hw_if->tx_mmc_int(pdata);
2222
2223 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2224 hw_if->rx_mmc_int(pdata);
2225
2226 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2227 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2228
2229 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2230 SNGLCOMPINT))
2231 wakeup_one(pdata);
2232 }
2233
2234 }
2235
2236 return (ret);
2237 } /* axgbe_dev_isr */
2238
2239 static void
axgbe_i2c_isr(void * arg)2240 axgbe_i2c_isr(void *arg)
2241 {
2242 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2243
2244 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2245 }
2246
2247 static void
axgbe_ecc_isr(void * arg)2248 axgbe_ecc_isr(void *arg)
2249 {
2250 /* TODO - implement */
2251 }
2252
2253 static void
axgbe_an_isr(void * arg)2254 axgbe_an_isr(void *arg)
2255 {
2256 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2257
2258 sc->pdata.phy_if.an_isr(&sc->pdata);
2259 }
2260
2261 static int
axgbe_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2262 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2263 {
2264 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2265 struct xgbe_prv_data *pdata = &sc->pdata;
2266 int ret;
2267
2268 if (qid < pdata->tx_q_count) {
2269 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2270 if (ret) {
2271 axgbe_error("Enable TX INT failed\n");
2272 return (ret);
2273 }
2274 } else
2275 axgbe_error("Queue ID exceed channel count\n");
2276
2277 return (0);
2278 }
2279
2280 static int
axgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2281 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2282 {
2283 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2284 struct xgbe_prv_data *pdata = &sc->pdata;
2285 int ret;
2286
2287 if (qid < pdata->rx_q_count) {
2288 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2289 if (ret) {
2290 axgbe_error("Enable RX INT failed\n");
2291 return (ret);
2292 }
2293 } else
2294 axgbe_error("Queue ID exceed channel count\n");
2295
2296 return (0);
2297 }
2298
2299 static void
axgbe_if_update_admin_status(if_ctx_t ctx)2300 axgbe_if_update_admin_status(if_ctx_t ctx)
2301 {
2302 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2303 struct xgbe_prv_data *pdata = &sc->pdata;
2304
2305 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2306 pdata->phy_link, sc->link_status, pdata->phy.speed);
2307
2308 if (pdata->phy_link < 0)
2309 return;
2310
2311 if (pdata->phy_link) {
2312 if (sc->link_status == LINK_STATE_DOWN) {
2313 sc->link_status = LINK_STATE_UP;
2314 if (pdata->phy.speed & SPEED_10000)
2315 iflib_link_state_change(ctx, LINK_STATE_UP,
2316 IF_Gbps(10));
2317 else if (pdata->phy.speed & SPEED_2500)
2318 iflib_link_state_change(ctx, LINK_STATE_UP,
2319 IF_Gbps(2.5));
2320 else if (pdata->phy.speed & SPEED_1000)
2321 iflib_link_state_change(ctx, LINK_STATE_UP,
2322 IF_Gbps(1));
2323 else if (pdata->phy.speed & SPEED_100)
2324 iflib_link_state_change(ctx, LINK_STATE_UP,
2325 IF_Mbps(100));
2326 else if (pdata->phy.speed & SPEED_10)
2327 iflib_link_state_change(ctx, LINK_STATE_UP,
2328 IF_Mbps(10));
2329 }
2330 } else {
2331 if (sc->link_status == LINK_STATE_UP) {
2332 sc->link_status = LINK_STATE_DOWN;
2333 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2334 }
2335 }
2336 }
2337
2338 static int
axgbe_if_media_change(if_ctx_t ctx)2339 axgbe_if_media_change(if_ctx_t ctx)
2340 {
2341 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2342 struct ifmedia *ifm = iflib_get_media(ctx);
2343
2344 sx_xlock(&sc->pdata.an_mutex);
2345 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2346 return (EINVAL);
2347
2348 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2349 case IFM_10G_KR:
2350 sc->pdata.phy.speed = SPEED_10000;
2351 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2352 break;
2353 case IFM_2500_KX:
2354 sc->pdata.phy.speed = SPEED_2500;
2355 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2356 break;
2357 case IFM_1000_KX:
2358 sc->pdata.phy.speed = SPEED_1000;
2359 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2360 break;
2361 case IFM_100_TX:
2362 sc->pdata.phy.speed = SPEED_100;
2363 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2364 break;
2365 case IFM_AUTO:
2366 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2367 break;
2368 }
2369 sx_xunlock(&sc->pdata.an_mutex);
2370
2371 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2372 }
2373
2374 static int
axgbe_if_promisc_set(if_ctx_t ctx,int flags)2375 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2376 {
2377 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2378 struct xgbe_prv_data *pdata = &sc->pdata;
2379 if_t ifp = pdata->netdev;
2380
2381 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n",
2382 __func__, XGMAC_IOREAD(pdata, MAC_PFR), if_getdrvflags(ifp),
2383 if_getflags(ifp));
2384
2385 if (if_getflags(ifp) & IFF_PPROMISC) {
2386
2387 axgbe_printf(1, "User requested to enter promisc mode\n");
2388
2389 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2390 axgbe_printf(1, "Already in promisc mode\n");
2391 return (0);
2392 }
2393
2394 axgbe_printf(1, "Entering promisc mode\n");
2395 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2396 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2397 } else {
2398
2399 axgbe_printf(1, "User requested to leave promisc mode\n");
2400
2401 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2402 axgbe_printf(1, "Already not in promisc mode\n");
2403 return (0);
2404 }
2405
2406 axgbe_printf(1, "Leaving promisc mode\n");
2407 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2408 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2409 }
2410
2411 return (0);
2412 }
2413
2414 static uint64_t
axgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)2415 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2416 {
2417 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2418 if_t ifp = iflib_get_ifp(ctx);
2419 struct xgbe_prv_data *pdata = &sc->pdata;
2420 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2421
2422 pdata->hw_if.read_mmc_stats(pdata);
2423
2424 switch(cnt) {
2425 case IFCOUNTER_IPACKETS:
2426 return (pstats->rxframecount_gb);
2427 case IFCOUNTER_IERRORS:
2428 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2429 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2430 case IFCOUNTER_OPACKETS:
2431 return (pstats->txframecount_gb);
2432 case IFCOUNTER_OERRORS:
2433 return (pstats->txframecount_gb - pstats->txframecount_g);
2434 case IFCOUNTER_IBYTES:
2435 return (pstats->rxoctetcount_gb);
2436 case IFCOUNTER_OBYTES:
2437 return (pstats->txoctetcount_gb);
2438 default:
2439 return (if_get_counter_default(ifp, cnt));
2440 }
2441 }
2442
2443 static int
axgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)2444 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2445 {
2446 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2447 struct xgbe_prv_data *pdata = &sc->pdata;
2448 int ret;
2449
2450 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2451 return (EINVAL);
2452
2453 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2454 pdata->rx_buf_size = ret;
2455 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2456
2457 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2458 return (0);
2459 }
2460
2461 static void
axgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2462 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2463 {
2464 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2465 struct xgbe_prv_data *pdata = &sc->pdata;
2466
2467 ifmr->ifm_status = IFM_AVALID;
2468 if (!sc->pdata.phy.link)
2469 return;
2470
2471 ifmr->ifm_active = IFM_ETHER;
2472 ifmr->ifm_status |= IFM_ACTIVE;
2473
2474 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2475 pdata->phy_if.phy_impl.cur_mode(pdata));
2476 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2477
2478 ifmr->ifm_active |= IFM_FDX;
2479 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2480 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2481 }
2482