1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Advanced Micro Devices, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Contact Information : 28 * Rajesh Kumar <rajesh1.kumar@amd.com> 29 * Shreyank Amartya <Shreyank.Amartya@amd.com> 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/systm.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include "xgbe.h" 54 #include "xgbe-common.h" 55 56 #include "miibus_if.h" 57 #include "ifdi_if.h" 58 #include "opt_inet.h" 59 #include "opt_inet6.h" 60 61 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data"); 62 63 extern struct if_txrx axgbe_txrx; 64 static int axgbe_sph_enable; 65 66 /* Function prototypes */ 67 static void *axgbe_register(device_t); 68 static int axgbe_if_attach_pre(if_ctx_t); 69 static int axgbe_if_attach_post(if_ctx_t); 70 static int axgbe_if_detach(if_ctx_t); 71 static void axgbe_if_stop(if_ctx_t); 72 static void axgbe_if_init(if_ctx_t); 73 74 /* Queue related routines */ 75 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 76 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 77 static int axgbe_alloc_channels(if_ctx_t); 78 static void axgbe_free_channels(struct axgbe_if_softc *); 79 static void axgbe_if_queues_free(if_ctx_t); 80 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 81 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 82 83 /* Interrupt related routines */ 84 static void axgbe_if_disable_intr(if_ctx_t); 85 static void axgbe_if_enable_intr(if_ctx_t); 86 static int axgbe_if_msix_intr_assign(if_ctx_t, int); 87 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int); 88 89 /* Init and Iflib routines */ 90 static void axgbe_pci_init(struct xgbe_prv_data *); 91 static void axgbe_pci_stop(if_ctx_t); 92 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *); 93 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *); 94 static int axgbe_if_mtu_set(if_ctx_t, uint32_t); 95 static void axgbe_if_update_admin_status(if_ctx_t); 96 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *); 97 static int axgbe_if_media_change(if_ctx_t); 98 static int axgbe_if_promisc_set(if_ctx_t, int); 99 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter); 100 static void axgbe_if_vlan_register(if_ctx_t, uint16_t); 101 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t); 102 #if __FreeBSD_version >= 1300000 103 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event); 104 #endif 105 static void axgbe_set_counts(if_ctx_t); 106 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *); 107 108 /* MII interface registered functions */ 109 static int axgbe_miibus_readreg(device_t, int, int); 110 static int axgbe_miibus_writereg(device_t, int, int, int); 111 static void axgbe_miibus_statchg(device_t); 112 113 /* ISR routines */ 114 static int axgbe_dev_isr(void *); 115 static void axgbe_ecc_isr(void *); 116 static void axgbe_i2c_isr(void *); 117 static void axgbe_an_isr(void *); 118 static int axgbe_msix_que(void *); 119 120 /* Timer routines */ 121 static void xgbe_service(void *, int); 122 static void xgbe_service_timer(void *); 123 static void xgbe_init_timers(struct xgbe_prv_data *); 124 static void xgbe_stop_timers(struct xgbe_prv_data *); 125 126 /* Dump routines */ 127 static void xgbe_dump_prop_registers(struct xgbe_prv_data *); 128 129 /* 130 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the 131 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X 132 * table. 133 */ 134 static struct resource_spec axgbe_pci_mac_spec[] = { 135 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */ 136 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */ 137 { -1, 0 } 138 }; 139 140 static pci_vendor_info_t axgbe_vendor_info_array[] = 141 { 142 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"), 143 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"), 144 PVID_END 145 }; 146 147 static struct xgbe_version_data xgbe_v2a = { 148 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2, 149 .xpcs_access = XGBE_XPCS_ACCESS_V2, 150 .mmc_64bit = 1, 151 .tx_max_fifo_size = 229376, 152 .rx_max_fifo_size = 229376, 153 .tx_tstamp_workaround = 1, 154 .ecc_support = 1, 155 .i2c_support = 1, 156 .irq_reissue_support = 1, 157 .tx_desc_prefetch = 5, 158 .rx_desc_prefetch = 5, 159 .an_cdr_workaround = 1, 160 }; 161 162 static struct xgbe_version_data xgbe_v2b = { 163 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2, 164 .xpcs_access = XGBE_XPCS_ACCESS_V2, 165 .mmc_64bit = 1, 166 .tx_max_fifo_size = 65536, 167 .rx_max_fifo_size = 65536, 168 .tx_tstamp_workaround = 1, 169 .ecc_support = 1, 170 .i2c_support = 1, 171 .irq_reissue_support = 1, 172 .tx_desc_prefetch = 5, 173 .rx_desc_prefetch = 5, 174 .an_cdr_workaround = 1, 175 }; 176 177 /* Device Interface */ 178 static device_method_t ax_methods[] = { 179 DEVMETHOD(device_register, axgbe_register), 180 DEVMETHOD(device_probe, iflib_device_probe), 181 DEVMETHOD(device_attach, iflib_device_attach), 182 DEVMETHOD(device_detach, iflib_device_detach), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg), 186 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg), 187 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg), 188 189 DEVMETHOD_END 190 }; 191 192 static driver_t ax_driver = { 193 "ax", ax_methods, sizeof(struct axgbe_if_softc), 194 }; 195 196 DRIVER_MODULE(axp, pci, ax_driver, 0, 0); 197 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0); 198 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array); 199 200 MODULE_DEPEND(ax, pci, 1, 1, 1); 201 MODULE_DEPEND(ax, ether, 1, 1, 1); 202 MODULE_DEPEND(ax, iflib, 1, 1, 1); 203 MODULE_DEPEND(ax, miibus, 1, 1, 1); 204 205 /* Iflib Interface */ 206 static device_method_t axgbe_if_methods[] = { 207 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre), 208 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post), 209 DEVMETHOD(ifdi_detach, axgbe_if_detach), 210 DEVMETHOD(ifdi_init, axgbe_if_init), 211 DEVMETHOD(ifdi_stop, axgbe_if_stop), 212 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign), 213 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr), 214 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr), 215 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable), 216 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable), 217 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc), 218 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc), 219 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free), 220 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status), 221 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set), 222 DEVMETHOD(ifdi_media_status, axgbe_if_media_status), 223 DEVMETHOD(ifdi_media_change, axgbe_if_media_change), 224 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set), 225 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter), 226 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register), 227 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister), 228 #if __FreeBSD_version >= 1300000 229 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart), 230 #endif 231 DEVMETHOD_END 232 }; 233 234 static driver_t axgbe_if_driver = { 235 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc) 236 }; 237 238 /* Iflib Shared Context */ 239 static struct if_shared_ctx axgbe_sctx_init = { 240 .isc_magic = IFLIB_MAGIC, 241 .isc_driver = &axgbe_if_driver, 242 .isc_q_align = PAGE_SIZE, 243 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header), 244 .isc_tx_maxsegsize = PAGE_SIZE, 245 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header), 246 .isc_tso_maxsegsize = PAGE_SIZE, 247 .isc_rx_maxsize = MJUM9BYTES, 248 .isc_rx_maxsegsize = MJUM9BYTES, 249 .isc_rx_nsegments = 1, 250 .isc_admin_intrcnt = 4, 251 252 .isc_vendor_info = axgbe_vendor_info_array, 253 .isc_driver_version = XGBE_DRV_VERSION, 254 255 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN}, 256 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT}, 257 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX}, 258 259 .isc_ntxqs = 1, 260 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH | 261 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD, 262 }; 263 264 static void * 265 axgbe_register(device_t dev) 266 { 267 int axgbe_nfl; 268 int axgbe_nrxqs; 269 int error, i; 270 char *value = NULL; 271 272 value = kern_getenv("dev.ax.sph_enable"); 273 if (value) { 274 axgbe_sph_enable = strtol(value, NULL, 10); 275 freeenv(value); 276 } else { 277 /* 278 * No tunable found, generate one with default values 279 * Note: only a reboot will reveal the new kenv 280 */ 281 error = kern_setenv("dev.ax.sph_enable", "1"); 282 if (error) { 283 printf("Error setting tunable, using default driver values\n"); 284 } 285 axgbe_sph_enable = 1; 286 } 287 288 if (!axgbe_sph_enable) { 289 axgbe_nfl = 1; 290 axgbe_nrxqs = 1; 291 } else { 292 axgbe_nfl = 2; 293 axgbe_nrxqs = 2; 294 } 295 296 axgbe_sctx_init.isc_nfl = axgbe_nfl; 297 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs; 298 299 for (i = 0 ; i < axgbe_nrxqs ; i++) { 300 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN; 301 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT; 302 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX; 303 } 304 305 return (&axgbe_sctx_init); 306 } 307 308 /* MII Interface Functions */ 309 static int 310 axgbe_miibus_readreg(device_t dev, int phy, int reg) 311 { 312 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev)); 313 struct xgbe_prv_data *pdata = &sc->pdata; 314 int val; 315 316 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg); 317 318 val = xgbe_phy_mii_read(pdata, phy, reg); 319 320 axgbe_printf(2, "%s: val 0x%x\n", __func__, val); 321 return (val & 0xFFFF); 322 } 323 324 static int 325 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val) 326 { 327 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev)); 328 struct xgbe_prv_data *pdata = &sc->pdata; 329 330 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val); 331 332 xgbe_phy_mii_write(pdata, phy, reg, val); 333 334 return(0); 335 } 336 337 static void 338 axgbe_miibus_statchg(device_t dev) 339 { 340 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev)); 341 struct xgbe_prv_data *pdata = &sc->pdata; 342 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus); 343 if_t ifp = pdata->netdev; 344 int bmsr; 345 346 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link, 347 pdata->phy_link); 348 349 if (mii == NULL || ifp == NULL || 350 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 351 return; 352 353 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 354 (IFM_ACTIVE | IFM_AVALID)) { 355 356 switch (IFM_SUBTYPE(mii->mii_media_active)) { 357 case IFM_10_T: 358 case IFM_100_TX: 359 pdata->phy.link = 1; 360 break; 361 case IFM_1000_T: 362 case IFM_1000_SX: 363 case IFM_2500_SX: 364 pdata->phy.link = 1; 365 break; 366 default: 367 pdata->phy.link = 0; 368 break; 369 } 370 } else 371 pdata->phy_link = 0; 372 373 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR); 374 if (bmsr & BMSR_ANEG) { 375 376 axgbe_printf(2, "%s: Autoneg Done\n", __func__); 377 378 /* Raise AN Interrupt */ 379 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 380 XGBE_AN_CL73_INT_MASK); 381 } 382 } 383 384 static int 385 axgbe_if_attach_pre(if_ctx_t ctx) 386 { 387 struct axgbe_if_softc *sc; 388 struct xgbe_prv_data *pdata; 389 struct resource *mac_res[2]; 390 if_softc_ctx_t scctx; 391 if_shared_ctx_t sctx; 392 device_t dev; 393 unsigned int ma_lo, ma_hi; 394 unsigned int reg; 395 int ret; 396 397 sc = iflib_get_softc(ctx); 398 sc->pdata.dev = dev = iflib_get_dev(ctx); 399 sc->sctx = sctx = iflib_get_sctx(ctx); 400 sc->scctx = scctx = iflib_get_softc_ctx(ctx); 401 sc->media = iflib_get_media(ctx); 402 sc->ctx = ctx; 403 sc->link_status = LINK_STATE_DOWN; 404 pdata = &sc->pdata; 405 pdata->netdev = iflib_get_ifp(ctx); 406 407 spin_lock_init(&pdata->xpcs_lock); 408 409 /* Initialize locks */ 410 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF); 411 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN); 412 413 /* Allocate VLAN bitmap */ 414 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO); 415 pdata->num_active_vlans = 0; 416 417 /* Get the version data */ 418 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev)); 419 if (pci_get_device(dev) == 0x1458) 420 sc->pdata.vdata = &xgbe_v2a; 421 else if (pci_get_device(dev) == 0x1459) 422 sc->pdata.vdata = &xgbe_v2b; 423 424 /* PCI setup */ 425 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) { 426 axgbe_error("Unable to allocate bus resources\n"); 427 ret = ENXIO; 428 goto free_vlans; 429 } 430 431 sc->pdata.xgmac_res = mac_res[0]; 432 sc->pdata.xpcs_res = mac_res[1]; 433 434 /* Set the PCS indirect addressing definition registers*/ 435 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 436 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 437 438 /* Configure the PCS indirect addressing support */ 439 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 440 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 441 pdata->xpcs_window <<= 6; 442 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 443 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 444 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 445 DBGPR("xpcs window def : %#010x\n", 446 pdata->xpcs_window_def_reg); 447 DBGPR("xpcs window sel : %#010x\n", 448 pdata->xpcs_window_sel_reg); 449 DBGPR("xpcs window : %#010x\n", 450 pdata->xpcs_window); 451 DBGPR("xpcs window size : %#010x\n", 452 pdata->xpcs_window_size); 453 DBGPR("xpcs window mask : %#010x\n", 454 pdata->xpcs_window_mask); 455 456 /* Enable all interrupts in the hardware */ 457 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 458 459 /* Retrieve the MAC address */ 460 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 461 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 462 pdata->mac_addr[0] = ma_lo & 0xff; 463 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff; 464 pdata->mac_addr[2] = (ma_lo >>16) & 0xff; 465 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff; 466 pdata->mac_addr[4] = ma_hi & 0xff; 467 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff; 468 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) { 469 axgbe_error("Invalid mac address\n"); 470 ret = EINVAL; 471 goto release_bus_resource; 472 } 473 iflib_set_mac(ctx, pdata->mac_addr); 474 475 /* Clock settings */ 476 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ; 477 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ; 478 479 /* Set the DMA coherency values */ 480 pdata->coherent = 1; 481 pdata->arcr = XGBE_DMA_PCI_ARCR; 482 pdata->awcr = XGBE_DMA_PCI_AWCR; 483 pdata->awarcr = XGBE_DMA_PCI_AWARCR; 484 485 /* Read the port property registers */ 486 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0); 487 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1); 488 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2); 489 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3); 490 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4); 491 DBGPR("port property 0 = %#010x\n", pdata->pp0); 492 DBGPR("port property 1 = %#010x\n", pdata->pp1); 493 DBGPR("port property 2 = %#010x\n", pdata->pp2); 494 DBGPR("port property 3 = %#010x\n", pdata->pp3); 495 DBGPR("port property 4 = %#010x\n", pdata->pp4); 496 497 /* Set the maximum channels and queues */ 498 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 499 MAX_TX_DMA); 500 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 501 MAX_RX_DMA); 502 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 503 MAX_TX_QUEUES); 504 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 505 MAX_RX_QUEUES); 506 DBGPR("max tx/rx channel count = %u/%u\n", 507 pdata->tx_max_channel_count, pdata->rx_max_channel_count); 508 DBGPR("max tx/rx hw queue count = %u/%u\n", 509 pdata->tx_max_q_count, pdata->rx_max_q_count); 510 511 axgbe_set_counts(ctx); 512 513 /* Set the maximum fifo amounts */ 514 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, 515 TX_FIFO_SIZE); 516 pdata->tx_max_fifo_size *= 16384; 517 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size, 518 pdata->vdata->tx_max_fifo_size); 519 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, 520 RX_FIFO_SIZE); 521 pdata->rx_max_fifo_size *= 16384; 522 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size, 523 pdata->vdata->rx_max_fifo_size); 524 DBGPR("max tx/rx max fifo size = %u/%u\n", 525 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size); 526 527 /* Initialize IFLIB if_softc_ctx_t */ 528 axgbe_init_iflib_softc_ctx(sc); 529 530 /* Alloc channels */ 531 if (axgbe_alloc_channels(ctx)) { 532 axgbe_error("Unable to allocate channel memory\n"); 533 ret = ENOMEM; 534 goto release_bus_resource; 535 } 536 537 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata); 538 539 /* create the workqueue */ 540 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK, 541 taskqueue_thread_enqueue, &pdata->dev_workqueue); 542 if (pdata->dev_workqueue == NULL) { 543 axgbe_error("Unable to allocate workqueue\n"); 544 ret = ENOMEM; 545 goto free_channels; 546 } 547 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET, 548 "axgbe dev taskq"); 549 if (ret) { 550 axgbe_error("Unable to start taskqueue\n"); 551 ret = ENOMEM; 552 goto free_task_queue; 553 } 554 555 /* Init timers */ 556 xgbe_init_timers(pdata); 557 558 return (0); 559 560 free_task_queue: 561 taskqueue_free(pdata->dev_workqueue); 562 563 free_channels: 564 axgbe_free_channels(sc); 565 566 release_bus_resource: 567 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res); 568 569 free_vlans: 570 free(pdata->active_vlans, M_AXGBE); 571 572 return (ret); 573 } /* axgbe_if_attach_pre */ 574 575 static void 576 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata) 577 { 578 xgbe_init_function_ptrs_dev(&pdata->hw_if); 579 xgbe_init_function_ptrs_phy(&pdata->phy_if); 580 xgbe_init_function_ptrs_i2c(&pdata->i2c_if); 581 xgbe_init_function_ptrs_desc(&pdata->desc_if); 582 583 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 584 } 585 586 static void 587 axgbe_set_counts(if_ctx_t ctx) 588 { 589 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 590 struct xgbe_prv_data *pdata = &sc->pdata; 591 cpuset_t lcpus; 592 int cpu_count, err; 593 size_t len; 594 595 /* Set all function pointers */ 596 xgbe_init_all_fptrs(pdata); 597 598 /* Populate the hardware features */ 599 xgbe_get_all_hw_features(pdata); 600 601 if (!pdata->tx_max_channel_count) 602 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 603 if (!pdata->rx_max_channel_count) 604 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 605 606 if (!pdata->tx_max_q_count) 607 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 608 if (!pdata->rx_max_q_count) 609 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 610 611 /* 612 * Calculate the number of Tx and Rx rings to be created 613 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 614 * the number of Tx queues to the number of Tx channels 615 * enabled 616 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 617 * number of Rx queues or maximum allowed 618 */ 619 620 /* Get cpu count from sysctl */ 621 len = sizeof(cpu_count); 622 err = kernel_sysctlbyname(curthread, "hw.ncpu", &cpu_count, &len, NULL, 623 0, NULL, 0); 624 if (err) { 625 axgbe_error("Unable to fetch number of cpus\n"); 626 cpu_count = 1; 627 } 628 629 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) { 630 axgbe_error("Unable to fetch CPU list\n"); 631 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */ 632 } 633 634 DBGPR("ncpu %d intrcpu %d\n", cpu_count, CPU_COUNT(&lcpus)); 635 636 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt); 637 pdata->tx_ring_count = min(pdata->tx_ring_count, 638 pdata->tx_max_channel_count); 639 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count); 640 641 pdata->tx_q_count = pdata->tx_ring_count; 642 643 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt); 644 pdata->rx_ring_count = min(pdata->rx_ring_count, 645 pdata->rx_max_channel_count); 646 647 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count); 648 649 DBGPR("TX/RX max channel count = %u/%u\n", 650 pdata->tx_max_channel_count, pdata->rx_max_channel_count); 651 DBGPR("TX/RX max queue count = %u/%u\n", 652 pdata->tx_max_q_count, pdata->rx_max_q_count); 653 DBGPR("TX/RX DMA ring count = %u/%u\n", 654 pdata->tx_ring_count, pdata->rx_ring_count); 655 DBGPR("TX/RX hardware queue count = %u/%u\n", 656 pdata->tx_q_count, pdata->rx_q_count); 657 } /* axgbe_set_counts */ 658 659 static void 660 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc) 661 { 662 struct xgbe_prv_data *pdata = &sc->pdata; 663 if_softc_ctx_t scctx = sc->scctx; 664 if_shared_ctx_t sctx = sc->sctx; 665 int i; 666 667 scctx->isc_nrxqsets = pdata->rx_q_count; 668 scctx->isc_ntxqsets = pdata->tx_q_count; 669 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev); 670 scctx->isc_tx_nsegments = 32; 671 672 for (i = 0; i < sctx->isc_ntxqs; i++) { 673 scctx->isc_txqsizes[i] = 674 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc), 675 128); 676 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc); 677 } 678 679 for (i = 0; i < sctx->isc_nrxqs; i++) { 680 scctx->isc_rxqsizes[i] = 681 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc), 682 128); 683 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc); 684 } 685 686 scctx->isc_tx_tso_segments_max = 32; 687 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE; 688 scctx->isc_tx_tso_segsize_max = PAGE_SIZE; 689 690 /* 691 * Set capabilities 692 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly 693 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in 694 * IFCAP_HWCSUM) is set 695 */ 696 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP | 697 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 | 698 CSUM_TSO); 699 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | 700 IFCAP_JUMBO_MTU | 701 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 702 IFCAP_VLAN_HWCSUM | 703 IFCAP_TSO | IFCAP_VLAN_HWTSO); 704 scctx->isc_capabilities = scctx->isc_capenable; 705 706 /* 707 * Set rss_table_size alone when adding RSS support. rss_table_mask 708 * will be set by IFLIB based on rss_table_size 709 */ 710 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE; 711 712 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES; 713 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES; 714 715 scctx->isc_txrx = &axgbe_txrx; 716 } 717 718 static int 719 axgbe_alloc_channels(if_ctx_t ctx) 720 { 721 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 722 struct xgbe_prv_data *pdata = &sc->pdata; 723 struct xgbe_channel *channel; 724 int i, j, count; 725 726 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count, 727 pdata->rx_ring_count); 728 729 /* Iflibe sets based on isc_ntxqsets/nrxqsets */ 730 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 731 732 /* Allocate channel memory */ 733 for (i = 0; i < count ; i++) { 734 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel), 735 M_AXGBE, M_NOWAIT | M_ZERO); 736 737 if (channel == NULL) { 738 for (j = 0; j < i; j++) { 739 free(pdata->channel[j], M_AXGBE); 740 pdata->channel[j] = NULL; 741 } 742 return (ENOMEM); 743 } 744 745 pdata->channel[i] = channel; 746 } 747 748 pdata->total_channel_count = count; 749 DBGPR("Channel count set to: %u\n", pdata->total_channel_count); 750 751 for (i = 0; i < count; i++) { 752 753 channel = pdata->channel[i]; 754 snprintf(channel->name, sizeof(channel->name), "channel-%d",i); 755 756 channel->pdata = pdata; 757 channel->queue_index = i; 758 channel->dma_tag = rman_get_bustag(pdata->xgmac_res); 759 bus_space_subregion(channel->dma_tag, 760 rman_get_bushandle(pdata->xgmac_res), 761 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC, 762 &channel->dma_handle); 763 channel->tx_ring = NULL; 764 channel->rx_ring = NULL; 765 } 766 767 return (0); 768 } /* axgbe_alloc_channels */ 769 770 static void 771 axgbe_free_channels(struct axgbe_if_softc *sc) 772 { 773 struct xgbe_prv_data *pdata = &sc->pdata; 774 int i; 775 776 for (i = 0; i < pdata->total_channel_count ; i++) { 777 free(pdata->channel[i], M_AXGBE); 778 pdata->channel[i] = NULL; 779 } 780 781 pdata->total_channel_count = 0; 782 pdata->channel_count = 0; 783 } 784 785 static void 786 xgbe_service(void *ctx, int pending) 787 { 788 struct xgbe_prv_data *pdata = ctx; 789 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata; 790 bool prev_state = false; 791 792 /* Get previous link status */ 793 prev_state = pdata->phy.link; 794 795 pdata->phy_if.phy_status(pdata); 796 797 if (prev_state != pdata->phy.link) { 798 pdata->phy_link = pdata->phy.link; 799 axgbe_if_update_admin_status(sc->ctx); 800 } 801 802 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata); 803 } 804 805 static void 806 xgbe_service_timer(void *data) 807 { 808 struct xgbe_prv_data *pdata = data; 809 810 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work); 811 } 812 813 static void 814 xgbe_init_timers(struct xgbe_prv_data *pdata) 815 { 816 callout_init(&pdata->service_timer, 1); 817 } 818 819 static void 820 xgbe_start_timers(struct xgbe_prv_data *pdata) 821 { 822 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata); 823 } 824 825 static void 826 xgbe_stop_timers(struct xgbe_prv_data *pdata) 827 { 828 callout_drain(&pdata->service_timer); 829 callout_stop(&pdata->service_timer); 830 } 831 832 static void 833 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 834 { 835 axgbe_printf(1, "\n************* PHY Reg dump *********************\n"); 836 837 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 838 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 839 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 840 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 841 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, 842 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 843 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, 844 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 845 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, 846 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 847 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, 848 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 849 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 850 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 851 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 852 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 853 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", 854 MDIO_AN_ADVERTISE, 855 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 856 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", 857 MDIO_AN_ADVERTISE + 1, 858 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 859 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", 860 MDIO_AN_ADVERTISE + 2, 861 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 862 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n", 863 MDIO_AN_COMP_STAT, 864 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 865 866 axgbe_printf(1, "\n************************************************\n"); 867 } 868 869 static void 870 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata) 871 { 872 int i; 873 874 axgbe_printf(1, "\n************* PROP Reg dump ********************\n"); 875 876 for (i = 0 ; i < 38 ; i++) { 877 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n", 878 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata, 879 (XP_PROP_0 + (i * 4)))); 880 } 881 } 882 883 static void 884 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch) 885 { 886 struct xgbe_channel *channel; 887 int i; 888 889 axgbe_printf(1, "\n************* DMA Reg dump *********************\n"); 890 891 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR, 892 XGMAC_IOREAD(pdata, DMA_MR)); 893 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR, 894 XGMAC_IOREAD(pdata, DMA_SBMR)); 895 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR, 896 XGMAC_IOREAD(pdata, DMA_ISR)); 897 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR, 898 XGMAC_IOREAD(pdata, DMA_AXIARCR)); 899 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR, 900 XGMAC_IOREAD(pdata, DMA_AXIAWCR)); 901 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR, 902 XGMAC_IOREAD(pdata, DMA_AXIAWARCR)); 903 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0, 904 XGMAC_IOREAD(pdata, DMA_DSR0)); 905 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1, 906 XGMAC_IOREAD(pdata, DMA_DSR1)); 907 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2, 908 XGMAC_IOREAD(pdata, DMA_DSR2)); 909 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3, 910 XGMAC_IOREAD(pdata, DMA_DSR3)); 911 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4, 912 XGMAC_IOREAD(pdata, DMA_DSR4)); 913 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR, 914 XGMAC_IOREAD(pdata, DMA_TXEDMACR)); 915 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR, 916 XGMAC_IOREAD(pdata, DMA_RXEDMACR)); 917 918 for (i = 0 ; i < 8 ; i++ ) { 919 920 if (ch >= 0) { 921 if (i != ch) 922 continue; 923 } 924 925 channel = pdata->channel[i]; 926 927 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i); 928 929 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n", 930 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR)); 931 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n", 932 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR)); 933 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n", 934 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR)); 935 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n", 936 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI)); 937 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n", 938 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO)); 939 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n", 940 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI)); 941 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n", 942 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO)); 943 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n", 944 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO)); 945 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n", 946 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO)); 947 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n", 948 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR)); 949 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n", 950 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR)); 951 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n", 952 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER)); 953 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n", 954 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT)); 955 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n", 956 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO)); 957 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n", 958 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO)); 959 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n", 960 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI)); 961 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n", 962 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO)); 963 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n", 964 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI)); 965 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n", 966 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO)); 967 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n", 968 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 969 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n", 970 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR)); 971 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n", 972 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL)); 973 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n", 974 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC)); 975 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n", 976 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO)); 977 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n", 978 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO)); 979 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n", 980 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO)); 981 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n", 982 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO)); 983 } 984 } 985 986 static void 987 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata) 988 { 989 int i; 990 991 axgbe_printf(1, "\n************* MTL Reg dump *********************\n"); 992 993 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR, 994 XGMAC_IOREAD(pdata, MTL_OMR)); 995 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR, 996 XGMAC_IOREAD(pdata, MTL_FDCR)); 997 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR, 998 XGMAC_IOREAD(pdata, MTL_FDSR)); 999 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR, 1000 XGMAC_IOREAD(pdata, MTL_FDDR)); 1001 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR, 1002 XGMAC_IOREAD(pdata, MTL_ISR)); 1003 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R, 1004 XGMAC_IOREAD(pdata, MTL_RQDCM0R)); 1005 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R, 1006 XGMAC_IOREAD(pdata, MTL_RQDCM1R)); 1007 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R, 1008 XGMAC_IOREAD(pdata, MTL_RQDCM2R)); 1009 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R, 1010 XGMAC_IOREAD(pdata, MTL_TCPM0R)); 1011 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R, 1012 XGMAC_IOREAD(pdata, MTL_TCPM1R)); 1013 1014 for (i = 0 ; i < 8 ; i++ ) { 1015 1016 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i); 1017 1018 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n", 1019 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR)); 1020 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n", 1021 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR)); 1022 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n", 1023 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR)); 1024 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n", 1025 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR)); 1026 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n", 1027 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR)); 1028 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n", 1029 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR)); 1030 1031 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n", 1032 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR)); 1033 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n", 1034 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR)); 1035 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n", 1036 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR)); 1037 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n", 1038 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR)); 1039 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n", 1040 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR)); 1041 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n", 1042 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER)); 1043 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n", 1044 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR)); 1045 } 1046 } 1047 1048 static void 1049 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata) 1050 { 1051 axgbe_printf(1, "\n************* MAC Reg dump **********************\n"); 1052 1053 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR, 1054 XGMAC_IOREAD(pdata, MAC_TCR)); 1055 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR, 1056 XGMAC_IOREAD(pdata, MAC_RCR)); 1057 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR, 1058 XGMAC_IOREAD(pdata, MAC_PFR)); 1059 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR, 1060 XGMAC_IOREAD(pdata, MAC_WTR)); 1061 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0, 1062 XGMAC_IOREAD(pdata, MAC_HTR0)); 1063 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1, 1064 XGMAC_IOREAD(pdata, MAC_HTR1)); 1065 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2, 1066 XGMAC_IOREAD(pdata, MAC_HTR2)); 1067 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3, 1068 XGMAC_IOREAD(pdata, MAC_HTR3)); 1069 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4, 1070 XGMAC_IOREAD(pdata, MAC_HTR4)); 1071 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5, 1072 XGMAC_IOREAD(pdata, MAC_HTR5)); 1073 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6, 1074 XGMAC_IOREAD(pdata, MAC_HTR6)); 1075 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7, 1076 XGMAC_IOREAD(pdata, MAC_HTR7)); 1077 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR, 1078 XGMAC_IOREAD(pdata, MAC_VLANTR)); 1079 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR, 1080 XGMAC_IOREAD(pdata, MAC_VLANHTR)); 1081 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR, 1082 XGMAC_IOREAD(pdata, MAC_VLANIR)); 1083 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR, 1084 XGMAC_IOREAD(pdata, MAC_IVLANIR)); 1085 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR, 1086 XGMAC_IOREAD(pdata, MAC_RETMR)); 1087 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR, 1088 XGMAC_IOREAD(pdata, MAC_Q0TFCR)); 1089 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR, 1090 XGMAC_IOREAD(pdata, MAC_Q1TFCR)); 1091 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR, 1092 XGMAC_IOREAD(pdata, MAC_Q2TFCR)); 1093 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR, 1094 XGMAC_IOREAD(pdata, MAC_Q3TFCR)); 1095 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR, 1096 XGMAC_IOREAD(pdata, MAC_Q4TFCR)); 1097 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR, 1098 XGMAC_IOREAD(pdata, MAC_Q5TFCR)); 1099 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR, 1100 XGMAC_IOREAD(pdata, MAC_Q6TFCR)); 1101 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR, 1102 XGMAC_IOREAD(pdata, MAC_Q7TFCR)); 1103 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR, 1104 XGMAC_IOREAD(pdata, MAC_RFCR)); 1105 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R, 1106 XGMAC_IOREAD(pdata, MAC_RQC0R)); 1107 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R, 1108 XGMAC_IOREAD(pdata, MAC_RQC1R)); 1109 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R, 1110 XGMAC_IOREAD(pdata, MAC_RQC2R)); 1111 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R, 1112 XGMAC_IOREAD(pdata, MAC_RQC3R)); 1113 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR, 1114 XGMAC_IOREAD(pdata, MAC_ISR)); 1115 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER, 1116 XGMAC_IOREAD(pdata, MAC_IER)); 1117 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR, 1118 XGMAC_IOREAD(pdata, MAC_RTSR)); 1119 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR, 1120 XGMAC_IOREAD(pdata, MAC_PMTCSR)); 1121 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR, 1122 XGMAC_IOREAD(pdata, MAC_RWKPFR)); 1123 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR, 1124 XGMAC_IOREAD(pdata, MAC_LPICSR)); 1125 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR, 1126 XGMAC_IOREAD(pdata, MAC_LPITCR)); 1127 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR, 1128 XGMAC_IOREAD(pdata, MAC_TIR)); 1129 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR, 1130 XGMAC_IOREAD(pdata, MAC_VR)); 1131 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR, 1132 XGMAC_IOREAD(pdata, MAC_DR)); 1133 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R, 1134 XGMAC_IOREAD(pdata, MAC_HWF0R)); 1135 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R, 1136 XGMAC_IOREAD(pdata, MAC_HWF1R)); 1137 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R, 1138 XGMAC_IOREAD(pdata, MAC_HWF2R)); 1139 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR, 1140 XGMAC_IOREAD(pdata, MAC_MDIOSCAR)); 1141 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR, 1142 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR)); 1143 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR, 1144 XGMAC_IOREAD(pdata, MAC_MDIOISR)); 1145 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER, 1146 XGMAC_IOREAD(pdata, MAC_MDIOIER)); 1147 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R, 1148 XGMAC_IOREAD(pdata, MAC_MDIOCL22R)); 1149 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR, 1150 XGMAC_IOREAD(pdata, MAC_GPIOCR)); 1151 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR, 1152 XGMAC_IOREAD(pdata, MAC_GPIOSR)); 1153 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR, 1154 XGMAC_IOREAD(pdata, MAC_MACA0HR)); 1155 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR, 1156 XGMAC_IOREAD(pdata, MAC_MACA0LR)); 1157 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR, 1158 XGMAC_IOREAD(pdata, MAC_MACA1HR)); 1159 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR, 1160 XGMAC_IOREAD(pdata, MAC_MACA1LR)); 1161 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR, 1162 XGMAC_IOREAD(pdata, MAC_RSSCR)); 1163 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR, 1164 XGMAC_IOREAD(pdata, MAC_RSSDR)); 1165 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR, 1166 XGMAC_IOREAD(pdata, MAC_RSSAR)); 1167 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR, 1168 XGMAC_IOREAD(pdata, MAC_TSCR)); 1169 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR, 1170 XGMAC_IOREAD(pdata, MAC_SSIR)); 1171 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR, 1172 XGMAC_IOREAD(pdata, MAC_STSR)); 1173 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR, 1174 XGMAC_IOREAD(pdata, MAC_STNR)); 1175 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR, 1176 XGMAC_IOREAD(pdata, MAC_STSUR)); 1177 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR, 1178 XGMAC_IOREAD(pdata, MAC_STNUR)); 1179 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR, 1180 XGMAC_IOREAD(pdata, MAC_TSAR)); 1181 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR, 1182 XGMAC_IOREAD(pdata, MAC_TSSR)); 1183 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR, 1184 XGMAC_IOREAD(pdata, MAC_TXSNR)); 1185 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR, 1186 XGMAC_IOREAD(pdata, MAC_TXSSR)); 1187 } 1188 1189 static void 1190 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata) 1191 { 1192 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 1193 1194 axgbe_printf(1, "\n************* RMON counters dump ***************\n"); 1195 1196 pdata->hw_if.read_mmc_stats(pdata); 1197 1198 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n", 1199 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb); 1200 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n", 1201 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb); 1202 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n", 1203 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g); 1204 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n", 1205 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g); 1206 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n", 1207 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb); 1208 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n", 1209 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb); 1210 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n", 1211 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb); 1212 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n", 1213 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb); 1214 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n", 1215 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb); 1216 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n", 1217 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb); 1218 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n", 1219 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb); 1220 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n", 1221 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb); 1222 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n", 1223 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb); 1224 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n", 1225 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror); 1226 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n", 1227 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g); 1228 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n", 1229 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g); 1230 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n", 1231 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes); 1232 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n", 1233 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g); 1234 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n", 1235 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb); 1236 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n", 1237 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb); 1238 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n", 1239 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g); 1240 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n", 1241 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g); 1242 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n", 1243 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g); 1244 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n", 1245 MMC_RXCRCERROR_LO, stats->rxcrcerror); 1246 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n", 1247 MMC_RXRUNTERROR, stats->rxrunterror); 1248 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n", 1249 MMC_RXJABBERERROR, stats->rxjabbererror); 1250 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n", 1251 MMC_RXUNDERSIZE_G, stats->rxundersize_g); 1252 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n", 1253 MMC_RXOVERSIZE_G, stats->rxoversize_g); 1254 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n", 1255 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb); 1256 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n", 1257 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb); 1258 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n", 1259 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb); 1260 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n", 1261 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb); 1262 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n", 1263 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb); 1264 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n", 1265 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb); 1266 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n", 1267 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g); 1268 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n", 1269 MMC_RXLENGTHERROR_LO, stats->rxlengtherror); 1270 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n", 1271 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype); 1272 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n", 1273 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes); 1274 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n", 1275 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow); 1276 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n", 1277 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb); 1278 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n", 1279 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror); 1280 } 1281 1282 void 1283 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata) 1284 { 1285 axgbe_printf(1, "*************** I2C Registers **************\n"); 1286 axgbe_printf(1, " IC_CON : %010x\n", 1287 XI2C_IOREAD(pdata, 0x00)); 1288 axgbe_printf(1, " IC_TAR : %010x\n", 1289 XI2C_IOREAD(pdata, 0x04)); 1290 axgbe_printf(1, " IC_HS_MADDR : %010x\n", 1291 XI2C_IOREAD(pdata, 0x0c)); 1292 axgbe_printf(1, " IC_INTR_STAT : %010x\n", 1293 XI2C_IOREAD(pdata, 0x2c)); 1294 axgbe_printf(1, " IC_INTR_MASK : %010x\n", 1295 XI2C_IOREAD(pdata, 0x30)); 1296 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n", 1297 XI2C_IOREAD(pdata, 0x34)); 1298 axgbe_printf(1, " IC_RX_TL : %010x\n", 1299 XI2C_IOREAD(pdata, 0x38)); 1300 axgbe_printf(1, " IC_TX_TL : %010x\n", 1301 XI2C_IOREAD(pdata, 0x3c)); 1302 axgbe_printf(1, " IC_ENABLE : %010x\n", 1303 XI2C_IOREAD(pdata, 0x6c)); 1304 axgbe_printf(1, " IC_STATUS : %010x\n", 1305 XI2C_IOREAD(pdata, 0x70)); 1306 axgbe_printf(1, " IC_TXFLR : %010x\n", 1307 XI2C_IOREAD(pdata, 0x74)); 1308 axgbe_printf(1, " IC_RXFLR : %010x\n", 1309 XI2C_IOREAD(pdata, 0x78)); 1310 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n", 1311 XI2C_IOREAD(pdata, 0x9c)); 1312 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n", 1313 XI2C_IOREAD(pdata, 0xf4)); 1314 } 1315 1316 static void 1317 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata) 1318 { 1319 int i; 1320 1321 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) { 1322 if (i && (i%8 == 0)) 1323 axgbe_printf(1, "\n"); 1324 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]); 1325 } 1326 axgbe_printf(1, "\n"); 1327 } 1328 1329 static void 1330 xgbe_default_config(struct xgbe_prv_data *pdata) 1331 { 1332 pdata->blen = DMA_SBMR_BLEN_64; 1333 pdata->pbl = DMA_PBL_128; 1334 pdata->aal = 1; 1335 pdata->rd_osr_limit = 8; 1336 pdata->wr_osr_limit = 8; 1337 pdata->tx_sf_mode = MTL_TSF_ENABLE; 1338 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 1339 pdata->tx_osp_mode = DMA_OSP_ENABLE; 1340 pdata->rx_sf_mode = MTL_RSF_DISABLE; 1341 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 1342 pdata->pause_autoneg = 1; 1343 pdata->tx_pause = 1; 1344 pdata->rx_pause = 1; 1345 pdata->phy_speed = SPEED_UNKNOWN; 1346 pdata->power_down = 0; 1347 pdata->enable_rss = 1; 1348 } 1349 1350 static int 1351 axgbe_if_attach_post(if_ctx_t ctx) 1352 { 1353 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1354 struct xgbe_prv_data *pdata = &sc->pdata; 1355 if_t ifp = pdata->netdev; 1356 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1357 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1358 if_softc_ctx_t scctx = sc->scctx; 1359 int i, ret; 1360 1361 /* set split header support based on tunable */ 1362 pdata->sph_enable = axgbe_sph_enable; 1363 1364 /* Initialize ECC timestamps */ 1365 pdata->tx_sec_period = ticks; 1366 pdata->tx_ded_period = ticks; 1367 pdata->rx_sec_period = ticks; 1368 pdata->rx_ded_period = ticks; 1369 pdata->desc_sec_period = ticks; 1370 pdata->desc_ded_period = ticks; 1371 1372 /* Reset the hardware */ 1373 ret = hw_if->exit(&sc->pdata); 1374 if (ret) 1375 axgbe_error("%s: exit error %d\n", __func__, ret); 1376 1377 /* Configure the defaults */ 1378 xgbe_default_config(pdata); 1379 1380 /* Set default max values if not provided */ 1381 if (!pdata->tx_max_fifo_size) 1382 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 1383 if (!pdata->rx_max_fifo_size) 1384 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 1385 1386 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__, 1387 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size); 1388 1389 /* Set and validate the number of descriptors for a ring */ 1390 MPASS(powerof2(XGBE_TX_DESC_CNT)); 1391 pdata->tx_desc_count = XGBE_TX_DESC_CNT; 1392 MPASS(powerof2(XGBE_RX_DESC_CNT)); 1393 pdata->rx_desc_count = XGBE_RX_DESC_CNT; 1394 1395 /* Adjust the number of queues based on interrupts assigned */ 1396 if (pdata->channel_irq_count) { 1397 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count, 1398 pdata->channel_irq_count); 1399 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count, 1400 pdata->channel_irq_count); 1401 1402 DBGPR("adjusted TX %u/%u RX %u/%u\n", 1403 pdata->tx_ring_count, pdata->tx_q_count, 1404 pdata->rx_ring_count, pdata->rx_q_count); 1405 } 1406 1407 /* Set channel count based on interrupts assigned */ 1408 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets, 1409 scctx->isc_nrxqsets); 1410 DBGPR("Channel count set to: %u\n", pdata->channel_count); 1411 1412 /* Get RSS key */ 1413 #ifdef RSS 1414 rss_getkey((uint8_t *)pdata->rss_key); 1415 #else 1416 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0); 1417 #endif 1418 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 1419 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 1420 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 1421 1422 /* Initialize the PHY device */ 1423 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround; 1424 phy_if->phy_init(pdata); 1425 1426 /* Set the coalescing */ 1427 xgbe_init_rx_coalesce(&sc->pdata); 1428 xgbe_init_tx_coalesce(&sc->pdata); 1429 1430 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 1431 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL); 1432 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL); 1433 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1434 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 1435 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL); 1436 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1437 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1438 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL); 1439 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1440 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL); 1441 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1442 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 1443 1444 /* Initialize the phy */ 1445 pdata->phy_link = -1; 1446 pdata->phy_speed = SPEED_UNKNOWN; 1447 ret = phy_if->phy_reset(pdata); 1448 if (ret) 1449 return (ret); 1450 1451 /* Calculate the Rx buffer size before allocating rings */ 1452 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev)); 1453 pdata->rx_buf_size = ret; 1454 DBGPR("%s: rx_buf_size %d\n", __func__, ret); 1455 1456 /* Setup RSS lookup table */ 1457 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) 1458 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, 1459 i % pdata->rx_ring_count); 1460 1461 /* 1462 * Mark the device down until it is initialized, which happens 1463 * when the device is accessed first (for configuring the iface, 1464 * eg: setting IP) 1465 */ 1466 set_bit(XGBE_DOWN, &pdata->dev_state); 1467 1468 DBGPR("mtu %d\n", if_getmtu(ifp)); 1469 scctx->isc_max_frame_size = if_getmtu(ifp) + 18; 1470 scctx->isc_min_frame_size = XGMAC_MIN_PACKET; 1471 1472 axgbe_sysctl_init(pdata); 1473 1474 axgbe_pci_init(pdata); 1475 1476 return (0); 1477 } /* axgbe_if_attach_post */ 1478 1479 static void 1480 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag, 1481 int rid) 1482 { 1483 if (tag) 1484 bus_teardown_intr(pdata->dev, res, tag); 1485 1486 if (res) 1487 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res); 1488 } 1489 1490 static void 1491 axgbe_interrupts_free(if_ctx_t ctx) 1492 { 1493 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1494 struct xgbe_prv_data *pdata = &sc->pdata; 1495 if_softc_ctx_t scctx = sc->scctx; 1496 struct xgbe_channel *channel; 1497 struct if_irq irq; 1498 int i; 1499 1500 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr); 1501 1502 /* Free dev_irq */ 1503 iflib_irq_free(ctx, &pdata->dev_irq); 1504 1505 /* Free ecc_irq */ 1506 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag, 1507 pdata->ecc_rid); 1508 1509 /* Free i2c_irq */ 1510 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag, 1511 pdata->i2c_rid); 1512 1513 /* Free an_irq */ 1514 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag, 1515 pdata->an_rid); 1516 1517 for (i = 0; i < scctx->isc_nrxqsets; i++) { 1518 1519 channel = pdata->channel[i]; 1520 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid); 1521 irq.ii_res = channel->dma_irq_res; 1522 irq.ii_tag = channel->dma_irq_tag; 1523 iflib_irq_free(ctx, &irq); 1524 } 1525 } 1526 1527 static int 1528 axgbe_if_detach(if_ctx_t ctx) 1529 { 1530 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1531 struct xgbe_prv_data *pdata = &sc->pdata; 1532 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1533 struct resource *mac_res[2]; 1534 1535 mac_res[0] = pdata->xgmac_res; 1536 mac_res[1] = pdata->xpcs_res; 1537 1538 phy_if->phy_exit(pdata); 1539 1540 /* Free Interrupts */ 1541 axgbe_interrupts_free(ctx); 1542 1543 /* Free workqueues */ 1544 taskqueue_free(pdata->dev_workqueue); 1545 1546 /* Release bus resources */ 1547 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res); 1548 1549 /* Free VLAN bitmap */ 1550 free(pdata->active_vlans, M_AXGBE); 1551 1552 axgbe_sysctl_exit(pdata); 1553 1554 return (0); 1555 } /* axgbe_if_detach */ 1556 1557 static void 1558 axgbe_pci_init(struct xgbe_prv_data *pdata) 1559 { 1560 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1561 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1562 int ret = 0; 1563 1564 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) { 1565 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__); 1566 return; 1567 } 1568 1569 hw_if->init(pdata); 1570 1571 ret = phy_if->phy_start(pdata); 1572 if (ret) { 1573 axgbe_error("%s: phy start %d\n", __func__, ret); 1574 ret = hw_if->exit(pdata); 1575 if (ret) 1576 axgbe_error("%s: exit error %d\n", __func__, ret); 1577 return; 1578 } 1579 1580 hw_if->enable_tx(pdata); 1581 hw_if->enable_rx(pdata); 1582 1583 xgbe_start_timers(pdata); 1584 1585 clear_bit(XGBE_DOWN, &pdata->dev_state); 1586 1587 xgbe_dump_phy_registers(pdata); 1588 xgbe_dump_prop_registers(pdata); 1589 xgbe_dump_dma_registers(pdata, -1); 1590 xgbe_dump_mtl_registers(pdata); 1591 xgbe_dump_mac_registers(pdata); 1592 xgbe_dump_rmon_counters(pdata); 1593 } 1594 1595 static void 1596 axgbe_if_init(if_ctx_t ctx) 1597 { 1598 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1599 struct xgbe_prv_data *pdata = &sc->pdata; 1600 1601 axgbe_pci_init(pdata); 1602 } 1603 1604 static void 1605 axgbe_pci_stop(if_ctx_t ctx) 1606 { 1607 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1608 struct xgbe_prv_data *pdata = &sc->pdata; 1609 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1610 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1611 int ret; 1612 1613 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) { 1614 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__); 1615 return; 1616 } 1617 1618 xgbe_stop_timers(pdata); 1619 taskqueue_drain_all(pdata->dev_workqueue); 1620 1621 hw_if->disable_tx(pdata); 1622 hw_if->disable_rx(pdata); 1623 1624 phy_if->phy_stop(pdata); 1625 1626 ret = hw_if->exit(pdata); 1627 if (ret) 1628 axgbe_error("%s: exit error %d\n", __func__, ret); 1629 1630 set_bit(XGBE_DOWN, &pdata->dev_state); 1631 } 1632 1633 static void 1634 axgbe_if_stop(if_ctx_t ctx) 1635 { 1636 axgbe_pci_stop(ctx); 1637 } 1638 1639 static void 1640 axgbe_if_disable_intr(if_ctx_t ctx) 1641 { 1642 /* TODO - implement */ 1643 } 1644 1645 static void 1646 axgbe_if_enable_intr(if_ctx_t ctx) 1647 { 1648 /* TODO - implement */ 1649 } 1650 1651 static int 1652 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs, 1653 int ntxqsets) 1654 { 1655 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1656 struct xgbe_prv_data *pdata = &sc->pdata; 1657 if_softc_ctx_t scctx = sc->scctx; 1658 struct xgbe_channel *channel; 1659 struct xgbe_ring *tx_ring; 1660 int i, j, k; 1661 1662 MPASS(scctx->isc_ntxqsets > 0); 1663 MPASS(scctx->isc_ntxqsets == ntxqsets); 1664 MPASS(ntxqs == 1); 1665 1666 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__, 1667 scctx->isc_ntxqsets, ntxqsets, ntxqs); 1668 1669 for (i = 0 ; i < ntxqsets; i++) { 1670 1671 channel = pdata->channel[i]; 1672 1673 tx_ring = (struct xgbe_ring*)malloc(ntxqs * 1674 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO); 1675 1676 if (tx_ring == NULL) { 1677 axgbe_error("Unable to allocate TX ring memory\n"); 1678 goto tx_ring_fail; 1679 } 1680 1681 channel->tx_ring = tx_ring; 1682 1683 for (j = 0; j < ntxqs; j++, tx_ring++) { 1684 tx_ring->rdata = 1685 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] * 1686 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT); 1687 1688 /* Get the virtual & physical address of hw queues */ 1689 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j]; 1690 tx_ring->rdesc_paddr = pa[i*ntxqs + j]; 1691 tx_ring->rdesc_count = scctx->isc_ntxd[j]; 1692 spin_lock_init(&tx_ring->lock); 1693 } 1694 } 1695 1696 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets); 1697 1698 return (0); 1699 1700 tx_ring_fail: 1701 1702 for (j = 0; j < i ; j++) { 1703 1704 channel = pdata->channel[j]; 1705 1706 tx_ring = channel->tx_ring; 1707 for (k = 0; k < ntxqs ; k++, tx_ring++) { 1708 if (tx_ring && tx_ring->rdata) 1709 free(tx_ring->rdata, M_AXGBE); 1710 } 1711 free(channel->tx_ring, M_AXGBE); 1712 1713 channel->tx_ring = NULL; 1714 } 1715 1716 return (ENOMEM); 1717 1718 } /* axgbe_if_tx_queues_alloc */ 1719 1720 static int 1721 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs, 1722 int nrxqsets) 1723 { 1724 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1725 struct xgbe_prv_data *pdata = &sc->pdata; 1726 if_softc_ctx_t scctx = sc->scctx; 1727 struct xgbe_channel *channel; 1728 struct xgbe_ring *rx_ring; 1729 int i, j, k; 1730 1731 MPASS(scctx->isc_nrxqsets > 0); 1732 MPASS(scctx->isc_nrxqsets == nrxqsets); 1733 if (!pdata->sph_enable) { 1734 MPASS(nrxqs == 1); 1735 } else { 1736 MPASS(nrxqs == 2); 1737 } 1738 1739 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__, 1740 scctx->isc_nrxqsets, nrxqsets, nrxqs); 1741 1742 for (i = 0 ; i < nrxqsets; i++) { 1743 1744 channel = pdata->channel[i]; 1745 1746 rx_ring = (struct xgbe_ring*)malloc(nrxqs * 1747 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO); 1748 1749 if (rx_ring == NULL) { 1750 axgbe_error("Unable to allocate RX ring memory\n"); 1751 goto rx_ring_fail; 1752 } 1753 1754 channel->rx_ring = rx_ring; 1755 1756 for (j = 0; j < nrxqs; j++, rx_ring++) { 1757 rx_ring->rdata = 1758 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] * 1759 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT); 1760 1761 /* Get the virtual and physical address of the hw queues */ 1762 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j]; 1763 rx_ring->rdesc_paddr = pa[i*nrxqs + j]; 1764 rx_ring->rdesc_count = scctx->isc_nrxd[j]; 1765 spin_lock_init(&rx_ring->lock); 1766 } 1767 } 1768 1769 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets); 1770 1771 return (0); 1772 1773 rx_ring_fail: 1774 1775 for (j = 0 ; j < i ; j++) { 1776 1777 channel = pdata->channel[j]; 1778 1779 rx_ring = channel->rx_ring; 1780 for (k = 0; k < nrxqs ; k++, rx_ring++) { 1781 if (rx_ring && rx_ring->rdata) 1782 free(rx_ring->rdata, M_AXGBE); 1783 } 1784 free(channel->rx_ring, M_AXGBE); 1785 1786 channel->rx_ring = NULL; 1787 } 1788 1789 return (ENOMEM); 1790 1791 } /* axgbe_if_rx_queues_alloc */ 1792 1793 static void 1794 axgbe_if_queues_free(if_ctx_t ctx) 1795 { 1796 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1797 struct xgbe_prv_data *pdata = &sc->pdata; 1798 if_softc_ctx_t scctx = sc->scctx; 1799 if_shared_ctx_t sctx = sc->sctx; 1800 struct xgbe_channel *channel; 1801 struct xgbe_ring *tx_ring; 1802 struct xgbe_ring *rx_ring; 1803 int i, j; 1804 1805 for (i = 0 ; i < scctx->isc_ntxqsets; i++) { 1806 1807 channel = pdata->channel[i]; 1808 1809 tx_ring = channel->tx_ring; 1810 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) { 1811 if (tx_ring && tx_ring->rdata) 1812 free(tx_ring->rdata, M_AXGBE); 1813 } 1814 free(channel->tx_ring, M_AXGBE); 1815 channel->tx_ring = NULL; 1816 } 1817 1818 for (i = 0 ; i < scctx->isc_nrxqsets; i++) { 1819 1820 channel = pdata->channel[i]; 1821 1822 rx_ring = channel->rx_ring; 1823 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) { 1824 if (rx_ring && rx_ring->rdata) 1825 free(rx_ring->rdata, M_AXGBE); 1826 } 1827 free(channel->rx_ring, M_AXGBE); 1828 channel->rx_ring = NULL; 1829 } 1830 1831 axgbe_free_channels(sc); 1832 } /* axgbe_if_queues_free */ 1833 1834 static void 1835 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag) 1836 { 1837 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1838 struct xgbe_prv_data *pdata = &sc->pdata; 1839 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1840 1841 if (!bit_test(pdata->active_vlans, vtag)) { 1842 axgbe_printf(0, "Registering VLAN %d\n", vtag); 1843 1844 bit_set(pdata->active_vlans, vtag); 1845 hw_if->update_vlan_hash_table(pdata); 1846 pdata->num_active_vlans++; 1847 1848 axgbe_printf(1, "Total active vlans: %d\n", 1849 pdata->num_active_vlans); 1850 } else 1851 axgbe_printf(0, "VLAN %d already registered\n", vtag); 1852 1853 xgbe_dump_active_vlans(pdata); 1854 } 1855 1856 static void 1857 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag) 1858 { 1859 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1860 struct xgbe_prv_data *pdata = &sc->pdata; 1861 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1862 1863 if (pdata->num_active_vlans == 0) { 1864 axgbe_printf(1, "No active VLANs to unregister\n"); 1865 return; 1866 } 1867 1868 if (bit_test(pdata->active_vlans, vtag)){ 1869 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag); 1870 1871 bit_clear(pdata->active_vlans, vtag); 1872 hw_if->update_vlan_hash_table(pdata); 1873 pdata->num_active_vlans--; 1874 1875 axgbe_printf(1, "Total active vlans: %d\n", 1876 pdata->num_active_vlans); 1877 } else 1878 axgbe_printf(0, "VLAN %d already unregistered\n", vtag); 1879 1880 xgbe_dump_active_vlans(pdata); 1881 } 1882 1883 #if __FreeBSD_version >= 1300000 1884 static bool 1885 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1886 { 1887 switch (event) { 1888 case IFLIB_RESTART_VLAN_CONFIG: 1889 default: 1890 return (true); 1891 } 1892 } 1893 #endif 1894 1895 static int 1896 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) 1897 { 1898 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1899 struct xgbe_prv_data *pdata = &sc->pdata; 1900 if_softc_ctx_t scctx = sc->scctx; 1901 struct xgbe_channel *channel; 1902 struct if_irq irq; 1903 int i, error, rid = 0, flags; 1904 char buf[16]; 1905 1906 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY); 1907 1908 pdata->isr_as_tasklet = 1; 1909 1910 if (scctx->isc_intr == IFLIB_INTR_MSI) { 1911 pdata->irq_count = 1; 1912 pdata->channel_irq_count = 1; 1913 return (0); 1914 } 1915 1916 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix, 1917 scctx->isc_ntxqsets, scctx->isc_nrxqsets); 1918 1919 flags = RF_ACTIVE; 1920 1921 /* DEV INTR SETUP */ 1922 rid++; 1923 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid, 1924 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq"); 1925 if (error) { 1926 axgbe_error("Failed to register device interrupt rid %d name %s\n", 1927 rid, "dev_irq"); 1928 return (error); 1929 } 1930 1931 /* ECC INTR SETUP */ 1932 rid++; 1933 pdata->ecc_rid = rid; 1934 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ, 1935 &rid, flags); 1936 if (!pdata->ecc_irq_res) { 1937 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n", 1938 rid, "ecc_irq"); 1939 return (ENOMEM); 1940 } 1941 1942 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE | 1943 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag); 1944 if (error) { 1945 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n", 1946 rid, "ecc_irq", error); 1947 return (error); 1948 } 1949 1950 /* I2C INTR SETUP */ 1951 rid++; 1952 pdata->i2c_rid = rid; 1953 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ, 1954 &rid, flags); 1955 if (!pdata->i2c_irq_res) { 1956 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n", 1957 rid, "i2c_irq"); 1958 return (ENOMEM); 1959 } 1960 1961 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE | 1962 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag); 1963 if (error) { 1964 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n", 1965 rid, "i2c_irq", error); 1966 return (error); 1967 } 1968 1969 /* AN INTR SETUP */ 1970 rid++; 1971 pdata->an_rid = rid; 1972 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ, 1973 &rid, flags); 1974 if (!pdata->an_irq_res) { 1975 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n", 1976 rid, "an_irq"); 1977 return (ENOMEM); 1978 } 1979 1980 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE | 1981 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag); 1982 if (error) { 1983 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n", 1984 rid, "an_irq", error); 1985 return (error); 1986 } 1987 1988 pdata->per_channel_irq = 1; 1989 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL; 1990 rid++; 1991 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) { 1992 1993 channel = pdata->channel[i]; 1994 1995 snprintf(buf, sizeof(buf), "rxq%d", i); 1996 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX, 1997 axgbe_msix_que, channel, channel->queue_index, buf); 1998 1999 if (error) { 2000 axgbe_error("Failed to allocated que int %d err: %d\n", 2001 i, error); 2002 return (error); 2003 } 2004 2005 channel->dma_irq_rid = rid; 2006 channel->dma_irq_res = irq.ii_res; 2007 channel->dma_irq_tag = irq.ii_tag; 2008 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n", 2009 __func__, scctx->isc_nrxqsets, i, rid); 2010 } 2011 pdata->irq_count = msix; 2012 pdata->channel_irq_count = scctx->isc_nrxqsets; 2013 2014 for (i = 0; i < scctx->isc_ntxqsets; i++) { 2015 2016 channel = pdata->channel[i]; 2017 2018 snprintf(buf, sizeof(buf), "txq%d", i); 2019 irq.ii_res = channel->dma_irq_res; 2020 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel, 2021 channel->queue_index, buf); 2022 } 2023 2024 return (0); 2025 } /* axgbe_if_msix_intr_assign */ 2026 2027 static int 2028 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel) 2029 { 2030 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2031 enum xgbe_int int_id; 2032 2033 if (channel->tx_ring && channel->rx_ring) 2034 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 2035 else if (channel->tx_ring) 2036 int_id = XGMAC_INT_DMA_CH_SR_TI; 2037 else if (channel->rx_ring) 2038 int_id = XGMAC_INT_DMA_CH_SR_RI; 2039 else 2040 return (-1); 2041 2042 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n", 2043 __func__, channel->queue_index, int_id); 2044 return (hw_if->enable_int(channel, int_id)); 2045 } 2046 2047 static void 2048 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel) 2049 { 2050 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2051 enum xgbe_int int_id; 2052 2053 if (channel->tx_ring && channel->rx_ring) 2054 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 2055 else if (channel->tx_ring) 2056 int_id = XGMAC_INT_DMA_CH_SR_TI; 2057 else if (channel->rx_ring) 2058 int_id = XGMAC_INT_DMA_CH_SR_RI; 2059 else 2060 return; 2061 2062 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n", 2063 __func__, channel->queue_index, int_id); 2064 hw_if->disable_int(channel, int_id); 2065 } 2066 2067 static void 2068 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) 2069 { 2070 unsigned int i; 2071 2072 for (i = 0; i < pdata->channel_count; i++) 2073 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]); 2074 } 2075 2076 static int 2077 axgbe_msix_que(void *arg) 2078 { 2079 struct xgbe_channel *channel = (struct xgbe_channel *)arg; 2080 struct xgbe_prv_data *pdata = channel->pdata; 2081 unsigned int dma_status; 2082 2083 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n", 2084 __func__, channel->queue_index, 2085 XGMAC_DMA_IOREAD(channel, DMA_CH_SR), 2086 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR), 2087 XGMAC_DMA_IOREAD(channel, DMA_CH_IER), 2088 XGMAC_IOREAD(pdata, DMA_ISR), 2089 XGMAC_IOREAD(pdata, MAC_ISR)); 2090 2091 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 2092 2093 /* Disable Tx and Rx channel interrupts */ 2094 xgbe_disable_rx_tx_int(pdata, channel); 2095 2096 /* Clear the interrupts */ 2097 dma_status = 0; 2098 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); 2099 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); 2100 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status); 2101 2102 return (FILTER_SCHEDULE_THREAD); 2103 } 2104 2105 static int 2106 axgbe_dev_isr(void *arg) 2107 { 2108 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg; 2109 struct xgbe_prv_data *pdata = &sc->pdata; 2110 struct xgbe_channel *channel; 2111 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2112 unsigned int i, dma_isr, dma_ch_isr; 2113 unsigned int mac_isr, mac_mdioisr; 2114 int ret = FILTER_HANDLED; 2115 2116 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); 2117 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr); 2118 2119 if (!dma_isr) 2120 return (FILTER_HANDLED); 2121 2122 for (i = 0; i < pdata->channel_count; i++) { 2123 2124 if (!(dma_isr & (1 << i))) 2125 continue; 2126 2127 channel = pdata->channel[i]; 2128 2129 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 2130 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__, 2131 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel, 2132 DMA_CH_DSR)); 2133 2134 /* 2135 * The TI or RI interrupt bits may still be set even if using 2136 * per channel DMA interrupts. Check to be sure those are not 2137 * enabled before using the private data napi structure. 2138 */ 2139 if (!pdata->per_channel_irq && 2140 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 2141 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { 2142 2143 /* Disable Tx and Rx interrupts */ 2144 xgbe_disable_rx_tx_ints(pdata); 2145 } else { 2146 2147 /* 2148 * Don't clear Rx/Tx status if doing per channel DMA 2149 * interrupts, these will be cleared by the ISR for 2150 * per channel DMA interrupts 2151 */ 2152 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); 2153 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); 2154 } 2155 2156 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) 2157 pdata->ext_stats.rx_buffer_unavailable++; 2158 2159 /* Restart the device on a Fatal Bus Error */ 2160 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) 2161 axgbe_error("%s: Fatal bus error reported 0x%x\n", 2162 __func__, dma_ch_isr); 2163 2164 /* Clear all interrupt signals */ 2165 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 2166 2167 ret = FILTER_SCHEDULE_THREAD; 2168 } 2169 2170 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { 2171 2172 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); 2173 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr); 2174 2175 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) 2176 hw_if->tx_mmc_int(pdata); 2177 2178 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) 2179 hw_if->rx_mmc_int(pdata); 2180 2181 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) { 2182 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR); 2183 2184 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR, 2185 SNGLCOMPINT)) 2186 wakeup_one(pdata); 2187 } 2188 2189 } 2190 2191 return (ret); 2192 } /* axgbe_dev_isr */ 2193 2194 static void 2195 axgbe_i2c_isr(void *arg) 2196 { 2197 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg; 2198 2199 sc->pdata.i2c_if.i2c_isr(&sc->pdata); 2200 } 2201 2202 static void 2203 axgbe_ecc_isr(void *arg) 2204 { 2205 /* TODO - implement */ 2206 } 2207 2208 static void 2209 axgbe_an_isr(void *arg) 2210 { 2211 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg; 2212 2213 sc->pdata.phy_if.an_isr(&sc->pdata); 2214 } 2215 2216 static int 2217 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 2218 { 2219 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2220 struct xgbe_prv_data *pdata = &sc->pdata; 2221 int ret; 2222 2223 if (qid < pdata->tx_q_count) { 2224 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]); 2225 if (ret) { 2226 axgbe_error("Enable TX INT failed\n"); 2227 return (ret); 2228 } 2229 } else 2230 axgbe_error("Queue ID exceed channel count\n"); 2231 2232 return (0); 2233 } 2234 2235 static int 2236 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 2237 { 2238 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2239 struct xgbe_prv_data *pdata = &sc->pdata; 2240 int ret; 2241 2242 if (qid < pdata->rx_q_count) { 2243 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]); 2244 if (ret) { 2245 axgbe_error("Enable RX INT failed\n"); 2246 return (ret); 2247 } 2248 } else 2249 axgbe_error("Queue ID exceed channel count\n"); 2250 2251 return (0); 2252 } 2253 2254 static void 2255 axgbe_if_update_admin_status(if_ctx_t ctx) 2256 { 2257 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2258 struct xgbe_prv_data *pdata = &sc->pdata; 2259 2260 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__, 2261 pdata->phy_link, sc->link_status, pdata->phy.speed); 2262 2263 if (pdata->phy_link < 0) 2264 return; 2265 2266 if (pdata->phy_link) { 2267 if (sc->link_status == LINK_STATE_DOWN) { 2268 sc->link_status = LINK_STATE_UP; 2269 if (pdata->phy.speed & SPEED_10000) 2270 iflib_link_state_change(ctx, LINK_STATE_UP, 2271 IF_Gbps(10)); 2272 else if (pdata->phy.speed & SPEED_2500) 2273 iflib_link_state_change(ctx, LINK_STATE_UP, 2274 IF_Gbps(2.5)); 2275 else if (pdata->phy.speed & SPEED_1000) 2276 iflib_link_state_change(ctx, LINK_STATE_UP, 2277 IF_Gbps(1)); 2278 else if (pdata->phy.speed & SPEED_100) 2279 iflib_link_state_change(ctx, LINK_STATE_UP, 2280 IF_Mbps(100)); 2281 else if (pdata->phy.speed & SPEED_10) 2282 iflib_link_state_change(ctx, LINK_STATE_UP, 2283 IF_Mbps(10)); 2284 } 2285 } else { 2286 if (sc->link_status == LINK_STATE_UP) { 2287 sc->link_status = LINK_STATE_DOWN; 2288 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2289 } 2290 } 2291 } 2292 2293 static int 2294 axgbe_if_media_change(if_ctx_t ctx) 2295 { 2296 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2297 struct ifmedia *ifm = iflib_get_media(ctx); 2298 2299 sx_xlock(&sc->pdata.an_mutex); 2300 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2301 return (EINVAL); 2302 2303 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2304 case IFM_10G_KR: 2305 sc->pdata.phy.speed = SPEED_10000; 2306 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2307 break; 2308 case IFM_2500_KX: 2309 sc->pdata.phy.speed = SPEED_2500; 2310 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2311 break; 2312 case IFM_1000_KX: 2313 sc->pdata.phy.speed = SPEED_1000; 2314 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2315 break; 2316 case IFM_100_TX: 2317 sc->pdata.phy.speed = SPEED_100; 2318 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2319 break; 2320 case IFM_AUTO: 2321 sc->pdata.phy.autoneg = AUTONEG_ENABLE; 2322 break; 2323 } 2324 sx_xunlock(&sc->pdata.an_mutex); 2325 2326 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata)); 2327 } 2328 2329 static int 2330 axgbe_if_promisc_set(if_ctx_t ctx, int flags) 2331 { 2332 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2333 struct xgbe_prv_data *pdata = &sc->pdata; 2334 if_t ifp = pdata->netdev; 2335 2336 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n", 2337 __func__, XGMAC_IOREAD(pdata, MAC_PFR), if_getdrvflags(ifp), 2338 if_getflags(ifp)); 2339 2340 if (if_getflags(ifp) & IFF_PPROMISC) { 2341 2342 axgbe_printf(1, "User requested to enter promisc mode\n"); 2343 2344 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) { 2345 axgbe_printf(1, "Already in promisc mode\n"); 2346 return (0); 2347 } 2348 2349 axgbe_printf(1, "Entering promisc mode\n"); 2350 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 2351 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 2352 } else { 2353 2354 axgbe_printf(1, "User requested to leave promisc mode\n"); 2355 2356 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) { 2357 axgbe_printf(1, "Already not in promisc mode\n"); 2358 return (0); 2359 } 2360 2361 axgbe_printf(1, "Leaving promisc mode\n"); 2362 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 2363 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 2364 } 2365 2366 return (0); 2367 } 2368 2369 static uint64_t 2370 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2371 { 2372 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2373 if_t ifp = iflib_get_ifp(ctx); 2374 struct xgbe_prv_data *pdata = &sc->pdata; 2375 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; 2376 2377 pdata->hw_if.read_mmc_stats(pdata); 2378 2379 switch(cnt) { 2380 case IFCOUNTER_IPACKETS: 2381 return (pstats->rxframecount_gb); 2382 case IFCOUNTER_IERRORS: 2383 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g - 2384 pstats->rxmulticastframes_g - pstats->rxunicastframes_g); 2385 case IFCOUNTER_OPACKETS: 2386 return (pstats->txframecount_gb); 2387 case IFCOUNTER_OERRORS: 2388 return (pstats->txframecount_gb - pstats->txframecount_g); 2389 case IFCOUNTER_IBYTES: 2390 return (pstats->rxoctetcount_gb); 2391 case IFCOUNTER_OBYTES: 2392 return (pstats->txoctetcount_gb); 2393 default: 2394 return (if_get_counter_default(ifp, cnt)); 2395 } 2396 } 2397 2398 static int 2399 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 2400 { 2401 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2402 struct xgbe_prv_data *pdata = &sc->pdata; 2403 int ret; 2404 2405 if (mtu > XGMAC_JUMBO_PACKET_MTU) 2406 return (EINVAL); 2407 2408 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu); 2409 pdata->rx_buf_size = ret; 2410 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret); 2411 2412 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2413 return (0); 2414 } 2415 2416 static void 2417 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 2418 { 2419 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2420 struct xgbe_prv_data *pdata = &sc->pdata; 2421 2422 ifmr->ifm_status = IFM_AVALID; 2423 if (!sc->pdata.phy.link) 2424 return; 2425 2426 ifmr->ifm_active = IFM_ETHER; 2427 ifmr->ifm_status |= IFM_ACTIVE; 2428 2429 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed, 2430 pdata->phy_if.phy_impl.cur_mode(pdata)); 2431 pdata->phy_if.phy_impl.get_type(pdata, ifmr); 2432 2433 ifmr->ifm_active |= IFM_FDX; 2434 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2435 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2436 } 2437