1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
5 * and Duncan Barclay<dmlb@dmlb.org>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/endian.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/mbuf.h>
36 #include <sys/module.h>
37 #include <sys/rman.h>
38 #include <sys/socket.h>
39 #include <sys/sockio.h>
40 #include <sys/sysctl.h>
41
42 #include <net/bpf.h>
43 #include <net/if.h>
44 #include <net/if_var.h>
45 #include <net/ethernet.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_types.h>
49 #include <net/if_vlan_var.h>
50
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56
57 #include <machine/bus.h>
58
59 #include <dev/bfe/if_bfereg.h>
60
61 MODULE_DEPEND(bfe, pci, 1, 1, 1);
62 MODULE_DEPEND(bfe, ether, 1, 1, 1);
63 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
64
65 /* "device miibus" required. See GENERIC if you get errors here. */
66 #include "miibus_if.h"
67
68 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
69
70 static struct bfe_type bfe_devs[] = {
71 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
72 "Broadcom BCM4401 Fast Ethernet" },
73 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
74 "Broadcom BCM4401-B0 Fast Ethernet" },
75 { 0, 0, NULL }
76 };
77
78 static int bfe_probe (device_t);
79 static int bfe_attach (device_t);
80 static int bfe_detach (device_t);
81 static int bfe_suspend (device_t);
82 static int bfe_resume (device_t);
83 static void bfe_release_resources (struct bfe_softc *);
84 static void bfe_intr (void *);
85 static int bfe_encap (struct bfe_softc *, struct mbuf **);
86 static void bfe_start (if_t);
87 static void bfe_start_locked (if_t);
88 static int bfe_ioctl (if_t, u_long, caddr_t);
89 static void bfe_init (void *);
90 static void bfe_init_locked (void *);
91 static void bfe_stop (struct bfe_softc *);
92 static void bfe_watchdog (struct bfe_softc *);
93 static int bfe_shutdown (device_t);
94 static void bfe_tick (void *);
95 static void bfe_txeof (struct bfe_softc *);
96 static void bfe_rxeof (struct bfe_softc *);
97 static void bfe_set_rx_mode (struct bfe_softc *);
98 static int bfe_list_rx_init (struct bfe_softc *);
99 static void bfe_list_tx_init (struct bfe_softc *);
100 static void bfe_discard_buf (struct bfe_softc *, int);
101 static int bfe_list_newbuf (struct bfe_softc *, int);
102 static void bfe_rx_ring_free (struct bfe_softc *);
103
104 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
105 static int bfe_ifmedia_upd (if_t);
106 static void bfe_ifmedia_sts (if_t, struct ifmediareq *);
107 static int bfe_miibus_readreg (device_t, int, int);
108 static int bfe_miibus_writereg (device_t, int, int, int);
109 static void bfe_miibus_statchg (device_t);
110 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
111 u_long, const int);
112 static void bfe_get_config (struct bfe_softc *sc);
113 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
114 static void bfe_stats_update (struct bfe_softc *);
115 static void bfe_clear_stats (struct bfe_softc *);
116 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
117 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
118 static int bfe_resetphy (struct bfe_softc *);
119 static int bfe_setupphy (struct bfe_softc *);
120 static void bfe_chip_reset (struct bfe_softc *);
121 static void bfe_chip_halt (struct bfe_softc *);
122 static void bfe_core_reset (struct bfe_softc *);
123 static void bfe_core_disable (struct bfe_softc *);
124 static int bfe_dma_alloc (struct bfe_softc *);
125 static void bfe_dma_free (struct bfe_softc *sc);
126 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
127 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
128 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS);
129
130 static device_method_t bfe_methods[] = {
131 /* Device interface */
132 DEVMETHOD(device_probe, bfe_probe),
133 DEVMETHOD(device_attach, bfe_attach),
134 DEVMETHOD(device_detach, bfe_detach),
135 DEVMETHOD(device_shutdown, bfe_shutdown),
136 DEVMETHOD(device_suspend, bfe_suspend),
137 DEVMETHOD(device_resume, bfe_resume),
138
139 /* MII interface */
140 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
141 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
142 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
143
144 DEVMETHOD_END
145 };
146
147 static driver_t bfe_driver = {
148 "bfe",
149 bfe_methods,
150 sizeof(struct bfe_softc)
151 };
152
153 DRIVER_MODULE(bfe, pci, bfe_driver, 0, 0);
154 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs,
155 nitems(bfe_devs) - 1);
156 DRIVER_MODULE(miibus, bfe, miibus_driver, 0, 0);
157
158 /*
159 * Probe for a Broadcom 4401 chip.
160 */
161 static int
bfe_probe(device_t dev)162 bfe_probe(device_t dev)
163 {
164 struct bfe_type *t;
165
166 t = bfe_devs;
167
168 while (t->bfe_name != NULL) {
169 if (pci_get_vendor(dev) == t->bfe_vid &&
170 pci_get_device(dev) == t->bfe_did) {
171 device_set_desc(dev, t->bfe_name);
172 return (BUS_PROBE_DEFAULT);
173 }
174 t++;
175 }
176
177 return (ENXIO);
178 }
179
180 struct bfe_dmamap_arg {
181 bus_addr_t bfe_busaddr;
182 };
183
184 static int
bfe_dma_alloc(struct bfe_softc * sc)185 bfe_dma_alloc(struct bfe_softc *sc)
186 {
187 struct bfe_dmamap_arg ctx;
188 struct bfe_rx_data *rd;
189 struct bfe_tx_data *td;
190 int error, i;
191
192 /*
193 * parent tag. Apparently the chip cannot handle any DMA address
194 * greater than 1GB.
195 */
196 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
197 1, 0, /* alignment, boundary */
198 BFE_DMA_MAXADDR, /* lowaddr */
199 BUS_SPACE_MAXADDR, /* highaddr */
200 NULL, NULL, /* filter, filterarg */
201 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
202 0, /* nsegments */
203 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
204 0, /* flags */
205 NULL, NULL, /* lockfunc, lockarg */
206 &sc->bfe_parent_tag);
207 if (error != 0) {
208 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
209 goto fail;
210 }
211
212 /* Create tag for Tx ring. */
213 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
214 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
215 BUS_SPACE_MAXADDR, /* lowaddr */
216 BUS_SPACE_MAXADDR, /* highaddr */
217 NULL, NULL, /* filter, filterarg */
218 BFE_TX_LIST_SIZE, /* maxsize */
219 1, /* nsegments */
220 BFE_TX_LIST_SIZE, /* maxsegsize */
221 0, /* flags */
222 NULL, NULL, /* lockfunc, lockarg */
223 &sc->bfe_tx_tag);
224 if (error != 0) {
225 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
226 goto fail;
227 }
228
229 /* Create tag for Rx ring. */
230 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
231 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
232 BUS_SPACE_MAXADDR, /* lowaddr */
233 BUS_SPACE_MAXADDR, /* highaddr */
234 NULL, NULL, /* filter, filterarg */
235 BFE_RX_LIST_SIZE, /* maxsize */
236 1, /* nsegments */
237 BFE_RX_LIST_SIZE, /* maxsegsize */
238 0, /* flags */
239 NULL, NULL, /* lockfunc, lockarg */
240 &sc->bfe_rx_tag);
241 if (error != 0) {
242 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
243 goto fail;
244 }
245
246 /* Create tag for Tx buffers. */
247 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
248 1, 0, /* alignment, boundary */
249 BUS_SPACE_MAXADDR, /* lowaddr */
250 BUS_SPACE_MAXADDR, /* highaddr */
251 NULL, NULL, /* filter, filterarg */
252 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
253 BFE_MAXTXSEGS, /* nsegments */
254 MCLBYTES, /* maxsegsize */
255 0, /* flags */
256 NULL, NULL, /* lockfunc, lockarg */
257 &sc->bfe_txmbuf_tag);
258 if (error != 0) {
259 device_printf(sc->bfe_dev,
260 "cannot create Tx buffer DMA tag.\n");
261 goto fail;
262 }
263
264 /* Create tag for Rx buffers. */
265 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
266 1, 0, /* alignment, boundary */
267 BUS_SPACE_MAXADDR, /* lowaddr */
268 BUS_SPACE_MAXADDR, /* highaddr */
269 NULL, NULL, /* filter, filterarg */
270 MCLBYTES, /* maxsize */
271 1, /* nsegments */
272 MCLBYTES, /* maxsegsize */
273 0, /* flags */
274 NULL, NULL, /* lockfunc, lockarg */
275 &sc->bfe_rxmbuf_tag);
276 if (error != 0) {
277 device_printf(sc->bfe_dev,
278 "cannot create Rx buffer DMA tag.\n");
279 goto fail;
280 }
281
282 /* Allocate DMA'able memory and load DMA map. */
283 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
284 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
285 if (error != 0) {
286 device_printf(sc->bfe_dev,
287 "cannot allocate DMA'able memory for Tx ring.\n");
288 goto fail;
289 }
290 ctx.bfe_busaddr = 0;
291 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
292 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
293 BUS_DMA_NOWAIT);
294 if (error != 0 || ctx.bfe_busaddr == 0) {
295 device_printf(sc->bfe_dev,
296 "cannot load DMA'able memory for Tx ring.\n");
297 goto fail;
298 }
299 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
300
301 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
302 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
303 if (error != 0) {
304 device_printf(sc->bfe_dev,
305 "cannot allocate DMA'able memory for Rx ring.\n");
306 goto fail;
307 }
308 ctx.bfe_busaddr = 0;
309 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
310 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
311 BUS_DMA_NOWAIT);
312 if (error != 0 || ctx.bfe_busaddr == 0) {
313 device_printf(sc->bfe_dev,
314 "cannot load DMA'able memory for Rx ring.\n");
315 goto fail;
316 }
317 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
318
319 /* Create DMA maps for Tx buffers. */
320 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
321 td = &sc->bfe_tx_ring[i];
322 td->bfe_mbuf = NULL;
323 td->bfe_map = NULL;
324 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
325 if (error != 0) {
326 device_printf(sc->bfe_dev,
327 "cannot create DMA map for Tx.\n");
328 goto fail;
329 }
330 }
331
332 /* Create spare DMA map for Rx buffers. */
333 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
334 if (error != 0) {
335 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
336 goto fail;
337 }
338 /* Create DMA maps for Rx buffers. */
339 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
340 rd = &sc->bfe_rx_ring[i];
341 rd->bfe_mbuf = NULL;
342 rd->bfe_map = NULL;
343 rd->bfe_ctrl = 0;
344 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
345 if (error != 0) {
346 device_printf(sc->bfe_dev,
347 "cannot create DMA map for Rx.\n");
348 goto fail;
349 }
350 }
351
352 fail:
353 return (error);
354 }
355
356 static void
bfe_dma_free(struct bfe_softc * sc)357 bfe_dma_free(struct bfe_softc *sc)
358 {
359 struct bfe_tx_data *td;
360 struct bfe_rx_data *rd;
361 int i;
362
363 /* Tx ring. */
364 if (sc->bfe_tx_tag != NULL) {
365 if (sc->bfe_tx_dma != 0)
366 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
367 if (sc->bfe_tx_list != NULL)
368 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
369 sc->bfe_tx_map);
370 sc->bfe_tx_dma = 0;
371 sc->bfe_tx_list = NULL;
372 bus_dma_tag_destroy(sc->bfe_tx_tag);
373 sc->bfe_tx_tag = NULL;
374 }
375
376 /* Rx ring. */
377 if (sc->bfe_rx_tag != NULL) {
378 if (sc->bfe_rx_dma != 0)
379 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
380 if (sc->bfe_rx_list != NULL)
381 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
382 sc->bfe_rx_map);
383 sc->bfe_rx_dma = 0;
384 sc->bfe_rx_list = NULL;
385 bus_dma_tag_destroy(sc->bfe_rx_tag);
386 sc->bfe_rx_tag = NULL;
387 }
388
389 /* Tx buffers. */
390 if (sc->bfe_txmbuf_tag != NULL) {
391 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
392 td = &sc->bfe_tx_ring[i];
393 if (td->bfe_map != NULL) {
394 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
395 td->bfe_map);
396 td->bfe_map = NULL;
397 }
398 }
399 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
400 sc->bfe_txmbuf_tag = NULL;
401 }
402
403 /* Rx buffers. */
404 if (sc->bfe_rxmbuf_tag != NULL) {
405 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
406 rd = &sc->bfe_rx_ring[i];
407 if (rd->bfe_map != NULL) {
408 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
409 rd->bfe_map);
410 rd->bfe_map = NULL;
411 }
412 }
413 if (sc->bfe_rx_sparemap != NULL) {
414 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
415 sc->bfe_rx_sparemap);
416 sc->bfe_rx_sparemap = NULL;
417 }
418 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
419 sc->bfe_rxmbuf_tag = NULL;
420 }
421
422 if (sc->bfe_parent_tag != NULL) {
423 bus_dma_tag_destroy(sc->bfe_parent_tag);
424 sc->bfe_parent_tag = NULL;
425 }
426 }
427
428 static int
bfe_attach(device_t dev)429 bfe_attach(device_t dev)
430 {
431 if_t ifp = NULL;
432 struct bfe_softc *sc;
433 int error = 0, rid;
434
435 sc = device_get_softc(dev);
436 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
437 MTX_DEF);
438 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
439
440 sc->bfe_dev = dev;
441
442 /*
443 * Map control/status registers.
444 */
445 pci_enable_busmaster(dev);
446
447 rid = PCIR_BAR(0);
448 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
449 RF_ACTIVE);
450 if (sc->bfe_res == NULL) {
451 device_printf(dev, "couldn't map memory\n");
452 error = ENXIO;
453 goto fail;
454 }
455
456 /* Allocate interrupt */
457 rid = 0;
458
459 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
460 RF_SHAREABLE | RF_ACTIVE);
461 if (sc->bfe_irq == NULL) {
462 device_printf(dev, "couldn't map interrupt\n");
463 error = ENXIO;
464 goto fail;
465 }
466
467 if (bfe_dma_alloc(sc) != 0) {
468 device_printf(dev, "failed to allocate DMA resources\n");
469 error = ENXIO;
470 goto fail;
471 }
472
473 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
475 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
476 sysctl_bfe_stats, "I", "Statistics");
477
478 /* Set up ifnet structure */
479 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
480 if (ifp == NULL) {
481 device_printf(dev, "failed to if_alloc()\n");
482 error = ENOSPC;
483 goto fail;
484 }
485 if_setsoftc(ifp, sc);
486 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
487 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
488 if_setioctlfn(ifp, bfe_ioctl);
489 if_setstartfn(ifp, bfe_start);
490 if_setinitfn(ifp, bfe_init);
491 if_setsendqlen(ifp, BFE_TX_QLEN);
492 if_setsendqready(ifp);
493
494 bfe_get_config(sc);
495
496 /* Reset the chip and turn on the PHY */
497 BFE_LOCK(sc);
498 bfe_chip_reset(sc);
499 BFE_UNLOCK(sc);
500
501 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
502 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
503 0);
504 if (error != 0) {
505 device_printf(dev, "attaching PHYs failed\n");
506 goto fail;
507 }
508
509 ether_ifattach(ifp, sc->bfe_enaddr);
510
511 /*
512 * Tell the upper layer(s) we support long frames.
513 */
514 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
515 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
516 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
517
518 /*
519 * Hook interrupt last to avoid having to lock softc
520 */
521 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
522 NULL, bfe_intr, sc, &sc->bfe_intrhand);
523
524 if (error) {
525 device_printf(dev, "couldn't set up irq\n");
526 goto fail;
527 }
528 fail:
529 if (error != 0)
530 bfe_detach(dev);
531 return (error);
532 }
533
534 static int
bfe_detach(device_t dev)535 bfe_detach(device_t dev)
536 {
537 struct bfe_softc *sc;
538 if_t ifp;
539
540 sc = device_get_softc(dev);
541
542 ifp = sc->bfe_ifp;
543
544 if (device_is_attached(dev)) {
545 BFE_LOCK(sc);
546 sc->bfe_flags |= BFE_FLAG_DETACH;
547 bfe_stop(sc);
548 BFE_UNLOCK(sc);
549 callout_drain(&sc->bfe_stat_co);
550 if (ifp != NULL)
551 ether_ifdetach(ifp);
552 }
553
554 BFE_LOCK(sc);
555 bfe_chip_reset(sc);
556 BFE_UNLOCK(sc);
557
558 bus_generic_detach(dev);
559 if (sc->bfe_miibus != NULL)
560 device_delete_child(dev, sc->bfe_miibus);
561
562 bfe_release_resources(sc);
563 bfe_dma_free(sc);
564 mtx_destroy(&sc->bfe_mtx);
565
566 return (0);
567 }
568
569 /*
570 * Stop all chip I/O so that the kernel's probe routines don't
571 * get confused by errant DMAs when rebooting.
572 */
573 static int
bfe_shutdown(device_t dev)574 bfe_shutdown(device_t dev)
575 {
576 struct bfe_softc *sc;
577
578 sc = device_get_softc(dev);
579 BFE_LOCK(sc);
580 bfe_stop(sc);
581
582 BFE_UNLOCK(sc);
583
584 return (0);
585 }
586
587 static int
bfe_suspend(device_t dev)588 bfe_suspend(device_t dev)
589 {
590 struct bfe_softc *sc;
591
592 sc = device_get_softc(dev);
593 BFE_LOCK(sc);
594 bfe_stop(sc);
595 BFE_UNLOCK(sc);
596
597 return (0);
598 }
599
600 static int
bfe_resume(device_t dev)601 bfe_resume(device_t dev)
602 {
603 struct bfe_softc *sc;
604 if_t ifp;
605
606 sc = device_get_softc(dev);
607 ifp = sc->bfe_ifp;
608 BFE_LOCK(sc);
609 bfe_chip_reset(sc);
610 if (if_getflags(ifp) & IFF_UP) {
611 bfe_init_locked(sc);
612 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
613 !if_sendq_empty(ifp))
614 bfe_start_locked(ifp);
615 }
616 BFE_UNLOCK(sc);
617
618 return (0);
619 }
620
621 static int
bfe_miibus_readreg(device_t dev,int phy,int reg)622 bfe_miibus_readreg(device_t dev, int phy, int reg)
623 {
624 struct bfe_softc *sc;
625 u_int32_t ret;
626
627 sc = device_get_softc(dev);
628 bfe_readphy(sc, reg, &ret);
629
630 return (ret);
631 }
632
633 static int
bfe_miibus_writereg(device_t dev,int phy,int reg,int val)634 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
635 {
636 struct bfe_softc *sc;
637
638 sc = device_get_softc(dev);
639 bfe_writephy(sc, reg, val);
640
641 return (0);
642 }
643
644 static void
bfe_miibus_statchg(device_t dev)645 bfe_miibus_statchg(device_t dev)
646 {
647 struct bfe_softc *sc;
648 struct mii_data *mii;
649 u_int32_t val;
650 #ifdef notyet
651 u_int32_t flow;
652 #endif
653
654 sc = device_get_softc(dev);
655 mii = device_get_softc(sc->bfe_miibus);
656
657 sc->bfe_flags &= ~BFE_FLAG_LINK;
658 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
659 (IFM_ACTIVE | IFM_AVALID)) {
660 switch (IFM_SUBTYPE(mii->mii_media_active)) {
661 case IFM_10_T:
662 case IFM_100_TX:
663 sc->bfe_flags |= BFE_FLAG_LINK;
664 break;
665 default:
666 break;
667 }
668 }
669
670 /* XXX Should stop Rx/Tx engine prior to touching MAC. */
671 val = CSR_READ_4(sc, BFE_TX_CTRL);
672 val &= ~BFE_TX_DUPLEX;
673 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
674 val |= BFE_TX_DUPLEX;
675 #ifdef notyet
676 flow = CSR_READ_4(sc, BFE_RXCONF);
677 flow &= ~BFE_RXCONF_FLOW;
678 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
679 IFM_ETH_RXPAUSE) != 0)
680 flow |= BFE_RXCONF_FLOW;
681 CSR_WRITE_4(sc, BFE_RXCONF, flow);
682 /*
683 * It seems that the hardware has Tx pause issues
684 * so enable only Rx pause.
685 */
686 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
687 flow &= ~BFE_FLOW_PAUSE_ENAB;
688 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
689 #endif
690 }
691 CSR_WRITE_4(sc, BFE_TX_CTRL, val);
692 }
693
694 static void
bfe_tx_ring_free(struct bfe_softc * sc)695 bfe_tx_ring_free(struct bfe_softc *sc)
696 {
697 int i;
698
699 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
700 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
701 bus_dmamap_sync(sc->bfe_txmbuf_tag,
702 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
703 bus_dmamap_unload(sc->bfe_txmbuf_tag,
704 sc->bfe_tx_ring[i].bfe_map);
705 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
706 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
707 }
708 }
709 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
710 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
712 }
713
714 static void
bfe_rx_ring_free(struct bfe_softc * sc)715 bfe_rx_ring_free(struct bfe_softc *sc)
716 {
717 int i;
718
719 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
720 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
721 bus_dmamap_sync(sc->bfe_rxmbuf_tag,
722 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
723 bus_dmamap_unload(sc->bfe_rxmbuf_tag,
724 sc->bfe_rx_ring[i].bfe_map);
725 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
726 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
727 }
728 }
729 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
730 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
732 }
733
734 static int
bfe_list_rx_init(struct bfe_softc * sc)735 bfe_list_rx_init(struct bfe_softc *sc)
736 {
737 struct bfe_rx_data *rd;
738 int i;
739
740 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
741 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
742 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
743 rd = &sc->bfe_rx_ring[i];
744 rd->bfe_mbuf = NULL;
745 rd->bfe_ctrl = 0;
746 if (bfe_list_newbuf(sc, i) != 0)
747 return (ENOBUFS);
748 }
749
750 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
751 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
752 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
753
754 return (0);
755 }
756
757 static void
bfe_list_tx_init(struct bfe_softc * sc)758 bfe_list_tx_init(struct bfe_softc *sc)
759 {
760 int i;
761
762 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
763 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
764 for (i = 0; i < BFE_TX_LIST_CNT; i++)
765 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
766
767 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
769 }
770
771 static void
bfe_discard_buf(struct bfe_softc * sc,int c)772 bfe_discard_buf(struct bfe_softc *sc, int c)
773 {
774 struct bfe_rx_data *r;
775 struct bfe_desc *d;
776
777 r = &sc->bfe_rx_ring[c];
778 d = &sc->bfe_rx_list[c];
779 d->bfe_ctrl = htole32(r->bfe_ctrl);
780 }
781
782 static int
bfe_list_newbuf(struct bfe_softc * sc,int c)783 bfe_list_newbuf(struct bfe_softc *sc, int c)
784 {
785 struct bfe_rxheader *rx_header;
786 struct bfe_desc *d;
787 struct bfe_rx_data *r;
788 struct mbuf *m;
789 bus_dma_segment_t segs[1];
790 bus_dmamap_t map;
791 u_int32_t ctrl;
792 int nsegs;
793
794 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
795 if (m == NULL)
796 return (ENOBUFS);
797 m->m_len = m->m_pkthdr.len = MCLBYTES;
798
799 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
800 m, segs, &nsegs, 0) != 0) {
801 m_freem(m);
802 return (ENOBUFS);
803 }
804
805 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
806 r = &sc->bfe_rx_ring[c];
807 if (r->bfe_mbuf != NULL) {
808 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
809 BUS_DMASYNC_POSTREAD);
810 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
811 }
812 map = r->bfe_map;
813 r->bfe_map = sc->bfe_rx_sparemap;
814 sc->bfe_rx_sparemap = map;
815 r->bfe_mbuf = m;
816
817 rx_header = mtod(m, struct bfe_rxheader *);
818 rx_header->len = 0;
819 rx_header->flags = 0;
820 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
821
822 ctrl = segs[0].ds_len & BFE_DESC_LEN;
823 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
824 __func__, ctrl));
825 if (c == BFE_RX_LIST_CNT - 1)
826 ctrl |= BFE_DESC_EOT;
827 r->bfe_ctrl = ctrl;
828
829 d = &sc->bfe_rx_list[c];
830 d->bfe_ctrl = htole32(ctrl);
831 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
832 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
833
834 return (0);
835 }
836
837 static void
bfe_get_config(struct bfe_softc * sc)838 bfe_get_config(struct bfe_softc *sc)
839 {
840 u_int8_t eeprom[128];
841
842 bfe_read_eeprom(sc, eeprom);
843
844 sc->bfe_enaddr[0] = eeprom[79];
845 sc->bfe_enaddr[1] = eeprom[78];
846 sc->bfe_enaddr[2] = eeprom[81];
847 sc->bfe_enaddr[3] = eeprom[80];
848 sc->bfe_enaddr[4] = eeprom[83];
849 sc->bfe_enaddr[5] = eeprom[82];
850
851 sc->bfe_phyaddr = eeprom[90] & 0x1f;
852 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
853
854 sc->bfe_core_unit = 0;
855 sc->bfe_dma_offset = BFE_PCI_DMA;
856 }
857
858 static void
bfe_pci_setup(struct bfe_softc * sc,u_int32_t cores)859 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
860 {
861 u_int32_t bar_orig, val;
862
863 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
864 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
865
866 val = CSR_READ_4(sc, BFE_SBINTVEC);
867 val |= cores;
868 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
869
870 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
871 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
872 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
873
874 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
875 }
876
877 static void
bfe_clear_stats(struct bfe_softc * sc)878 bfe_clear_stats(struct bfe_softc *sc)
879 {
880 uint32_t reg;
881
882 BFE_LOCK_ASSERT(sc);
883
884 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
885 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
886 CSR_READ_4(sc, reg);
887 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
888 CSR_READ_4(sc, reg);
889 }
890
891 static int
bfe_resetphy(struct bfe_softc * sc)892 bfe_resetphy(struct bfe_softc *sc)
893 {
894 u_int32_t val;
895
896 bfe_writephy(sc, 0, BMCR_RESET);
897 DELAY(100);
898 bfe_readphy(sc, 0, &val);
899 if (val & BMCR_RESET) {
900 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
901 return (ENXIO);
902 }
903 return (0);
904 }
905
906 static void
bfe_chip_halt(struct bfe_softc * sc)907 bfe_chip_halt(struct bfe_softc *sc)
908 {
909 BFE_LOCK_ASSERT(sc);
910 /* disable interrupts - not that it actually does..*/
911 CSR_WRITE_4(sc, BFE_IMASK, 0);
912 CSR_READ_4(sc, BFE_IMASK);
913
914 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
915 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
916
917 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
918 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
919 DELAY(10);
920 }
921
922 static void
bfe_chip_reset(struct bfe_softc * sc)923 bfe_chip_reset(struct bfe_softc *sc)
924 {
925 u_int32_t val;
926
927 BFE_LOCK_ASSERT(sc);
928
929 /* Set the interrupt vector for the enet core */
930 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
931
932 /* is core up? */
933 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
934 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
935 if (val == BFE_CLOCK) {
936 /* It is, so shut it down */
937 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
938 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
939 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
940 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
941 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
942 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
943 100, 0);
944 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
945 }
946
947 bfe_core_reset(sc);
948 bfe_clear_stats(sc);
949
950 /*
951 * We want the phy registers to be accessible even when
952 * the driver is "downed" so initialize MDC preamble, frequency,
953 * and whether internal or external phy here.
954 */
955
956 /* 4402 has 62.5Mhz SB clock and internal phy */
957 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
958
959 /* Internal or external PHY? */
960 val = CSR_READ_4(sc, BFE_DEVCTRL);
961 if (!(val & BFE_IPP))
962 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
963 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
964 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
965 DELAY(100);
966 }
967
968 /* Enable CRC32 generation and set proper LED modes */
969 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
970
971 /* Reset or clear powerdown control bit */
972 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
973
974 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
975 BFE_LAZY_FC_MASK));
976
977 /*
978 * We don't want lazy interrupts, so just send them at
979 * the end of a frame, please
980 */
981 BFE_OR(sc, BFE_RCV_LAZY, 0);
982
983 /* Set max lengths, accounting for VLAN tags */
984 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
985 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
986
987 /* Set watermark XXX - magic */
988 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
989
990 /*
991 * Initialise DMA channels
992 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
993 */
994 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
995 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
996
997 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
998 BFE_RX_CTRL_ENABLE);
999 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1000
1001 bfe_resetphy(sc);
1002 bfe_setupphy(sc);
1003 }
1004
1005 static void
bfe_core_disable(struct bfe_softc * sc)1006 bfe_core_disable(struct bfe_softc *sc)
1007 {
1008 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1009 return;
1010
1011 /*
1012 * Set reject, wait for it set, then wait for the core to stop
1013 * being busy, then set reset and reject and enable the clocks.
1014 */
1015 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1016 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1017 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1018 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1019 BFE_RESET));
1020 CSR_READ_4(sc, BFE_SBTMSLOW);
1021 DELAY(10);
1022 /* Leave reset and reject set */
1023 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1024 DELAY(10);
1025 }
1026
1027 static void
bfe_core_reset(struct bfe_softc * sc)1028 bfe_core_reset(struct bfe_softc *sc)
1029 {
1030 u_int32_t val;
1031
1032 /* Disable the core */
1033 bfe_core_disable(sc);
1034
1035 /* and bring it back up */
1036 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1037 CSR_READ_4(sc, BFE_SBTMSLOW);
1038 DELAY(10);
1039
1040 /* Chip bug, clear SERR, IB and TO if they are set. */
1041 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1042 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1043 val = CSR_READ_4(sc, BFE_SBIMSTATE);
1044 if (val & (BFE_IBE | BFE_TO))
1045 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1046
1047 /* Clear reset and allow it to move through the core */
1048 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1049 CSR_READ_4(sc, BFE_SBTMSLOW);
1050 DELAY(10);
1051
1052 /* Leave the clock set */
1053 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1054 CSR_READ_4(sc, BFE_SBTMSLOW);
1055 DELAY(10);
1056 }
1057
1058 static void
bfe_cam_write(struct bfe_softc * sc,u_char * data,int index)1059 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1060 {
1061 u_int32_t val;
1062
1063 val = ((u_int32_t) data[2]) << 24;
1064 val |= ((u_int32_t) data[3]) << 16;
1065 val |= ((u_int32_t) data[4]) << 8;
1066 val |= ((u_int32_t) data[5]);
1067 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1068 val = (BFE_CAM_HI_VALID |
1069 (((u_int32_t) data[0]) << 8) |
1070 (((u_int32_t) data[1])));
1071 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1072 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1073 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1074 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1075 }
1076
1077 static u_int
bfe_write_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1078 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1079 {
1080 struct bfe_softc *sc = arg;
1081
1082 bfe_cam_write(sc, LLADDR(sdl), cnt + 1);
1083
1084 return (1);
1085 }
1086
1087 static void
bfe_set_rx_mode(struct bfe_softc * sc)1088 bfe_set_rx_mode(struct bfe_softc *sc)
1089 {
1090 if_t ifp = sc->bfe_ifp;
1091 u_int32_t val;
1092
1093 BFE_LOCK_ASSERT(sc);
1094
1095 val = CSR_READ_4(sc, BFE_RXCONF);
1096
1097 if (if_getflags(ifp) & IFF_PROMISC)
1098 val |= BFE_RXCONF_PROMISC;
1099 else
1100 val &= ~BFE_RXCONF_PROMISC;
1101
1102 if (if_getflags(ifp) & IFF_BROADCAST)
1103 val &= ~BFE_RXCONF_DBCAST;
1104 else
1105 val |= BFE_RXCONF_DBCAST;
1106
1107 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1108 bfe_cam_write(sc, if_getlladdr(sc->bfe_ifp), 0);
1109
1110 if (if_getflags(ifp) & IFF_ALLMULTI)
1111 val |= BFE_RXCONF_ALLMULTI;
1112 else {
1113 val &= ~BFE_RXCONF_ALLMULTI;
1114 if_foreach_llmaddr(ifp, bfe_write_maddr, sc);
1115 }
1116
1117 CSR_WRITE_4(sc, BFE_RXCONF, val);
1118 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1119 }
1120
1121 static void
bfe_dma_map(void * arg,bus_dma_segment_t * segs,int nseg,int error)1122 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1123 {
1124 struct bfe_dmamap_arg *ctx;
1125
1126 if (error != 0)
1127 return;
1128
1129 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1130
1131 ctx = (struct bfe_dmamap_arg *)arg;
1132 ctx->bfe_busaddr = segs[0].ds_addr;
1133 }
1134
1135 static void
bfe_release_resources(struct bfe_softc * sc)1136 bfe_release_resources(struct bfe_softc *sc)
1137 {
1138
1139 if (sc->bfe_intrhand != NULL)
1140 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1141
1142 if (sc->bfe_irq != NULL)
1143 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1144
1145 if (sc->bfe_res != NULL)
1146 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1147 sc->bfe_res);
1148
1149 if (sc->bfe_ifp != NULL)
1150 if_free(sc->bfe_ifp);
1151 }
1152
1153 static void
bfe_read_eeprom(struct bfe_softc * sc,u_int8_t * data)1154 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1155 {
1156 long i;
1157 u_int16_t *ptr = (u_int16_t *)data;
1158
1159 for(i = 0; i < 128; i += 2)
1160 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1161 }
1162
1163 static int
bfe_wait_bit(struct bfe_softc * sc,u_int32_t reg,u_int32_t bit,u_long timeout,const int clear)1164 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1165 u_long timeout, const int clear)
1166 {
1167 u_long i;
1168
1169 for (i = 0; i < timeout; i++) {
1170 u_int32_t val = CSR_READ_4(sc, reg);
1171
1172 if (clear && !(val & bit))
1173 break;
1174 if (!clear && (val & bit))
1175 break;
1176 DELAY(10);
1177 }
1178 if (i == timeout) {
1179 device_printf(sc->bfe_dev,
1180 "BUG! Timeout waiting for bit %08x of register "
1181 "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1182 return (-1);
1183 }
1184 return (0);
1185 }
1186
1187 static int
bfe_readphy(struct bfe_softc * sc,u_int32_t reg,u_int32_t * val)1188 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1189 {
1190 int err;
1191
1192 /* Clear MII ISR */
1193 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1194 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1195 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1196 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1197 (reg << BFE_MDIO_RA_SHIFT) |
1198 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1199 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1200 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1201
1202 return (err);
1203 }
1204
1205 static int
bfe_writephy(struct bfe_softc * sc,u_int32_t reg,u_int32_t val)1206 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1207 {
1208 int status;
1209
1210 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1211 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1212 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1213 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1214 (reg << BFE_MDIO_RA_SHIFT) |
1215 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1216 (val & BFE_MDIO_DATA_DATA)));
1217 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1218
1219 return (status);
1220 }
1221
1222 /*
1223 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1224 * twice
1225 */
1226 static int
bfe_setupphy(struct bfe_softc * sc)1227 bfe_setupphy(struct bfe_softc *sc)
1228 {
1229 u_int32_t val;
1230
1231 /* Enable activity LED */
1232 bfe_readphy(sc, 26, &val);
1233 bfe_writephy(sc, 26, val & 0x7fff);
1234 bfe_readphy(sc, 26, &val);
1235
1236 /* Enable traffic meter LED mode */
1237 bfe_readphy(sc, 27, &val);
1238 bfe_writephy(sc, 27, val | (1 << 6));
1239
1240 return (0);
1241 }
1242
1243 static void
bfe_stats_update(struct bfe_softc * sc)1244 bfe_stats_update(struct bfe_softc *sc)
1245 {
1246 struct bfe_hw_stats *stats;
1247 if_t ifp;
1248 uint32_t mib[BFE_MIB_CNT];
1249 uint32_t reg, *val;
1250
1251 BFE_LOCK_ASSERT(sc);
1252
1253 val = mib;
1254 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1255 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1256 *val++ = CSR_READ_4(sc, reg);
1257 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1258 *val++ = CSR_READ_4(sc, reg);
1259
1260 ifp = sc->bfe_ifp;
1261 stats = &sc->bfe_stats;
1262 /* Tx stat. */
1263 stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1264 stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1265 stats->tx_octets += mib[MIB_TX_O];
1266 stats->tx_frames += mib[MIB_TX_P];
1267 stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1268 stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1269 stats->tx_pkts_64 += mib[MIB_TX_64];
1270 stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1271 stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1272 stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1273 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1274 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1275 stats->tx_jabbers += mib[MIB_TX_JABBER];
1276 stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1277 stats->tx_frag_frames += mib[MIB_TX_FRAG];
1278 stats->tx_underruns += mib[MIB_TX_URUNS];
1279 stats->tx_colls += mib[MIB_TX_TCOLS];
1280 stats->tx_single_colls += mib[MIB_TX_SCOLS];
1281 stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1282 stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1283 stats->tx_late_colls += mib[MIB_TX_LCOLS];
1284 stats->tx_deferrals += mib[MIB_TX_DEFERED];
1285 stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1286 stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1287 /* Rx stat. */
1288 stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1289 stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1290 stats->rx_octets += mib[MIB_RX_O];
1291 stats->rx_frames += mib[MIB_RX_P];
1292 stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1293 stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1294 stats->rx_pkts_64 += mib[MIB_RX_64];
1295 stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1296 stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1297 stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1298 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1299 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1300 stats->rx_jabbers += mib[MIB_RX_JABBER];
1301 stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1302 stats->rx_frag_frames += mib[MIB_RX_FRAG];
1303 stats->rx_missed_frames += mib[MIB_RX_MISS];
1304 stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1305 stats->rx_runts += mib[MIB_RX_USIZE];
1306 stats->rx_crc_errs += mib[MIB_RX_CRC];
1307 stats->rx_align_errs += mib[MIB_RX_ALIGN];
1308 stats->rx_symbol_errs += mib[MIB_RX_SYM];
1309 stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1310 stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1311
1312 /* Update counters in ifnet. */
1313 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]);
1314 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]);
1315 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] +
1316 (u_long)mib[MIB_TX_ECOLS] +
1317 (u_long)mib[MIB_TX_DEFERED] +
1318 (u_long)mib[MIB_TX_CLOST]);
1319
1320 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]);
1321
1322 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] +
1323 mib[MIB_RX_MISS] +
1324 mib[MIB_RX_CRCA] +
1325 mib[MIB_RX_USIZE] +
1326 mib[MIB_RX_CRC] +
1327 mib[MIB_RX_ALIGN] +
1328 mib[MIB_RX_SYM]);
1329 }
1330
1331 static void
bfe_txeof(struct bfe_softc * sc)1332 bfe_txeof(struct bfe_softc *sc)
1333 {
1334 struct bfe_tx_data *r;
1335 if_t ifp;
1336 int i, chipidx;
1337
1338 BFE_LOCK_ASSERT(sc);
1339
1340 ifp = sc->bfe_ifp;
1341
1342 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1343 chipidx /= sizeof(struct bfe_desc);
1344
1345 i = sc->bfe_tx_cons;
1346 if (i == chipidx)
1347 return;
1348 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1350 /* Go through the mbufs and free those that have been transmitted */
1351 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1352 r = &sc->bfe_tx_ring[i];
1353 sc->bfe_tx_cnt--;
1354 if (r->bfe_mbuf == NULL)
1355 continue;
1356 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1357 BUS_DMASYNC_POSTWRITE);
1358 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1359
1360 m_freem(r->bfe_mbuf);
1361 r->bfe_mbuf = NULL;
1362 }
1363
1364 if (i != sc->bfe_tx_cons) {
1365 /* we freed up some mbufs */
1366 sc->bfe_tx_cons = i;
1367 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1368 }
1369
1370 if (sc->bfe_tx_cnt == 0)
1371 sc->bfe_watchdog_timer = 0;
1372 }
1373
1374 /* Pass a received packet up the stack */
1375 static void
bfe_rxeof(struct bfe_softc * sc)1376 bfe_rxeof(struct bfe_softc *sc)
1377 {
1378 struct mbuf *m;
1379 if_t ifp;
1380 struct bfe_rxheader *rxheader;
1381 struct bfe_rx_data *r;
1382 int cons, prog;
1383 u_int32_t status, current, len, flags;
1384
1385 BFE_LOCK_ASSERT(sc);
1386 cons = sc->bfe_rx_cons;
1387 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1388 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1389
1390 ifp = sc->bfe_ifp;
1391
1392 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1393 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1394
1395 for (prog = 0; current != cons; prog++,
1396 BFE_INC(cons, BFE_RX_LIST_CNT)) {
1397 r = &sc->bfe_rx_ring[cons];
1398 m = r->bfe_mbuf;
1399 /*
1400 * Rx status should be read from mbuf such that we can't
1401 * delay bus_dmamap_sync(9). This hardware limiation
1402 * results in inefficient mbuf usage as bfe(4) couldn't
1403 * reuse mapped buffer from errored frame.
1404 */
1405 if (bfe_list_newbuf(sc, cons) != 0) {
1406 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1407 bfe_discard_buf(sc, cons);
1408 continue;
1409 }
1410 rxheader = mtod(m, struct bfe_rxheader*);
1411 len = le16toh(rxheader->len);
1412 flags = le16toh(rxheader->flags);
1413
1414 /* Remove CRC bytes. */
1415 len -= ETHER_CRC_LEN;
1416
1417 /* flag an error and try again */
1418 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1419 m_freem(m);
1420 continue;
1421 }
1422
1423 /* Make sure to skip header bytes written by hardware. */
1424 m_adj(m, BFE_RX_OFFSET);
1425 m->m_len = m->m_pkthdr.len = len;
1426
1427 m->m_pkthdr.rcvif = ifp;
1428 BFE_UNLOCK(sc);
1429 if_input(ifp, m);
1430 BFE_LOCK(sc);
1431 }
1432
1433 if (prog > 0) {
1434 sc->bfe_rx_cons = cons;
1435 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1436 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1437 }
1438 }
1439
1440 static void
bfe_intr(void * xsc)1441 bfe_intr(void *xsc)
1442 {
1443 struct bfe_softc *sc = xsc;
1444 if_t ifp;
1445 u_int32_t istat;
1446
1447 ifp = sc->bfe_ifp;
1448
1449 BFE_LOCK(sc);
1450
1451 istat = CSR_READ_4(sc, BFE_ISTAT);
1452
1453 /*
1454 * Defer unsolicited interrupts - This is necessary because setting the
1455 * chips interrupt mask register to 0 doesn't actually stop the
1456 * interrupts
1457 */
1458 istat &= BFE_IMASK_DEF;
1459 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1460 CSR_READ_4(sc, BFE_ISTAT);
1461
1462 /* not expecting this interrupt, disregard it */
1463 if (istat == 0 || (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1464 BFE_UNLOCK(sc);
1465 return;
1466 }
1467
1468 /* A packet was received */
1469 if (istat & BFE_ISTAT_RX)
1470 bfe_rxeof(sc);
1471
1472 /* A packet was sent */
1473 if (istat & BFE_ISTAT_TX)
1474 bfe_txeof(sc);
1475
1476 if (istat & BFE_ISTAT_ERRORS) {
1477 if (istat & BFE_ISTAT_DSCE) {
1478 device_printf(sc->bfe_dev, "Descriptor Error\n");
1479 bfe_stop(sc);
1480 BFE_UNLOCK(sc);
1481 return;
1482 }
1483
1484 if (istat & BFE_ISTAT_DPE) {
1485 device_printf(sc->bfe_dev,
1486 "Descriptor Protocol Error\n");
1487 bfe_stop(sc);
1488 BFE_UNLOCK(sc);
1489 return;
1490 }
1491 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1492 bfe_init_locked(sc);
1493 }
1494
1495 /* We have packets pending, fire them out */
1496 if (!if_sendq_empty(ifp))
1497 bfe_start_locked(ifp);
1498
1499 BFE_UNLOCK(sc);
1500 }
1501
1502 static int
bfe_encap(struct bfe_softc * sc,struct mbuf ** m_head)1503 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1504 {
1505 struct bfe_desc *d;
1506 struct bfe_tx_data *r, *r1;
1507 struct mbuf *m;
1508 bus_dmamap_t map;
1509 bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1510 uint32_t cur, si;
1511 int error, i, nsegs;
1512
1513 BFE_LOCK_ASSERT(sc);
1514
1515 M_ASSERTPKTHDR((*m_head));
1516
1517 si = cur = sc->bfe_tx_prod;
1518 r = &sc->bfe_tx_ring[cur];
1519 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1520 txsegs, &nsegs, 0);
1521 if (error == EFBIG) {
1522 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
1523 if (m == NULL) {
1524 m_freem(*m_head);
1525 *m_head = NULL;
1526 return (ENOMEM);
1527 }
1528 *m_head = m;
1529 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1530 *m_head, txsegs, &nsegs, 0);
1531 if (error != 0) {
1532 m_freem(*m_head);
1533 *m_head = NULL;
1534 return (error);
1535 }
1536 } else if (error != 0)
1537 return (error);
1538 if (nsegs == 0) {
1539 m_freem(*m_head);
1540 *m_head = NULL;
1541 return (EIO);
1542 }
1543
1544 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1545 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1546 return (ENOBUFS);
1547 }
1548
1549 for (i = 0; i < nsegs; i++) {
1550 d = &sc->bfe_tx_list[cur];
1551 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1552 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1553 if (cur == BFE_TX_LIST_CNT - 1)
1554 /*
1555 * Tell the chip to wrap to the start of
1556 * the descriptor list.
1557 */
1558 d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1559 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
1560 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1561 BFE_PCI_DMA);
1562 BFE_INC(cur, BFE_TX_LIST_CNT);
1563 }
1564
1565 /* Update producer index. */
1566 sc->bfe_tx_prod = cur;
1567
1568 /* Set EOF on the last descriptor. */
1569 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1570 d = &sc->bfe_tx_list[cur];
1571 d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1572
1573 /* Lastly set SOF on the first descriptor to avoid races. */
1574 d = &sc->bfe_tx_list[si];
1575 d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1576
1577 r1 = &sc->bfe_tx_ring[cur];
1578 map = r->bfe_map;
1579 r->bfe_map = r1->bfe_map;
1580 r1->bfe_map = map;
1581 r1->bfe_mbuf = *m_head;
1582 sc->bfe_tx_cnt += nsegs;
1583
1584 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1585
1586 return (0);
1587 }
1588
1589 /*
1590 * Set up to transmit a packet.
1591 */
1592 static void
bfe_start(if_t ifp)1593 bfe_start(if_t ifp)
1594 {
1595 BFE_LOCK((struct bfe_softc *)if_getsoftc(ifp));
1596 bfe_start_locked(ifp);
1597 BFE_UNLOCK((struct bfe_softc *)if_getsoftc(ifp));
1598 }
1599
1600 /*
1601 * Set up to transmit a packet. The softc is already locked.
1602 */
1603 static void
bfe_start_locked(if_t ifp)1604 bfe_start_locked(if_t ifp)
1605 {
1606 struct bfe_softc *sc;
1607 struct mbuf *m_head;
1608 int queued;
1609
1610 sc = if_getsoftc(ifp);
1611
1612 BFE_LOCK_ASSERT(sc);
1613
1614 /*
1615 * Not much point trying to send if the link is down
1616 * or we have nothing to send.
1617 */
1618 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1619 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1620 return;
1621
1622 for (queued = 0; !if_sendq_empty(ifp) &&
1623 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1624 m_head = if_dequeue(ifp);
1625 if (m_head == NULL)
1626 break;
1627
1628 /*
1629 * Pack the data into the tx ring. If we dont have
1630 * enough room, let the chip drain the ring.
1631 */
1632 if (bfe_encap(sc, &m_head)) {
1633 if (m_head == NULL)
1634 break;
1635 if_sendq_prepend(ifp, m_head);
1636 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1637 break;
1638 }
1639
1640 queued++;
1641
1642 /*
1643 * If there's a BPF listener, bounce a copy of this frame
1644 * to him.
1645 */
1646 BPF_MTAP(ifp, m_head);
1647 }
1648
1649 if (queued) {
1650 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1651 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1652 /* Transmit - twice due to apparent hardware bug */
1653 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1654 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1655 /*
1656 * XXX It seems the following write is not necessary
1657 * to kick Tx command. What might be required would be
1658 * a way flushing PCI posted write. Reading the register
1659 * back ensures the flush operation. In addition,
1660 * hardware will execute PCI posted write in the long
1661 * run and watchdog timer for the kick command was set
1662 * to 5 seconds. Therefore I think the second write
1663 * access is not necessary or could be replaced with
1664 * read operation.
1665 */
1666 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1667 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1668
1669 /*
1670 * Set a timeout in case the chip goes out to lunch.
1671 */
1672 sc->bfe_watchdog_timer = 5;
1673 }
1674 }
1675
1676 static void
bfe_init(void * xsc)1677 bfe_init(void *xsc)
1678 {
1679 BFE_LOCK((struct bfe_softc *)xsc);
1680 bfe_init_locked(xsc);
1681 BFE_UNLOCK((struct bfe_softc *)xsc);
1682 }
1683
1684 static void
bfe_init_locked(void * xsc)1685 bfe_init_locked(void *xsc)
1686 {
1687 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1688 if_t ifp = sc->bfe_ifp;
1689 struct mii_data *mii;
1690
1691 BFE_LOCK_ASSERT(sc);
1692
1693 mii = device_get_softc(sc->bfe_miibus);
1694
1695 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1696 return;
1697
1698 bfe_stop(sc);
1699 bfe_chip_reset(sc);
1700
1701 if (bfe_list_rx_init(sc) == ENOBUFS) {
1702 device_printf(sc->bfe_dev,
1703 "%s: Not enough memory for list buffers\n", __func__);
1704 bfe_stop(sc);
1705 return;
1706 }
1707 bfe_list_tx_init(sc);
1708
1709 bfe_set_rx_mode(sc);
1710
1711 /* Enable the chip and core */
1712 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1713 /* Enable interrupts */
1714 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1715
1716 /* Clear link state and change media. */
1717 sc->bfe_flags &= ~BFE_FLAG_LINK;
1718 mii_mediachg(mii);
1719
1720 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1721 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1722
1723 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1724 }
1725
1726 /*
1727 * Set media options.
1728 */
1729 static int
bfe_ifmedia_upd(if_t ifp)1730 bfe_ifmedia_upd(if_t ifp)
1731 {
1732 struct bfe_softc *sc;
1733 struct mii_data *mii;
1734 struct mii_softc *miisc;
1735 int error;
1736
1737 sc = if_getsoftc(ifp);
1738 BFE_LOCK(sc);
1739
1740 mii = device_get_softc(sc->bfe_miibus);
1741 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1742 PHY_RESET(miisc);
1743 error = mii_mediachg(mii);
1744 BFE_UNLOCK(sc);
1745
1746 return (error);
1747 }
1748
1749 /*
1750 * Report current media status.
1751 */
1752 static void
bfe_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1753 bfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1754 {
1755 struct bfe_softc *sc = if_getsoftc(ifp);
1756 struct mii_data *mii;
1757
1758 BFE_LOCK(sc);
1759 mii = device_get_softc(sc->bfe_miibus);
1760 mii_pollstat(mii);
1761 ifmr->ifm_active = mii->mii_media_active;
1762 ifmr->ifm_status = mii->mii_media_status;
1763 BFE_UNLOCK(sc);
1764 }
1765
1766 static int
bfe_ioctl(if_t ifp,u_long command,caddr_t data)1767 bfe_ioctl(if_t ifp, u_long command, caddr_t data)
1768 {
1769 struct bfe_softc *sc = if_getsoftc(ifp);
1770 struct ifreq *ifr = (struct ifreq *) data;
1771 struct mii_data *mii;
1772 int error = 0;
1773
1774 switch (command) {
1775 case SIOCSIFFLAGS:
1776 BFE_LOCK(sc);
1777 if (if_getflags(ifp) & IFF_UP) {
1778 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1779 bfe_set_rx_mode(sc);
1780 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1781 bfe_init_locked(sc);
1782 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1783 bfe_stop(sc);
1784 BFE_UNLOCK(sc);
1785 break;
1786 case SIOCADDMULTI:
1787 case SIOCDELMULTI:
1788 BFE_LOCK(sc);
1789 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1790 bfe_set_rx_mode(sc);
1791 BFE_UNLOCK(sc);
1792 break;
1793 case SIOCGIFMEDIA:
1794 case SIOCSIFMEDIA:
1795 mii = device_get_softc(sc->bfe_miibus);
1796 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1797 break;
1798 default:
1799 error = ether_ioctl(ifp, command, data);
1800 break;
1801 }
1802
1803 return (error);
1804 }
1805
1806 static void
bfe_watchdog(struct bfe_softc * sc)1807 bfe_watchdog(struct bfe_softc *sc)
1808 {
1809 if_t ifp;
1810
1811 BFE_LOCK_ASSERT(sc);
1812
1813 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1814 return;
1815
1816 ifp = sc->bfe_ifp;
1817
1818 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1819
1820 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1821 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1822 bfe_init_locked(sc);
1823
1824 if (!if_sendq_empty(ifp))
1825 bfe_start_locked(ifp);
1826 }
1827
1828 static void
bfe_tick(void * xsc)1829 bfe_tick(void *xsc)
1830 {
1831 struct bfe_softc *sc = xsc;
1832 struct mii_data *mii;
1833
1834 BFE_LOCK_ASSERT(sc);
1835
1836 mii = device_get_softc(sc->bfe_miibus);
1837 mii_tick(mii);
1838 bfe_stats_update(sc);
1839 bfe_watchdog(sc);
1840 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1841 }
1842
1843 /*
1844 * Stop the adapter and free any mbufs allocated to the
1845 * RX and TX lists.
1846 */
1847 static void
bfe_stop(struct bfe_softc * sc)1848 bfe_stop(struct bfe_softc *sc)
1849 {
1850 if_t ifp;
1851
1852 BFE_LOCK_ASSERT(sc);
1853
1854 ifp = sc->bfe_ifp;
1855 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1856 sc->bfe_flags &= ~BFE_FLAG_LINK;
1857 callout_stop(&sc->bfe_stat_co);
1858 sc->bfe_watchdog_timer = 0;
1859
1860 bfe_chip_halt(sc);
1861 bfe_tx_ring_free(sc);
1862 bfe_rx_ring_free(sc);
1863 }
1864
1865 static int
sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)1866 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1867 {
1868 struct bfe_softc *sc;
1869 struct bfe_hw_stats *stats;
1870 int error, result;
1871
1872 result = -1;
1873 error = sysctl_handle_int(oidp, &result, 0, req);
1874
1875 if (error != 0 || req->newptr == NULL)
1876 return (error);
1877
1878 if (result != 1)
1879 return (error);
1880
1881 sc = (struct bfe_softc *)arg1;
1882 stats = &sc->bfe_stats;
1883
1884 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1885 printf("Transmit good octets : %ju\n",
1886 (uintmax_t)stats->tx_good_octets);
1887 printf("Transmit good frames : %ju\n",
1888 (uintmax_t)stats->tx_good_frames);
1889 printf("Transmit octets : %ju\n",
1890 (uintmax_t)stats->tx_octets);
1891 printf("Transmit frames : %ju\n",
1892 (uintmax_t)stats->tx_frames);
1893 printf("Transmit broadcast frames : %ju\n",
1894 (uintmax_t)stats->tx_bcast_frames);
1895 printf("Transmit multicast frames : %ju\n",
1896 (uintmax_t)stats->tx_mcast_frames);
1897 printf("Transmit frames 64 bytes : %ju\n",
1898 (uint64_t)stats->tx_pkts_64);
1899 printf("Transmit frames 65 to 127 bytes : %ju\n",
1900 (uint64_t)stats->tx_pkts_65_127);
1901 printf("Transmit frames 128 to 255 bytes : %ju\n",
1902 (uint64_t)stats->tx_pkts_128_255);
1903 printf("Transmit frames 256 to 511 bytes : %ju\n",
1904 (uint64_t)stats->tx_pkts_256_511);
1905 printf("Transmit frames 512 to 1023 bytes : %ju\n",
1906 (uint64_t)stats->tx_pkts_512_1023);
1907 printf("Transmit frames 1024 to max bytes : %ju\n",
1908 (uint64_t)stats->tx_pkts_1024_max);
1909 printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1910 printf("Transmit oversized frames : %ju\n",
1911 (uint64_t)stats->tx_oversize_frames);
1912 printf("Transmit fragmented frames : %ju\n",
1913 (uint64_t)stats->tx_frag_frames);
1914 printf("Transmit underruns : %u\n", stats->tx_colls);
1915 printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1916 printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1917 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1918 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1919 printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1920 printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1921 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1922 printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1923
1924 printf("Receive good octets : %ju\n",
1925 (uintmax_t)stats->rx_good_octets);
1926 printf("Receive good frames : %ju\n",
1927 (uintmax_t)stats->rx_good_frames);
1928 printf("Receive octets : %ju\n",
1929 (uintmax_t)stats->rx_octets);
1930 printf("Receive frames : %ju\n",
1931 (uintmax_t)stats->rx_frames);
1932 printf("Receive broadcast frames : %ju\n",
1933 (uintmax_t)stats->rx_bcast_frames);
1934 printf("Receive multicast frames : %ju\n",
1935 (uintmax_t)stats->rx_mcast_frames);
1936 printf("Receive frames 64 bytes : %ju\n",
1937 (uint64_t)stats->rx_pkts_64);
1938 printf("Receive frames 65 to 127 bytes : %ju\n",
1939 (uint64_t)stats->rx_pkts_65_127);
1940 printf("Receive frames 128 to 255 bytes : %ju\n",
1941 (uint64_t)stats->rx_pkts_128_255);
1942 printf("Receive frames 256 to 511 bytes : %ju\n",
1943 (uint64_t)stats->rx_pkts_256_511);
1944 printf("Receive frames 512 to 1023 bytes : %ju\n",
1945 (uint64_t)stats->rx_pkts_512_1023);
1946 printf("Receive frames 1024 to max bytes : %ju\n",
1947 (uint64_t)stats->rx_pkts_1024_max);
1948 printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1949 printf("Receive oversized frames : %ju\n",
1950 (uint64_t)stats->rx_oversize_frames);
1951 printf("Receive fragmented frames : %ju\n",
1952 (uint64_t)stats->rx_frag_frames);
1953 printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1954 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1955 printf("Receive undersized frames : %u\n", stats->rx_runts);
1956 printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1957 printf("Receive align errors : %u\n", stats->rx_align_errs);
1958 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1959 printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1960 printf("Receive control frames : %u\n", stats->rx_control_frames);
1961
1962 return (error);
1963 }
1964