1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
5 * Copyright (c) 2023, Emmanuel Vadot <manu@freebsd.org>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/rman.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <machine/bus.h>
36
37 #include <dev/fdt/simplebus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #include <dev/clk/clk_div.h>
43 #include <dev/clk/clk_fixed.h>
44 #include <dev/clk/clk_mux.h>
45
46 #include <dev/clk/rockchip/rk_cru.h>
47 #include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h>
48
49
50 #define RK3568_PLLSEL_CON(x) ((x) * 0x20)
51 #define CRU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
52 #define CRU_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
53 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
54
55 #define RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd) \
56 { \
57 .freq = _hz, \
58 .refdiv = _ref, \
59 .fbdiv = _fb, \
60 .postdiv1 = _post1, \
61 .postdiv2 = _post2, \
62 .dsmpd = _dspd, \
63 }
64
65 /* PLL clock */
66 #define RK_PLL(_id, _name, _pnames, _off, _shift) \
67 { \
68 .type = RK3328_CLK_PLL, \
69 .clk.pll = &(struct rk_clk_pll_def) { \
70 .clkdef.id = _id, \
71 .clkdef.name = _name, \
72 .clkdef.parent_names = _pnames, \
73 .clkdef.parent_cnt = nitems(_pnames), \
74 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
75 .base_offset = RK3568_PLLSEL_CON(_off), \
76 .mode_reg = 0xc0, \
77 .mode_shift = _shift, \
78 .rates = rk3568_pll_rates, \
79 }, \
80 }
81
82 struct rk_clk_pll_rate rk3568_pll_rates[] = {
83 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */
84 RK_PLLRATE(2208000000, 1, 92, 1, 1, 1),
85 RK_PLLRATE(2184000000, 1, 91, 1, 1, 1),
86 RK_PLLRATE(2160000000, 1, 90, 1, 1, 1),
87 RK_PLLRATE(2088000000, 1, 87, 1, 1, 1),
88 RK_PLLRATE(2064000000, 1, 86, 1, 1, 1),
89 RK_PLLRATE(2040000000, 1, 85, 1, 1, 1),
90 RK_PLLRATE(2016000000, 1, 84, 1, 1, 1),
91 RK_PLLRATE(1992000000, 1, 83, 1, 1, 1),
92 RK_PLLRATE(1920000000, 1, 80, 1, 1, 1),
93 RK_PLLRATE(1896000000, 1, 79, 1, 1, 1),
94 RK_PLLRATE(1800000000, 1, 75, 1, 1, 1),
95 RK_PLLRATE(1704000000, 1, 71, 1, 1, 1),
96 RK_PLLRATE(1608000000, 1, 67, 1, 1, 1),
97 RK_PLLRATE(1600000000, 3, 200, 1, 1, 1),
98 RK_PLLRATE(1584000000, 1, 132, 2, 1, 1),
99 RK_PLLRATE(1560000000, 1, 130, 2, 1, 1),
100 RK_PLLRATE(1536000000, 1, 128, 2, 1, 1),
101 RK_PLLRATE(1512000000, 1, 126, 2, 1, 1),
102 RK_PLLRATE(1488000000, 1, 124, 2, 1, 1),
103 RK_PLLRATE(1464000000, 1, 122, 2, 1, 1),
104 RK_PLLRATE(1440000000, 1, 120, 2, 1, 1),
105 RK_PLLRATE(1416000000, 1, 118, 2, 1, 1),
106 RK_PLLRATE(1400000000, 3, 350, 2, 1, 1),
107 RK_PLLRATE(1392000000, 1, 116, 2, 1, 1),
108 RK_PLLRATE(1368000000, 1, 114, 2, 1, 1),
109 RK_PLLRATE(1344000000, 1, 112, 2, 1, 1),
110 RK_PLLRATE(1320000000, 1, 110, 2, 1, 1),
111 RK_PLLRATE(1296000000, 1, 108, 2, 1, 1),
112 RK_PLLRATE(1272000000, 1, 106, 2, 1, 1),
113 RK_PLLRATE(1248000000, 1, 104, 2, 1, 1),
114 RK_PLLRATE(1200000000, 1, 100, 2, 1, 1),
115 RK_PLLRATE(1188000000, 1, 99, 2, 1, 1),
116 RK_PLLRATE(1104000000, 1, 92, 2, 1, 1),
117 RK_PLLRATE(1100000000, 3, 275, 2, 1, 1),
118 RK_PLLRATE(1008000000, 1, 84, 2, 1, 1),
119 RK_PLLRATE(1000000000, 3, 250, 2, 1, 1),
120 RK_PLLRATE(912000000, 1, 76, 2, 1, 1),
121 RK_PLLRATE(816000000, 1, 68, 2, 1, 1),
122 RK_PLLRATE(800000000, 3, 200, 2, 1, 1),
123 RK_PLLRATE(700000000, 3, 350, 4, 1, 1),
124 RK_PLLRATE(696000000, 1, 116, 4, 1, 1),
125 RK_PLLRATE(600000000, 1, 100, 4, 1, 1),
126 RK_PLLRATE(594000000, 1, 99, 4, 1, 1),
127 RK_PLLRATE(500000000, 1, 125, 6, 1, 1),
128 RK_PLLRATE(408000000, 1, 68, 2, 2, 1),
129 RK_PLLRATE(312000000, 1, 78, 6, 1, 1),
130 RK_PLLRATE(216000000, 1, 72, 4, 2, 1),
131 RK_PLLRATE(200000000, 1, 100, 3, 4, 1),
132 RK_PLLRATE(148500000, 1, 99, 4, 4, 1),
133 RK_PLLRATE(100000000, 1, 150, 6, 6, 1),
134 RK_PLLRATE(96000000, 1, 96, 6, 4, 1),
135 RK_PLLRATE(74250000, 2, 99, 4, 4, 1),
136 {},
137 };
138
139 static struct rk_clk_armclk_rates rk3568_armclk_rates[] = {
140 {2208000000, 1},
141 {2160000000, 1},
142 {2064000000, 1},
143 {2016000000, 1},
144 {1992000000, 1},
145 {1800000000, 1},
146 {1704000000, 1},
147 {1608000000, 1},
148 {1512000000, 1},
149 {1488000000, 1},
150 {1416000000, 1},
151 {1200000000, 1},
152 {1104000000, 1},
153 {1008000000, 1},
154 { 816000000, 1},
155 { 696000000, 1},
156 { 600000000, 1},
157 { 408000000, 1},
158 { 312000000, 1},
159 { 216000000, 1},
160 { 96000000, 1},
161 {},
162 };
163
164 /* Parent clock defines */
165 PLIST(mux_pll_p) = { "xin24m" };
166 PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
167 PLIST(mux_armclk_p) = { "apll", "gpll" };
168 PLIST(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac",
169 "i2s0_mclkin", "xin_osc0_half" };
170 PLIST(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac",
171 "i2s0_mclkin", "xin_osc0_half" };
172 PLIST(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac",
173 "i2s1_mclkin", "xin_osc0_half" };
174 PLIST(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac",
175 "i2s1_mclkin", "xin_osc0_half" };
176 PLIST(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac",
177 "i2s2_mclkin", "xin_osc0_half"};
178 PLIST(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac",
179 "i2s3_mclkin", "xin_osc0_half" };
180 PLIST(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac",
181 "i2s3_mclkin", "xin_osc0_half" };
182 PLIST(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
183 PLIST(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
184 PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
185 PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
186 PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
187 PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
188 PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
189 PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
190 PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
191 PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
192 PLIST(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
193 PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
194 PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
195 PLIST(npll_gpll_p) = { "npll", "gpll" };
196 PLIST(cpll_gpll_p) = { "cpll", "gpll" };
197 PLIST(gpll_cpll_p) = { "gpll", "cpll" };
198 PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
199 PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
200 PLIST(sclk_core_pre_p) = { "sclk_core_src", "npll" };
201 PLIST(gpll150_gpll100_gpll75_xin24m_p) = { "clk_gpll_div_150m", "clk_gpll_div_100m", "clk_gpll_div_75m",
202 "xin24m" };
203 PLIST(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
204 PLIST(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"};
205 PLIST(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
206 PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
207 PLIST(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
208 PLIST(gpll200_gpll150_gpll100_xin24m_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m",
209 "clk_gpll_div_100m", "xin24m" };
210 PLIST(gpll100_gpll75_gpll50_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m" };
211 PLIST(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
212 PLIST(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
213 PLIST(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
214 PLIST(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
215 PLIST(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
216 PLIST(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
217 PLIST(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
218 PLIST(mclk_pdm_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", "clk_gpll_div_200m", "clk_gpll_div_100m" };
219 PLIST(clk_i2c_p) = { "clk_gpll_div_200m", "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };
220 PLIST(gpll200_gpll150_gpll100_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_gpll_div_100m" };
221 PLIST(gpll300_gpll200_gpll100_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", "clk_gpll_div_100m" };
222 PLIST(clk_nandc_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", "xin24m" };
223 PLIST(sclk_sfc_p) = { "xin24m", "clk_cpll_div_50m", "clk_gpll_div_75m", "clk_gpll_div_100m",
224 "clk_cpll_div_125m", "clk_gpll_div_150m" };
225 PLIST(gpll200_gpll150_cpll125_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_125m" };
226 PLIST(cclk_emmc_p) = { "xin24m", "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m",
227 "clk_cpll_div_50m", "clk_osc0_div_375k" };
228 PLIST(aclk_pipe_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_gpll_div_200m", "xin24m" };
229 PLIST(gpll200_cpll125_p) = { "clk_gpll_div_200m", "clk_cpll_div_125m" };
230 PLIST(gpll300_gpll200_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m",
231 "clk_gpll_div_100m", "xin24m" };
232 PLIST(clk_sdmmc_p) = { "xin24m", "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_cpll_div_100m",
233 "clk_cpll_div_50m", "clk_osc0_div_750k" };
234 PLIST(cpll125_cpll50_cpll25_xin24m_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m",
235 "xin24m" };
236 PLIST(clk_gmac_ptp_p) = { "clk_cpll_div_62P5m", "clk_gpll_div_100m", "clk_cpll_div_50m", "xin24m" };
237 PLIST(cpll333_gpll300_gpll200_p) = { "clk_cpll_div_333m", "clk_gpll_div_300m", "clk_gpll_div_200m" };
238 PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
239 PLIST(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
240 PLIST(gpll300_cpll250_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m",
241 "clk_gpll_div_100m", "xin24m" };
242 PLIST(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
243 PLIST(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
244 PLIST(gpll400_cpll333_gpll200_p) = { "clk_gpll_div_400m", "clk_cpll_div_333m", "clk_gpll_div_200m" };
245 PLIST(gpll100_gpll75_cpll50_xin24m_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m",
246 "xin24m" };
247 PLIST(xin24m_gpll100_cpll100_p) = { "xin24m", "clk_gpll_div_100m", "clk_cpll_div_100m" };
248 PLIST(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
249 PLIST(gpll100_xin24m_cpll100_p) = { "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };
250 PLIST(gpll200_xin24m_cpll100_p) = { "clk_gpll_div_200m", "xin24m", "clk_cpll_div_100m" };
251 PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
252 PLIST(cpll500_gpll400_gpll300_xin24m_p) = { "clk_cpll_div_500m", "clk_gpll_div_400m",
253 "clk_gpll_div_300m", "xin24m" };
254 PLIST(gpll400_gpll300_gpll200_xin24m_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m",
255 "clk_gpll_div_200m", "xin24m" };
256 PLIST(xin24m_cpll100_p) = { "xin24m", "clk_cpll_div_100m" };
257 PLIST(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
258 PLIST(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0",
259 "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
260 PLIST(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
261 PLIST(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed",
262 "clk_gmac0_xpcs_mii" };
263 PLIST(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
264 PLIST(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1",
265 "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
266 PLIST(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
267 PLIST(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed",
268 "clk_gmac1_xpcs_mii" };
269 PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" };
270 PLIST(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
271 PLIST(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" };
272
273 /* CLOCKS */
274 static struct rk_clk rk3568_clks[] = {
275 /* External clocks */
276 LINK("xin24m"),
277 LINK("clk_rtc_32k"),
278 LINK("usb480m_phy"),
279 LINK("mpll"), /* It lives in SCRU */
280 LINK("i2s0_mclkin"),
281 LINK("i2s1_mclkin"),
282 LINK("i2s2_mclkin"),
283 LINK("i2s3_mclkin"),
284 LINK("gpu_pvtpll_out"),
285 LINK("npu_pvtpll_out"),
286 LINK("gmac0_clkin"),
287 LINK("gmac1_clkin"),
288 LINK("clk_gmac0_xpcs_mii"),
289 LINK("clk_gmac1_xpcs_mii"),
290 LINK("dummy"),
291
292 /* PLL's */
293 RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0),
294 RK_PLL(PLL_DPLL, "dpll", mux_pll_p, 1, 2),
295 RK_PLL(PLL_GPLL, "gpll", mux_pll_p, 2, 6),
296 RK_PLL(PLL_CPLL, "cpll", mux_pll_p, 3, 4),
297 RK_PLL(PLL_NPLL, "npll", mux_pll_p, 4, 10),
298 RK_PLL(PLL_VPLL, "vpll", mux_pll_p, 5, 12),
299 ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5,
300 6, 1, 0, 1),
301 FFACT(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2),
302 FFACT(0, "xin_osc0_half", "xin24m", 1, 2),
303 MUX(USB480M, "usb480m", mux_usb480m_p, 0, -16, 14, 2),
304
305 /* Clocks */
306
307 /* CRU_CLKSEL_CON00 */
308 /* 0:4 clk_core0_div DIV */
309 /* 5 Reserved */
310 /* 6 clk_core_i_sel MUX */
311 /* 7 clk_core_ndft_sel MUX */
312 /* 8:12 clk_core1_div DIV */
313 /* 13:14 Reserved */
314 /* 15 clk_core_ndft_mux_sel MUX */
315
316 /* CRU_CLKSEL_CON01 */
317 /* 0:4 clk_core2_div DIV */
318 /* 5:7 Reserved */
319 /* 8:12 clk_core3_div DIV */
320 /* 13:15 Reserved */
321
322 /* CRU_CLKSEL_CON02 */
323 COMP(0, "sclk_core_src_c", apll_gpll_npll_p, 0, 2, 0, 4, 8, 2),
324 /* 4:7 Reserved */
325 /* 10:14 Reserved */
326 MUX(0, "sclk_core_pre_sel", sclk_core_pre_p, 0, 2, 15, 1),
327
328 /* CRU_CLKSEL_CON03 */
329 CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5),
330 /* 5:7 Reserved */
331 CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5),
332 /* 13:15 Reserved */
333
334 /* CRU_CLKSEL_CON04 */
335 CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5),
336 /* 5:7 Reserved */
337 CDIV(0, "periphclk_core_pre_div", "armclk", 0, 4, 8, 5),
338 /* 13:15 Reserved */
339
340 /* CRU_CLKSEL_CON05 */
341 /* 0:7 Reserved */
342 /* 8:12 aclk_core_ndft_div DIV */
343 /* 13 Reserved */
344 /* 14:15 aclk_core_biu2bus_sel MUX */
345
346 /* CRU_CLKSEL_CON06 */
347 COMP(0, "clk_gpu_pre_c", mpll_gpll_cpll_npll_p, 0, 6, 0, 4, 6, 2),
348 /* 4:5 Reserved */
349 CDIV(0, "aclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 8, 2),
350 /* 10 Reserved */
351 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux_sel", clk_gpu_pre_mux_p, 0, 6, 11, 1),
352 CDIV(0, "pclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 12, 4),
353
354 /* CRU_CLKSEL_CON07 */
355 COMP(0, "clk_npu_src_c", npll_gpll_p, 0, 7, 0, 4, 6, 1),
356 COMP(0, "clk_npu_np5_c", npll_gpll_p, 0, 7, 4, 2, 7, 1),
357 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 0, 7,
358 8, 1),
359 /* 9:14 Reserved */
360 MUX(CLK_NPU, "clk_npu", clk_npu_p, 0, 7, 15, 1),
361
362 /* CRU_CLKSEL_CON08 */
363 CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4),
364 CDIV(0, "pclk_npu_pre_div", "clk_npu", 0, 8, 4, 4),
365 /* 8:15 Reserved */
366
367 /* CRU_CLKSEL_CON09 */
368 COMP(0, "clk_ddrphy1x_src_c", dpll_gpll_cpll_p, 0, 9, 0, 5, 6, 2),
369 /* 5 Reserved */
370 /* 8:14 Reserved */
371 MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, RK_CLK_COMPOSITE_GRF, 9,
372 15, 1),
373
374 /* CRU_CLKSEL_CON10 */
375 CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2),
376 MUX(0, "aclk_perimid_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 10, 4, 2),
377 MUX(0, "hclk_perimid_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 6, 2),
378 MUX(0, "aclk_gic_audio_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 10, 8, 2),
379 MUX(0, "hclk_gic_audio_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 10, 2),
380 MUX(0, "dclk_sdmmc_buffer_sel", gpll100_gpll75_gpll50_p, 0, 10, 12, 2),
381 /* 14:15 Reserved */
382
383 /* CRU_CLKSEL_CON11 */
384 COMP(0, "clk_i2s0_8ch_tx_src_c", gpll_cpll_npll_p, 0, 11, 0, 7, 8, 2),
385 /* 7 Reserved */
386 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 0, 11, 10,
387 2),
388 /* 12:14 Reserved */
389 MUX(0, "i2s0_mclkout_tx_sel", i2s0_mclkout_tx_p, 0, 11, 15, 1),
390
391 /* CRU_CLKSEL_CON12 */
392 FRACT(0, "clk_i2s0_8ch_tx_frac_div", "clk_i2s0_8ch_tx_src", 0, 12),
393
394 /* CRU_CLKSEL_CON13 */
395 COMP(0, "clk_i2s0_8ch_rx_src_c", gpll_cpll_npll_p, 0, 13, 0, 7, 8, 2),
396 /* 7 Reserved */
397 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 0, 13, 10,
398 2),
399 /* 12:14 Reserved */
400 MUX(0, "i2s0_mclkout_rx_sel", i2s0_mclkout_rx_p, 0, 13, 15, 1),
401
402 /* CRU_CLKSEL_CON14 */
403 FRACT(0, "clk_i2s0_8ch_rx_frac_div", "clk_i2s0_8ch_rx_src", 0, 14),
404
405 /* CRU_CLKSEL_CON15 */
406 COMP(0, "clk_i2s1_8ch_tx_src_c", gpll_cpll_npll_p, 0, 15, 0, 7, 8, 2),
407 /* 7 Reserved */
408 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 0, 15, 10,
409 2),
410 /* 12:14 Reserved */
411 MUX(0, "i2s1_mclkout_tx_sel", i2s1_mclkout_tx_p, 0, 11, 15, 1),
412
413 /* CRU_CLKSEL_CON16 */
414 FRACT(0, "clk_i2s1_8ch_tx_frac_div", "clk_i2s1_8ch_tx_src", 0, 16),
415
416 /* CRU_CLKSEL_CON17 */
417 COMP(0, "clk_i2s1_8ch_rx_src_c", gpll_cpll_npll_p, 0, 17, 0, 7, 8, 2),
418 /* 7 Reserved */
419 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 0, 17, 10,
420 2),
421 /* 12:14 Reserved */
422 MUX(0, "i2s1_mclkout_rx_sel", i2s1_mclkout_rx_p, 0, 17, 15, 1),
423
424 /* CRU_CLKSEL_CON18 */
425 FRACT(0, "clk_i2s1_8ch_rx_frac_div", "clk_i2s1_8ch_rx_src", 0, 18),
426
427 /* CRU_CLKSEL_CON19 */
428 COMP(0, "clk_i2s2_2ch_src_c", gpll_cpll_npll_p, 0, 19, 0, 7, 8, 2),
429 /* 7 Reserved */
430 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 0, 19, 10,
431 2),
432 /* 12:14 Reserved */
433 MUX(0, "i2s2_mclkout_sel", i2s2_mclkout_p, 0, 19, 15, 1),
434
435 /* CRU_CLKSEL_CON20 */
436 FRACT(0, "clk_i2s2_2ch_frac_div", "clk_i2s2_2ch_src", 0, 20),
437
438 /* CRU_CLKSEL_CON21 */
439 COMP(0, "clk_i2s3_2ch_tx_src_c", gpll_cpll_npll_p, 0, 21, 0, 7, 8, 2),
440 /* 7 Reserved */
441 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 0, 21, 10,
442 2),
443 /* 12:14 Reserved */
444 MUX(0, "i2s3_mclkout_tx_sel", i2s3_mclkout_tx_p, 0, 21, 15, 1),
445
446 /* CRU_CLKSEL_CON22 */
447 FRACT(0, "clk_i2s3_2ch_tx_frac_div", "clk_i2s3_2ch_tx_src", 0, 22),
448
449 /* CRU_CLKSEL_CON23 */
450 COMP(0, "mclk_spdif_8ch_src_c", cpll_gpll_p, 0, 23, 0, 7, 14, 1),
451 /* 7 Reserved */
452 MUX(0, "mclk_pdm_sel", mclk_pdm_p, 0, 23, 8, 2),
453 MUX(0, "clk_acdcdig_i2c_sel", clk_i2c_p, 0, 23, 10, 2),
454 /* 12:13 Reserved */
455 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 0, 23, 15,
456 1),
457
458 /* CRU_CLKSEL_CON24 */
459 FRACT(0, "mclk_spdif_8ch_frac_div", "mclk_spdif_8ch_src", 0, 24),
460
461 /* CRU_CLKSEL_CON25 */
462 COMP(0, "sclk_audpwm_src_c", gpll_cpll_p, 0, 25, 0, 5, 14, 1),
463 /* 6:13 Reserved */
464 MUX(SCLK_AUDPWM, "sck_audpwm_sel", sclk_audpwm_p, 0, 25, 15, 1),
465
466 /* CRU_CLKSEL_CON26 */
467 FRACT(0, "sclk_audpwm_frac_frac", "sclk_audpwm_src", 0, 26),
468
469 /* CRU_CLKSEL_CON27 */
470 MUX(0, "aclk_secure_flash_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 27, 0, 2),
471 MUX(0, "hclk_secure_flash_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 27, 2, 2),
472 MUX(0, "clk_crypto_ns_core_sel", gpll200_gpll150_gpll100_p, 0, 27, 4, 2),
473 MUX(0, "clk_crypto_ns_pka_sel", gpll300_gpll200_gpll100_p, 0, 27, 6, 2),
474 /* 8:15 Reserved */
475
476 /* CRU_CLKSEL_CON28 */
477 MUX(0, "nclk_nandc_sel", clk_nandc_p, 0, 28, 0, 2),
478 /* 2:3 Reserved */
479 MUX(0, "sclk_sfc_sel", sclk_sfc_p, 0, 28, 4, 3),
480 /* 7 Reserved */
481 MUX(0, "bclk_emmc_sel", gpll200_gpll150_cpll125_p, 0, 28, 8, 2),
482 /* 10:11 Reserved */
483 MUX(0, "cclk_emmc_sel", cclk_emmc_p, 0, 28, 12, 3),
484 /* 15 Reserved */
485
486 /* CRU_CLKSEL_CON29 */
487 MUX(0, "aclk_pipe_sel", aclk_pipe_p, 0, 29, 0, 2),
488 /* 2:3 Reserved */
489 CDIV(0, "pclk_pipe_div", "aclk_pipe", 0, 29, 4, 4),
490 MUX(0, "clk_usb3otg0_suspend_sel", xin24m_32k_p, 0, 29, 8, 1),
491 MUX(0, "clk_usb3otg1_suspend_sel", xin24m_32k_p, 0, 29, 9, 1),
492 /* 10:12 Reserved */
493 MUX(0, "clk_xpcs_eee_sel", gpll200_cpll125_p, 0, 29, 13, 1),
494 /* 14:15 Reserved */
495
496 /* CRU_CLKSEL_CON30 */
497 MUX(0, "aclk_php_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 30, 0, 2),
498 MUX(0, "hclk_php_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 30, 2, 2),
499 CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4),
500 MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p, 0, 30, 8, 3),
501 /* 11 Reserved */
502 MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p, 0, 30, 12, 3),
503 /* 15 Reserved */
504
505 /* CRU_CLKSEL_CON31 */
506 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 0, 31,
507 0, 2),
508 MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 0, 31, 2, 1),
509 MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed",
510 mux_gmac0_rmii_speed_p, 0, 31, 3, 1),
511 MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed",
512 mux_gmac0_rgmii_speed_p, 0, 31, 4, 2),
513 MUX(0, "clk_mac0_2top_sel", clk_mac_2top_p, 0, 31, 8, 2),
514 MUX(0, "clk_gmac0_ptp_ref_sel", clk_gmac_ptp_p, 0, 31, 12, 2),
515 MUX(0, "clk_mac0_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 31, 14, 2),
516
517 FFACT(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5),
518 FFACT(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50),
519 FFACT(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2),
520 FFACT(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20),
521
522 /* CRU_CLKSEL_CON32 */
523 MUX(0, "aclk_usb_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 32, 0, 2),
524 MUX(0, "hclk_usb_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 32, 4, 2),
525 CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4),
526 MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p, 0, 32, 8, 3),
527 /* 11:15 Reserved */
528
529 /* CRU_CLKSEL_CON33 */
530 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 0, 33,
531 0, 2),
532 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 0, 33, 2, 1),
533 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed",
534 mux_gmac1_rmii_speed_p, 0, 33, 3, 1),
535 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed",
536 mux_gmac1_rgmii_speed_p, 0, 33, 4, 2),
537 /* 6:7 Reserved */
538 MUX(0, "clk_mac1_2top_sel", clk_mac_2top_p, 0, 33, 8, 2),
539 MUX(0, "clk_gmac1_ptp_ref_sel", clk_gmac_ptp_p, 0, 33, 12, 2),
540 MUX(0, "clk_mac1_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 33, 14, 2),
541
542 FFACT(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5),
543 FFACT(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50),
544 FFACT(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2),
545 FFACT(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20),
546
547 /* CRU_CLKSEL_CON34 */
548 MUX(0, "aclk_vi_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 34, 0, 2),
549 /* 2:3 Reserved */
550 CDIV(0, "hclk_vi_div", "aclk_vi", 0, 34, 4, 4),
551 CDIV(0, "pclk_vi_div", "aclk_vi", 0, 34, 8, 4),
552 /* 12:13 Reserved */
553 MUX(0, "dclk_vicap1_sel", cpll333_gpll300_gpll200_p, 0, 34, 14, 2),
554
555 /* CRU_CLKSEL_CON35 */
556 COMP(0, "clk_isp_c", cpll_gpll_hpll_p, 0, 35, 0, 5, 6, 2),
557 /* 5 Reserved */
558 COMP(0, "clk_cif_out_c", gpll_usb480m_xin24m_p, 0, 35, 8, 6, 14, 2),
559
560 /* CRU_CLKSEL_CON36 */
561 COMP(0, "clk_cam0_out_c", gpll_usb480m_xin24m_p, 0, 36, 0, 6, 6, 2),
562 COMP(0, "clk_cam1_out_c", gpll_usb480m_xin24m_p, 0, 36, 8, 6, 14, 2),
563
564 /* CRU_CLKSEL_CON37 */
565 MUX(0, "aclk_vo_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 37, 0, 2),
566 /* 2:7 Reserved */
567 CDIV(0, "hclk_vo_div", "aclk_vo", 0, 37, 8, 4),
568 CDIV(0, "pclk_vo_div", "aclk_vo", 0, 37, 12, 4),
569
570 /* CRU_CLKSEL_CON38 */
571 COMP(0, "aclk_vop_pre_c", cpll_gpll_hpll_vpll_p, 0, 38, 0, 5, 6, 2),
572 /* 5 Reserved */
573 MUX(0, "clk_edp_200m_sel", gpll200_gpll150_cpll125_p, 0, 38, 8, 2),
574 /* 10:15 Reserved */
575
576 /* CRU_CLKSEL_CON39 */
577 COMP(0, "dclk_vop0_c", hpll_vpll_gpll_cpll_p, 0, 39, 0, 8, 10, 2),
578 /* 12:15 Reserved */
579
580 /* CRU_CLKSEL_CON40 */
581 COMP(0, "dclk_vop1_c", hpll_vpll_gpll_cpll_p, 0, 40, 0, 8, 10, 2),
582 /* 12:15 Reserved */
583
584 /* CRU_CLKSEL_CON41 */
585 COMP(0, "dclk_vop2_c", hpll_vpll_gpll_cpll_p, 0, 41, 0, 8, 10, 2),
586 /* 12:15 Reserved */
587
588 /* CRU_CLKSEL_CON42 */
589 COMP(0, "aclk_vpu_pre_c", gpll_cpll_p, 0, 42, 0, 5, 7, 1),
590 /* 5:6 Reserved */
591 CDIV(0, "hclk_vpu_pre_div", "aclk_vpu_pre", 0, 42, 8, 4),
592 /* 12:15 Reserved */
593
594 /* CRU_CLKSEL_CON43 */
595 MUX(0, "aclk_rga_pre_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 43, 0, 2),
596 MUX(0, "clk_rga_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 2, 2),
597 MUX(0, "clk_iep_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 4, 2),
598 MUX(0, "dclk_ebc_sel", gpll400_cpll333_gpll200_p, 0, 43, 6, 2),
599 CDIV(0, "hclk_rga_pre_div", "aclk_rga_pre", 0, 43, 8, 4),
600 CDIV(0, "pclk_rga_pre_div", "aclk_rga_pre", 0, 43, 12, 4),
601
602 /* CRU_CLKSEL_CON44 */
603 COMP(0, "aclk_rkvenc_pre_c", gpll_cpll_npll_p, 0, 44, 0, 5, 6, 2),
604 /* 5 Reserved */
605 CDIV(0, "hclk_rkvenc_pre_div", "aclk_rkvenc_pre", 0, 44, 8, 4),
606 /* 12:15 Reserved */
607
608 /* CRU_CLKSEL_CON45 */
609 COMP(0, "clk_rkvenc_core_c", gpll_cpll_npll_vpll_p, 0, 45, 0, 5, 14, 2),
610 /* 5:13 Reserved */
611
612 /* CRU_CLKSEL_CON46 */
613
614 /* CRU_CLKSEL_CON47 */
615 COMP(0, "aclk_rkvdec_pre_c", aclk_rkvdec_pre_p, 0, 47, 0, 5, 7, 1),
616 /* 5:6 Reserved */
617 CDIV(0, "hclk_rkvdec_pre_div", "aclk_rkvdec_pre", 0, 47, 8, 4),
618 /* 12:15 Reserved */
619
620 /* CRU_CLKSEL_CON48 */
621 COMP(0, "clk_rkvdec_ca_c", gpll_cpll_npll_vpll_p, 0, 48, 0, 5, 6, 2),
622 /* 5 Reserved */
623 /* 8:15 Reserved */
624
625 /* CRU_CLKSEL_CON49 */
626 COMP(0, "clk_rkvdec_hevc_ca_c", gpll_cpll_npll_vpll_p, 0, 49, 0, 5, 6, 2),
627 /* 5 Reserved */
628 COMP(0, "clk_rkvdec_core_c", clk_rkvdec_core_p, 0, 49, 8, 5, 14, 2),
629 /* 13 Reserved */
630
631 /* CRU_CLKSEL_CON50 */
632 MUX(0, "aclk_bus_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 50, 0, 2),
633 /* 2:3 Reserved */
634 MUX(0, "pclk_bus_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 50, 4, 2),
635 /* 6:15 Reserved */
636
637 /* CRU_CLKSEL_CON51 */
638 COMP(0, "clk_tsadc_tsen_c", xin24m_gpll100_cpll100_p, 0, 51, 0, 3, 4, 2),
639 /* 6:7 Reserved */
640 CDIV(0, "clk_tsadc_div", "clk_tsadc_tsen", 0, 51, 8, 7),
641 /* 15 Reserved */
642
643 /* CRU_CLKSEL_CON52 */
644 COMP(0, "clk_uart1_src_c", gpll_cpll_usb480m_p, 0, 52, 0, 7, 8, 2),
645 /* 7 Reserved */
646 /* 10:11 Reserved */
647 MUX(0, "sclk_uart1_sel", sclk_uart1_p, 0, 52, 12, 2),
648
649 /* CRU_CLKSEL_CON53 */
650 FRACT(0, "clk_uart1_frac_frac", "clk_uart1_src", 0, 53),
651
652 /* CRU_CLKSEL_CON54 */
653 COMP(0, "clk_uart2_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2),
654 /* 7 Reserved */
655 /* 10:11 Reserved */
656 MUX(0, "sclk_uart2_sel", sclk_uart2_p, 0, 52, 12, 2),
657
658 /* CRU_CLKSEL_CON55 */
659 FRACT(0, "clk_uart2_frac_frac", "clk_uart2_src", 0, 55),
660
661 /* CRU_CLKSEL_CON56 */
662 COMP(0, "clk_uart3_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2),
663 /* 7 Reserved */
664 /* 10:11 Reserved */
665 MUX(0, "sclk_uart3_sel", sclk_uart3_p, 0, 56, 12, 2),
666
667 /* CRU_CLKSEL_CON57 */
668 FRACT(0, "clk_uart3_frac_frac", "clk_uart3_src", 0, 57),
669
670 /* CRU_CLKSEL_CON58 */
671 COMP(0, "clk_uart4_src_c", gpll_cpll_usb480m_p, 0, 58, 0, 7, 8, 2),
672 /* 7 Reserved */
673 /* 10:11 Reserved */
674 MUX(0, "sclk_uart4_sel", sclk_uart4_p, 0, 58, 12, 2),
675
676 /* CRU_CLKSEL_CON59 */
677 FRACT(0, "clk_uart4_frac_frac", "clk_uart4_src", 0, 59),
678
679 /* CRU_CLKSEL_CON60 */
680 COMP(0, "clk_uart5_src_c", gpll_cpll_usb480m_p, 0, 60, 0, 7, 8, 2),
681 /* 7 Reserved */
682 /* 10:11 Reserved */
683 MUX(0, "sclk_uart5_sel", sclk_uart5_p, 0, 60, 12, 2),
684
685 /* CRU_CLKSEL_CON61 */
686 FRACT(0, "clk_uart5_frac_frac", "clk_uart5_src", 0, 61),
687
688 /* CRU_CLKSEL_CON62 */
689 COMP(0, "clk_uart6_src_c", gpll_cpll_usb480m_p, 0, 62, 0, 7, 8, 2),
690 /* 7 Reserved */
691 /* 10:11 Reserved */
692 MUX(0, "sclk_uart6_sel", sclk_uart6_p, 0, 62, 12, 2),
693
694 /* CRU_CLKSEL_CON63 */
695 FRACT(0, "clk_uart6_frac_frac", "clk_uart6_src", 0, 63),
696
697 /* CRU_CLKSEL_CON64 */
698 COMP(0, "clk_uart7_src_c", gpll_cpll_usb480m_p, 0, 64, 0, 7, 8, 2),
699 /* 7 Reserved */
700 /* 10:11 Reserved */
701 MUX(0, "sclk_uart7_sel", sclk_uart7_p, 0, 64, 12, 2),
702
703 /* CRU_CLKSEL_CON65 */
704 FRACT(0, "clk_uart7_frac_frac", "clk_uart7_src", 0, 65),
705
706 /* CRU_CLKSEL_CON66 */
707 COMP(0, "clk_uart8_src_c", gpll_cpll_usb480m_p, 0, 66, 0, 7, 8, 2),
708 /* 7 Reserved */
709 /* 10:11 Reserved */
710 MUX(0, "sclk_uart8_sel", sclk_uart8_p, 0, 66, 12, 2),
711
712 /* CRU_CLKSEL_CON67 */
713 FRACT(0, "clk_uart8_frac_frac", "clk_uart8_src", 0, 67),
714
715 /* CRU_CLKSEL_CON68 */
716 COMP(0, "clk_uart9_src_c", gpll_cpll_usb480m_p, 0, 68, 0, 7, 8, 2),
717 /* 7 Reserved */
718 /* 10:11 Reserved */
719 MUX(0, "sclk_uart9_sel", sclk_uart9_p, 0, 68, 12, 2),
720
721 /* CRU_CLKSEL_CON69 */
722 FRACT(0, "clk_uart9_frac_frac", "clk_uart9_src", 0, 69),
723
724 /* CRU_CLKSEL_CON70 */
725 COMP(0, "clk_can0_c", gpll_cpll_p, 0, 70, 0, 5, 7, 1),
726 /* 5:6 Reserved */
727 COMP(0, "clk_can1_c", gpll_cpll_p, 0, 70, 8, 5, 15, 1),
728 /* 13:14 Reserved */
729
730 /* CRU_CLKSEL_CON71 */
731 COMP(0, "clk_can2_c", gpll_cpll_p, 0, 71, 0, 5, 7, 1),
732 /* 5:6 Reserved */
733 MUX(0, "clk_i2c_sel", clk_i2c_p, 0, 71, 8, 2),
734 /* 10:15 Reserved */
735
736 /* CRU_CLKSEL_CON72 */
737 MUX(0, "clk_spi0_sel", gpll200_xin24m_cpll100_p, 0, 72, 0, 2),
738 MUX(0, "clk_spi1_sel", gpll200_xin24m_cpll100_p, 0, 72, 2, 2),
739 MUX(0, "clk_spi2_sel", gpll200_xin24m_cpll100_p, 0, 72, 4, 2),
740 MUX(0, "clk_spi3_sel", gpll200_xin24m_cpll100_p, 0, 72, 6, 2),
741 MUX(0, "clk_pwm1_sel", gpll100_xin24m_cpll100_p, 0, 72, 8, 2),
742 MUX(0, "clk_pwm2_sel", gpll100_xin24m_cpll100_p, 0, 72, 10, 2),
743 MUX(0, "clk_pwm3_sel", gpll100_xin24m_cpll100_p, 0, 72, 12, 2),
744 MUX(0, "dbclk_gpio_sel", xin24m_32k_p, 0, 72, 14, 1),
745 /* 15 Reserved */
746
747 /* CRU_CLKSEL_CON73 */
748 MUX(0, "aclk_top_high_sel", cpll500_gpll400_gpll300_xin24m_p, 0, 73, 0, 2),
749 /* 2:3 Reserved */
750 MUX(0, "aclk_top_low_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 73, 4, 2),
751 /* 6:7 Reserved */
752 MUX(0, "hclk_top_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 73, 8, 2),
753 /* 10:11 Reserved */
754 MUX(0, "pclk_top_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 73, 12, 2),
755 /* 14 Reserved */
756 MUX(0, "clk_optc_arb_sel", xin24m_cpll100_p, 0, 73, 15 , 1),
757
758 /* CRU_CLKSEL_CON74 */
759 /* 0:7 clk_testout_div CDIV */
760 /* 8:12 clk_testout_sel MUX */
761
762 /* CRU_CLKSEL_CON75 */
763 CDIV(0, "clk_gpll_div_400m_div", "gpll", 0, 75, 0, 5),
764 CDIV(0, "clk_gpll_div_300m_div", "gpll", 0, 75, 8, 5),
765
766 /* CRU_CLKSEL_CON76 */
767 CDIV(0, "clk_gpll_div_200m_div", "gpll", 0, 76, 0, 5),
768 CDIV(0, "clk_gpll_div_150m_div", "gpll", 0, 76, 8, 5),
769
770 /* CRU_CLKSEL_CON77 */
771 CDIV(0, "clk_gpll_div_100m_div", "gpll", 0, 77, 0, 5),
772 CDIV(0, "clk_gpll_div_75m_div", "gpll", 0, 77, 8, 5),
773
774 /* CRU_CLKSEL_CON78 */
775 CDIV(0, "clk_gpll_div_20m_div", "gpll", 0, 78, 0, 6),
776 CDIV(0, "clk_cpll_div_500m_div", "cpll", 0, 78, 8, 5),
777
778 /* CRU_CLKSEL_CON79 */
779 CDIV(0, "clk_cpll_div_333m_div", "cpll", 0, 79, 0, 6),
780 CDIV(0, "clk_cpll_div_250m_div", "cpll", 0, 79, 8, 5),
781
782 /* CRU_CLKSEL_CON80 */
783 CDIV(0, "clk_cpll_div_125m_div", "cpll", 0, 80, 0, 6),
784 CDIV(0, "clk_cpll_div_62P5m_div", "cpll", 0, 80, 8, 5),
785
786 /* CRU_CLKSEL_CON81 */
787 CDIV(0, "clk_cpll_div_50m_div", "cpll", 0, 81, 0, 6),
788 CDIV(0, "clk_cpll_div_25m_div", "cpll", 0, 81, 8, 5),
789
790 /* CRU_CLKSEL_CON82 */
791 CDIV(0, "clk_cpll_div_100m_div", "cpll", 0, 82, 0, 6),
792 CDIV(0, "clk_osc0_div_750k_div", "xin24m", 0, 82, 8, 5),
793
794 /* CRU_CLKSEL_CON83 */
795 CDIV(0, "clk_i2s3_2ch_rx_src_div", "clk_i2s3_2ch_rx_src_sel", 0, 83, 0, 7),
796 /* 7 Reserved */
797 MUX(0, "clk_i2s3_2ch_rx_src_sel", gpll_cpll_npll_p, 0, 83, 8, 2),
798 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 0, 83, 10,
799 2),
800 /* 12:14 Reserved */
801 MUX(0, "i2s3_mclkout_rx_sel", i2s3_mclkout_rx_p, 0, 83, 15, 1),
802
803 /* CRU_CLKSEL_CON84 */
804 FRACT(0, "clk_i2s3_2ch_rx_frac_div", "clk_i2s3_2ch_rx_src", 0, 84),
805 };
806
807 /* GATES */
808 static struct rk_cru_gate rk3568_gates[] = {
809 /* CRU_CLKGATE_CON00 */
810 /* 0 clk_core */
811 /* 1 clk_core0 */
812 /* 2 clk_core1 */
813 /* 3 clk_core2 */
814 /* 4 clk_core3 */
815 GATE(0, "sclk_core_src", "sclk_core_src_c", 0, 5),
816 /* 6 clk_npll_core */
817 /* 7 sclk_core */
818 GATE(0, "atclk_core", "atclk_core_div", 0, 8),
819 GATE(0, "gicclk_core", "gicclk_core_div", 0, 9),
820 GATE(0, "pclk_core_pre", "pclk_core_pre_div", 0, 10),
821 GATE(0, "periphclk_core_pre", "periphclk_core_pre_div", 0, 11),
822 /* 12 pclk_core */
823 /* 13 periphclk_core */
824 /* 14 tsclk_core */
825 /* 15 cntclk_core */
826
827 /* CRU_CLKGATE_CON01 */
828 /* 0 aclk_core */
829 /* 1 aclk_core_biuddr */
830 /* 2 aclk_core_biu2bus */
831 /* 3 pclk_dgb_biu */
832 /* 4 pclk_dbg */
833 /* 5 pclk_dbg_daplite */
834 /* 6 aclk_adb400_core2gic */
835 /* 7 aclk_adb400_gic2core */
836 /* 8 pclk_core_grf */
837 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9),
838 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10),
839 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11),
840 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12),
841 /* 13 clk_core_div2 */
842 /* 14 clk_apll_core */
843 /* 15 clk_jtag */
844
845 /* CRU_CLKGATE_CON02 */
846 /* 0 clk_gpu_src */
847 GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0),
848 /* 1 Reserved */
849 GATE(PCLK_GPU_PRE, "pclk_gpu_pre", "pclk_gpu_pre_div", 2, 2),
850 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_c", 2, 3),
851 /* 4 aclk_gpu_biu */
852 /* 5 pclk_gpu_biu */
853 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6),
854 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7),
855 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8),
856 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9),
857 /* 10 clk_gpu_div2 */
858 GATE(ACLK_GPU_PRE, "aclk_gpu_pre", "aclk_gpu_pre_div", 2, 11),
859 /* 12:15 Reserved */
860
861 /* CRU_CLKGATE_CON03 */
862 GATE(CLK_NPU_SRC, "clk_npu_src", "clk_npu_src_c", 3, 0),
863 GATE(CLK_NPU_NP5, "clk_npu_np5", "clk_npu_np5_c", 3, 1),
864 GATE(HCLK_NPU_PRE, "hclk_npu_pre", "hclk_npu_pre_div", 3, 2),
865 GATE(PCLK_NPU_PRE, "pclk_npu_pre", "pclk_npu_pre_div", 3, 3),
866 /* 4 aclk_npu_biu */
867 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4),
868 /* 5 hclk_npu_biu */
869 /* 6 pclk_npu_biu */
870 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7),
871 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8),
872 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9),
873 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10),
874 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft",3, 11),
875 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12),
876 /* 13 clk_npu_div2 */
877 /* 14:15 Reserved */
878
879 /* CRU_CLKGATE_CON04 */
880 GATE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", "clk_ddrphy1x_src_c", 4, 0),
881 /* 1 clk_dpll_ddr */
882 GATE(CLK_MSCH, "clk_msch", "clk_msch_div", 4, 2),
883 /* 3 clk_hwffc_ctrl */
884 /* 4 aclk_ddrscramble */
885 /* 5 aclk_msch */
886 /* 6 clk_ddr_alwayson */
887 /* 7 Reserved */
888 /* 8 aclk_ddrsplit */
889 /* 9 clk_ddrdft_ctl */
890 /* 10 Reserved */
891 /* 11 aclk_dma2ddr */
892 /* 12 Reserved */
893 /* 13 clk_ddrmon */
894 /* 14 Reserved */
895 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15),
896
897 /* CRU_CLKGATE_CON05 */
898 GATE(ACLK_GIC_AUDIO, "aclk_gic_audio", "aclk_gic_audio_sel", 5, 0),
899 GATE(HCLK_GIC_AUDIO, "hclk_gic_audio", "hclk_gic_audio_sel", 5, 1),
900 /* 2 aclk_gic_audio_biu */
901 /* 3 hclk_gic_audio_biu */
902 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4),
903 /* 5 aclk_gicadb_core2gic */
904 /* 6 aclk_gicadb_gic2core */
905 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7),
906 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8),
907 GATE(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", "dclk_sdmmc_buffer_sel", 5, 9),
908 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10),
909 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11),
910 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12),
911 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13),
912 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14),
913 GATE(MCLK_PDM, "mclk_pdm", "mclk_pdm_sel", 5, 15),
914
915 /* CRU_CLKGATE_CON06 */
916 GATE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_src_c", 6, 0),
917 GATE(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_frac_div", 6, 1),
918 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2),
919 GATE(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", "i2s0_mclkout_tx_sel", 6, 3),
920 GATE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_src_c", 6, 4),
921 GATE(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_frac_div", 6, 5),
922 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6),
923 GATE(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", "i2s0_mclkout_rx_sel", 6, 7),
924 GATE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_src_c", 6, 8),
925 GATE(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_frac_div", 6, 9),
926 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10),
927 GATE(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", "i2s1_mclkout_tx_sel", 6, 11),
928 GATE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_src_c", 6, 12),
929 GATE(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_frac_div", 6, 13),
930 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14),
931 GATE(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", "i2s1_mclkout_rx_sel", 6, 15),
932
933 /* CRU_CLKGATE_CON07 */
934 GATE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "clk_i2s2_2ch_src_c", 7, 0),
935 GATE(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_frac_div", 7, 1),
936 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2),
937 GATE(I2S2_MCLKOUT, "i2s2_mclkout", "i2s2_mclkout_sel", 7, 3),
938 GATE(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_src_c", 7, 4),
939 GATE(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_frac_div", 7, 5),
940 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6),
941 GATE(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", "i2s3_mclkout_tx_sel", 7, 7),
942 GATE(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_src_div", 7, 8),
943 GATE(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_frac_div", 7, 9),
944 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10),
945 GATE(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", "i2s3_mclkout_rx_sel", 7, 11),
946 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12),
947 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13),
948 GATE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", "mclk_spdif_8ch_src_c", 7, 14),
949 GATE(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_frac_div", 7, 15),
950
951 /* CRU_CLKGATE_CON08 */
952 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0),
953 GATE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", "sclk_audpwm_src_c", 8, 1),
954 GATE(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_frac_frac", 8, 2),
955 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3),
956 GATE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", "clk_acdcdig_i2c_sel", 8, 4),
957 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5),
958 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6),
959 GATE(ACLK_SECURE_FLASH, "aclk_secure_flash", "aclk_secure_flash_sel", 8, 7),
960 GATE(HCLK_SECURE_FLASH, "hclk_secure_flash", "hclk_secure_flash_sel", 8, 8),
961 /* 9 aclk_secure_flash_biu */
962 /* 10 hclk_secure_flash_biu */
963 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11),
964 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12),
965 GATE(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", "clk_crypto_ns_core_sel", 8, 13),
966 GATE(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", "clk_crypto_ns_pka_sel", 8, 14),
967 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 8, 15),
968
969 /* CRU_CLKGATE_CON09 */
970 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0),
971 GATE(NCLK_NANDC, "nclk_nandc", "nclk_nandc_sel", 9, 1),
972 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2),
973 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3),
974 GATE(SCLK_SFC, "sclk_sfc", "sclk_sfc_sel", 9, 4),
975 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5),
976 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6),
977 GATE(BCLK_EMMC, "bclk_emmc", "bclk_emmc_sel", 9, 7),
978 GATE(CCLK_EMMC, "cclk_emmc", "cclk_emmc_sel", 9, 8),
979 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9),
980 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10),
981 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11),
982 /* 12:15 Reserved */
983
984 /* CRU_CLKGATE_CON10 */
985 GATE(ACLK_PIPE, "aclk_pipe", "aclk_pipe_sel", 10, 0),
986 GATE(PCLK_PIPE, "pclk_pipe", "pclk_pipe_div", 10, 1),
987 /* 2 aclk_pipe_biu */
988 /* 3 pclk_pipe_biu */
989 GATE(CLK_XPCS_EEE, "clk_xpcs_eee", "clk_xpcs_eee_sel", 10, 4),
990 /* 5 clk_xpcs_rx_div10 */
991 /* 6 clk_xpcs_tx_div10 */
992 /* 7 pclk_pipe_grf */
993 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8),
994 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9),
995 GATE(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_sel", 10, 10),
996 /* 11 clk_usb3otg0_pipe */
997 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12),
998 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13),
999 GATE(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_sel", 10, 14),
1000 /* 15 clk_usb3otg1_pipe */
1001
1002 /* CRU_CLKGATE_CON11 */
1003 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0),
1004 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "clk_gpll_div_20m", 11, 1),
1005 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "clk_cpll_div_50m", 11, 2),
1006 /* 3 clk_sata0_pipe */
1007 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4),
1008 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "clk_gpll_div_20m", 11, 5),
1009 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "clk_cpll_div_50m", 11, 6),
1010 /* 7 clk_sata1_pipe */
1011 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8),
1012 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "clk_gpll_div_20m", 11, 9),
1013 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "clk_cpll_div_50m", 11, 10),
1014 /* 11 clk_sata2_pipe */
1015 /* 12:15 Reserved */
1016
1017 /* CRU_CLKGATE_CON12 */
1018 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0),
1019 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1),
1020 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2),
1021 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3),
1022 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4),
1023 /* 5 clk_pcie20_pipe */
1024 /* 6:7 Reserved */
1025 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8),
1026 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9),
1027 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10),
1028 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11),
1029 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 12, 12),
1030 /* 13 clk_pcie30x1_pipe */
1031 /* 14:15 Reserved */
1032
1033 /* CRU_CLKGATE_CON13 */
1034 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0),
1035 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1),
1036 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2),
1037 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3),
1038 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 13, 4),
1039 /* 5 clk_pcie30x2_pipe */
1040 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6),
1041 /* 7 clk_xpcs_qsgmii_tx */
1042 /* 8 clk_xpcs_qsgmii_rx */
1043 /* 9 clk_xpcs_xgxs_tx */
1044 /* 10 Reserved */
1045 /* 11 clk_xpcs_xgxs_rx */
1046 /* 12 clk_xpcs_mii0_tx */
1047 /* 13 clk_xpcs_mii0_rx */
1048 /* 14 clk_xpcs_mii1_tx */
1049 /* 15 clk_xpcs_mii1_rx */
1050
1051 /* CRU_CLKGATE_CON14 */
1052 GATE(ACLK_PERIMID, "aclk_perimid", "aclk_perimid_sel", 14, 0),
1053 GATE(HCLK_PERIMID, "hclk_perimid", "hclk_perimid_sel", 14, 1),
1054 /* 2 aclk_perimid_biu */
1055 /* 3 hclk_perimid_biu */
1056 /* 4:7 Reserved */
1057 GATE(ACLK_PHP, "aclk_php", "aclk_php_sel", 14, 8),
1058 GATE(HCLK_PHP, "hclk_php", "hclk_php_sel", 14, 9),
1059 GATE(PCLK_PHP, "pclk_php", "pclk_php_div", 14, 10),
1060 /* 11 aclk_php_biu */
1061 /* 12 hclk_php_biu */
1062 /* 13 pclk_php_biu */
1063 /* 14:15 Reserved */
1064
1065 /* CRU_CLKGATE_CON15 */
1066 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0),
1067 GATE(CLK_SDMMC0, "clk_sdmmc0", "clk_sdmmc0_sel", 15, 1),
1068 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2),
1069 GATE(CLK_SDMMC1, "clk_sdmmc1", "clk_sdmmc1_sel", 15, 3),
1070 GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_sel", 15, 4),
1071 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5),
1072 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6),
1073 GATE(CLK_MAC0_2TOP, "clk_mac0_2top", "clk_mac0_2top_sel", 15, 7),
1074 GATE(CLK_MAC0_OUT, "clk_mac0_out", "clk_mac0_out_sel", 15, 8),
1075 /* 9:11 Reserved */
1076 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12),
1077 /* 13:15 Reserved */
1078
1079 /* CRU_CLKGATE_CON16 */
1080 GATE(ACLK_USB, "aclk_usb", "aclk_usb_sel", 16, 0),
1081 GATE(HCLK_USB, "hclk_usb", "hclk_usb_sel", 16, 1),
1082 GATE(PCLK_USB, "pclk_usb", "pclk_usb_div", 16, 2),
1083 /* 3 aclk_usb_biu */
1084 /* 4 hclk_usb_biu */
1085 /* 5 pclk_usb_biu */
1086 /* 6 pclk_usb_grf */
1087 /* 7:11 Reserved */
1088 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12),
1089 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13),
1090 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14),
1091 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15),
1092
1093 /* CRU_CLKGATE_CON17 */
1094 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0),
1095 GATE(CLK_SDMMC2, "clk_sdmmc2", "clk_sdmmc2_sel", 17, 1),
1096 GATE(CLK_GMAC1_PTP_REF, "clK_gmac1_ptp_ref", "clk_gmac1_ptp_ref_sel", 17, 2),
1097 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3),
1098 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4),
1099 GATE(CLK_MAC1_2TOP, "clk_mac1_2top", "clk_mac1_2top_sel", 17, 5),
1100 GATE(CLK_MAC1_OUT, "clk_mac1_out", "clk_mac1_out_sel", 17, 6),
1101 /* 7:9 Reserved */
1102 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10),
1103 /* 11:15 Reserved */
1104
1105 /* CRU_CLKGATE_CON18 */
1106 GATE(ACLK_VI, "aclk_vi", "aclk_vi_sel", 18, 0),
1107 GATE(HCLK_VI, "hclk_vi", "hclk_vi_div", 18, 1),
1108 GATE(PCLK_VI, "pclk_vi", "pclk_vi_div", 18, 2),
1109 /* 3 aclk_vi_biu */
1110 /* 4 hclk_vi_biu */
1111 /* 5 pclk_vi_biu */
1112 /* 6:8 Reserved */
1113 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9),
1114 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10),
1115 GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap1_sel", 18, 11),
1116 /* 12:15 Reserved */
1117
1118 /* CRU_CLKGATE_CON19 */
1119 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0),
1120 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1),
1121 GATE(CLK_ISP, "clk_isp", "clk_isp_c", 19, 2),
1122 /* 3 Reserved */
1123 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4),
1124 /* 5:7 Reserved */
1125 GATE(CLK_CIF_OUT, "clk_cif_out", "clk_cif_out_c", 19, 8),
1126 GATE(CLK_CAM0_OUT, "clk_cam0_out", "clk_cam0_out_c", 19, 9),
1127 GATE(CLK_CAM1_OUT, "clk_cam1_out", "clk_cam1_out_c", 19, 9),
1128 /* 11:15 Reserved */
1129
1130 /* CRU_CLKGATE_CON20 */
1131 /* 0 Reserved or aclk_vo ??? */
1132 GATE(ACLK_VO, "aclk_vo", "aclk_vo_sel", 20, 0),
1133 GATE(HCLK_VO, "hclk_vo", "hclk_vo_div", 20, 1),
1134 GATE(PCLK_VO, "pclk_vo", "pclk_vo_div", 20, 2),
1135 /* 3 aclk_vo_biu */
1136 /* 4 hclk_vo_biu */
1137 /* 5 pclk_vo_biu */
1138 GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 20, 6),
1139 /* 7 aclk_vop_biu */
1140 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8),
1141 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9),
1142 GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_c", 20, 10),
1143 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_c", 20, 11),
1144 GATE(DCLK_VOP2, "dclk_vop2", "dclk_vop2_c", 20, 12),
1145 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13),
1146 /* 14:15 Reserved */
1147
1148 /* CRU_CLKGATE_CON21 */
1149 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0),
1150 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1),
1151 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2),
1152 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3),
1153 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4),
1154 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5),
1155 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6),
1156 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7),
1157 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8),
1158 GATE(CLK_EDP_200M, "clk_edp_200m", "clk_edp_200m_sel", 21, 9),
1159 /* 10:15 Reserved */
1160
1161 /* CRU_CLKGATE_CON22 */
1162 GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 22, 0),
1163 GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre_c", 22, 1),
1164 /* 2 aclk_vpu_biu */
1165 /* 3 hclk_vpu_biu */
1166 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4),
1167 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5),
1168 /* 6:11 Reserved */
1169 GATE(PCLK_RGA_PRE, "pclk_rga_pre", "pclk_rga_pre_div", 22, 12),
1170 /* 13 pclk_rga_biu */
1171 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14),
1172 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15),
1173
1174 /* CRU_CLKGATE_CON23 */
1175 GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_sel", 23, 0),
1176 GATE(HCLK_RGA_PRE, "hclk_rga_pre", "hclk_rga_pre_div", 23, 1),
1177 /* 2 aclk_rga_biu */
1178 /* 3 hclk_rga_biu */
1179 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4),
1180 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5),
1181 GATE(CLK_RGA_CORE, "clk_rga_core", "clk_rga_core_sel", 23, 6),
1182 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7),
1183 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8),
1184 GATE(CLK_IEP_CORE, "clk_iep_core", "clk_iep_core_sel", 23, 9),
1185 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10),
1186 GATE(DCLK_EBC, "dclk_ebc", "dclk_ebc_sel", 23, 11),
1187 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12),
1188 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13),
1189 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14),
1190 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15),
1191
1192 /* CRU_CLKGATE_CON24 */
1193 GATE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", "aclk_rkvenc_pre_c", 24, 0),
1194 GATE(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "hclk_rkvenc_pre_div", 24, 1),
1195 /* 2 Reserved */
1196 /* 3 aclk_rkvenc_biu */
1197 /* 4 hclk_rkvenc_biu */
1198 /* 5 Reserved */
1199 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6),
1200 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7),
1201 GATE(CLK_RKVENC_CORE, "clk_rkvenc_core", "clk_rkvenc_core_c", 24, 8),
1202 /* 9:15 Reserved */
1203
1204 /* CRU_CLKGATE_CON25 */
1205 GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_pre_c", 25, 0),
1206 GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "hclk_rkvdec_pre_div", 25, 1),
1207 /* 2 aclk_rkvdec_biu */
1208 /* 3 hclk_rkvdec_biu */
1209 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4),
1210 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5),
1211 GATE(CLK_RKVDEC_CA, "clk_rkvdec_ca", "clk_rkvdec_ca_c", 25, 6),
1212 GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "clk_rkvdec_core_c", 25, 7),
1213 GATE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", "clk_rkvdec_hevc_ca_c", 25, 8),
1214 /* 9:15 Reserved */
1215
1216 /* CRU_CLKGATE_CON26 */
1217 GATE(ACLK_BUS, "aclk_bus", "aclk_bus_sel", 26, 0),
1218 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_sel", 26, 1),
1219 /* 2 aclk_bus_biu */
1220 /* 3 pclk_bus_biu */
1221 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4),
1222 GATE(CLK_TSADC_TSEN, "clk_tsadc_tsen", "clk_tsadc_tsen_c", 26, 5),
1223 GATE(CLK_TSADC, "clk_tsadc", "clk_tsadc_div", 26, 6),
1224 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7),
1225 GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8),
1226 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9),
1227 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10),
1228 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11),
1229 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12),
1230 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13),
1231 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14),
1232 /* 15 Reserved */
1233
1234 /* CRU_CLKGATE_CON27 */
1235 /* 0 pclk_grf */
1236 /* 1 pclk_grf_vccio12 */
1237 /* 2 pclk_grf_vccio34 */
1238 /* 3 pclk_grf_vccio567 */
1239 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5),
1240 GATE(CLK_CAN0, "clk_can0", "clk_can0_c", 27, 6),
1241 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7),
1242 GATE(CLK_CAN1, "clk_can1", "clk_can1_c", 27, 8),
1243 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9),
1244 GATE(CLK_CAN2, "clk_can2", "clk_can2_c", 27, 10),
1245 /* 11 Reserved */
1246 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12),
1247 GATE(CLK_UART1_SRC, "clk_uart1_src", "clk_uart1_src_c", 27, 13),
1248 GATE(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_frac_frac", 27, 14),
1249 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_sel", 27, 15),
1250
1251 /* CRU_CLKGATE_CON28 */
1252 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0),
1253 GATE(CLK_UART2_SRC, "clk_uart2_src", "clk_uart2_src_c", 28, 1),
1254 GATE(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_frac_frac", 28, 2),
1255 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_sel", 28, 3),
1256 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4),
1257 GATE(CLK_UART3_SRC, "clk_uart3_src", "clk_uart3_src_c", 28, 5),
1258 GATE(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_frac_frac", 28, 6),
1259 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_sel", 28, 7),
1260 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8),
1261 GATE(CLK_UART4_SRC, "clk_uart4_src", "clk_uart4_src_c", 28, 9),
1262 GATE(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_frac_frac", 28, 10),
1263 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_sel", 28, 11),
1264 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12),
1265 GATE(CLK_UART5_SRC, "clk_uart5_src", "clk_uart5_src_c", 28, 13),
1266 GATE(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_frac_frac", 28, 14),
1267 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_sel", 28, 15),
1268
1269 /* CRU_CLKGATE_CON29 */
1270 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0),
1271 GATE(CLK_UART6_SRC, "clk_uart6_src", "clk_uart6_src_c", 29, 1),
1272 GATE(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_frac_frac", 29, 2),
1273 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_sel", 29, 3),
1274 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4),
1275 GATE(CLK_UART7_SRC, "clk_uart7_src", "clk_uart7_src_c", 29, 5),
1276 GATE(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_frac_frac", 29, 6),
1277 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_sel", 29, 7),
1278 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8),
1279 GATE(CLK_UART8_SRC, "clk_uart8_src", "clk_uart8_src_c", 29, 9),
1280 GATE(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_frac_frac", 29, 10),
1281 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_sel", 29, 11),
1282 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12),
1283 GATE(CLK_UART9_SRC, "clk_uart9_src", "clk_uart9_src_c", 29, 13),
1284 GATE(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_frac_frac", 29, 14),
1285 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_sel", 29, 15),
1286
1287 /* CRU_CLKGATE_CON30 */
1288 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0),
1289 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1),
1290 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2),
1291 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3),
1292 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4),
1293 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5),
1294 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6),
1295 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7),
1296 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8),
1297 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9),
1298 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10),
1299 GATE(CLK_SPI0, "clk_spi0", "clk_spi0_sel", 30, 11),
1300 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12),
1301 GATE(CLK_SPI1, "clk_spi1", "clk_spi1_sel", 30, 13),
1302 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14),
1303 GATE(CLK_SPI2, "clk_spi2", "clk_spi2_sel", 30, 15),
1304
1305 /* CRU_CLKGATE_CON31 */
1306 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0),
1307 GATE(CLK_SPI3, "clk_spi3", "clk_spi3_sel", 31, 1),
1308 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2),
1309 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3),
1310 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4),
1311 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5),
1312 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6),
1313 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7),
1314 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8),
1315 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9),
1316 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10),
1317 GATE(CLK_PWM1, "clk_pwm1", "clk_pwm1_sel", 31, 11),
1318 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12),
1319 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13),
1320 GATE(CLK_PWM2, "clk_pwm2", "clk_pwm2_sel", 31, 14),
1321 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15),
1322
1323 /* CRU_CLKGATE_CON32 */
1324 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0),
1325 GATE(CLK_PWM3, "clk_pwm3", "clk_pwm3_sel", 32, 1),
1326 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2),
1327 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3),
1328 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4),
1329 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5),
1330 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6),
1331 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7),
1332 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8),
1333 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9),
1334 GATE(CLK_I2C, "clk_i2c", "clk_i2c_sel", 32, 10),
1335 GATE(DBCLK_GPIO, "dbclk_gpio", "dbclk_gpio_sel", 32, 11),
1336 /* 12 clk_timer */
1337 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13),
1338 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14),
1339 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15),
1340
1341 /* CRU_CLKGATE_CON33 */
1342 GATE(ACLK_TOP_HIGH, "aclk_top_high", "aclk_top_high_sel", 33, 0),
1343 GATE(ACLK_TOP_LOW, "aclk_top_low", "aclk_top_low_sel", 33, 1),
1344 GATE(HCLK_TOP, "hclk_top", "hclk_top_sel", 33, 2),
1345 GATE(PCLK_TOP, "pclk_top", "pclk_top_sel", 33, 3),
1346 /* 4 aclk_top_high_biu */
1347 /* 5 aclk_top_low_biu */
1348 /* 6 hclk_top_biu */
1349 /* 7 pclk_top_biu */
1350 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8),
1351 GATE(CLK_OPTC_ARB, "clk_optc_arb", "clk_optc_arb_sel", 33, 9),
1352 /* 10:11 Reserved */
1353 /* 12 pclk_top_cru */
1354 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13),
1355 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14),
1356 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15),
1357
1358 /* CRU_CLKGATE_CON34 */
1359 /* 0 pclk_apb2asb_chip_left */
1360 /* 1 pclk_apb2asb_chip_bottom */
1361 /* 2 pclk_asb2apb_chip_left */
1362 /* 3 pclk_asb2apb_chip_bottom */
1363 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4),
1364 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5),
1365 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6),
1366 /* 7 pclk_usb2phy0_grf */
1367 /* 8 pclk_usb2phy1_grf */
1368 /* 9 pclk_ddrphy */
1369 /* 10 clk_ddrphy */
1370 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11),
1371 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12),
1372 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13),
1373 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14),
1374 /* 15 clk_testout */
1375
1376 /* CRU_CLKGATE_CON35 */
1377 GATE(0, "clk_gpll_div_400m", "clk_gpll_div_400m_div", 35, 0),
1378 GATE(0, "clk_gpll_div_300m", "clk_gpll_div_300m_div", 35, 1),
1379 GATE(0, "clk_gpll_div_200m", "clk_gpll_div_200m_div", 35, 2),
1380 GATE(0, "clk_gpll_div_150m", "clk_gpll_div_150m_div", 35, 3),
1381 GATE(0, "clk_gpll_div_100m", "clk_gpll_div_100m_div", 35, 4),
1382 GATE(0, "clk_gpll_div_75m", "clk_gpll_div_75m_div", 35, 5),
1383 GATE(0, "clk_gpll_div_20m", "clk_gpll_div_20m_div", 35, 6),
1384 GATE(CPLL_500M, "clk_cpll_div_500m", "clk_cpll_div_500m_div", 35, 7),
1385 GATE(CPLL_333M, "clk_cpll_div_333m", "clk_cpll_div_333m_div", 35, 8),
1386 GATE(CPLL_250M, "clk_cpll_div_250m", "clk_cpll_div_250m_div", 35, 9),
1387 GATE(CPLL_125M, "clk_cpll_div_125m", "clk_cpll_div_125m_div", 35, 10),
1388 GATE(CPLL_100M, "clk_cpll_div_100m", "clk_cpll_div_100m_div", 35, 11),
1389 GATE(CPLL_62P5M, "clk_cpll_div_62P5m", "clk_cpll_div_62P5m_div", 35, 12),
1390 GATE(CPLL_50M, "clk_cpll_div_50m", "clk_cpll_div_50m_div", 35, 13),
1391 GATE(CPLL_25M, "clk_cpll_div_25m", "clk_cpll_div_25m_div", 35, 14),
1392 GATE(0, "clk_osc0_div_750k", "clk_osc0_div_750k_div", 35, 15),
1393 };
1394
1395
1396 static int
rk3568_cru_probe(device_t dev)1397 rk3568_cru_probe(device_t dev)
1398 {
1399
1400 if (!ofw_bus_status_okay(dev))
1401 return (ENXIO);
1402
1403 if (ofw_bus_is_compatible(dev, "rockchip,rk3568-cru")) {
1404 device_set_desc(dev, "Rockchip RK3568 Clock & Reset Unit");
1405 return (BUS_PROBE_DEFAULT);
1406 }
1407 return (ENXIO);
1408 }
1409
1410 static int
rk3568_cru_attach(device_t dev)1411 rk3568_cru_attach(device_t dev)
1412 {
1413 struct rk_cru_softc *sc;
1414
1415 sc = device_get_softc(dev);
1416 sc->dev = dev;
1417 sc->clks = rk3568_clks;
1418 sc->nclks = nitems(rk3568_clks);
1419 sc->gates = rk3568_gates;
1420 sc->ngates = nitems(rk3568_gates);
1421 sc->reset_offset = 0x400;
1422 sc->reset_num = 478;
1423
1424 return (rk_cru_attach(dev));
1425 }
1426
1427 static device_method_t methods[] = {
1428 /* Device interface */
1429 DEVMETHOD(device_probe, rk3568_cru_probe),
1430 DEVMETHOD(device_attach, rk3568_cru_attach),
1431
1432 DEVMETHOD_END
1433 };
1434
1435 DEFINE_CLASS_1(rk3568_cru, rk3568_cru_driver, methods,
1436 sizeof(struct rk_cru_softc), rk_cru_driver);
1437
1438 EARLY_DRIVER_MODULE(rk3568_cru, simplebus, rk3568_cru_driver,
1439 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1440