xref: /freebsd/sys/dev/clk/rockchip/rk3568_cru.c (revision be82b3a0)
177f22241SEmmanuel Vadot /*-
277f22241SEmmanuel Vadot  * SPDX-License-Identifier: BSD-2-Clause
377f22241SEmmanuel Vadot  *
477f22241SEmmanuel Vadot  * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
577f22241SEmmanuel Vadot  * Copyright (c) 2023, Emmanuel Vadot <manu@freebsd.org>
677f22241SEmmanuel Vadot  *
777f22241SEmmanuel Vadot  * Redistribution and use in source and binary forms, with or without
877f22241SEmmanuel Vadot  * modification, are permitted provided that the following conditions
977f22241SEmmanuel Vadot  * are met:
1077f22241SEmmanuel Vadot  * 1. Redistributions of source code must retain the above copyright
1177f22241SEmmanuel Vadot  *    notice, this list of conditions and the following disclaimer.
1277f22241SEmmanuel Vadot  * 2. Redistributions in binary form must reproduce the above copyright
1377f22241SEmmanuel Vadot  *    notice, this list of conditions and the following disclaimer in the
1477f22241SEmmanuel Vadot  *    documentation and/or other materials provided with the distribution.
1577f22241SEmmanuel Vadot  *
1677f22241SEmmanuel Vadot  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
1777f22241SEmmanuel Vadot  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
1877f22241SEmmanuel Vadot  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
1977f22241SEmmanuel Vadot  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2077f22241SEmmanuel Vadot  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
2177f22241SEmmanuel Vadot  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2277f22241SEmmanuel Vadot  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
2377f22241SEmmanuel Vadot  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
2477f22241SEmmanuel Vadot  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2577f22241SEmmanuel Vadot  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2677f22241SEmmanuel Vadot  * SUCH DAMAGE.
2777f22241SEmmanuel Vadot  */
2877f22241SEmmanuel Vadot 
2977f22241SEmmanuel Vadot #include <sys/param.h>
3077f22241SEmmanuel Vadot #include <sys/systm.h>
3177f22241SEmmanuel Vadot #include <sys/bus.h>
3277f22241SEmmanuel Vadot #include <sys/rman.h>
3377f22241SEmmanuel Vadot #include <sys/kernel.h>
3477f22241SEmmanuel Vadot #include <sys/module.h>
3577f22241SEmmanuel Vadot #include <machine/bus.h>
3677f22241SEmmanuel Vadot 
3777f22241SEmmanuel Vadot #include <dev/fdt/simplebus.h>
3877f22241SEmmanuel Vadot 
3977f22241SEmmanuel Vadot #include <dev/ofw/ofw_bus.h>
4077f22241SEmmanuel Vadot #include <dev/ofw/ofw_bus_subr.h>
4177f22241SEmmanuel Vadot 
42be82b3a0SEmmanuel Vadot #include <dev/clk/clk_div.h>
43be82b3a0SEmmanuel Vadot #include <dev/clk/clk_fixed.h>
44be82b3a0SEmmanuel Vadot #include <dev/clk/clk_mux.h>
4577f22241SEmmanuel Vadot 
4677f22241SEmmanuel Vadot #include <dev/clk/rockchip/rk_cru.h>
4777f22241SEmmanuel Vadot #include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h>
4877f22241SEmmanuel Vadot 
4977f22241SEmmanuel Vadot 
5077f22241SEmmanuel Vadot #define	RK3568_PLLSEL_CON(x)		((x) * 0x20)
5177f22241SEmmanuel Vadot #define	CRU_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
5277f22241SEmmanuel Vadot #define	CRU_CLKGATE_CON(x)		((x) * 0x4 + 0x300)
5377f22241SEmmanuel Vadot #define	RK3568_SOFTRST_CON(x)		((x) * 0x4 + 0x400)
5477f22241SEmmanuel Vadot 
5577f22241SEmmanuel Vadot #define	RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd)		\
5677f22241SEmmanuel Vadot {									\
5777f22241SEmmanuel Vadot 	.freq = _hz,							\
5877f22241SEmmanuel Vadot 	.refdiv = _ref,							\
5977f22241SEmmanuel Vadot 	.fbdiv = _fb,							\
6077f22241SEmmanuel Vadot 	.postdiv1 = _post1,						\
6177f22241SEmmanuel Vadot 	.postdiv2 = _post2,						\
6277f22241SEmmanuel Vadot 	.dsmpd = _dspd,							\
6377f22241SEmmanuel Vadot }
6477f22241SEmmanuel Vadot 
6577f22241SEmmanuel Vadot /* PLL clock */
6677f22241SEmmanuel Vadot #define	RK_PLL(_id, _name, _pnames, _off, _shift)			\
6777f22241SEmmanuel Vadot {									\
6877f22241SEmmanuel Vadot 	.type = RK3328_CLK_PLL,						\
6977f22241SEmmanuel Vadot 	.clk.pll = &(struct rk_clk_pll_def) {				\
7077f22241SEmmanuel Vadot 		.clkdef.id = _id,					\
7177f22241SEmmanuel Vadot 		.clkdef.name = _name,					\
7277f22241SEmmanuel Vadot 		.clkdef.parent_names = _pnames,				\
7377f22241SEmmanuel Vadot 		.clkdef.parent_cnt = nitems(_pnames),			\
7477f22241SEmmanuel Vadot 		.clkdef.flags = CLK_NODE_STATIC_STRINGS,		\
7577f22241SEmmanuel Vadot 		.base_offset = RK3568_PLLSEL_CON(_off),			\
7677f22241SEmmanuel Vadot 		.mode_reg = 0xc0,					\
7777f22241SEmmanuel Vadot 		.mode_shift = _shift,					\
7877f22241SEmmanuel Vadot 		.rates = rk3568_pll_rates,				\
7977f22241SEmmanuel Vadot 	},								\
8077f22241SEmmanuel Vadot }
8177f22241SEmmanuel Vadot 
8277f22241SEmmanuel Vadot struct rk_clk_pll_rate rk3568_pll_rates[] = {
8377f22241SEmmanuel Vadot 	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */
8477f22241SEmmanuel Vadot 	RK_PLLRATE(2208000000, 1, 92, 1, 1, 1),
8577f22241SEmmanuel Vadot 	RK_PLLRATE(2184000000, 1, 91, 1, 1, 1),
8677f22241SEmmanuel Vadot 	RK_PLLRATE(2160000000, 1, 90, 1, 1, 1),
8777f22241SEmmanuel Vadot 	RK_PLLRATE(2088000000, 1, 87, 1, 1, 1),
8877f22241SEmmanuel Vadot 	RK_PLLRATE(2064000000, 1, 86, 1, 1, 1),
8977f22241SEmmanuel Vadot 	RK_PLLRATE(2040000000, 1, 85, 1, 1, 1),
9077f22241SEmmanuel Vadot 	RK_PLLRATE(2016000000, 1, 84, 1, 1, 1),
9177f22241SEmmanuel Vadot 	RK_PLLRATE(1992000000, 1, 83, 1, 1, 1),
9277f22241SEmmanuel Vadot 	RK_PLLRATE(1920000000, 1, 80, 1, 1, 1),
9377f22241SEmmanuel Vadot 	RK_PLLRATE(1896000000, 1, 79, 1, 1, 1),
9477f22241SEmmanuel Vadot 	RK_PLLRATE(1800000000, 1, 75, 1, 1, 1),
9577f22241SEmmanuel Vadot 	RK_PLLRATE(1704000000, 1, 71, 1, 1, 1),
9677f22241SEmmanuel Vadot 	RK_PLLRATE(1608000000, 1, 67, 1, 1, 1),
9777f22241SEmmanuel Vadot 	RK_PLLRATE(1600000000, 3, 200, 1, 1, 1),
9877f22241SEmmanuel Vadot 	RK_PLLRATE(1584000000, 1, 132, 2, 1, 1),
9977f22241SEmmanuel Vadot 	RK_PLLRATE(1560000000, 1, 130, 2, 1, 1),
10077f22241SEmmanuel Vadot 	RK_PLLRATE(1536000000, 1, 128, 2, 1, 1),
10177f22241SEmmanuel Vadot 	RK_PLLRATE(1512000000, 1, 126, 2, 1, 1),
10277f22241SEmmanuel Vadot 	RK_PLLRATE(1488000000, 1, 124, 2, 1, 1),
10377f22241SEmmanuel Vadot 	RK_PLLRATE(1464000000, 1, 122, 2, 1, 1),
10477f22241SEmmanuel Vadot 	RK_PLLRATE(1440000000, 1, 120, 2, 1, 1),
10577f22241SEmmanuel Vadot 	RK_PLLRATE(1416000000, 1, 118, 2, 1, 1),
10677f22241SEmmanuel Vadot 	RK_PLLRATE(1400000000, 3, 350, 2, 1, 1),
10777f22241SEmmanuel Vadot 	RK_PLLRATE(1392000000, 1, 116, 2, 1, 1),
10877f22241SEmmanuel Vadot 	RK_PLLRATE(1368000000, 1, 114, 2, 1, 1),
10977f22241SEmmanuel Vadot 	RK_PLLRATE(1344000000, 1, 112, 2, 1, 1),
11077f22241SEmmanuel Vadot 	RK_PLLRATE(1320000000, 1, 110, 2, 1, 1),
11177f22241SEmmanuel Vadot 	RK_PLLRATE(1296000000, 1, 108, 2, 1, 1),
11277f22241SEmmanuel Vadot 	RK_PLLRATE(1272000000, 1, 106, 2, 1, 1),
11377f22241SEmmanuel Vadot 	RK_PLLRATE(1248000000, 1, 104, 2, 1, 1),
11477f22241SEmmanuel Vadot 	RK_PLLRATE(1200000000, 1, 100, 2, 1, 1),
11577f22241SEmmanuel Vadot 	RK_PLLRATE(1188000000, 1, 99, 2, 1, 1),
11677f22241SEmmanuel Vadot 	RK_PLLRATE(1104000000, 1, 92, 2, 1, 1),
11777f22241SEmmanuel Vadot 	RK_PLLRATE(1100000000, 3, 275, 2, 1, 1),
11877f22241SEmmanuel Vadot 	RK_PLLRATE(1008000000, 1, 84, 2, 1, 1),
11977f22241SEmmanuel Vadot 	RK_PLLRATE(1000000000, 3, 250, 2, 1, 1),
12077f22241SEmmanuel Vadot 	RK_PLLRATE(912000000, 1, 76, 2, 1, 1),
12177f22241SEmmanuel Vadot 	RK_PLLRATE(816000000, 1, 68, 2, 1, 1),
12277f22241SEmmanuel Vadot 	RK_PLLRATE(800000000, 3, 200, 2, 1, 1),
12377f22241SEmmanuel Vadot 	RK_PLLRATE(700000000, 3, 350, 4, 1, 1),
12477f22241SEmmanuel Vadot 	RK_PLLRATE(696000000, 1, 116, 4, 1, 1),
12577f22241SEmmanuel Vadot 	RK_PLLRATE(600000000, 1, 100, 4, 1, 1),
12677f22241SEmmanuel Vadot 	RK_PLLRATE(594000000, 1, 99, 4, 1, 1),
12777f22241SEmmanuel Vadot 	RK_PLLRATE(500000000, 1, 125, 6, 1, 1),
12877f22241SEmmanuel Vadot 	RK_PLLRATE(408000000, 1, 68, 2, 2, 1),
12977f22241SEmmanuel Vadot 	RK_PLLRATE(312000000, 1, 78, 6, 1, 1),
13077f22241SEmmanuel Vadot 	RK_PLLRATE(216000000, 1, 72, 4, 2, 1),
13177f22241SEmmanuel Vadot 	RK_PLLRATE(200000000, 1, 100, 3, 4, 1),
13277f22241SEmmanuel Vadot 	RK_PLLRATE(148500000, 1, 99, 4, 4, 1),
13377f22241SEmmanuel Vadot 	RK_PLLRATE(100000000, 1, 150, 6, 6, 1),
13477f22241SEmmanuel Vadot 	RK_PLLRATE(96000000, 1, 96, 6, 4, 1),
13577f22241SEmmanuel Vadot 	RK_PLLRATE(74250000, 2, 99, 4, 4, 1),
13677f22241SEmmanuel Vadot 	{},
13777f22241SEmmanuel Vadot };
13877f22241SEmmanuel Vadot 
13977f22241SEmmanuel Vadot static struct rk_clk_armclk_rates rk3568_armclk_rates[] = {
14077f22241SEmmanuel Vadot 	{2208000000, 1},
14177f22241SEmmanuel Vadot 	{2160000000, 1},
14277f22241SEmmanuel Vadot 	{2064000000, 1},
14377f22241SEmmanuel Vadot 	{2016000000, 1},
14477f22241SEmmanuel Vadot 	{1992000000, 1},
14577f22241SEmmanuel Vadot 	{1800000000, 1},
14677f22241SEmmanuel Vadot 	{1704000000, 1},
14777f22241SEmmanuel Vadot 	{1608000000, 1},
14877f22241SEmmanuel Vadot 	{1512000000, 1},
14977f22241SEmmanuel Vadot 	{1488000000, 1},
15077f22241SEmmanuel Vadot 	{1416000000, 1},
15177f22241SEmmanuel Vadot 	{1200000000, 1},
15277f22241SEmmanuel Vadot 	{1104000000, 1},
15377f22241SEmmanuel Vadot 	{1008000000, 1},
15477f22241SEmmanuel Vadot 	{ 816000000, 1},
15577f22241SEmmanuel Vadot 	{ 696000000, 1},
15677f22241SEmmanuel Vadot 	{ 600000000, 1},
15777f22241SEmmanuel Vadot 	{ 408000000, 1},
15877f22241SEmmanuel Vadot 	{ 312000000, 1},
15977f22241SEmmanuel Vadot 	{ 216000000, 1},
16077f22241SEmmanuel Vadot 	{  96000000, 1},
16177f22241SEmmanuel Vadot 	{},
16277f22241SEmmanuel Vadot };
16377f22241SEmmanuel Vadot 
16477f22241SEmmanuel Vadot /* Parent clock defines */
16577f22241SEmmanuel Vadot PLIST(mux_pll_p) = { "xin24m" };
16677f22241SEmmanuel Vadot PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
16777f22241SEmmanuel Vadot PLIST(mux_armclk_p) = { "apll", "gpll" };
16877f22241SEmmanuel Vadot PLIST(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac",
16977f22241SEmmanuel Vadot     "i2s0_mclkin", "xin_osc0_half" };
17077f22241SEmmanuel Vadot PLIST(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac",
17177f22241SEmmanuel Vadot     "i2s0_mclkin", "xin_osc0_half" };
17277f22241SEmmanuel Vadot PLIST(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac",
17377f22241SEmmanuel Vadot     "i2s1_mclkin", "xin_osc0_half" };
17477f22241SEmmanuel Vadot PLIST(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac",
17577f22241SEmmanuel Vadot     "i2s1_mclkin", "xin_osc0_half" };
17677f22241SEmmanuel Vadot PLIST(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac",
17777f22241SEmmanuel Vadot     "i2s2_mclkin", "xin_osc0_half"};
17877f22241SEmmanuel Vadot PLIST(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac",
17977f22241SEmmanuel Vadot     "i2s3_mclkin", "xin_osc0_half" };
18077f22241SEmmanuel Vadot PLIST(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac",
18177f22241SEmmanuel Vadot     "i2s3_mclkin", "xin_osc0_half" };
18277f22241SEmmanuel Vadot PLIST(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
18377f22241SEmmanuel Vadot PLIST(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
18477f22241SEmmanuel Vadot PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
18577f22241SEmmanuel Vadot PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
18677f22241SEmmanuel Vadot PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
18777f22241SEmmanuel Vadot PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
18877f22241SEmmanuel Vadot PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
18977f22241SEmmanuel Vadot PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
19077f22241SEmmanuel Vadot PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
19177f22241SEmmanuel Vadot PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
19277f22241SEmmanuel Vadot PLIST(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
19377f22241SEmmanuel Vadot PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
19477f22241SEmmanuel Vadot PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
19577f22241SEmmanuel Vadot PLIST(npll_gpll_p) = { "npll", "gpll" };
19677f22241SEmmanuel Vadot PLIST(cpll_gpll_p) = { "cpll", "gpll" };
19777f22241SEmmanuel Vadot PLIST(gpll_cpll_p) = { "gpll", "cpll" };
19877f22241SEmmanuel Vadot PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
19977f22241SEmmanuel Vadot PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
20077f22241SEmmanuel Vadot PLIST(sclk_core_pre_p) = { "sclk_core_src", "npll" };
20177f22241SEmmanuel Vadot PLIST(gpll150_gpll100_gpll75_xin24m_p) = { "clk_gpll_div_150m", "clk_gpll_div_100m", "clk_gpll_div_75m",
20277f22241SEmmanuel Vadot     "xin24m" };
20377f22241SEmmanuel Vadot PLIST(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
20477f22241SEmmanuel Vadot PLIST(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"};
20577f22241SEmmanuel Vadot PLIST(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
20677f22241SEmmanuel Vadot PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
20777f22241SEmmanuel Vadot PLIST(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
20877f22241SEmmanuel Vadot PLIST(gpll200_gpll150_gpll100_xin24m_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m",
20977f22241SEmmanuel Vadot     "clk_gpll_div_100m", "xin24m" };
21077f22241SEmmanuel Vadot PLIST(gpll100_gpll75_gpll50_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m" };
21177f22241SEmmanuel Vadot PLIST(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
21277f22241SEmmanuel Vadot PLIST(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
21377f22241SEmmanuel Vadot PLIST(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
21477f22241SEmmanuel Vadot PLIST(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
21577f22241SEmmanuel Vadot PLIST(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
21677f22241SEmmanuel Vadot PLIST(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
21777f22241SEmmanuel Vadot PLIST(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
21877f22241SEmmanuel Vadot PLIST(mclk_pdm_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", "clk_gpll_div_200m", "clk_gpll_div_100m" };
21977f22241SEmmanuel Vadot PLIST(clk_i2c_p) = { "clk_gpll_div_200m", "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };
22077f22241SEmmanuel Vadot PLIST(gpll200_gpll150_gpll100_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_gpll_div_100m" };
22177f22241SEmmanuel Vadot PLIST(gpll300_gpll200_gpll100_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", "clk_gpll_div_100m" };
22277f22241SEmmanuel Vadot PLIST(clk_nandc_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", "xin24m" };
22377f22241SEmmanuel Vadot PLIST(sclk_sfc_p) = { "xin24m", "clk_cpll_div_50m", "clk_gpll_div_75m", "clk_gpll_div_100m",
22477f22241SEmmanuel Vadot     "clk_cpll_div_125m", "clk_gpll_div_150m" };
22577f22241SEmmanuel Vadot PLIST(gpll200_gpll150_cpll125_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_125m" };
22677f22241SEmmanuel Vadot PLIST(cclk_emmc_p) = { "xin24m", "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m",
22777f22241SEmmanuel Vadot     "clk_cpll_div_50m", "clk_osc0_div_375k" };
22877f22241SEmmanuel Vadot PLIST(aclk_pipe_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_gpll_div_200m", "xin24m" };
22977f22241SEmmanuel Vadot PLIST(gpll200_cpll125_p) = { "clk_gpll_div_200m", "clk_cpll_div_125m" };
23077f22241SEmmanuel Vadot PLIST(gpll300_gpll200_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m",
23177f22241SEmmanuel Vadot     "clk_gpll_div_100m", "xin24m" };
23277f22241SEmmanuel Vadot PLIST(clk_sdmmc_p) = { "xin24m", "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_cpll_div_100m",
23377f22241SEmmanuel Vadot     "clk_cpll_div_50m", "clk_osc0_div_750k" };
23477f22241SEmmanuel Vadot PLIST(cpll125_cpll50_cpll25_xin24m_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m",
23577f22241SEmmanuel Vadot     "xin24m" };
23677f22241SEmmanuel Vadot PLIST(clk_gmac_ptp_p) = { "clk_cpll_div_62P5m", "clk_gpll_div_100m", "clk_cpll_div_50m", "xin24m" };
23777f22241SEmmanuel Vadot PLIST(cpll333_gpll300_gpll200_p) = { "clk_cpll_div_333m", "clk_gpll_div_300m", "clk_gpll_div_200m" };
23877f22241SEmmanuel Vadot PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
23977f22241SEmmanuel Vadot PLIST(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
24077f22241SEmmanuel Vadot PLIST(gpll300_cpll250_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m",
24177f22241SEmmanuel Vadot     "clk_gpll_div_100m", "xin24m" };
24277f22241SEmmanuel Vadot PLIST(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
24377f22241SEmmanuel Vadot PLIST(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
24477f22241SEmmanuel Vadot PLIST(gpll400_cpll333_gpll200_p) = { "clk_gpll_div_400m", "clk_cpll_div_333m", "clk_gpll_div_200m" };
24577f22241SEmmanuel Vadot PLIST(gpll100_gpll75_cpll50_xin24m_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m",
24677f22241SEmmanuel Vadot     "xin24m" };
24777f22241SEmmanuel Vadot PLIST(xin24m_gpll100_cpll100_p) = { "xin24m", "clk_gpll_div_100m", "clk_cpll_div_100m" };
24877f22241SEmmanuel Vadot PLIST(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
24977f22241SEmmanuel Vadot PLIST(gpll100_xin24m_cpll100_p) = { "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };
25077f22241SEmmanuel Vadot PLIST(gpll200_xin24m_cpll100_p) = { "clk_gpll_div_200m", "xin24m", "clk_cpll_div_100m" };
25177f22241SEmmanuel Vadot PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
25277f22241SEmmanuel Vadot PLIST(cpll500_gpll400_gpll300_xin24m_p) = { "clk_cpll_div_500m", "clk_gpll_div_400m",
25377f22241SEmmanuel Vadot     "clk_gpll_div_300m", "xin24m" };
25477f22241SEmmanuel Vadot PLIST(gpll400_gpll300_gpll200_xin24m_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m",
25577f22241SEmmanuel Vadot     "clk_gpll_div_200m", "xin24m" };
25677f22241SEmmanuel Vadot PLIST(xin24m_cpll100_p) = { "xin24m", "clk_cpll_div_100m" };
25777f22241SEmmanuel Vadot PLIST(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
25877f22241SEmmanuel Vadot PLIST(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0",
25977f22241SEmmanuel Vadot     "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
26077f22241SEmmanuel Vadot PLIST(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
26177f22241SEmmanuel Vadot PLIST(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed",
26277f22241SEmmanuel Vadot     "clk_gmac0_xpcs_mii" };
26377f22241SEmmanuel Vadot PLIST(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
26477f22241SEmmanuel Vadot PLIST(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1",
26577f22241SEmmanuel Vadot     "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
26677f22241SEmmanuel Vadot PLIST(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
26777f22241SEmmanuel Vadot PLIST(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed",
26877f22241SEmmanuel Vadot     "clk_gmac1_xpcs_mii" };
26977f22241SEmmanuel Vadot PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" };
27077f22241SEmmanuel Vadot PLIST(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
27177f22241SEmmanuel Vadot PLIST(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" };
27277f22241SEmmanuel Vadot 
27377f22241SEmmanuel Vadot /* CLOCKS */
27477f22241SEmmanuel Vadot static struct rk_clk rk3568_clks[] = {
27577f22241SEmmanuel Vadot 	/* External clocks */
27677f22241SEmmanuel Vadot 	LINK("xin24m"),
27777f22241SEmmanuel Vadot 	LINK("clk_rtc_32k"),
27877f22241SEmmanuel Vadot 	LINK("usb480m_phy"),
27977f22241SEmmanuel Vadot 	LINK("mpll"),	/* It lives in SCRU */
28077f22241SEmmanuel Vadot 	LINK("i2s0_mclkin"),
28177f22241SEmmanuel Vadot 	LINK("i2s1_mclkin"),
28277f22241SEmmanuel Vadot 	LINK("i2s2_mclkin"),
28377f22241SEmmanuel Vadot 	LINK("i2s3_mclkin"),
28477f22241SEmmanuel Vadot 	LINK("gpu_pvtpll_out"),
28577f22241SEmmanuel Vadot 	LINK("npu_pvtpll_out"),
28677f22241SEmmanuel Vadot 	LINK("gmac0_clkin"),
28777f22241SEmmanuel Vadot 	LINK("gmac1_clkin"),
28877f22241SEmmanuel Vadot 	LINK("clk_gmac0_xpcs_mii"),
28977f22241SEmmanuel Vadot 	LINK("clk_gmac1_xpcs_mii"),
29077f22241SEmmanuel Vadot 	LINK("dummy"),
29177f22241SEmmanuel Vadot 
29277f22241SEmmanuel Vadot 	/* PLL's */
29377f22241SEmmanuel Vadot 	RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0),
29477f22241SEmmanuel Vadot 	RK_PLL(PLL_DPLL, "dpll", mux_pll_p, 1, 2),
29577f22241SEmmanuel Vadot 	RK_PLL(PLL_GPLL, "gpll", mux_pll_p, 2, 6),
29677f22241SEmmanuel Vadot 	RK_PLL(PLL_CPLL, "cpll", mux_pll_p, 3, 4),
29777f22241SEmmanuel Vadot 	RK_PLL(PLL_NPLL, "npll", mux_pll_p, 4, 10),
29877f22241SEmmanuel Vadot 	RK_PLL(PLL_VPLL, "vpll", mux_pll_p, 5, 12),
29977f22241SEmmanuel Vadot 	ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5,
30077f22241SEmmanuel Vadot 	    6, 1, 0, 1),
30177f22241SEmmanuel Vadot 	FFACT(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2),
30277f22241SEmmanuel Vadot 	FFACT(0, "xin_osc0_half", "xin24m", 1, 2),
30377f22241SEmmanuel Vadot 	MUX(USB480M, "usb480m", mux_usb480m_p, 0, -16, 14, 2),
30477f22241SEmmanuel Vadot 
30577f22241SEmmanuel Vadot 	/* Clocks */
30677f22241SEmmanuel Vadot 
30777f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON00 */
30877f22241SEmmanuel Vadot 	/* 0:4 clk_core0_div DIV */
30977f22241SEmmanuel Vadot 	/* 5 Reserved */
31077f22241SEmmanuel Vadot 	/* 6 clk_core_i_sel MUX */
31177f22241SEmmanuel Vadot 	/* 7 clk_core_ndft_sel MUX */
31277f22241SEmmanuel Vadot 	/* 8:12 clk_core1_div DIV */
31377f22241SEmmanuel Vadot 	/* 13:14 Reserved */
31477f22241SEmmanuel Vadot 	/* 15 clk_core_ndft_mux_sel MUX */
31577f22241SEmmanuel Vadot 
31677f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON01 */
31777f22241SEmmanuel Vadot 	/* 0:4 clk_core2_div DIV */
31877f22241SEmmanuel Vadot 	/* 5:7 Reserved */
31977f22241SEmmanuel Vadot 	/* 8:12 clk_core3_div DIV */
32077f22241SEmmanuel Vadot 	/* 13:15 Reserved */
32177f22241SEmmanuel Vadot 
32277f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON02 */
32377f22241SEmmanuel Vadot 	COMP(0, "sclk_core_src_c", apll_gpll_npll_p, 0, 2, 0, 4, 8, 2),
32477f22241SEmmanuel Vadot 	/* 4:7 Reserved */
32577f22241SEmmanuel Vadot 	/* 10:14 Reserved */
32677f22241SEmmanuel Vadot 	MUX(0, "sclk_core_pre_sel", sclk_core_pre_p, 0, 2, 15, 1),
32777f22241SEmmanuel Vadot 
32877f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON03 */
32977f22241SEmmanuel Vadot 	CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5),
33077f22241SEmmanuel Vadot 	/* 5:7 Reserved */
33177f22241SEmmanuel Vadot 	CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5),
33277f22241SEmmanuel Vadot 	/* 13:15 Reserved */
33377f22241SEmmanuel Vadot 
33477f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON04 */
33577f22241SEmmanuel Vadot 	CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5),
33677f22241SEmmanuel Vadot 	/* 5:7 Reserved */
33777f22241SEmmanuel Vadot 	CDIV(0, "periphclk_core_pre_div", "armclk", 0, 4, 8, 5),
33877f22241SEmmanuel Vadot 	/* 13:15 Reserved */
33977f22241SEmmanuel Vadot 
34077f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON05 */
34177f22241SEmmanuel Vadot 	/* 0:7 Reserved */
34277f22241SEmmanuel Vadot 	/* 8:12 aclk_core_ndft_div DIV */
34377f22241SEmmanuel Vadot 	/* 13 Reserved */
34477f22241SEmmanuel Vadot 	/* 14:15 aclk_core_biu2bus_sel MUX */
34577f22241SEmmanuel Vadot 
34677f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON06 */
34777f22241SEmmanuel Vadot 	COMP(0, "clk_gpu_pre_c", mpll_gpll_cpll_npll_p, 0, 6, 0, 4, 6, 2),
34877f22241SEmmanuel Vadot 	/* 4:5 Reserved */
34977f22241SEmmanuel Vadot 	CDIV(0, "aclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 8, 2),
35077f22241SEmmanuel Vadot 	/* 10 Reserved */
35177f22241SEmmanuel Vadot 	MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux_sel", clk_gpu_pre_mux_p, 0, 6, 11, 1),
35277f22241SEmmanuel Vadot 	CDIV(0, "pclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 12, 4),
35377f22241SEmmanuel Vadot 
35477f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON07 */
35577f22241SEmmanuel Vadot 	COMP(0, "clk_npu_src_c", npll_gpll_p, 0, 7, 0, 4, 6, 1),
35677f22241SEmmanuel Vadot 	COMP(0, "clk_npu_np5_c", npll_gpll_p, 0, 7, 4, 2, 7, 1),
35777f22241SEmmanuel Vadot 	MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 0, 7,
35877f22241SEmmanuel Vadot 	    8, 1),
35977f22241SEmmanuel Vadot 	/* 9:14 Reserved */
36077f22241SEmmanuel Vadot 	MUX(CLK_NPU, "clk_npu", clk_npu_p, 0, 7, 15, 1),
36177f22241SEmmanuel Vadot 
36277f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON08 */
36377f22241SEmmanuel Vadot 	CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4),
36477f22241SEmmanuel Vadot 	CDIV(0, "pclk_npu_pre_div", "clk_npu", 0, 8, 4, 4),
36577f22241SEmmanuel Vadot 	/* 8:15 Reserved */
36677f22241SEmmanuel Vadot 
36777f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON09 */
36877f22241SEmmanuel Vadot 	COMP(0, "clk_ddrphy1x_src_c", dpll_gpll_cpll_p, 0, 9, 0, 5, 6, 2),
36977f22241SEmmanuel Vadot 	/* 5 Reserved */
37077f22241SEmmanuel Vadot 	/* 8:14 Reserved */
37177f22241SEmmanuel Vadot 	MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, RK_CLK_COMPOSITE_GRF, 9,
37277f22241SEmmanuel Vadot 	    15, 1),
37377f22241SEmmanuel Vadot 
37477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON10 */
37577f22241SEmmanuel Vadot 	CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2),
37677f22241SEmmanuel Vadot 	MUX(0, "aclk_perimid_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 10, 4, 2),
37777f22241SEmmanuel Vadot 	MUX(0, "hclk_perimid_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 6, 2),
37877f22241SEmmanuel Vadot 	MUX(0, "aclk_gic_audio_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 10, 8, 2),
37977f22241SEmmanuel Vadot 	MUX(0, "hclk_gic_audio_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 10, 2),
38077f22241SEmmanuel Vadot 	MUX(0, "dclk_sdmmc_buffer_sel", gpll100_gpll75_gpll50_p, 0, 10, 12, 2),
38177f22241SEmmanuel Vadot 	/* 14:15 Reserved */
38277f22241SEmmanuel Vadot 
38377f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON11 */
38477f22241SEmmanuel Vadot 	COMP(0, "clk_i2s0_8ch_tx_src_c", gpll_cpll_npll_p, 0, 11, 0, 7, 8, 2),
38577f22241SEmmanuel Vadot 	/* 7 Reserved */
38677f22241SEmmanuel Vadot 	MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 0, 11, 10,
38777f22241SEmmanuel Vadot 	    2),
38877f22241SEmmanuel Vadot 	/* 12:14 Reserved */
38977f22241SEmmanuel Vadot 	MUX(0, "i2s0_mclkout_tx_sel", i2s0_mclkout_tx_p, 0, 11, 15, 1),
39077f22241SEmmanuel Vadot 
39177f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON12 */
39277f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s0_8ch_tx_frac_div", "clk_i2s0_8ch_tx_src", 0, 12),
39377f22241SEmmanuel Vadot 
39477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON13 */
39577f22241SEmmanuel Vadot 	COMP(0, "clk_i2s0_8ch_rx_src_c", gpll_cpll_npll_p, 0, 13, 0, 7, 8, 2),
39677f22241SEmmanuel Vadot 	/* 7 Reserved */
39777f22241SEmmanuel Vadot 	MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 0, 13, 10,
39877f22241SEmmanuel Vadot 	    2),
39977f22241SEmmanuel Vadot 	/* 12:14 Reserved */
40077f22241SEmmanuel Vadot 	MUX(0, "i2s0_mclkout_rx_sel", i2s0_mclkout_rx_p, 0, 13, 15, 1),
40177f22241SEmmanuel Vadot 
40277f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON14 */
40377f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s0_8ch_rx_frac_div", "clk_i2s0_8ch_rx_src", 0, 14),
40477f22241SEmmanuel Vadot 
40577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON15 */
40677f22241SEmmanuel Vadot 	COMP(0, "clk_i2s1_8ch_tx_src_c", gpll_cpll_npll_p, 0, 15, 0, 7, 8, 2),
40777f22241SEmmanuel Vadot 	/* 7 Reserved */
40877f22241SEmmanuel Vadot 	MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 0, 15, 10,
40977f22241SEmmanuel Vadot 	    2),
41077f22241SEmmanuel Vadot 	/* 12:14 Reserved */
41177f22241SEmmanuel Vadot 	MUX(0, "i2s1_mclkout_tx_sel", i2s1_mclkout_tx_p, 0, 11, 15, 1),
41277f22241SEmmanuel Vadot 
41377f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON16 */
41477f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s1_8ch_tx_frac_div", "clk_i2s1_8ch_tx_src", 0, 16),
41577f22241SEmmanuel Vadot 
41677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON17 */
41777f22241SEmmanuel Vadot 	COMP(0, "clk_i2s1_8ch_rx_src_c", gpll_cpll_npll_p, 0, 17, 0, 7, 8, 2),
41877f22241SEmmanuel Vadot 	/* 7 Reserved */
41977f22241SEmmanuel Vadot 	MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 0, 17, 10,
42077f22241SEmmanuel Vadot 	    2),
42177f22241SEmmanuel Vadot 	/* 12:14 Reserved */
42277f22241SEmmanuel Vadot 	MUX(0, "i2s1_mclkout_rx_sel", i2s1_mclkout_rx_p, 0, 17, 15, 1),
42377f22241SEmmanuel Vadot 
42477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON18 */
42577f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s1_8ch_rx_frac_div", "clk_i2s1_8ch_rx_src", 0, 18),
42677f22241SEmmanuel Vadot 
42777f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON19 */
42877f22241SEmmanuel Vadot 	COMP(0, "clk_i2s2_2ch_src_c", gpll_cpll_npll_p, 0, 19, 0, 7, 8, 2),
42977f22241SEmmanuel Vadot 	/* 7 Reserved */
43077f22241SEmmanuel Vadot 	MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 0, 19, 10,
43177f22241SEmmanuel Vadot 	    2),
43277f22241SEmmanuel Vadot 	/* 12:14 Reserved */
43377f22241SEmmanuel Vadot 	MUX(0, "i2s2_mclkout_sel", i2s2_mclkout_p, 0, 19, 15, 1),
43477f22241SEmmanuel Vadot 
43577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON20 */
43677f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s2_2ch_frac_div", "clk_i2s2_2ch_src", 0, 20),
43777f22241SEmmanuel Vadot 
43877f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON21 */
43977f22241SEmmanuel Vadot 	COMP(0, "clk_i2s3_2ch_tx_src_c", gpll_cpll_npll_p, 0, 21, 0, 7, 8, 2),
44077f22241SEmmanuel Vadot 	/* 7 Reserved */
44177f22241SEmmanuel Vadot 	MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 0, 21, 10,
44277f22241SEmmanuel Vadot 	    2),
44377f22241SEmmanuel Vadot 	/* 12:14 Reserved */
44477f22241SEmmanuel Vadot 	MUX(0, "i2s3_mclkout_tx_sel", i2s3_mclkout_tx_p, 0, 21, 15, 1),
44577f22241SEmmanuel Vadot 
44677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON22 */
44777f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s3_2ch_tx_frac_div", "clk_i2s3_2ch_tx_src", 0, 22),
44877f22241SEmmanuel Vadot 
44977f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON23 */
45077f22241SEmmanuel Vadot 	COMP(0, "mclk_spdif_8ch_src_c", cpll_gpll_p, 0, 23, 0, 7, 14, 1),
45177f22241SEmmanuel Vadot 	/* 7 Reserved */
45277f22241SEmmanuel Vadot 	MUX(0, "mclk_pdm_sel", mclk_pdm_p, 0, 23, 8, 2),
45377f22241SEmmanuel Vadot 	MUX(0, "clk_acdcdig_i2c_sel", clk_i2c_p, 0, 23, 10, 2),
45477f22241SEmmanuel Vadot 	/* 12:13 Reserved */
45577f22241SEmmanuel Vadot 	MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 0, 23, 15,
45677f22241SEmmanuel Vadot 	    1),
45777f22241SEmmanuel Vadot 
45877f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON24 */
45977f22241SEmmanuel Vadot 	FRACT(0, "mclk_spdif_8ch_frac_div", "mclk_spdif_8ch_src", 0, 24),
46077f22241SEmmanuel Vadot 
46177f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON25 */
46277f22241SEmmanuel Vadot 	COMP(0, "sclk_audpwm_src_c", gpll_cpll_p, 0, 25, 0, 5, 14, 1),
46377f22241SEmmanuel Vadot 	/* 6:13 Reserved */
46477f22241SEmmanuel Vadot 	MUX(SCLK_AUDPWM, "sck_audpwm_sel", sclk_audpwm_p, 0, 25, 15, 1),
46577f22241SEmmanuel Vadot 
46677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON26 */
46777f22241SEmmanuel Vadot 	FRACT(0, "sclk_audpwm_frac_frac", "sclk_audpwm_src", 0, 26),
46877f22241SEmmanuel Vadot 
46977f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON27 */
47077f22241SEmmanuel Vadot 	MUX(0, "aclk_secure_flash_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 27, 0, 2),
47177f22241SEmmanuel Vadot 	MUX(0, "hclk_secure_flash_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 27, 2, 2),
47277f22241SEmmanuel Vadot 	MUX(0, "clk_crypto_ns_core_sel", gpll200_gpll150_gpll100_p, 0, 27, 4, 2),
47377f22241SEmmanuel Vadot 	MUX(0, "clk_crypto_ns_pka_sel", gpll300_gpll200_gpll100_p, 0, 27, 6, 2),
47477f22241SEmmanuel Vadot 	/* 8:15 Reserved */
47577f22241SEmmanuel Vadot 
47677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON28 */
47777f22241SEmmanuel Vadot 	MUX(0, "nclk_nandc_sel", clk_nandc_p, 0, 28, 0, 2),
47877f22241SEmmanuel Vadot 	/* 2:3 Reserved */
47977f22241SEmmanuel Vadot 	MUX(0, "sclk_sfc_sel", sclk_sfc_p, 0, 28, 4, 3),
48077f22241SEmmanuel Vadot 	/* 7 Reserved */
48177f22241SEmmanuel Vadot 	MUX(0, "bclk_emmc_sel", gpll200_gpll150_cpll125_p, 0, 28, 8, 2),
48277f22241SEmmanuel Vadot 	/* 10:11 Reserved */
48377f22241SEmmanuel Vadot 	MUX(0, "cclk_emmc_sel", cclk_emmc_p, 0, 28, 12, 3),
48477f22241SEmmanuel Vadot 	/* 15 Reserved */
48577f22241SEmmanuel Vadot 
48677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON29 */
48777f22241SEmmanuel Vadot 	MUX(0, "aclk_pipe_sel", aclk_pipe_p, 0, 29, 0, 2),
48877f22241SEmmanuel Vadot 	/* 2:3 Reserved */
48977f22241SEmmanuel Vadot 	CDIV(0, "pclk_pipe_div", "aclk_pipe", 0, 29, 4, 4),
49077f22241SEmmanuel Vadot 	MUX(0, "clk_usb3otg0_suspend_sel", xin24m_32k_p, 0, 29, 8, 1),
49177f22241SEmmanuel Vadot 	MUX(0, "clk_usb3otg1_suspend_sel", xin24m_32k_p, 0, 29, 9, 1),
49277f22241SEmmanuel Vadot 	/* 10:12 Reserved */
49377f22241SEmmanuel Vadot 	MUX(0, "clk_xpcs_eee_sel", gpll200_cpll125_p, 0, 29, 13, 1),
49477f22241SEmmanuel Vadot 	/* 14:15 Reserved */
49577f22241SEmmanuel Vadot 
49677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON30 */
49777f22241SEmmanuel Vadot 	MUX(0, "aclk_php_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 30, 0, 2),
49877f22241SEmmanuel Vadot 	MUX(0, "hclk_php_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 30, 2, 2),
49977f22241SEmmanuel Vadot 	CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4),
50077f22241SEmmanuel Vadot 	MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p, 0, 30, 8, 3),
50177f22241SEmmanuel Vadot 	/* 11 Reserved */
50277f22241SEmmanuel Vadot 	MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p, 0, 30, 12, 3),
50377f22241SEmmanuel Vadot 	/* 15 Reserved */
50477f22241SEmmanuel Vadot 
50577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON31 */
50677f22241SEmmanuel Vadot 	MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 0, 31,
50777f22241SEmmanuel Vadot 	    0, 2),
50877f22241SEmmanuel Vadot 	MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 0, 31, 2, 1),
50977f22241SEmmanuel Vadot 	MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed",
51077f22241SEmmanuel Vadot 	    mux_gmac0_rmii_speed_p, 0, 31, 3, 1),
51177f22241SEmmanuel Vadot 	MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed",
51277f22241SEmmanuel Vadot 	    mux_gmac0_rgmii_speed_p, 0, 31, 4, 2),
51377f22241SEmmanuel Vadot 	MUX(0, "clk_mac0_2top_sel", clk_mac_2top_p, 0, 31, 8, 2),
51477f22241SEmmanuel Vadot 	MUX(0, "clk_gmac0_ptp_ref_sel", clk_gmac_ptp_p, 0, 31, 12, 2),
51577f22241SEmmanuel Vadot 	MUX(0, "clk_mac0_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 31, 14, 2),
51677f22241SEmmanuel Vadot 
51777f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5),
51877f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50),
51977f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2),
52077f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20),
52177f22241SEmmanuel Vadot 
52277f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON32 */
52377f22241SEmmanuel Vadot 	MUX(0, "aclk_usb_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 32, 0, 2),
52477f22241SEmmanuel Vadot 	MUX(0, "hclk_usb_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 32, 4, 2),
52577f22241SEmmanuel Vadot 	CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4),
52677f22241SEmmanuel Vadot 	MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p, 0, 32, 8, 3),
52777f22241SEmmanuel Vadot 	/* 11:15 Reserved */
52877f22241SEmmanuel Vadot 
52977f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON33 */
53077f22241SEmmanuel Vadot 	MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 0, 33,
53177f22241SEmmanuel Vadot 	    0, 2),
53277f22241SEmmanuel Vadot 	MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 0, 33, 2, 1),
53377f22241SEmmanuel Vadot 	MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed",
53477f22241SEmmanuel Vadot 	    mux_gmac1_rmii_speed_p, 0, 33, 3, 1),
53577f22241SEmmanuel Vadot 	MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed",
53677f22241SEmmanuel Vadot 	    mux_gmac1_rgmii_speed_p, 0, 33, 4, 2),
53777f22241SEmmanuel Vadot 	/* 6:7 Reserved */
53877f22241SEmmanuel Vadot 	MUX(0, "clk_mac1_2top_sel", clk_mac_2top_p, 0, 33, 8, 2),
53977f22241SEmmanuel Vadot 	MUX(0, "clk_gmac1_ptp_ref_sel", clk_gmac_ptp_p, 0, 33, 12, 2),
54077f22241SEmmanuel Vadot 	MUX(0, "clk_mac1_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 33, 14, 2),
54177f22241SEmmanuel Vadot 
54277f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5),
54377f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50),
54477f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2),
54577f22241SEmmanuel Vadot 	FFACT(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20),
54677f22241SEmmanuel Vadot 
54777f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON34 */
54877f22241SEmmanuel Vadot 	MUX(0, "aclk_vi_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 34, 0, 2),
54977f22241SEmmanuel Vadot 	/* 2:3 Reserved */
55077f22241SEmmanuel Vadot 	CDIV(0, "hclk_vi_div", "aclk_vi", 0, 34, 4, 4),
55177f22241SEmmanuel Vadot 	CDIV(0, "pclk_vi_div", "aclk_vi", 0, 34, 8, 4),
55277f22241SEmmanuel Vadot 	/* 12:13 Reserved */
55377f22241SEmmanuel Vadot 	MUX(0, "dclk_vicap1_sel", cpll333_gpll300_gpll200_p, 0, 34, 14, 2),
55477f22241SEmmanuel Vadot 
55577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON35 */
55677f22241SEmmanuel Vadot 	COMP(0, "clk_isp_c", cpll_gpll_hpll_p, 0, 35, 0, 5, 6, 2),
55777f22241SEmmanuel Vadot 	/* 5 Reserved */
55877f22241SEmmanuel Vadot 	COMP(0, "clk_cif_out_c", gpll_usb480m_xin24m_p, 0, 35, 8, 6, 14, 2),
55977f22241SEmmanuel Vadot 
56077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON36 */
56177f22241SEmmanuel Vadot 	COMP(0, "clk_cam0_out_c", gpll_usb480m_xin24m_p, 0, 36, 0, 6, 6, 2),
56277f22241SEmmanuel Vadot 	COMP(0, "clk_cam1_out_c", gpll_usb480m_xin24m_p, 0, 36, 8, 6, 14, 2),
56377f22241SEmmanuel Vadot 
56477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON37 */
56577f22241SEmmanuel Vadot 	MUX(0, "aclk_vo_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 37, 0, 2),
56677f22241SEmmanuel Vadot 	/* 2:7 Reserved */
56777f22241SEmmanuel Vadot 	CDIV(0, "hclk_vo_div", "aclk_vo", 0, 37, 8, 4),
56877f22241SEmmanuel Vadot 	CDIV(0, "pclk_vo_div", "aclk_vo", 0, 37, 12, 4),
56977f22241SEmmanuel Vadot 
57077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON38 */
57177f22241SEmmanuel Vadot 	COMP(0, "aclk_vop_pre_c", cpll_gpll_hpll_vpll_p, 0, 38, 0, 5, 6, 2),
57277f22241SEmmanuel Vadot 	/* 5 Reserved */
57377f22241SEmmanuel Vadot 	MUX(0, "clk_edp_200m_sel", gpll200_gpll150_cpll125_p, 0, 38, 8, 2),
57477f22241SEmmanuel Vadot 	/* 10:15 Reserved */
57577f22241SEmmanuel Vadot 
57677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON39 */
57777f22241SEmmanuel Vadot 	COMP(0, "dclk_vop0_c", hpll_vpll_gpll_cpll_p, 0, 39, 0, 8, 10, 2),
57877f22241SEmmanuel Vadot 	/* 12:15 Reserved */
57977f22241SEmmanuel Vadot 
58077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON40 */
58177f22241SEmmanuel Vadot 	COMP(0, "dclk_vop1_c", hpll_vpll_gpll_cpll_p, 0, 40, 0, 8, 10, 2),
58277f22241SEmmanuel Vadot 	/* 12:15 Reserved */
58377f22241SEmmanuel Vadot 
58477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON41 */
58577f22241SEmmanuel Vadot 	COMP(0, "dclk_vop2_c", hpll_vpll_gpll_cpll_p, 0, 41, 0, 8, 10, 2),
58677f22241SEmmanuel Vadot 	/* 12:15 Reserved */
58777f22241SEmmanuel Vadot 
58877f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON42 */
58977f22241SEmmanuel Vadot 	COMP(0, "aclk_vpu_pre_c", gpll_cpll_p, 0, 42, 0, 5, 7, 1),
59077f22241SEmmanuel Vadot 	/* 5:6 Reserved */
59177f22241SEmmanuel Vadot 	CDIV(0, "hclk_vpu_pre_div", "aclk_vpu_pre", 0, 42, 8, 4),
59277f22241SEmmanuel Vadot 	/* 12:15 Reserved */
59377f22241SEmmanuel Vadot 
59477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON43 */
59577f22241SEmmanuel Vadot 	MUX(0, "aclk_rga_pre_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 43, 0, 2),
59677f22241SEmmanuel Vadot 	MUX(0, "clk_rga_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 2, 2),
59777f22241SEmmanuel Vadot 	MUX(0, "clk_iep_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 4, 2),
59877f22241SEmmanuel Vadot 	MUX(0, "dclk_ebc_sel", gpll400_cpll333_gpll200_p, 0, 43, 6, 2),
59977f22241SEmmanuel Vadot 	CDIV(0, "hclk_rga_pre_div", "aclk_rga_pre", 0, 43, 8, 4),
60077f22241SEmmanuel Vadot 	CDIV(0, "pclk_rga_pre_div", "aclk_rga_pre", 0, 43, 12, 4),
60177f22241SEmmanuel Vadot 
60277f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON44 */
60377f22241SEmmanuel Vadot 	COMP(0, "aclk_rkvenc_pre_c", gpll_cpll_npll_p, 0, 44, 0, 5, 6, 2),
60477f22241SEmmanuel Vadot 	/* 5 Reserved */
60577f22241SEmmanuel Vadot 	CDIV(0, "hclk_rkvenc_pre_div", "aclk_rkvenc_pre", 0, 44, 8, 4),
60677f22241SEmmanuel Vadot 	/* 12:15 Reserved */
60777f22241SEmmanuel Vadot 
60877f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON45 */
60977f22241SEmmanuel Vadot 	COMP(0, "clk_rkvenc_core_c", gpll_cpll_npll_vpll_p, 0, 45, 0, 5, 14, 2),
61077f22241SEmmanuel Vadot 	/* 5:13 Reserved */
61177f22241SEmmanuel Vadot 
61277f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON46 */
61377f22241SEmmanuel Vadot 
61477f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON47 */
61577f22241SEmmanuel Vadot 	COMP(0, "aclk_rkvdec_pre_c", aclk_rkvdec_pre_p, 0, 47, 0, 5, 7, 1),
61677f22241SEmmanuel Vadot 	/* 5:6 Reserved */
61777f22241SEmmanuel Vadot 	CDIV(0, "hclk_rkvdec_pre_div", "aclk_rkvdec_pre", 0, 47, 8, 4),
61877f22241SEmmanuel Vadot 	/* 12:15 Reserved */
61977f22241SEmmanuel Vadot 
62077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON48 */
62177f22241SEmmanuel Vadot 	COMP(0, "clk_rkvdec_ca_c", gpll_cpll_npll_vpll_p, 0, 48, 0, 5, 6, 2),
62277f22241SEmmanuel Vadot 	/* 5 Reserved */
62377f22241SEmmanuel Vadot 	/* 8:15 Reserved */
62477f22241SEmmanuel Vadot 
62577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON49 */
62677f22241SEmmanuel Vadot 	COMP(0, "clk_rkvdec_hevc_ca_c", gpll_cpll_npll_vpll_p, 0, 49, 0, 5, 6, 2),
62777f22241SEmmanuel Vadot 	/* 5 Reserved */
62877f22241SEmmanuel Vadot 	COMP(0, "clk_rkvdec_core_c", clk_rkvdec_core_p, 0, 49, 8, 5, 14, 2),
62977f22241SEmmanuel Vadot 	/* 13 Reserved */
63077f22241SEmmanuel Vadot 
63177f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON50 */
63277f22241SEmmanuel Vadot 	MUX(0, "aclk_bus_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 50, 0, 2),
63377f22241SEmmanuel Vadot 	/* 2:3 Reserved */
63477f22241SEmmanuel Vadot 	MUX(0, "pclk_bus_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 50, 4, 2),
63577f22241SEmmanuel Vadot 	/* 6:15 Reserved */
63677f22241SEmmanuel Vadot 
63777f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON51 */
63877f22241SEmmanuel Vadot 	COMP(0, "clk_tsadc_tsen_c", xin24m_gpll100_cpll100_p, 0, 51, 0, 3, 4, 2),
63977f22241SEmmanuel Vadot 	/* 6:7 Reserved */
64077f22241SEmmanuel Vadot 	CDIV(0, "clk_tsadc_div", "clk_tsadc_tsen", 0, 51, 8, 7),
64177f22241SEmmanuel Vadot 	/* 15 Reserved */
64277f22241SEmmanuel Vadot 
64377f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON52 */
64477f22241SEmmanuel Vadot 	COMP(0, "clk_uart1_src_c", gpll_cpll_usb480m_p, 0, 52, 0, 7, 8, 2),
64577f22241SEmmanuel Vadot 	/* 7 Reserved */
64677f22241SEmmanuel Vadot 	/* 10:11 Reserved */
64777f22241SEmmanuel Vadot 	MUX(0, "sclk_uart1_sel", sclk_uart1_p, 0, 52, 12, 2),
64877f22241SEmmanuel Vadot 
64977f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON53 */
65077f22241SEmmanuel Vadot 	FRACT(0, "clk_uart1_frac_frac", "clk_uart1_src", 0, 53),
65177f22241SEmmanuel Vadot 
65277f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON54 */
65377f22241SEmmanuel Vadot 	COMP(0, "clk_uart2_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2),
65477f22241SEmmanuel Vadot 	/* 7 Reserved */
65577f22241SEmmanuel Vadot 	/* 10:11 Reserved */
65677f22241SEmmanuel Vadot 	MUX(0, "sclk_uart2_sel", sclk_uart2_p, 0, 52, 12, 2),
65777f22241SEmmanuel Vadot 
65877f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON55 */
65977f22241SEmmanuel Vadot 	FRACT(0, "clk_uart2_frac_frac", "clk_uart2_src", 0, 55),
66077f22241SEmmanuel Vadot 
66177f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON56 */
66277f22241SEmmanuel Vadot 	COMP(0, "clk_uart3_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2),
66377f22241SEmmanuel Vadot 	/* 7 Reserved */
66477f22241SEmmanuel Vadot 	/* 10:11 Reserved */
66577f22241SEmmanuel Vadot 	MUX(0, "sclk_uart3_sel", sclk_uart3_p, 0, 56, 12, 2),
66677f22241SEmmanuel Vadot 
66777f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON57 */
66877f22241SEmmanuel Vadot 	FRACT(0, "clk_uart3_frac_frac", "clk_uart3_src", 0, 57),
66977f22241SEmmanuel Vadot 
67077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON58 */
67177f22241SEmmanuel Vadot 	COMP(0, "clk_uart4_src_c", gpll_cpll_usb480m_p, 0, 58, 0, 7, 8, 2),
67277f22241SEmmanuel Vadot 	/* 7 Reserved */
67377f22241SEmmanuel Vadot 	/* 10:11 Reserved */
67477f22241SEmmanuel Vadot 	MUX(0, "sclk_uart4_sel", sclk_uart4_p, 0, 58, 12, 2),
67577f22241SEmmanuel Vadot 
67677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON59 */
67777f22241SEmmanuel Vadot 	FRACT(0, "clk_uart4_frac_frac", "clk_uart4_src", 0, 59),
67877f22241SEmmanuel Vadot 
67977f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON60 */
68077f22241SEmmanuel Vadot 	COMP(0, "clk_uart5_src_c", gpll_cpll_usb480m_p, 0, 60, 0, 7, 8, 2),
68177f22241SEmmanuel Vadot 	/* 7 Reserved */
68277f22241SEmmanuel Vadot 	/* 10:11 Reserved */
68377f22241SEmmanuel Vadot 	MUX(0, "sclk_uart5_sel", sclk_uart5_p, 0, 60, 12, 2),
68477f22241SEmmanuel Vadot 
68577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON61 */
68677f22241SEmmanuel Vadot 	FRACT(0, "clk_uart5_frac_frac", "clk_uart5_src", 0, 61),
68777f22241SEmmanuel Vadot 
68877f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON62 */
68977f22241SEmmanuel Vadot 	COMP(0, "clk_uart6_src_c", gpll_cpll_usb480m_p, 0, 62, 0, 7, 8, 2),
69077f22241SEmmanuel Vadot 	/* 7 Reserved */
69177f22241SEmmanuel Vadot 	/* 10:11 Reserved */
69277f22241SEmmanuel Vadot 	MUX(0, "sclk_uart6_sel", sclk_uart6_p, 0, 62, 12, 2),
69377f22241SEmmanuel Vadot 
69477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON63 */
69577f22241SEmmanuel Vadot 	FRACT(0, "clk_uart6_frac_frac", "clk_uart6_src", 0, 63),
69677f22241SEmmanuel Vadot 
69777f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON64 */
69877f22241SEmmanuel Vadot 	COMP(0, "clk_uart7_src_c", gpll_cpll_usb480m_p, 0, 64, 0, 7, 8, 2),
69977f22241SEmmanuel Vadot 	/* 7 Reserved */
70077f22241SEmmanuel Vadot 	/* 10:11 Reserved */
70177f22241SEmmanuel Vadot 	MUX(0, "sclk_uart7_sel", sclk_uart7_p, 0, 64, 12, 2),
70277f22241SEmmanuel Vadot 
70377f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON65 */
70477f22241SEmmanuel Vadot 	FRACT(0, "clk_uart7_frac_frac", "clk_uart7_src", 0, 65),
70577f22241SEmmanuel Vadot 
70677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON66 */
70777f22241SEmmanuel Vadot 	COMP(0, "clk_uart8_src_c", gpll_cpll_usb480m_p, 0, 66, 0, 7, 8, 2),
70877f22241SEmmanuel Vadot 	/* 7 Reserved */
70977f22241SEmmanuel Vadot 	/* 10:11 Reserved */
71077f22241SEmmanuel Vadot 	MUX(0, "sclk_uart8_sel", sclk_uart8_p, 0, 66, 12, 2),
71177f22241SEmmanuel Vadot 
71277f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON67 */
71377f22241SEmmanuel Vadot 	FRACT(0, "clk_uart8_frac_frac", "clk_uart8_src", 0, 67),
71477f22241SEmmanuel Vadot 
71577f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON68 */
71677f22241SEmmanuel Vadot 	COMP(0, "clk_uart9_src_c", gpll_cpll_usb480m_p, 0, 68, 0, 7, 8, 2),
71777f22241SEmmanuel Vadot 	/* 7 Reserved */
71877f22241SEmmanuel Vadot 	/* 10:11 Reserved */
71977f22241SEmmanuel Vadot 	MUX(0, "sclk_uart9_sel", sclk_uart9_p, 0, 68, 12, 2),
72077f22241SEmmanuel Vadot 
72177f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON69 */
72277f22241SEmmanuel Vadot 	FRACT(0, "clk_uart9_frac_frac", "clk_uart9_src", 0, 69),
72377f22241SEmmanuel Vadot 
72477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON70 */
72577f22241SEmmanuel Vadot 	COMP(0, "clk_can0_c", gpll_cpll_p, 0, 70, 0, 5, 7, 1),
72677f22241SEmmanuel Vadot 	/* 5:6 Reserved */
72777f22241SEmmanuel Vadot 	COMP(0, "clk_can1_c", gpll_cpll_p, 0, 70, 8, 5, 15, 1),
72877f22241SEmmanuel Vadot 	/* 13:14 Reserved */
72977f22241SEmmanuel Vadot 
73077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON71 */
73177f22241SEmmanuel Vadot 	COMP(0, "clk_can2_c", gpll_cpll_p, 0, 71, 0, 5, 7, 1),
73277f22241SEmmanuel Vadot 	/* 5:6 Reserved */
73377f22241SEmmanuel Vadot 	MUX(0, "clk_i2c_sel", clk_i2c_p, 0, 71, 8, 2),
73477f22241SEmmanuel Vadot 	/* 10:15 Reserved */
73577f22241SEmmanuel Vadot 
73677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON72 */
73777f22241SEmmanuel Vadot 	MUX(0, "clk_spi0_sel", gpll200_xin24m_cpll100_p, 0, 72, 0, 2),
73877f22241SEmmanuel Vadot 	MUX(0, "clk_spi1_sel", gpll200_xin24m_cpll100_p, 0, 72, 2, 2),
73977f22241SEmmanuel Vadot 	MUX(0, "clk_spi2_sel", gpll200_xin24m_cpll100_p, 0, 72, 4, 2),
74077f22241SEmmanuel Vadot 	MUX(0, "clk_spi3_sel", gpll200_xin24m_cpll100_p, 0, 72, 6, 2),
74177f22241SEmmanuel Vadot 	MUX(0, "clk_pwm1_sel", gpll100_xin24m_cpll100_p, 0, 72, 8, 2),
74277f22241SEmmanuel Vadot 	MUX(0, "clk_pwm2_sel", gpll100_xin24m_cpll100_p, 0, 72, 10, 2),
74377f22241SEmmanuel Vadot 	MUX(0, "clk_pwm3_sel", gpll100_xin24m_cpll100_p, 0, 72, 12, 2),
74477f22241SEmmanuel Vadot 	MUX(0, "dbclk_gpio_sel", xin24m_32k_p, 0, 72, 14, 1),
74577f22241SEmmanuel Vadot 	/* 15 Reserved */
74677f22241SEmmanuel Vadot 
74777f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON73 */
74877f22241SEmmanuel Vadot 	MUX(0, "aclk_top_high_sel", cpll500_gpll400_gpll300_xin24m_p, 0, 73, 0, 2),
74977f22241SEmmanuel Vadot 	/* 2:3 Reserved */
75077f22241SEmmanuel Vadot 	MUX(0, "aclk_top_low_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 73, 4, 2),
75177f22241SEmmanuel Vadot 	/* 6:7 Reserved */
75277f22241SEmmanuel Vadot 	MUX(0, "hclk_top_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 73, 8, 2),
75377f22241SEmmanuel Vadot 	/* 10:11 Reserved */
75477f22241SEmmanuel Vadot 	MUX(0, "pclk_top_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 73, 12, 2),
75577f22241SEmmanuel Vadot 	/* 14 Reserved */
75677f22241SEmmanuel Vadot 	MUX(0, "clk_optc_arb_sel", xin24m_cpll100_p, 0, 73, 15 , 1),
75777f22241SEmmanuel Vadot 
75877f22241SEmmanuel Vadot 	/* CRU_CLKSEL_CON74 */
75977f22241SEmmanuel Vadot 	/* 0:7 clk_testout_div CDIV */
76077f22241SEmmanuel Vadot 	/* 8:12 clk_testout_sel MUX */
76177f22241SEmmanuel Vadot 
76277f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON75 */
76377f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_400m_div", "gpll", 0, 75, 0, 5),
76477f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_300m_div", "gpll", 0, 75, 8, 5),
76577f22241SEmmanuel Vadot 
76677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON76 */
76777f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_200m_div", "gpll", 0, 76, 0, 5),
76877f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_150m_div", "gpll", 0, 76, 8, 5),
76977f22241SEmmanuel Vadot 
77077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON77 */
77177f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_100m_div", "gpll", 0, 77, 0, 5),
77277f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_75m_div", "gpll", 0, 77, 8, 5),
77377f22241SEmmanuel Vadot 
77477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON78 */
77577f22241SEmmanuel Vadot 	CDIV(0, "clk_gpll_div_20m_div", "gpll", 0, 78, 0, 6),
77677f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_500m_div", "cpll", 0, 78, 8, 5),
77777f22241SEmmanuel Vadot 
77877f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON79 */
77977f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_333m_div", "cpll", 0, 79, 0, 6),
78077f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_250m_div", "cpll", 0, 79, 8, 5),
78177f22241SEmmanuel Vadot 
78277f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON80 */
78377f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_125m_div", "cpll", 0, 80, 0, 6),
78477f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_62P5m_div", "cpll", 0, 80, 8, 5),
78577f22241SEmmanuel Vadot 
78677f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON81 */
78777f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_50m_div", "cpll", 0, 81, 0, 6),
78877f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_25m_div", "cpll", 0, 81, 8, 5),
78977f22241SEmmanuel Vadot 
79077f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON82 */
79177f22241SEmmanuel Vadot 	CDIV(0, "clk_cpll_div_100m_div", "cpll", 0, 82, 0, 6),
79277f22241SEmmanuel Vadot 	CDIV(0, "clk_osc0_div_750k_div", "xin24m", 0, 82, 8, 5),
79377f22241SEmmanuel Vadot 
79477f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON83 */
79577f22241SEmmanuel Vadot 	CDIV(0, "clk_i2s3_2ch_rx_src_div", "clk_i2s3_2ch_rx_src_sel", 0, 83, 0, 7),
79677f22241SEmmanuel Vadot 	/* 7 Reserved */
79777f22241SEmmanuel Vadot 	MUX(0, "clk_i2s3_2ch_rx_src_sel", gpll_cpll_npll_p, 0, 83, 8, 2),
79877f22241SEmmanuel Vadot 	MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 0, 83, 10,
79977f22241SEmmanuel Vadot 	    2),
80077f22241SEmmanuel Vadot 	/* 12:14 Reserved */
80177f22241SEmmanuel Vadot 	MUX(0, "i2s3_mclkout_rx_sel", i2s3_mclkout_rx_p, 0, 83, 15, 1),
80277f22241SEmmanuel Vadot 
80377f22241SEmmanuel Vadot 	/*  CRU_CLKSEL_CON84 */
80477f22241SEmmanuel Vadot 	FRACT(0, "clk_i2s3_2ch_rx_frac_div", "clk_i2s3_2ch_rx_src", 0, 84),
80577f22241SEmmanuel Vadot };
80677f22241SEmmanuel Vadot 
80777f22241SEmmanuel Vadot /* GATES */
80877f22241SEmmanuel Vadot static struct rk_cru_gate rk3568_gates[] = {
80977f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON00 */
81077f22241SEmmanuel Vadot 	/* 0 clk_core */
81177f22241SEmmanuel Vadot 	/* 1 clk_core0 */
81277f22241SEmmanuel Vadot 	/* 2 clk_core1 */
81377f22241SEmmanuel Vadot 	/* 3 clk_core2 */
81477f22241SEmmanuel Vadot 	/* 4 clk_core3 */
81577f22241SEmmanuel Vadot 	GATE(0, "sclk_core_src", "sclk_core_src_c",			0, 5),
81677f22241SEmmanuel Vadot 	/* 6 clk_npll_core */
81777f22241SEmmanuel Vadot 	/* 7 sclk_core */
81877f22241SEmmanuel Vadot 	GATE(0, "atclk_core", "atclk_core_div",				0, 8),
81977f22241SEmmanuel Vadot 	GATE(0, "gicclk_core", "gicclk_core_div",			0, 9),
82077f22241SEmmanuel Vadot 	GATE(0, "pclk_core_pre", "pclk_core_pre_div",			0, 10),
82177f22241SEmmanuel Vadot 	GATE(0, "periphclk_core_pre", "periphclk_core_pre_div",		0, 11),
82277f22241SEmmanuel Vadot 	/* 12 pclk_core */
82377f22241SEmmanuel Vadot 	/* 13 periphclk_core */
82477f22241SEmmanuel Vadot 	/* 14 tsclk_core */
82577f22241SEmmanuel Vadot 	/* 15 cntclk_core */
82677f22241SEmmanuel Vadot 
82777f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON01 */
82877f22241SEmmanuel Vadot 	/* 0 aclk_core */
82977f22241SEmmanuel Vadot 	/* 1 aclk_core_biuddr */
83077f22241SEmmanuel Vadot 	/* 2 aclk_core_biu2bus */
83177f22241SEmmanuel Vadot 	/* 3 pclk_dgb_biu */
83277f22241SEmmanuel Vadot 	/* 4 pclk_dbg */
83377f22241SEmmanuel Vadot 	/* 5 pclk_dbg_daplite */
83477f22241SEmmanuel Vadot 	/* 6 aclk_adb400_core2gic */
83577f22241SEmmanuel Vadot 	/* 7 aclk_adb400_gic2core */
83677f22241SEmmanuel Vadot 	/* 8 pclk_core_grf */
83777f22241SEmmanuel Vadot 	GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre",		1, 9),
83877f22241SEmmanuel Vadot 	GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m",			1, 10),
83977f22241SEmmanuel Vadot 	GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk",	1, 11),
84077f22241SEmmanuel Vadot 	GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk",		1, 12),
84177f22241SEmmanuel Vadot 	/* 13 clk_core_div2 */
84277f22241SEmmanuel Vadot 	/* 14 clk_apll_core */
84377f22241SEmmanuel Vadot 	/* 15 clk_jtag */
84477f22241SEmmanuel Vadot 
84577f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON02 */
84677f22241SEmmanuel Vadot 	/* 0 clk_gpu_src */
84777f22241SEmmanuel Vadot 	GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0),
84877f22241SEmmanuel Vadot 	/* 1 Reserved */
84977f22241SEmmanuel Vadot 	GATE(PCLK_GPU_PRE, "pclk_gpu_pre", "pclk_gpu_pre_div",		2, 2),
85077f22241SEmmanuel Vadot 	GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_c",			2, 3),
85177f22241SEmmanuel Vadot 	/* 4 aclk_gpu_biu */
85277f22241SEmmanuel Vadot 	/* 5 pclk_gpu_biu */
85377f22241SEmmanuel Vadot 	GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre",		2, 6),
85477f22241SEmmanuel Vadot 	GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m",			2, 7),
85577f22241SEmmanuel Vadot 	GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src",	2, 8),
85677f22241SEmmanuel Vadot 	GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src",		2, 9),
85777f22241SEmmanuel Vadot 	/* 10 clk_gpu_div2 */
85877f22241SEmmanuel Vadot 	GATE(ACLK_GPU_PRE, "aclk_gpu_pre", "aclk_gpu_pre_div",		2, 11),
85977f22241SEmmanuel Vadot 	/* 12:15 Reserved */
86077f22241SEmmanuel Vadot 
86177f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON03 */
86277f22241SEmmanuel Vadot 	GATE(CLK_NPU_SRC, "clk_npu_src", "clk_npu_src_c",		3, 0),
86377f22241SEmmanuel Vadot 	GATE(CLK_NPU_NP5, "clk_npu_np5", "clk_npu_np5_c",		3, 1),
86477f22241SEmmanuel Vadot 	GATE(HCLK_NPU_PRE, "hclk_npu_pre", "hclk_npu_pre_div",		3, 2),
86577f22241SEmmanuel Vadot 	GATE(PCLK_NPU_PRE, "pclk_npu_pre", "pclk_npu_pre_div",		3, 3),
86677f22241SEmmanuel Vadot 	/* 4 aclk_npu_biu */
86777f22241SEmmanuel Vadot 	GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu",			3, 4),
86877f22241SEmmanuel Vadot 	/* 5 hclk_npu_biu */
86977f22241SEmmanuel Vadot 	/* 6 pclk_npu_biu */
87077f22241SEmmanuel Vadot 	GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre",			3, 7),
87177f22241SEmmanuel Vadot 	GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre",			3, 8),
87277f22241SEmmanuel Vadot 	GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre",		3, 9),
87377f22241SEmmanuel Vadot 	GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m",			3, 10),
87477f22241SEmmanuel Vadot 	GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft",3, 11),
87577f22241SEmmanuel Vadot 	GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft",	3, 12),
87677f22241SEmmanuel Vadot 	/* 13 clk_npu_div2 */
87777f22241SEmmanuel Vadot 	/* 14:15 Reserved */
87877f22241SEmmanuel Vadot 
87977f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON04 */
88077f22241SEmmanuel Vadot 	GATE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", "clk_ddrphy1x_src_c",	4, 0),
88177f22241SEmmanuel Vadot 	/* 1 clk_dpll_ddr */
88277f22241SEmmanuel Vadot 	GATE(CLK_MSCH, "clk_msch", "clk_msch_div",			4, 2),
88377f22241SEmmanuel Vadot 	/* 3 clk_hwffc_ctrl */
88477f22241SEmmanuel Vadot 	/* 4 aclk_ddrscramble */
88577f22241SEmmanuel Vadot 	/* 5 aclk_msch */
88677f22241SEmmanuel Vadot 	/* 6 clk_ddr_alwayson */
88777f22241SEmmanuel Vadot 	/* 7 Reserved */
88877f22241SEmmanuel Vadot 	/* 8 aclk_ddrsplit */
88977f22241SEmmanuel Vadot 	/* 9 clk_ddrdft_ctl */
89077f22241SEmmanuel Vadot 	/* 10 Reserved */
89177f22241SEmmanuel Vadot 	/* 11 aclk_dma2ddr */
89277f22241SEmmanuel Vadot 	/* 12 Reserved */
89377f22241SEmmanuel Vadot 	/* 13 clk_ddrmon */
89477f22241SEmmanuel Vadot 	/* 14 Reserved */
89577f22241SEmmanuel Vadot 	GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m",			4, 15),
89677f22241SEmmanuel Vadot 
89777f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON05 */
89877f22241SEmmanuel Vadot 	GATE(ACLK_GIC_AUDIO, "aclk_gic_audio", "aclk_gic_audio_sel",	5, 0),
89977f22241SEmmanuel Vadot 	GATE(HCLK_GIC_AUDIO, "hclk_gic_audio", "hclk_gic_audio_sel",	5, 1),
90077f22241SEmmanuel Vadot 	/* 2 aclk_gic_audio_biu */
90177f22241SEmmanuel Vadot 	/* 3 hclk_gic_audio_biu */
90277f22241SEmmanuel Vadot 	GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio",		5, 4),
90377f22241SEmmanuel Vadot 	/* 5 aclk_gicadb_core2gic */
90477f22241SEmmanuel Vadot 	/* 6 aclk_gicadb_gic2core */
90577f22241SEmmanuel Vadot 	GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio",		5, 7),
90677f22241SEmmanuel Vadot 	GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio",	5, 8),
90777f22241SEmmanuel Vadot 	GATE(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", "dclk_sdmmc_buffer_sel", 5, 9),
90877f22241SEmmanuel Vadot 	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio",		5, 10),
90977f22241SEmmanuel Vadot 	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio",		5, 11),
91077f22241SEmmanuel Vadot 	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio",		5, 12),
91177f22241SEmmanuel Vadot 	GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio",		5, 13),
91277f22241SEmmanuel Vadot 	GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio",			5, 14),
91377f22241SEmmanuel Vadot 	GATE(MCLK_PDM, "mclk_pdm", "mclk_pdm_sel", 5, 15),
91477f22241SEmmanuel Vadot 
91577f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON06 */
91677f22241SEmmanuel Vadot 	GATE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_src_c",	6, 0),
91777f22241SEmmanuel Vadot 	GATE(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_frac_div",	6, 1),
91877f22241SEmmanuel Vadot 	GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx",			6, 2),
91977f22241SEmmanuel Vadot 	GATE(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", "i2s0_mclkout_tx_sel",			6, 3),
92077f22241SEmmanuel Vadot 	GATE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_src_c",	6, 4),
92177f22241SEmmanuel Vadot 	GATE(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_frac_div",	6, 5),
92277f22241SEmmanuel Vadot 	GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx",			6, 6),
92377f22241SEmmanuel Vadot 	GATE(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", "i2s0_mclkout_rx_sel",			6, 7),
92477f22241SEmmanuel Vadot 	GATE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_src_c",	6, 8),
92577f22241SEmmanuel Vadot 	GATE(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_frac_div",	6, 9),
92677f22241SEmmanuel Vadot 	GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx",			6, 10),
92777f22241SEmmanuel Vadot 	GATE(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", "i2s1_mclkout_tx_sel",			6, 11),
92877f22241SEmmanuel Vadot 	GATE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_src_c",	6, 12),
92977f22241SEmmanuel Vadot 	GATE(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_frac_div",	6, 13),
93077f22241SEmmanuel Vadot 	GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx",			6, 14),
93177f22241SEmmanuel Vadot 	GATE(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", "i2s1_mclkout_rx_sel",			6, 15),
93277f22241SEmmanuel Vadot 
93377f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON07 */
93477f22241SEmmanuel Vadot 	GATE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "clk_i2s2_2ch_src_c",		7, 0),
93577f22241SEmmanuel Vadot 	GATE(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_frac_div",		7, 1),
93677f22241SEmmanuel Vadot 	GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch",				7, 2),
93777f22241SEmmanuel Vadot 	GATE(I2S2_MCLKOUT, "i2s2_mclkout", "i2s2_mclkout_sel",				7, 3),
93877f22241SEmmanuel Vadot 	GATE(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_src_c",		7, 4),
93977f22241SEmmanuel Vadot 	GATE(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_frac_div",	7, 5),
94077f22241SEmmanuel Vadot 	GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx",			7, 6),
94177f22241SEmmanuel Vadot 	GATE(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", "i2s3_mclkout_tx_sel",			7, 7),
94277f22241SEmmanuel Vadot 	GATE(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_src_div",		7, 8),
94377f22241SEmmanuel Vadot 	GATE(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_frac_div",	7, 9),
94477f22241SEmmanuel Vadot 	GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx",			7, 10),
94577f22241SEmmanuel Vadot 	GATE(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", "i2s3_mclkout_rx_sel",			7, 11),
94677f22241SEmmanuel Vadot 	GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio",					7, 12),
94777f22241SEmmanuel Vadot 	GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio",			7, 13),
94877f22241SEmmanuel Vadot 	GATE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", "mclk_spdif_8ch_src_c",	7, 14),
94977f22241SEmmanuel Vadot 	GATE(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_frac_div",	7, 15),
95077f22241SEmmanuel Vadot 
95177f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON08 */
95277f22241SEmmanuel Vadot 	GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio",				8, 0),
95377f22241SEmmanuel Vadot 	GATE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", "sclk_audpwm_src_c",			8, 1),
95477f22241SEmmanuel Vadot 	GATE(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_frac_frac",		8, 2),
95577f22241SEmmanuel Vadot 	GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio",				8, 3),
95677f22241SEmmanuel Vadot 	GATE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", "clk_acdcdig_i2c_sel",			8, 4),
95777f22241SEmmanuel Vadot 	GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx",			8, 5),
95877f22241SEmmanuel Vadot 	GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx",			8, 6),
95977f22241SEmmanuel Vadot 	GATE(ACLK_SECURE_FLASH, "aclk_secure_flash", "aclk_secure_flash_sel",		8, 7),
96077f22241SEmmanuel Vadot 	GATE(HCLK_SECURE_FLASH, "hclk_secure_flash", "hclk_secure_flash_sel",		8, 8),
96177f22241SEmmanuel Vadot 	/* 9 aclk_secure_flash_biu */
96277f22241SEmmanuel Vadot 	/* 10 hclk_secure_flash_biu */
96377f22241SEmmanuel Vadot 	GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash",			8, 11),
96477f22241SEmmanuel Vadot 	GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash",			8, 12),
96577f22241SEmmanuel Vadot 	GATE(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", "clk_crypto_ns_core_sel",	8, 13),
96677f22241SEmmanuel Vadot 	GATE(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", "clk_crypto_ns_pka_sel",		8, 14),
96777f22241SEmmanuel Vadot 	GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash",		8, 15),
96877f22241SEmmanuel Vadot 
96977f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON09 */
97077f22241SEmmanuel Vadot 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash",				9, 0),
97177f22241SEmmanuel Vadot 	GATE(NCLK_NANDC, "nclk_nandc", "nclk_nandc_sel",				9, 1),
97277f22241SEmmanuel Vadot 	GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash",					9, 2),
97377f22241SEmmanuel Vadot 	GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash",				9, 3),
97477f22241SEmmanuel Vadot 	GATE(SCLK_SFC, "sclk_sfc", "sclk_sfc_sel",					9, 4),
97577f22241SEmmanuel Vadot 	GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash",				9, 5),
97677f22241SEmmanuel Vadot 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash",				9, 6),
97777f22241SEmmanuel Vadot 	GATE(BCLK_EMMC, "bclk_emmc", "bclk_emmc_sel",					9, 7),
97877f22241SEmmanuel Vadot 	GATE(CCLK_EMMC, "cclk_emmc", "cclk_emmc_sel",					9, 8),
97977f22241SEmmanuel Vadot 	GATE(TCLK_EMMC, "tclk_emmc", "xin24m",						9, 9),
98077f22241SEmmanuel Vadot 	GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash",				9, 10),
98177f22241SEmmanuel Vadot 	GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash",				9, 11),
98277f22241SEmmanuel Vadot 	/* 12:15 Reserved */
98377f22241SEmmanuel Vadot 
98477f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON10 */
98577f22241SEmmanuel Vadot 	GATE(ACLK_PIPE, "aclk_pipe", "aclk_pipe_sel",					10, 0),
98677f22241SEmmanuel Vadot 	GATE(PCLK_PIPE, "pclk_pipe", "pclk_pipe_div",					10, 1),
98777f22241SEmmanuel Vadot 	/* 2 aclk_pipe_biu */
98877f22241SEmmanuel Vadot 	/* 3 pclk_pipe_biu */
98977f22241SEmmanuel Vadot 	GATE(CLK_XPCS_EEE, "clk_xpcs_eee", "clk_xpcs_eee_sel",				10, 4),
99077f22241SEmmanuel Vadot 	/* 5 clk_xpcs_rx_div10 */
99177f22241SEmmanuel Vadot 	/* 6 clk_xpcs_tx_div10 */
99277f22241SEmmanuel Vadot 	/* 7 pclk_pipe_grf */
99377f22241SEmmanuel Vadot 	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe",				10, 8),
99477f22241SEmmanuel Vadot 	GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m",				10, 9),
99577f22241SEmmanuel Vadot 	GATE(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_sel",	10, 10),
99677f22241SEmmanuel Vadot 	/* 11 clk_usb3otg0_pipe */
99777f22241SEmmanuel Vadot 	GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe",				10, 12),
99877f22241SEmmanuel Vadot 	GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m",				10, 13),
99977f22241SEmmanuel Vadot 	GATE(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_sel",	10, 14),
100077f22241SEmmanuel Vadot 	/* 15 clk_usb3otg1_pipe */
100177f22241SEmmanuel Vadot 
100277f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON11 */
100377f22241SEmmanuel Vadot 	GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe",					11, 0),
100477f22241SEmmanuel Vadot 	GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "clk_gpll_div_20m",		11, 1),
100577f22241SEmmanuel Vadot 	GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "clk_cpll_div_50m",			11, 2),
100677f22241SEmmanuel Vadot 	/* 3 clk_sata0_pipe */
100777f22241SEmmanuel Vadot 	GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe",					11, 4),
100877f22241SEmmanuel Vadot 	GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "clk_gpll_div_20m",		11, 5),
100977f22241SEmmanuel Vadot 	GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "clk_cpll_div_50m",			11, 6),
101077f22241SEmmanuel Vadot 	/* 7 clk_sata1_pipe */
101177f22241SEmmanuel Vadot 	GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe",					11, 8),
101277f22241SEmmanuel Vadot 	GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "clk_gpll_div_20m",		11, 9),
101377f22241SEmmanuel Vadot 	GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "clk_cpll_div_50m",			11, 10),
101477f22241SEmmanuel Vadot 	/* 11 clk_sata2_pipe */
101577f22241SEmmanuel Vadot 	/* 12:15 Reserved */
101677f22241SEmmanuel Vadot 
101777f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON12 */
101877f22241SEmmanuel Vadot 	GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe",				12, 0),
101977f22241SEmmanuel Vadot 	GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe",				12, 1),
102077f22241SEmmanuel Vadot 	GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe",				12, 2),
102177f22241SEmmanuel Vadot 	GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe",					12, 3),
102277f22241SEmmanuel Vadot 	GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m",			12, 4),
102377f22241SEmmanuel Vadot 	/* 5 clk_pcie20_pipe */
102477f22241SEmmanuel Vadot 	/* 6:7 Reserved */
102577f22241SEmmanuel Vadot 	GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe",			12, 8),
102677f22241SEmmanuel Vadot 	GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe",			12, 9),
102777f22241SEmmanuel Vadot 	GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe",			12, 10),
102877f22241SEmmanuel Vadot 	GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe",				12, 11),
102977f22241SEmmanuel Vadot 	GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m",			12, 12),
103077f22241SEmmanuel Vadot 	/* 13 clk_pcie30x1_pipe */
103177f22241SEmmanuel Vadot 	/* 14:15 Reserved */
103277f22241SEmmanuel Vadot 
103377f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON13 */
103477f22241SEmmanuel Vadot 	GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe",			13, 0),
103577f22241SEmmanuel Vadot 	GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe",			13, 1),
103677f22241SEmmanuel Vadot 	GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe",			13, 2),
103777f22241SEmmanuel Vadot 	GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe",				13, 3),
103877f22241SEmmanuel Vadot 	GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m",			13, 4),
103977f22241SEmmanuel Vadot 	/* 5 clk_pcie30x2_pipe */
104077f22241SEmmanuel Vadot 	GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe",					13, 6),
104177f22241SEmmanuel Vadot 	/* 7 clk_xpcs_qsgmii_tx */
104277f22241SEmmanuel Vadot 	/* 8 clk_xpcs_qsgmii_rx */
104377f22241SEmmanuel Vadot 	/* 9 clk_xpcs_xgxs_tx */
104477f22241SEmmanuel Vadot 	/* 10 Reserved */
104577f22241SEmmanuel Vadot 	/* 11 clk_xpcs_xgxs_rx */
104677f22241SEmmanuel Vadot 	/* 12 clk_xpcs_mii0_tx */
104777f22241SEmmanuel Vadot 	/* 13 clk_xpcs_mii0_rx */
104877f22241SEmmanuel Vadot 	/* 14 clk_xpcs_mii1_tx */
104977f22241SEmmanuel Vadot 	/* 15 clk_xpcs_mii1_rx */
105077f22241SEmmanuel Vadot 
105177f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON14 */
105277f22241SEmmanuel Vadot 	GATE(ACLK_PERIMID, "aclk_perimid", "aclk_perimid_sel",				14, 0),
105377f22241SEmmanuel Vadot 	GATE(HCLK_PERIMID, "hclk_perimid", "hclk_perimid_sel",				14, 1),
105477f22241SEmmanuel Vadot 	/* 2 aclk_perimid_biu */
105577f22241SEmmanuel Vadot 	/* 3 hclk_perimid_biu */
105677f22241SEmmanuel Vadot 	/* 4:7 Reserved */
105777f22241SEmmanuel Vadot 	GATE(ACLK_PHP, "aclk_php", "aclk_php_sel",					14, 8),
105877f22241SEmmanuel Vadot 	GATE(HCLK_PHP, "hclk_php", "hclk_php_sel",					14, 9),
105977f22241SEmmanuel Vadot 	GATE(PCLK_PHP, "pclk_php", "pclk_php_div",					14, 10),
106077f22241SEmmanuel Vadot 	/* 11 aclk_php_biu */
106177f22241SEmmanuel Vadot 	/* 12 hclk_php_biu */
106277f22241SEmmanuel Vadot 	/* 13 pclk_php_biu */
106377f22241SEmmanuel Vadot 	/* 14:15 Reserved */
106477f22241SEmmanuel Vadot 
106577f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON15 */
106677f22241SEmmanuel Vadot 	GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php",					15, 0),
106777f22241SEmmanuel Vadot 	GATE(CLK_SDMMC0, "clk_sdmmc0", "clk_sdmmc0_sel",				15, 1),
106877f22241SEmmanuel Vadot 	GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php",					15, 2),
106977f22241SEmmanuel Vadot 	GATE(CLK_SDMMC1, "clk_sdmmc1", "clk_sdmmc1_sel",				15, 3),
107077f22241SEmmanuel Vadot 	GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_sel",		15, 4),
107177f22241SEmmanuel Vadot 	GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php",					15, 5),
107277f22241SEmmanuel Vadot 	GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php",					15, 6),
107377f22241SEmmanuel Vadot 	GATE(CLK_MAC0_2TOP, "clk_mac0_2top", "clk_mac0_2top_sel",			15, 7),
107477f22241SEmmanuel Vadot 	GATE(CLK_MAC0_OUT, "clk_mac0_out", "clk_mac0_out_sel",				15, 8),
107577f22241SEmmanuel Vadot 	/* 9:11 Reserved */
107677f22241SEmmanuel Vadot 	GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top",			15, 12),
107777f22241SEmmanuel Vadot 	/* 13:15 Reserved */
107877f22241SEmmanuel Vadot 
107977f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON16 */
108077f22241SEmmanuel Vadot 	GATE(ACLK_USB, "aclk_usb", "aclk_usb_sel",					16, 0),
108177f22241SEmmanuel Vadot 	GATE(HCLK_USB, "hclk_usb", "hclk_usb_sel",					16, 1),
108277f22241SEmmanuel Vadot 	GATE(PCLK_USB, "pclk_usb", "pclk_usb_div",					16, 2),
108377f22241SEmmanuel Vadot 	/* 3 aclk_usb_biu */
108477f22241SEmmanuel Vadot 	/* 4 hclk_usb_biu */
108577f22241SEmmanuel Vadot 	/* 5 pclk_usb_biu */
108677f22241SEmmanuel Vadot 	/* 6 pclk_usb_grf */
108777f22241SEmmanuel Vadot 	/* 7:11 Reserved */
108877f22241SEmmanuel Vadot 	GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb",				16, 12),
108977f22241SEmmanuel Vadot 	GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb",			16, 13),
109077f22241SEmmanuel Vadot 	GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb",				16, 14),
109177f22241SEmmanuel Vadot 	GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb",			16, 15),
109277f22241SEmmanuel Vadot 
109377f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON17 */
109477f22241SEmmanuel Vadot 	GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb",					17, 0),
109577f22241SEmmanuel Vadot 	GATE(CLK_SDMMC2, "clk_sdmmc2", "clk_sdmmc2_sel",				17, 1),
109677f22241SEmmanuel Vadot 	GATE(CLK_GMAC1_PTP_REF, "clK_gmac1_ptp_ref", "clk_gmac1_ptp_ref_sel",		17, 2),
109777f22241SEmmanuel Vadot 	GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb",					17, 3),
109877f22241SEmmanuel Vadot 	GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb",					17, 4),
109977f22241SEmmanuel Vadot 	GATE(CLK_MAC1_2TOP, "clk_mac1_2top", "clk_mac1_2top_sel",			17, 5),
110077f22241SEmmanuel Vadot 	GATE(CLK_MAC1_OUT, "clk_mac1_out", "clk_mac1_out_sel",				17, 6),
110177f22241SEmmanuel Vadot 	/* 7:9 Reserved */
110277f22241SEmmanuel Vadot 	GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top",			17, 10),
110377f22241SEmmanuel Vadot 	/* 11:15 Reserved */
110477f22241SEmmanuel Vadot 
110577f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON18 */
110677f22241SEmmanuel Vadot 	GATE(ACLK_VI, "aclk_vi", "aclk_vi_sel",						18, 0),
110777f22241SEmmanuel Vadot 	GATE(HCLK_VI, "hclk_vi", "hclk_vi_div",						18, 1),
110877f22241SEmmanuel Vadot 	GATE(PCLK_VI, "pclk_vi", "pclk_vi_div",						18, 2),
110977f22241SEmmanuel Vadot 	/* 3 aclk_vi_biu */
111077f22241SEmmanuel Vadot 	/* 4 hclk_vi_biu */
111177f22241SEmmanuel Vadot 	/* 5 pclk_vi_biu */
111277f22241SEmmanuel Vadot 	/* 6:8 Reserved */
111377f22241SEmmanuel Vadot 	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi",					18, 9),
111477f22241SEmmanuel Vadot 	GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi",					18, 10),
111577f22241SEmmanuel Vadot 	GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap1_sel",				18, 11),
111677f22241SEmmanuel Vadot 	/* 12:15 Reserved */
111777f22241SEmmanuel Vadot 
111877f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON19 */
111977f22241SEmmanuel Vadot 	GATE(ACLK_ISP, "aclk_isp", "aclk_vi",						19, 0),
112077f22241SEmmanuel Vadot 	GATE(HCLK_ISP, "hclk_isp", "hclk_vi",						19, 1),
112177f22241SEmmanuel Vadot 	GATE(CLK_ISP, "clk_isp", "clk_isp_c",						19, 2),
112277f22241SEmmanuel Vadot 	/* 3 Reserved */
112377f22241SEmmanuel Vadot 	GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi",				19, 4),
112477f22241SEmmanuel Vadot 	/* 5:7 Reserved */
112577f22241SEmmanuel Vadot 	GATE(CLK_CIF_OUT, "clk_cif_out", "clk_cif_out_c",				19, 8),
112677f22241SEmmanuel Vadot 	GATE(CLK_CAM0_OUT, "clk_cam0_out", "clk_cam0_out_c",				19, 9),
112777f22241SEmmanuel Vadot 	GATE(CLK_CAM1_OUT, "clk_cam1_out", "clk_cam1_out_c",				19, 9),
112877f22241SEmmanuel Vadot 	/* 11:15 Reserved */
112977f22241SEmmanuel Vadot 
113077f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON20 */
113177f22241SEmmanuel Vadot 	/* 0 Reserved or aclk_vo ??? */
113277f22241SEmmanuel Vadot 	GATE(ACLK_VO, "aclk_vo", "aclk_vo_sel",						20, 0),
113377f22241SEmmanuel Vadot 	GATE(HCLK_VO, "hclk_vo", "hclk_vo_div",						20, 1),
113477f22241SEmmanuel Vadot 	GATE(PCLK_VO, "pclk_vo", "pclk_vo_div",						20, 2),
113577f22241SEmmanuel Vadot 	/* 3 aclk_vo_biu */
113677f22241SEmmanuel Vadot 	/* 4 hclk_vo_biu */
113777f22241SEmmanuel Vadot 	/* 5 pclk_vo_biu */
113877f22241SEmmanuel Vadot 	GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c",				20, 6),
113977f22241SEmmanuel Vadot 	/* 7 aclk_vop_biu */
114077f22241SEmmanuel Vadot 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre",					20, 8),
114177f22241SEmmanuel Vadot 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo",						20, 9),
114277f22241SEmmanuel Vadot 	GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_c",					20, 10),
114377f22241SEmmanuel Vadot 	GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_c",					20, 11),
114477f22241SEmmanuel Vadot 	GATE(DCLK_VOP2, "dclk_vop2", "dclk_vop2_c",					20, 12),
114577f22241SEmmanuel Vadot 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m",					20, 13),
114677f22241SEmmanuel Vadot 	/* 14:15 Reserved */
114777f22241SEmmanuel Vadot 
114877f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON21 */
114977f22241SEmmanuel Vadot 	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo",						21, 0),
115077f22241SEmmanuel Vadot 	GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo",						21, 1),
115177f22241SEmmanuel Vadot 	GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo",						21, 2),
115277f22241SEmmanuel Vadot 	GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo",				21, 3),
115377f22241SEmmanuel Vadot 	GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m",					21, 4),
115477f22241SEmmanuel Vadot 	GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k",				21, 5),
115577f22241SEmmanuel Vadot 	GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo",					21, 6),
115677f22241SEmmanuel Vadot 	GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo",					21, 7),
115777f22241SEmmanuel Vadot 	GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo",					21, 8),
115877f22241SEmmanuel Vadot 	GATE(CLK_EDP_200M, "clk_edp_200m", "clk_edp_200m_sel",				21, 9),
115977f22241SEmmanuel Vadot 	/* 10:15 Reserved */
116077f22241SEmmanuel Vadot 
116177f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON22 */
116277f22241SEmmanuel Vadot 	GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c",				22, 0),
116377f22241SEmmanuel Vadot 	GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre_c",				22, 1),
116477f22241SEmmanuel Vadot 	/* 2 aclk_vpu_biu */
116577f22241SEmmanuel Vadot 	/* 3 hclk_vpu_biu */
116677f22241SEmmanuel Vadot 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre",					22, 4),
116777f22241SEmmanuel Vadot 	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre",					22, 5),
116877f22241SEmmanuel Vadot 	/* 6:11 Reserved */
116977f22241SEmmanuel Vadot 	GATE(PCLK_RGA_PRE, "pclk_rga_pre", "pclk_rga_pre_div",				22, 12),
117077f22241SEmmanuel Vadot 	/* 13 pclk_rga_biu */
117177f22241SEmmanuel Vadot 	GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre",					22, 14),
117277f22241SEmmanuel Vadot 	GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre",					22, 15),
117377f22241SEmmanuel Vadot 
117477f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON23 */
117577f22241SEmmanuel Vadot 	GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_sel",				23, 0),
117677f22241SEmmanuel Vadot 	GATE(HCLK_RGA_PRE, "hclk_rga_pre", "hclk_rga_pre_div",				23, 1),
117777f22241SEmmanuel Vadot 	/* 2 aclk_rga_biu */
117877f22241SEmmanuel Vadot 	/* 3 hclk_rga_biu */
117977f22241SEmmanuel Vadot 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre",					23, 4),
118077f22241SEmmanuel Vadot 	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre",					23, 5),
118177f22241SEmmanuel Vadot 	GATE(CLK_RGA_CORE, "clk_rga_core", "clk_rga_core_sel",				23, 6),
118277f22241SEmmanuel Vadot 	GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre",					23, 7),
118377f22241SEmmanuel Vadot 	GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre",					23, 8),
118477f22241SEmmanuel Vadot 	GATE(CLK_IEP_CORE, "clk_iep_core", "clk_iep_core_sel",				23, 9),
118577f22241SEmmanuel Vadot 	GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre",					23, 10),
118677f22241SEmmanuel Vadot 	GATE(DCLK_EBC, "dclk_ebc", "dclk_ebc_sel",					23, 11),
118777f22241SEmmanuel Vadot 	GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre",					23, 12),
118877f22241SEmmanuel Vadot 	GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre",					23, 13),
118977f22241SEmmanuel Vadot 	GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre",					23, 14),
119077f22241SEmmanuel Vadot 	GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre",					23, 15),
119177f22241SEmmanuel Vadot 
119277f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON24 */
119377f22241SEmmanuel Vadot 	GATE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", "aclk_rkvenc_pre_c",			24, 0),
119477f22241SEmmanuel Vadot 	GATE(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "hclk_rkvenc_pre_div",			24, 1),
119577f22241SEmmanuel Vadot 	/* 2 Reserved */
119677f22241SEmmanuel Vadot 	/* 3 aclk_rkvenc_biu */
119777f22241SEmmanuel Vadot 	/* 4 hclk_rkvenc_biu */
119877f22241SEmmanuel Vadot 	/* 5 Reserved */
119977f22241SEmmanuel Vadot 	GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre",				24, 6),
120077f22241SEmmanuel Vadot 	GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre",				24, 7),
120177f22241SEmmanuel Vadot 	GATE(CLK_RKVENC_CORE, "clk_rkvenc_core", "clk_rkvenc_core_c",			24, 8),
120277f22241SEmmanuel Vadot 	/* 9:15 Reserved */
120377f22241SEmmanuel Vadot 
120477f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON25 */
120577f22241SEmmanuel Vadot 	GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_pre_c",			25, 0),
120677f22241SEmmanuel Vadot 	GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "hclk_rkvdec_pre_div",			25, 1),
120777f22241SEmmanuel Vadot 	/* 2 aclk_rkvdec_biu */
120877f22241SEmmanuel Vadot 	/* 3 hclk_rkvdec_biu */
120977f22241SEmmanuel Vadot 	GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre",				25, 4),
121077f22241SEmmanuel Vadot 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre",				25, 5),
121177f22241SEmmanuel Vadot 	GATE(CLK_RKVDEC_CA, "clk_rkvdec_ca", "clk_rkvdec_ca_c",			25, 6),
121277f22241SEmmanuel Vadot 	GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "clk_rkvdec_core_c",			25, 7),
121377f22241SEmmanuel Vadot 	GATE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", "clk_rkvdec_hevc_ca_c",	25, 8),
121477f22241SEmmanuel Vadot 	/* 9:15 Reserved */
121577f22241SEmmanuel Vadot 
121677f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON26 */
121777f22241SEmmanuel Vadot 	GATE(ACLK_BUS, "aclk_bus", "aclk_bus_sel",					26, 0),
121877f22241SEmmanuel Vadot 	GATE(PCLK_BUS, "pclk_bus", "pclk_bus_sel",					26, 1),
121977f22241SEmmanuel Vadot 	/* 2 aclk_bus_biu */
122077f22241SEmmanuel Vadot 	/* 3 pclk_bus_biu */
122177f22241SEmmanuel Vadot 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus",					26, 4),
122277f22241SEmmanuel Vadot 	GATE(CLK_TSADC_TSEN, "clk_tsadc_tsen", "clk_tsadc_tsen_c",			26, 5),
122377f22241SEmmanuel Vadot 	GATE(CLK_TSADC, "clk_tsadc", "clk_tsadc_div",					26, 6),
122477f22241SEmmanuel Vadot 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus",					26, 7),
122577f22241SEmmanuel Vadot 	GATE(CLK_SARADC, "clk_saradc", "xin24m",					26, 8),
122677f22241SEmmanuel Vadot 	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash",				26, 9),
122777f22241SEmmanuel Vadot 	GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m",				26, 10),
122877f22241SEmmanuel Vadot 	GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half",			26, 11),
122977f22241SEmmanuel Vadot 	GATE(PCLK_SCR, "pclk_scr", "pclk_bus",						26, 12),
123077f22241SEmmanuel Vadot 	GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus",					26, 13),
123177f22241SEmmanuel Vadot 	GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m",					26, 14),
123277f22241SEmmanuel Vadot 	/* 15 Reserved */
123377f22241SEmmanuel Vadot 
123477f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON27 */
123577f22241SEmmanuel Vadot 	/* 0 pclk_grf */
123677f22241SEmmanuel Vadot 	/* 1 pclk_grf_vccio12 */
123777f22241SEmmanuel Vadot 	/* 2 pclk_grf_vccio34 */
123877f22241SEmmanuel Vadot 	/* 3 pclk_grf_vccio567 */
123977f22241SEmmanuel Vadot 	GATE(PCLK_CAN0, "pclk_can0", "pclk_bus",					27, 5),
124077f22241SEmmanuel Vadot 	GATE(CLK_CAN0, "clk_can0", "clk_can0_c",					27, 6),
124177f22241SEmmanuel Vadot 	GATE(PCLK_CAN1, "pclk_can1", "pclk_bus",					27, 7),
124277f22241SEmmanuel Vadot 	GATE(CLK_CAN1, "clk_can1", "clk_can1_c",					27, 8),
124377f22241SEmmanuel Vadot 	GATE(PCLK_CAN2, "pclk_can2", "pclk_bus",					27, 9),
124477f22241SEmmanuel Vadot 	GATE(CLK_CAN2, "clk_can2", "clk_can2_c",					27, 10),
124577f22241SEmmanuel Vadot 	/* 11 Reserved */
124677f22241SEmmanuel Vadot 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus",					27, 12),
124777f22241SEmmanuel Vadot 	GATE(CLK_UART1_SRC, "clk_uart1_src", "clk_uart1_src_c",			27, 13),
124877f22241SEmmanuel Vadot 	GATE(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_frac_frac",			27, 14),
124977f22241SEmmanuel Vadot 	GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_sel",				27, 15),
125077f22241SEmmanuel Vadot 
125177f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON28 */
125277f22241SEmmanuel Vadot 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus",					28, 0),
125377f22241SEmmanuel Vadot 	GATE(CLK_UART2_SRC, "clk_uart2_src", "clk_uart2_src_c",			28, 1),
125477f22241SEmmanuel Vadot 	GATE(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_frac_frac",			28, 2),
125577f22241SEmmanuel Vadot 	GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_sel",				28, 3),
125677f22241SEmmanuel Vadot 	GATE(PCLK_UART3, "pclk_uart3", "pclk_bus",					28, 4),
125777f22241SEmmanuel Vadot 	GATE(CLK_UART3_SRC, "clk_uart3_src", "clk_uart3_src_c",			28, 5),
125877f22241SEmmanuel Vadot 	GATE(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_frac_frac",			28, 6),
125977f22241SEmmanuel Vadot 	GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_sel",				28, 7),
126077f22241SEmmanuel Vadot 	GATE(PCLK_UART4, "pclk_uart4", "pclk_bus",					28, 8),
126177f22241SEmmanuel Vadot 	GATE(CLK_UART4_SRC, "clk_uart4_src", "clk_uart4_src_c",			28, 9),
126277f22241SEmmanuel Vadot 	GATE(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_frac_frac",			28, 10),
126377f22241SEmmanuel Vadot 	GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_sel",				28, 11),
126477f22241SEmmanuel Vadot 	GATE(PCLK_UART5, "pclk_uart5", "pclk_bus",					28, 12),
126577f22241SEmmanuel Vadot 	GATE(CLK_UART5_SRC, "clk_uart5_src", "clk_uart5_src_c",			28, 13),
126677f22241SEmmanuel Vadot 	GATE(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_frac_frac", 			28, 14),
126777f22241SEmmanuel Vadot 	GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_sel",				28, 15),
126877f22241SEmmanuel Vadot 
126977f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON29 */
127077f22241SEmmanuel Vadot 	GATE(PCLK_UART6, "pclk_uart6", "pclk_bus",					29, 0),
127177f22241SEmmanuel Vadot 	GATE(CLK_UART6_SRC, "clk_uart6_src", "clk_uart6_src_c",			29, 1),
127277f22241SEmmanuel Vadot 	GATE(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_frac_frac",			29, 2),
127377f22241SEmmanuel Vadot 	GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_sel",				29, 3),
127477f22241SEmmanuel Vadot 	GATE(PCLK_UART7, "pclk_uart7", "pclk_bus",					29, 4),
127577f22241SEmmanuel Vadot 	GATE(CLK_UART7_SRC, "clk_uart7_src", "clk_uart7_src_c",			29, 5),
127677f22241SEmmanuel Vadot 	GATE(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_frac_frac",			29, 6),
127777f22241SEmmanuel Vadot 	GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_sel",				29, 7),
127877f22241SEmmanuel Vadot 	GATE(PCLK_UART8, "pclk_uart8", "pclk_bus",					29, 8),
127977f22241SEmmanuel Vadot 	GATE(CLK_UART8_SRC, "clk_uart8_src", "clk_uart8_src_c",			29, 9),
128077f22241SEmmanuel Vadot 	GATE(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_frac_frac",			29, 10),
128177f22241SEmmanuel Vadot 	GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_sel",				29, 11),
128277f22241SEmmanuel Vadot 	GATE(PCLK_UART9, "pclk_uart9", "pclk_bus",					29, 12),
128377f22241SEmmanuel Vadot 	GATE(CLK_UART9_SRC, "clk_uart9_src", "clk_uart9_src_c",			29, 13),
128477f22241SEmmanuel Vadot 	GATE(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_frac_frac",			29, 14),
128577f22241SEmmanuel Vadot 	GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_sel",				29, 15),
128677f22241SEmmanuel Vadot 
128777f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON30 */
128877f22241SEmmanuel Vadot 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus",					30, 0),
128977f22241SEmmanuel Vadot 	GATE(CLK_I2C1, "clk_i2c1", "clk_i2c",						30, 1),
129077f22241SEmmanuel Vadot 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus",					30, 2),
129177f22241SEmmanuel Vadot 	GATE(CLK_I2C2, "clk_i2c2", "clk_i2c",						30, 3),
129277f22241SEmmanuel Vadot 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus",					30, 4),
129377f22241SEmmanuel Vadot 	GATE(CLK_I2C3, "clk_i2c3", "clk_i2c",						30, 5),
129477f22241SEmmanuel Vadot 	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus",					30, 6),
129577f22241SEmmanuel Vadot 	GATE(CLK_I2C4, "clk_i2c4", "clk_i2c",						30, 7),
129677f22241SEmmanuel Vadot 	GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus",					30, 8),
129777f22241SEmmanuel Vadot 	GATE(CLK_I2C5, "clk_i2c5", "clk_i2c",						30, 9),
129877f22241SEmmanuel Vadot 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus",					30, 10),
129977f22241SEmmanuel Vadot 	GATE(CLK_SPI0, "clk_spi0", "clk_spi0_sel",					30, 11),
130077f22241SEmmanuel Vadot 	GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus",					30, 12),
130177f22241SEmmanuel Vadot 	GATE(CLK_SPI1, "clk_spi1", "clk_spi1_sel",					30, 13),
130277f22241SEmmanuel Vadot 	GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus",					30, 14),
130377f22241SEmmanuel Vadot 	GATE(CLK_SPI2, "clk_spi2", "clk_spi2_sel",					30, 15),
130477f22241SEmmanuel Vadot 
130577f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON31 */
130677f22241SEmmanuel Vadot 	GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus",					31, 0),
130777f22241SEmmanuel Vadot 	GATE(CLK_SPI3, "clk_spi3", "clk_spi3_sel",					31, 1),
130877f22241SEmmanuel Vadot 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus",					31, 2),
130977f22241SEmmanuel Vadot 	GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio",					31, 3),
131077f22241SEmmanuel Vadot 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus",					31, 4),
131177f22241SEmmanuel Vadot 	GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio",					31, 5),
131277f22241SEmmanuel Vadot 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus",					31, 6),
131377f22241SEmmanuel Vadot 	GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio",					31, 7),
131477f22241SEmmanuel Vadot 	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus",					31, 8),
131577f22241SEmmanuel Vadot 	GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio",					31, 9),
131677f22241SEmmanuel Vadot 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus",					31, 10),
131777f22241SEmmanuel Vadot 	GATE(CLK_PWM1, "clk_pwm1", "clk_pwm1_sel",					31, 11),
131877f22241SEmmanuel Vadot 	GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m",				31, 12),
131977f22241SEmmanuel Vadot 	GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus",					31, 13),
132077f22241SEmmanuel Vadot 	GATE(CLK_PWM2, "clk_pwm2", "clk_pwm2_sel",					31, 14),
132177f22241SEmmanuel Vadot 	GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m",				31, 15),
132277f22241SEmmanuel Vadot 
132377f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON32 */
132477f22241SEmmanuel Vadot 	GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus",					32, 0),
132577f22241SEmmanuel Vadot 	GATE(CLK_PWM3, "clk_pwm3", "clk_pwm3_sel",					32, 1),
132677f22241SEmmanuel Vadot 	GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m",				32, 2),
132777f22241SEmmanuel Vadot 	GATE(PCLK_TIMER, "pclk_timer", "pclk_bus",					32, 3),
132877f22241SEmmanuel Vadot 	GATE(CLK_TIMER0, "clk_timer0", "xin24m",					32, 4),
132977f22241SEmmanuel Vadot 	GATE(CLK_TIMER1, "clk_timer1", "xin24m",					32, 5),
133077f22241SEmmanuel Vadot 	GATE(CLK_TIMER2, "clk_timer2", "xin24m",					32, 6),
133177f22241SEmmanuel Vadot 	GATE(CLK_TIMER3, "clk_timer3", "xin24m",					32, 7),
133277f22241SEmmanuel Vadot 	GATE(CLK_TIMER4, "clk_timer4", "xin24m",					32, 8),
133377f22241SEmmanuel Vadot 	GATE(CLK_TIMER5, "clk_timer5", "xin24m",					32, 9),
133477f22241SEmmanuel Vadot 	GATE(CLK_I2C, "clk_i2c", "clk_i2c_sel",						32, 10),
133577f22241SEmmanuel Vadot 	GATE(DBCLK_GPIO, "dbclk_gpio", "dbclk_gpio_sel",				32, 11),
133677f22241SEmmanuel Vadot 	/* 12 clk_timer */
133777f22241SEmmanuel Vadot 	GATE(ACLK_MCU, "aclk_mcu", "aclk_bus",						32, 13),
133877f22241SEmmanuel Vadot 	GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus",					32, 14),
133977f22241SEmmanuel Vadot 	GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus",					32, 15),
134077f22241SEmmanuel Vadot 
134177f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON33 */
134277f22241SEmmanuel Vadot 	GATE(ACLK_TOP_HIGH, "aclk_top_high", "aclk_top_high_sel",			33, 0),
134377f22241SEmmanuel Vadot 	GATE(ACLK_TOP_LOW, "aclk_top_low", "aclk_top_low_sel",				33, 1),
134477f22241SEmmanuel Vadot 	GATE(HCLK_TOP, "hclk_top", "hclk_top_sel",					33, 2),
134577f22241SEmmanuel Vadot 	GATE(PCLK_TOP, "pclk_top", "pclk_top_sel",					33, 3),
134677f22241SEmmanuel Vadot 	/* 4 aclk_top_high_biu */
134777f22241SEmmanuel Vadot 	/* 5 aclk_top_low_biu */
134877f22241SEmmanuel Vadot 	/* 6 hclk_top_biu */
134977f22241SEmmanuel Vadot 	/* 7 pclk_top_biu */
135077f22241SEmmanuel Vadot 	GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top",				33, 8),
135177f22241SEmmanuel Vadot 	GATE(CLK_OPTC_ARB, "clk_optc_arb", "clk_optc_arb_sel",				33, 9),
135277f22241SEmmanuel Vadot 	/* 10:11 Reserved */
135377f22241SEmmanuel Vadot 	/* 12 pclk_top_cru */
135477f22241SEmmanuel Vadot 	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top",				33, 13),
135577f22241SEmmanuel Vadot 	GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top",				33, 14),
135677f22241SEmmanuel Vadot 	GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top",				33, 15),
135777f22241SEmmanuel Vadot 
135877f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON34 */
135977f22241SEmmanuel Vadot 	/* 0 pclk_apb2asb_chip_left */
136077f22241SEmmanuel Vadot 	/* 1 pclk_apb2asb_chip_bottom */
136177f22241SEmmanuel Vadot 	/* 2 pclk_asb2apb_chip_left */
136277f22241SEmmanuel Vadot 	/* 3 pclk_asb2apb_chip_bottom */
136377f22241SEmmanuel Vadot 	GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top",				34, 4),
136477f22241SEmmanuel Vadot 	GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top",				34, 5),
136577f22241SEmmanuel Vadot 	GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top",				34, 6),
136677f22241SEmmanuel Vadot 	/* 7 pclk_usb2phy0_grf */
136777f22241SEmmanuel Vadot 	/* 8 pclk_usb2phy1_grf */
136877f22241SEmmanuel Vadot 	/* 9 pclk_ddrphy */
136977f22241SEmmanuel Vadot 	/* 10 clk_ddrphy */
137077f22241SEmmanuel Vadot 	GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top",				34, 11),
137177f22241SEmmanuel Vadot 	GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m",					34, 12),
137277f22241SEmmanuel Vadot 	GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top",					34, 13),
137377f22241SEmmanuel Vadot 	GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top",				34, 14),
137477f22241SEmmanuel Vadot 	/* 15 clk_testout */
137577f22241SEmmanuel Vadot 
137677f22241SEmmanuel Vadot 	/* CRU_CLKGATE_CON35 */
137777f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_400m", "clk_gpll_div_400m_div",				35, 0),
137877f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_300m", "clk_gpll_div_300m_div",				35, 1),
137977f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_200m", "clk_gpll_div_200m_div",				35, 2),
138077f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_150m", "clk_gpll_div_150m_div",				35, 3),
138177f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_100m", "clk_gpll_div_100m_div",				35, 4),
138277f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_75m", "clk_gpll_div_75m_div",				35, 5),
138377f22241SEmmanuel Vadot 	GATE(0, "clk_gpll_div_20m", "clk_gpll_div_20m_div",				35, 6),
138477f22241SEmmanuel Vadot 	GATE(CPLL_500M, "clk_cpll_div_500m", "clk_cpll_div_500m_div",			35, 7),
138577f22241SEmmanuel Vadot 	GATE(CPLL_333M, "clk_cpll_div_333m", "clk_cpll_div_333m_div",			35, 8),
138677f22241SEmmanuel Vadot 	GATE(CPLL_250M, "clk_cpll_div_250m", "clk_cpll_div_250m_div",			35, 9),
138777f22241SEmmanuel Vadot 	GATE(CPLL_125M, "clk_cpll_div_125m", "clk_cpll_div_125m_div",			35, 10),
138877f22241SEmmanuel Vadot 	GATE(CPLL_100M, "clk_cpll_div_100m", "clk_cpll_div_100m_div",			35, 11),
138977f22241SEmmanuel Vadot 	GATE(CPLL_62P5M, "clk_cpll_div_62P5m", "clk_cpll_div_62P5m_div",		35, 12),
139077f22241SEmmanuel Vadot 	GATE(CPLL_50M, "clk_cpll_div_50m", "clk_cpll_div_50m_div",			35, 13),
139177f22241SEmmanuel Vadot 	GATE(CPLL_25M, "clk_cpll_div_25m", "clk_cpll_div_25m_div",			35, 14),
139277f22241SEmmanuel Vadot 	GATE(0, "clk_osc0_div_750k", "clk_osc0_div_750k_div",				35, 15),
139377f22241SEmmanuel Vadot };
139477f22241SEmmanuel Vadot 
139577f22241SEmmanuel Vadot 
139677f22241SEmmanuel Vadot static int
rk3568_cru_probe(device_t dev)139777f22241SEmmanuel Vadot rk3568_cru_probe(device_t dev)
139877f22241SEmmanuel Vadot {
139977f22241SEmmanuel Vadot 
140077f22241SEmmanuel Vadot 	if (!ofw_bus_status_okay(dev))
140177f22241SEmmanuel Vadot 		return (ENXIO);
140277f22241SEmmanuel Vadot 
140377f22241SEmmanuel Vadot 	if (ofw_bus_is_compatible(dev, "rockchip,rk3568-cru")) {
140477f22241SEmmanuel Vadot 		device_set_desc(dev, "Rockchip RK3568 Clock & Reset Unit");
140577f22241SEmmanuel Vadot 		return (BUS_PROBE_DEFAULT);
140677f22241SEmmanuel Vadot 	}
140777f22241SEmmanuel Vadot 	return (ENXIO);
140877f22241SEmmanuel Vadot }
140977f22241SEmmanuel Vadot 
141077f22241SEmmanuel Vadot static int
rk3568_cru_attach(device_t dev)141177f22241SEmmanuel Vadot rk3568_cru_attach(device_t dev)
141277f22241SEmmanuel Vadot {
141377f22241SEmmanuel Vadot 	struct rk_cru_softc *sc;
141477f22241SEmmanuel Vadot 
141577f22241SEmmanuel Vadot 	sc = device_get_softc(dev);
141677f22241SEmmanuel Vadot 	sc->dev = dev;
141777f22241SEmmanuel Vadot 	sc->clks = rk3568_clks;
141877f22241SEmmanuel Vadot 	sc->nclks = nitems(rk3568_clks);
141977f22241SEmmanuel Vadot 	sc->gates = rk3568_gates;
142077f22241SEmmanuel Vadot 	sc->ngates = nitems(rk3568_gates);
142177f22241SEmmanuel Vadot 	sc->reset_offset = 0x400;
142277f22241SEmmanuel Vadot 	sc->reset_num = 478;
142377f22241SEmmanuel Vadot 
142477f22241SEmmanuel Vadot 	return (rk_cru_attach(dev));
142577f22241SEmmanuel Vadot }
142677f22241SEmmanuel Vadot 
142777f22241SEmmanuel Vadot static device_method_t methods[] = {
142877f22241SEmmanuel Vadot 	/* Device interface */
142977f22241SEmmanuel Vadot 	DEVMETHOD(device_probe,		rk3568_cru_probe),
143077f22241SEmmanuel Vadot 	DEVMETHOD(device_attach,	rk3568_cru_attach),
143177f22241SEmmanuel Vadot 
143277f22241SEmmanuel Vadot 	DEVMETHOD_END
143377f22241SEmmanuel Vadot };
143477f22241SEmmanuel Vadot 
143577f22241SEmmanuel Vadot DEFINE_CLASS_1(rk3568_cru, rk3568_cru_driver, methods,
143677f22241SEmmanuel Vadot     sizeof(struct rk_cru_softc), rk_cru_driver);
143777f22241SEmmanuel Vadot 
143877f22241SEmmanuel Vadot EARLY_DRIVER_MODULE(rk3568_cru, simplebus, rk3568_cru_driver,
143977f22241SEmmanuel Vadot     0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1440