1 /*-
2 * Copyright (c) 2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_platform.h"
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/bus.h>
33 #include <sys/lock.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/proc.h>
37 #include <sys/pcpu.h>
38 #include <sys/sched.h>
39
40 #include <machine/bus.h>
41 #include <machine/tlb.h>
42
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <powerpc/mpc85xx/mpc85xx.h>
47
48 #include "qman.h"
49 #include "portals.h"
50
51 extern e_RxStoreResponse qman_received_frame_callback(t_Handle, t_Handle,
52 t_Handle, uint32_t, t_DpaaFD *);
53 extern e_RxStoreResponse qman_rejected_frame_callback(t_Handle, t_Handle,
54 t_Handle, uint32_t, t_DpaaFD *, t_QmRejectedFrameInfo *);
55
56 t_Handle qman_portal_setup(struct qman_softc *);
57
58 struct dpaa_portals_softc *qp_sc;
59
60 int
qman_portals_attach(device_t dev)61 qman_portals_attach(device_t dev)
62 {
63 struct dpaa_portals_softc *sc;
64
65 sc = qp_sc = device_get_softc(dev);
66
67 /* Map bman portal to physical address space */
68 if (law_enable(OCP85XX_TGTIF_QMAN, sc->sc_dp_pa, sc->sc_dp_size)) {
69 qman_portals_detach(dev);
70 return (ENXIO);
71 }
72 /* Set portal properties for XX_VirtToPhys() */
73 XX_PortalSetInfo(dev);
74
75 return (bus_generic_attach(dev));
76 }
77
78 int
qman_portals_detach(device_t dev)79 qman_portals_detach(device_t dev)
80 {
81 struct dpaa_portals_softc *sc;
82 int i;
83
84 qp_sc = NULL;
85 sc = device_get_softc(dev);
86
87 for (i = 0; i < ARRAY_SIZE(sc->sc_dp); i++) {
88 if (sc->sc_dp[i].dp_ph != NULL) {
89 thread_lock(curthread);
90 sched_bind(curthread, i);
91 thread_unlock(curthread);
92
93 QM_PORTAL_Free(sc->sc_dp[i].dp_ph);
94
95 thread_lock(curthread);
96 sched_unbind(curthread);
97 thread_unlock(curthread);
98 }
99
100 if (sc->sc_dp[i].dp_ires != NULL) {
101 XX_DeallocIntr((uintptr_t)sc->sc_dp[i].dp_ires);
102 bus_release_resource(dev, SYS_RES_IRQ,
103 sc->sc_dp[i].dp_irid, sc->sc_dp[i].dp_ires);
104 }
105 }
106 for (i = 0; i < ARRAY_SIZE(sc->sc_rres); i++) {
107 if (sc->sc_rres[i] != NULL)
108 bus_release_resource(dev, SYS_RES_MEMORY,
109 sc->sc_rrid[i],
110 sc->sc_rres[i]);
111 }
112
113 return (0);
114 }
115
116 t_Handle
qman_portal_setup(struct qman_softc * qsc)117 qman_portal_setup(struct qman_softc *qsc)
118 {
119 struct dpaa_portals_softc *sc;
120 t_QmPortalParam qpp;
121 unsigned int cpu;
122 uintptr_t p;
123 t_Handle portal;
124
125 /* Return NULL if we're not ready or while detach */
126 if (qp_sc == NULL)
127 return (NULL);
128
129 sc = qp_sc;
130
131 sched_pin();
132 portal = NULL;
133 cpu = PCPU_GET(cpuid);
134
135 /* Check if portal is ready */
136 while (atomic_cmpset_acq_ptr((uintptr_t *)&sc->sc_dp[cpu].dp_ph,
137 0, -1) == 0) {
138 p = atomic_load_acq_ptr((uintptr_t *)&sc->sc_dp[cpu].dp_ph);
139
140 /* Return if portal is already initialized */
141 if (p != 0 && p != -1) {
142 sched_unpin();
143 return ((t_Handle)p);
144 }
145
146 /* Not inititialized and "owned" by another thread */
147 sched_relinquish(curthread);
148 }
149
150 /* Map portal registers */
151 dpaa_portal_map_registers(sc);
152
153 /* Configure and initialize portal */
154 qpp.ceBaseAddress = rman_get_bushandle(sc->sc_rres[0]);
155 qpp.ciBaseAddress = rman_get_bushandle(sc->sc_rres[1]);
156 qpp.h_Qm = qsc->sc_qh;
157 qpp.swPortalId = cpu;
158 qpp.irq = (uintptr_t)sc->sc_dp[cpu].dp_ires;
159 qpp.fdLiodnOffset = 0;
160 qpp.f_DfltFrame = qman_received_frame_callback;
161 qpp.f_RejectedFrame = qman_rejected_frame_callback;
162 qpp.h_App = qsc;
163
164 portal = QM_PORTAL_Config(&qpp);
165 if (portal == NULL)
166 goto err;
167
168 if (QM_PORTAL_Init(portal) != E_OK)
169 goto err;
170
171 if (QM_PORTAL_AddPoolChannel(portal, QMAN_COMMON_POOL_CHANNEL) != E_OK)
172 goto err;
173
174 atomic_store_rel_ptr((uintptr_t *)&sc->sc_dp[cpu].dp_ph,
175 (uintptr_t)portal);
176 sched_unpin();
177
178 return (portal);
179
180 err:
181 if (portal != NULL)
182 QM_PORTAL_Free(portal);
183
184 atomic_store_rel_32((uint32_t *)&sc->sc_dp[cpu].dp_ph, 0);
185 sched_unpin();
186
187 return (NULL);
188 }
189