1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
3 #ifndef _ENETC_HW_H_
4 #define _ENETC_HW_H_
5
6 #include <sys/cdefs.h>
7
8 #include <sys/param.h>
9
10 #define BIT(x) (1UL << (x))
11 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
12 #define ilog2(x) (flsl(x) - 1)
13
14 #define PCI_VENDOR_FREESCALE 0x1957
15
16 /* ENETC device IDs */
17 #define ENETC_DEV_ID_PF 0xe100
18 #define ENETC_DEV_ID_VF 0xef00
19 #define ENETC_DEV_ID_PTP 0xee02
20
21 /* ENETC register block BAR */
22 #define ENETC_BAR_REGS 0
23
24 /** SI regs, offset: 0h */
25 #define ENETC_SIMR 0
26 #define ENETC_SIMR_EN BIT(31)
27 #define ENETC_SIMR_DRXG BIT(16)
28 #define ENETC_SIMR_RSSE BIT(0)
29 #define ENETC_SICTR0 0x18
30 #define ENETC_SICTR1 0x1c
31 #define ENETC_SIPCAPR0 0x20
32 #define ENETC_SIPCAPR0_QBV BIT(4)
33 #define ENETC_SIPCAPR0_PSFP BIT(9)
34 #define ENETC_SIPCAPR0_RSS BIT(8)
35 #define ENETC_SIPCAPR1 0x24
36 #define ENETC_SITGTGR 0x30
37 #define ENETC_SIRBGCR 0x38
38 /* cache attribute registers for transactions initiated by ENETC */
39 #define ENETC_SICAR0 0x40
40 #define ENETC_SICAR1 0x44
41 #define ENETC_SICAR2 0x48
42 /* rd snoop, no alloc
43 * wr snoop, no alloc, partial cache line update for BDs and full cache line
44 * update for data
45 */
46 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
47 #define ENETC_SICAR_WR_COHERENT 0x00006727
48 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
49
50 #define ENETC_SIPMAR0 0x80
51 #define ENETC_SIPMAR1 0x84
52
53 /* VF-PF Message passing */
54 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
55
56 #define ENETC_PSIMSGRR 0x204
57 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)
58 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
59 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
60 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
61
62 #define ENETC_VSIMSGSR 0x204 /* RO */
63 #define ENETC_VSIMSGSR_MB BIT(0)
64 #define ENETC_VSIMSGSR_MS BIT(1)
65 #define ENETC_VSIMSGSNDAR0 0x210
66 #define ENETC_VSIMSGSNDAR1 0x214
67
68 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
69 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
70
71 /* SI statistics */
72 #define ENETC_SIROCT 0x300
73 #define ENETC_SIRFRM 0x308
74 #define ENETC_SIRUCA 0x310
75 #define ENETC_SIRMCA 0x318
76 #define ENETC_SITOCT 0x320
77 #define ENETC_SITFRM 0x328
78 #define ENETC_SITUCA 0x330
79 #define ENETC_SITMCA 0x338
80 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
81
82 /* Control BDR regs */
83 #define ENETC_SICBDRMR 0x800
84 #define ENETC_SICBDRMR_EN BIT(31)
85 #define ENETC_SICBDRSR 0x804 /* RO */
86 #define ENETC_SICBDRBAR0 0x810
87 #define ENETC_SICBDRBAR1 0x814
88 #define ENETC_SICBDRPIR 0x818
89 #define ENETC_SICBDRCIR 0x81c
90 #define ENETC_SICBDRLENR 0x820
91
92 #define ENETC_SICAPR0 0x900
93 #define ENETC_SICAPR1 0x904
94
95 #define ENETC_PSIIER 0xa00
96 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
97 #define ENETC_PSIIDR 0xa08
98 #define ENETC_SITXIDR 0xa18
99 #define ENETC_SIRXIDR 0xa28
100 #define ENETC_SIMSIVR 0xa30
101
102 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
103 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
104
105 #define ENETC_SIUEFDCR 0xe28
106
107 #define ENETC_SIRFSCAPR 0x1200
108 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
109 #define ENETC_SIRSSCAPR 0x1600
110 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
111
112 /** SI BDR sub-blocks, n = 0..7 */
113 enum enetc_bdr_type {TX, RX};
114 #define ENETC_BDR_OFF(i) ((i) * 0x200)
115 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
116 /* RX BDR reg offsets */
117 #define ENETC_RBMR 0
118 #define ENETC_RBMR_AL BIT(0)
119 #define ENETC_RBMR_BDS BIT(2)
120 #define ENETC_RBMR_VTE BIT(5)
121 #define ENETC_RBMR_EN BIT(31)
122 #define ENETC_RBSR 0x4
123 #define ENETC_RBBSR 0x8
124 #define ENETC_RBCIR 0xc
125 #define ENETC_RBBAR0 0x10
126 #define ENETC_RBBAR1 0x14
127 #define ENETC_RBPIR 0x18
128 #define ENETC_RBLENR 0x20
129 #define ENETC_RBIER 0xa0
130 #define ENETC_RBIER_RXTIE BIT(0)
131 #define ENETC_RBIDR 0xa4
132 #define ENETC_RBICR0 0xa8
133 #define ENETC_RBICR0_ICEN BIT(31)
134 #define ENETC_RBICR0_ICPT_MASK 0x1ff
135 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK)
136 #define ENETC_RBICR1 0xac
137
138 /* TX BDR reg offsets */
139 #define ENETC_TBMR 0
140 #define ENETC_TBSR_BUSY BIT(0)
141 #define ENETC_TBMR_VIH BIT(9)
142 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
143 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
144 #define ENETC_TBMR_EN BIT(31)
145 #define ENETC_TBSR 0x4
146 #define ENETC_TBBAR0 0x10
147 #define ENETC_TBBAR1 0x14
148 #define ENETC_TBPIR 0x18
149 #define ENETC_TBCIR 0x1c
150 #define ENETC_TBCIR_IDX_MASK 0xffff
151 #define ENETC_TBLENR 0x20
152 #define ENETC_TBIER 0xa0
153 #define ENETC_TBIER_TXT BIT(0)
154 #define ENETC_TBIER_TXF BIT(1)
155 #define ENETC_TBIDR 0xa4
156 #define ENETC_TBICR0 0xa8
157 #define ENETC_TBICR0_ICEN BIT(31)
158 #define ENETC_TBICR0_ICPT_MASK 0xf
159 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK)
160 #define ENETC_TBICR1 0xac
161
162 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
163
164 /* Port regs, offset: 1_0000h */
165 #define ENETC_PORT_BASE 0x10000
166 #define ENETC_PMR 0x0000
167 #define ENETC_PMR_SI0EN BIT(16)
168 #define ENETC_PMR_EN GENMASK(18, 16)
169 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
170 #define ENETC_PMR_PSPEED_10M 0
171 #define ENETC_PMR_PSPEED_100M BIT(8)
172 #define ENETC_PMR_PSPEED_1000M BIT(9)
173 #define ENETC_PMR_PSPEED_2500M BIT(10)
174 #define ENETC_PSR 0x0004 /* RO */
175 #define ENETC_PSIPMR 0x0018
176 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
177 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
178 #define ENETC_PSIPVMR 0x001c
179 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
180 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
181 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
182 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
183 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
184 #define ENETC_PVCLCTR 0x0208
185 #define ENETC_PCVLANR1 0x0210
186 #define ENETC_PCVLANR2 0x0214
187 #define ENETC_VLAN_TYPE_C BIT(0)
188 #define ENETC_VLAN_TYPE_S BIT(1)
189 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
190 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
191 #define ENETC_PSIVLAN_EN BIT(31)
192 #define ENETC_PSIVLAN_SET_QOS(val) ((uint32_t)(val) << 12)
193 #define ENETC_PTXMBAR 0x0608
194 #define ENETC_PCAPR0 0x0900
195 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
196 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
197 #define ENETC_PCAPR1 0x0904
198 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
199 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
200 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
201 #define ENETC_PSICFGR0_VTE BIT(12)
202 #define ENETC_PSICFGR0_SIVIE BIT(14)
203 #define ENETC_PSICFGR0_ASE BIT(15)
204 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
205
206 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
207 #define ENETC_CBSE BIT(31)
208 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
209 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
210 #define ENETC_RSSHASH_KEY_SIZE 40
211 #define ENETC_PRSSCAPR 0x1404
212 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
213 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
214 #define ENETC_PSIVLANFMR 0x1700
215 #define ENETC_PSIVLANFMR_VS BIT(0)
216 #define ENETC_PRFSMR 0x1800
217 #define ENETC_PRFSMR_RFSE BIT(31)
218 #define ENETC_PRFSCAPR 0x1804
219 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
220 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
221 #define ENETC_PFPMR 0x1900
222 #define ENETC_PFPMR_PMACE BIT(1)
223 #define ENETC_PFPMR_MWLM BIT(0)
224 #define ENETC_EMDIO_BASE 0x1c00
225 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
226 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
227 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
228 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
229 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
230 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
231 #define ENETC_MMCSR 0x1f00
232 #define ENETC_MMCSR_ME BIT(16)
233 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
234
235 #define ENETC_PAR_PORT_CFG 0x3050
236 #define ENETC_PAR_PORT_L4CD BIT(0)
237 #define ENETC_PAR_PORT_L3CD BIT(1)
238
239 #define ENETC_PM0_CMD_CFG 0x8008
240 #define ENETC_PM1_CMD_CFG 0x9008
241 #define ENETC_PM0_TX_EN BIT(0)
242 #define ENETC_PM0_RX_EN BIT(1)
243 #define ENETC_PM0_PROMISC BIT(4)
244 #define ENETC_PM0_CMD_XGLP BIT(10)
245 #define ENETC_PM0_CMD_TXP BIT(11)
246 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
247 #define ENETC_PM0_CMD_SFD BIT(21)
248 #define ENETC_PM0_MAXFRM 0x8014
249 #define ENETC_SET_TX_MTU(val) ((val) << 16)
250 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
251 #define ENETC_PM0_RX_FIFO 0x801c
252 #define ENETC_PM0_RX_FIFO_VAL 1
253
254 #define ENETC_PM_IMDIO_BASE 0x8030
255
256 #define ENETC_PM0_IF_MODE 0x8300
257 #define ENETC_PM0_IFM_RG BIT(2)
258 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
259 #define ENETC_PM0_IFM_EN_AUTO BIT(15)
260 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13)
261 #define ENETC_PM0_IFM_SSP_1000 (2 << 13)
262 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
263 #define ENETC_PM0_IFM_SSP_10 (1 << 13)
264 #define ENETC_PM0_IFM_FULL_DPX BIT(12)
265 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
266 #define ENETC_PM0_IFM_IFMODE_XGMII 0
267 #define ENETC_PM0_IFM_IFMODE_GMII 2
268 #define ENETC_PSIDCAPR 0x1b08
269 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
270 #define ENETC_PSFCAPR 0x1b18
271 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
272 #define ENETC_PSGCAPR 0x1b28
273 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16)
274 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
275 #define ENETC_PFMCAPR 0x1b38
276 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
277
278 /* MAC counters */
279 #define ENETC_PM0_REOCT 0x8100
280 #define ENETC_PM0_RALN 0x8110
281 #define ENETC_PM0_RXPF 0x8118
282 #define ENETC_PM0_RFRM 0x8120
283 #define ENETC_PM0_RFCS 0x8128
284 #define ENETC_PM0_RVLAN 0x8130
285 #define ENETC_PM0_RERR 0x8138
286 #define ENETC_PM0_RUCA 0x8140
287 #define ENETC_PM0_RMCA 0x8148
288 #define ENETC_PM0_RBCA 0x8150
289 #define ENETC_PM0_RDRP 0x8158
290 #define ENETC_PM0_RPKT 0x8160
291 #define ENETC_PM0_RUND 0x8168
292 #define ENETC_PM0_R64 0x8170
293 #define ENETC_PM0_R127 0x8178
294 #define ENETC_PM0_R255 0x8180
295 #define ENETC_PM0_R511 0x8188
296 #define ENETC_PM0_R1023 0x8190
297 #define ENETC_PM0_R1522 0x8198
298 #define ENETC_PM0_R1523X 0x81A0
299 #define ENETC_PM0_ROVR 0x81A8
300 #define ENETC_PM0_RJBR 0x81B0
301 #define ENETC_PM0_RFRG 0x81B8
302 #define ENETC_PM0_RCNP 0x81C0
303 #define ENETC_PM0_RDRNTP 0x81C8
304 #define ENETC_PM0_TEOCT 0x8200
305 #define ENETC_PM0_TOCT 0x8208
306 #define ENETC_PM0_TCRSE 0x8210
307 #define ENETC_PM0_TXPF 0x8218
308 #define ENETC_PM0_TFRM 0x8220
309 #define ENETC_PM0_TFCS 0x8228
310 #define ENETC_PM0_TVLAN 0x8230
311 #define ENETC_PM0_TERR 0x8238
312 #define ENETC_PM0_TUCA 0x8240
313 #define ENETC_PM0_TMCA 0x8248
314 #define ENETC_PM0_TBCA 0x8250
315 #define ENETC_PM0_TPKT 0x8260
316 #define ENETC_PM0_TUND 0x8268
317 #define ENETC_PM0_T64 0x8270
318 #define ENETC_PM0_T127 0x8278
319 #define ENETC_PM0_T255 0x8280
320 #define ENETC_PM0_T511 0x8288
321 #define ENETC_PM0_T1023 0x8290
322 #define ENETC_PM0_T1522 0x8298
323 #define ENETC_PM0_T1523X 0x82A0
324 #define ENETC_PM0_TCNP 0x82C0
325 #define ENETC_PM0_TDFR 0x82D0
326 #define ENETC_PM0_TMCOL 0x82D8
327 #define ENETC_PM0_TSCOL 0x82E0
328 #define ENETC_PM0_TLCOL 0x82E8
329 #define ENETC_PM0_TECOL 0x82F0
330
331 /* Port counters */
332 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
333 #define ENETC_PBFDSIR 0x0810
334 #define ENETC_PFDMSAPR 0x0814
335 #define ENETC_UFDMF 0x1680
336 #define ENETC_MFDMF 0x1684
337 #define ENETC_PUFDVFR 0x1780
338 #define ENETC_PMFDVFR 0x1784
339 #define ENETC_PBFDVFR 0x1788
340
341 /** Global regs, offset: 2_0000h */
342 #define ENETC_GLOBAL_BASE 0x20000
343 #define ENETC_G_EIPBRR0 0x0bf8
344 #define ENETC_G_EIPBRR1 0x0bfc
345 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
346 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
347
348 /* Buffer Descriptors (BD) */
349 union enetc_tx_bd {
350 struct {
351 uint64_t addr;
352 uint16_t buf_len;
353 uint16_t frm_len;
354 union {
355 struct {
356 uint8_t reserved[3];
357 uint8_t flags;
358 }; /* default layout */
359 uint32_t txstart;
360 uint32_t lstatus;
361 };
362 };
363 struct {
364 uint32_t tstamp;
365 uint16_t tpid;
366 uint16_t vid;
367 uint8_t reserved[6];
368 uint8_t e_flags;
369 uint8_t flags;
370 } ext; /* Tx BD extension */
371 struct {
372 uint32_t tstamp;
373 uint8_t reserved[10];
374 uint8_t status;
375 uint8_t flags;
376 } wb; /* writeback descriptor */
377 };
378
379 enum enetc_txbd_flags {
380 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */
381 ENETC_TXBD_FLAGS_TSE = BIT(1),
382 ENETC_TXBD_FLAGS_W = BIT(2),
383 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */
384 ENETC_TXBD_FLAGS_TXSTART = BIT(4),
385 ENETC_TXBD_FLAGS_FI = BIT(5),
386 ENETC_TXBD_FLAGS_EX = BIT(6),
387 ENETC_TXBD_FLAGS_F = BIT(7)
388 };
389 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
390 #define ENETC_TXBD_FLAGS_OFFSET 24
391
enetc_clear_tx_bd(union enetc_tx_bd * txbd)392 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
393 {
394 memset(txbd, 0, sizeof(*txbd));
395 }
396
397 /* Extension flags */
398 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
399 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
400
401 union enetc_rx_bd {
402 struct {
403 uint64_t addr;
404 uint8_t reserved[8];
405 } w;
406 struct {
407 uint16_t inet_csum;
408 uint16_t parse_summary;
409 uint32_t rss_hash;
410 uint16_t buf_len;
411 uint16_t vlan_opt;
412 union {
413 struct {
414 uint16_t flags;
415 uint16_t error;
416 };
417 uint32_t lstatus;
418 };
419 } r;
420 struct {
421 uint32_t tstamp;
422 uint8_t reserved[12];
423 } ext;
424 };
425
426 #define ENETC_RXBD_PARSER_ERROR BIT(15)
427
428 #define ENETC_RXBD_LSTATUS_R BIT(30)
429 #define ENETC_RXBD_LSTATUS_F BIT(31)
430 #define ENETC_RXBD_ERR_MASK 0xff
431 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
432 #define ENETC_RXBD_FLAG_RSSV BIT(8)
433 #define ENETC_RXBD_FLAG_VLAN BIT(9)
434 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
435 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
436
437 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
438 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
439 #define ENETC_MAX_NUM_VFS 2
440
441 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
442 #define ENETC_CBD_STATUS_MASK 0xf
443
444 struct enetc_cmd_rfse {
445 uint8_t smac_h[6];
446 uint8_t smac_m[6];
447 uint8_t dmac_h[6];
448 uint8_t dmac_m[6];
449 uint32_t sip_h[4]; /* Big-endian */
450 uint32_t sip_m[4]; /* Big-endian */
451 uint32_t dip_h[4]; /* Big-endian */
452 uint32_t dip_m[4]; /* Big-endian */
453 uint16_t ethtype_h;
454 uint16_t ethtype_m;
455 uint16_t ethtype4_h;
456 uint16_t ethtype4_m;
457 uint16_t sport_h;
458 uint16_t sport_m;
459 uint16_t dport_h;
460 uint16_t dport_m;
461 uint16_t vlan_h;
462 uint16_t vlan_m;
463 uint8_t proto_h;
464 uint8_t proto_m;
465 uint16_t flags;
466 uint16_t result;
467 uint16_t mode;
468 };
469
470 #define ENETC_RFSE_EN BIT(15)
471 #define ENETC_RFSE_MODE_BD 2
472
473 #define ENETC_SI_INT_IDX 0
474 /* base index for Rx/Tx interrupts */
475 #define ENETC_BDR_INT_BASE_IDX 1
476
477 /* Messaging */
478
479 /* Command completion status */
480 enum enetc_msg_cmd_status {
481 ENETC_MSG_CMD_STATUS_OK,
482 ENETC_MSG_CMD_STATUS_FAIL
483 };
484
485 /* VSI-PSI command message types */
486 enum enetc_msg_cmd_type {
487 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
488 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
489 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
490 };
491
492 /* VSI-PSI command action types */
493 enum enetc_msg_cmd_action_type {
494 ENETC_MSG_CMD_MNG_ADD = 1,
495 ENETC_MSG_CMD_MNG_REMOVE
496 };
497
498 /* PSI-VSI command header format */
499 struct enetc_msg_cmd_header {
500 uint16_t type; /* command class type */
501 uint16_t id; /* denotes the specific required action */
502 };
503
504 enum bdcr_cmd_class {
505 BDCR_CMD_UNSPEC = 0,
506 BDCR_CMD_MAC_FILTER,
507 BDCR_CMD_VLAN_FILTER,
508 BDCR_CMD_RSS,
509 BDCR_CMD_RFS,
510 BDCR_CMD_PORT_GCL,
511 BDCR_CMD_RECV_CLASSIFIER,
512 BDCR_CMD_STREAM_IDENTIFY,
513 BDCR_CMD_STREAM_FILTER,
514 BDCR_CMD_STREAM_GCL,
515 BDCR_CMD_FLOW_METER,
516 __BDCR_CMD_MAX_LEN,
517 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
518 };
519
520 enum bdcr_cmd_rss {
521 BDCR_CMD_RSS_WRITE = 1,
522 BDCR_CMD_RSS_READ = 2,
523 };
524
525 /* class 5, command 0 */
526 struct tgs_gcl_conf {
527 uint8_t atc; /* init gate value */
528 uint8_t res[7];
529 struct {
530 uint8_t res1[4];
531 uint16_t acl_len;
532 uint8_t res2[2];
533 };
534 };
535
536 /* gate control list entry */
537 struct gce {
538 uint32_t period;
539 uint8_t gate;
540 uint8_t res[3];
541 };
542
543 /* tgs_gcl_conf address point to this data space */
544 struct tgs_gcl_data {
545 uint32_t btl;
546 uint32_t bth;
547 uint32_t ct;
548 uint32_t cte;
549 struct gce entry[];
550 };
551
552 /* class 7, command 0, Stream Identity Entry Configuration */
553 struct streamid_conf {
554 uint32_t stream_handle; /* init gate value */
555 uint32_t iports;
556 uint8_t id_type;
557 uint8_t oui[3];
558 uint8_t res[3];
559 uint8_t en;
560 };
561
562 #define ENETC_CBDR_SID_VID_MASK 0xfff
563 #define ENETC_CBDR_SID_VIDM BIT(12)
564 #define ENETC_CBDR_SID_TG_MASK 0xc000
565 /* streamid_conf address point to this data space */
566 struct streamid_data {
567 union {
568 uint8_t dmac[6];
569 uint8_t smac[6];
570 };
571 uint16_t vid_vidm_tg;
572 };
573
574 #define ENETC_CBDR_SFI_PRI_MASK 0x7
575 #define ENETC_CBDR_SFI_PRIM BIT(3)
576 #define ENETC_CBDR_SFI_BLOV BIT(4)
577 #define ENETC_CBDR_SFI_BLEN BIT(5)
578 #define ENETC_CBDR_SFI_MSDUEN BIT(6)
579 #define ENETC_CBDR_SFI_FMITEN BIT(7)
580 #define ENETC_CBDR_SFI_ENABLE BIT(7)
581 /* class 8, command 0, Stream Filter Instance, Short Format */
582 struct sfi_conf {
583 uint32_t stream_handle;
584 uint8_t multi;
585 uint8_t res[2];
586 uint8_t sthm;
587 /* Max Service Data Unit or Flow Meter Instance Table index.
588 * Depending on the value of FLT this represents either Max
589 * Service Data Unit (max frame size) allowed by the filter
590 * entry or is an index into the Flow Meter Instance table
591 * index identifying the policer which will be used to police
592 * it.
593 */
594 uint16_t fm_inst_table_index;
595 uint16_t msdu;
596 uint16_t sg_inst_table_index;
597 uint8_t res1[2];
598 uint32_t input_ports;
599 uint8_t res2[3];
600 uint8_t en;
601 };
602
603 /* class 8, command 2 stream Filter Instance status query short format
604 * command no need structure define
605 * Stream Filter Instance Query Statistics Response data
606 */
607 struct sfi_counter_data {
608 uint32_t matchl;
609 uint32_t matchh;
610 uint32_t msdu_dropl;
611 uint32_t msdu_droph;
612 uint32_t stream_gate_dropl;
613 uint32_t stream_gate_droph;
614 uint32_t flow_meter_dropl;
615 uint32_t flow_meter_droph;
616 };
617
618 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
619 #define ENETC_CBDR_SGI_OIPV_EN BIT(3)
620 #define ENETC_CBDR_SGI_CGTST BIT(6)
621 #define ENETC_CBDR_SGI_OGTST BIT(7)
622 #define ENETC_CBDR_SGI_CFG_CHG BIT(1)
623 #define ENETC_CBDR_SGI_CFG_PND BIT(2)
624 #define ENETC_CBDR_SGI_OEX BIT(4)
625 #define ENETC_CBDR_SGI_OEXEN BIT(5)
626 #define ENETC_CBDR_SGI_IRX BIT(6)
627 #define ENETC_CBDR_SGI_IRXEN BIT(7)
628 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
629 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
630 #define ENETC_CBDR_SGI_EN BIT(7)
631 /* class 9, command 0, Stream Gate Instance Table, Short Format
632 * class 9, command 2, Stream Gate Instance Table entry query write back
633 * Short Format
634 */
635 struct sgi_table {
636 uint8_t res[8];
637 uint8_t oipv;
638 uint8_t res0[2];
639 uint8_t ocgtst;
640 uint8_t res1[7];
641 uint8_t gset;
642 uint8_t oacl_len;
643 uint8_t res2[2];
644 uint8_t en;
645 };
646
647 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
648 #define ENETC_CBDR_SGI_AIPV_EN BIT(3)
649 #define ENETC_CBDR_SGI_AGTST BIT(7)
650
651 /* class 9, command 1, Stream Gate Control List, Long Format */
652 struct sgcl_conf {
653 uint8_t aipv;
654 uint8_t res[2];
655 uint8_t agtst;
656 uint8_t res1[4];
657 union {
658 struct {
659 uint8_t res2[4];
660 uint8_t acl_len;
661 uint8_t res3[3];
662 };
663 uint8_t cct[8]; /* Config change time */
664 };
665 };
666
667 #define ENETC_CBDR_SGL_IOMEN BIT(0)
668 #define ENETC_CBDR_SGL_IPVEN BIT(3)
669 #define ENETC_CBDR_SGL_GTST BIT(4)
670 #define ENETC_CBDR_SGL_IPV_MASK 0xe
671 /* Stream Gate Control List Entry */
672 struct sgce {
673 uint32_t interval;
674 uint8_t msdu[3];
675 uint8_t multi;
676 };
677
678 /* stream control list class 9 , cmd 1 data buffer */
679 struct sgcl_data {
680 uint32_t btl;
681 uint32_t bth;
682 uint32_t ct;
683 uint32_t cte;
684 struct sgce sgcl[0];
685 };
686
687 #define ENETC_CBDR_FMI_MR BIT(0)
688 #define ENETC_CBDR_FMI_MREN BIT(1)
689 #define ENETC_CBDR_FMI_DOY BIT(2)
690 #define ENETC_CBDR_FMI_CM BIT(3)
691 #define ENETC_CBDR_FMI_CF BIT(4)
692 #define ENETC_CBDR_FMI_NDOR BIT(5)
693 #define ENETC_CBDR_FMI_OALEN BIT(6)
694 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
695
696 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
697 struct fmi_conf {
698 uint32_t cir;
699 uint32_t cbs;
700 uint32_t eir;
701 uint32_t ebs;
702 uint8_t conf;
703 uint8_t res1;
704 uint8_t ir_fpp;
705 uint8_t res2[4];
706 uint8_t en;
707 };
708
709 struct enetc_cbd {
710 union{
711 struct sfi_conf sfi_conf;
712 struct sgi_table sgi_table;
713 struct fmi_conf fmi_conf;
714 struct {
715 uint32_t addr[2];
716 union {
717 uint32_t opt[4];
718 struct tgs_gcl_conf gcl_conf;
719 struct streamid_conf sid_set;
720 struct sgcl_conf sgcl_conf;
721 };
722 }; /* Long format */
723 uint32_t data[6];
724 };
725 uint16_t index;
726 uint16_t length;
727 uint8_t cmd;
728 uint8_t cls;
729 uint8_t _res;
730 uint8_t status_flags;
731 };
732
733 #define ENETC_CLK 400000000ULL
734
735 /* port time gating control register */
736 #define ENETC_QBV_PTGCR_OFFSET 0x11a00
737 #define ENETC_QBV_TGE BIT(31)
738 #define ENETC_QBV_TGPE BIT(30)
739
740 /* Port time gating capability register */
741 #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08
742 #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0)
743
744 /* Port time specific departure */
745 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
746 #define ENETC_TSDE BIT(31)
747
748 /* PSFP setting */
749 #define ENETC_PPSFPMR 0x11b00
750 #define ENETC_PPSFPMR_PSFPEN BIT(0)
751 #define ENETC_PPSFPMR_VS BIT(1)
752 #define ENETC_PPSFPMR_PVC BIT(2)
753 #define ENETC_PPSFPMR_PVZC BIT(3)
754
755 #endif
756