1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1995, David Greenman
5 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 /*
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 */
36
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
39 #endif
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
46 #include <sys/mbuf.h>
47 #include <sys/lock.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/rman.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_var.h>
60 #include <net/if_arp.h>
61 #include <net/if_dl.h>
62 #include <net/if_media.h>
63 #include <net/if_types.h>
64 #include <net/if_vlan_var.h>
65
66 #include <netinet/in.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/ip.h>
69 #include <netinet/tcp.h>
70 #include <netinet/udp.h>
71
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
74 #include <machine/resource.h>
75
76 #include <dev/pci/pcivar.h>
77 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
78
79 #include <dev/mii/mii.h>
80 #include <dev/mii/miivar.h>
81
82 #include <dev/fxp/if_fxpreg.h>
83 #include <dev/fxp/if_fxpvar.h>
84 #include <dev/fxp/rcvbundl.h>
85
86 MODULE_DEPEND(fxp, pci, 1, 1, 1);
87 MODULE_DEPEND(fxp, ether, 1, 1, 1);
88 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
89 #include "miibus_if.h"
90
91 /*
92 * NOTE! On !x86 we typically have an alignment constraint. The
93 * card DMAs the packet immediately following the RFA. However,
94 * the first thing in the packet is a 14-byte Ethernet header.
95 * This means that the packet is misaligned. To compensate,
96 * we actually offset the RFA 2 bytes into the cluster. This
97 * alignes the packet after the Ethernet header at a 32-bit
98 * boundary. HOWEVER! This means that the RFA is misaligned!
99 */
100 #define RFA_ALIGNMENT_FUDGE 2
101
102 /*
103 * Set initial transmit threshold at 64 (512 bytes). This is
104 * increased by 64 (512 bytes) at a time, to maximum of 192
105 * (1536 bytes), if an underrun occurs.
106 */
107 static int tx_threshold = 64;
108
109 /*
110 * The configuration byte map has several undefined fields which
111 * must be one or must be zero. Set up a template for these bits.
112 * The actual configuration is performed in fxp_init_body.
113 *
114 * See struct fxp_cb_config for the bit definitions.
115 */
116 static const u_char fxp_cb_config_template[] = {
117 0x0, 0x0, /* cb_status */
118 0x0, 0x0, /* cb_command */
119 0x0, 0x0, 0x0, 0x0, /* link_addr */
120 0x0, /* 0 */
121 0x0, /* 1 */
122 0x0, /* 2 */
123 0x0, /* 3 */
124 0x0, /* 4 */
125 0x0, /* 5 */
126 0x32, /* 6 */
127 0x0, /* 7 */
128 0x0, /* 8 */
129 0x0, /* 9 */
130 0x6, /* 10 */
131 0x0, /* 11 */
132 0x0, /* 12 */
133 0x0, /* 13 */
134 0xf2, /* 14 */
135 0x48, /* 15 */
136 0x0, /* 16 */
137 0x40, /* 17 */
138 0xf0, /* 18 */
139 0x0, /* 19 */
140 0x3f, /* 20 */
141 0x5, /* 21 */
142 0x0, /* 22 */
143 0x0, /* 23 */
144 0x0, /* 24 */
145 0x0, /* 25 */
146 0x0, /* 26 */
147 0x0, /* 27 */
148 0x0, /* 28 */
149 0x0, /* 29 */
150 0x0, /* 30 */
151 0x0 /* 31 */
152 };
153
154 /*
155 * Claim various Intel PCI device identifiers for this driver. The
156 * sub-vendor and sub-device field are extensively used to identify
157 * particular variants, but we don't currently differentiate between
158 * them.
159 */
160 static const struct fxp_ident fxp_ident_table[] = {
161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
167 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
169 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
171 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
172 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
174 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
176 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
177 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
178 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
179 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
180 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
181 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
182 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
183 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
184 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
185 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
186 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
187 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
188 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
189 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
191 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
202 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
203 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
204 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
205 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
206 { 0, 0, -1, 0, NULL },
207 };
208
209 #ifdef FXP_IP_CSUM_WAR
210 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
211 #else
212 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
213 #endif
214
215 static int fxp_probe(device_t dev);
216 static int fxp_attach(device_t dev);
217 static int fxp_detach(device_t dev);
218 static int fxp_shutdown(device_t dev);
219 static int fxp_suspend(device_t dev);
220 static int fxp_resume(device_t dev);
221
222 static const struct fxp_ident *fxp_find_ident(device_t dev);
223 static void fxp_intr(void *xsc);
224 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp,
225 struct mbuf *m, uint16_t status, int pos);
226 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp,
227 uint8_t statack, int count);
228 static void fxp_init(void *xsc);
229 static void fxp_init_body(struct fxp_softc *sc, int);
230 static void fxp_tick(void *xsc);
231 static void fxp_start(if_t ifp);
232 static void fxp_start_body(if_t ifp);
233 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
234 static void fxp_txeof(struct fxp_softc *sc);
235 static void fxp_stop(struct fxp_softc *sc);
236 static void fxp_release(struct fxp_softc *sc);
237 static int fxp_ioctl(if_t ifp, u_long command,
238 caddr_t data);
239 static void fxp_watchdog(struct fxp_softc *sc);
240 static void fxp_add_rfabuf(struct fxp_softc *sc,
241 struct fxp_rx *rxp);
242 static void fxp_discard_rfabuf(struct fxp_softc *sc,
243 struct fxp_rx *rxp);
244 static int fxp_new_rfabuf(struct fxp_softc *sc,
245 struct fxp_rx *rxp);
246 static void fxp_mc_addrs(struct fxp_softc *sc);
247 static void fxp_mc_setup(struct fxp_softc *sc);
248 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
249 int autosize);
250 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
251 uint16_t data);
252 static void fxp_autosize_eeprom(struct fxp_softc *sc);
253 static void fxp_load_eeprom(struct fxp_softc *sc);
254 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
255 int offset, int words);
256 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
257 int offset, int words);
258 static int fxp_ifmedia_upd(if_t ifp);
259 static void fxp_ifmedia_sts(if_t ifp,
260 struct ifmediareq *ifmr);
261 static int fxp_serial_ifmedia_upd(if_t ifp);
262 static void fxp_serial_ifmedia_sts(if_t ifp,
263 struct ifmediareq *ifmr);
264 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
265 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
266 int value);
267 static void fxp_miibus_statchg(device_t dev);
268 static void fxp_load_ucode(struct fxp_softc *sc);
269 static void fxp_update_stats(struct fxp_softc *sc);
270 static void fxp_sysctl_node(struct fxp_softc *sc);
271 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
272 int low, int high);
273 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
274 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
275 static void fxp_scb_wait(struct fxp_softc *sc);
276 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
277 static void fxp_dma_wait(struct fxp_softc *sc,
278 volatile uint16_t *status, bus_dma_tag_t dmat,
279 bus_dmamap_t map);
280
281 static device_method_t fxp_methods[] = {
282 /* Device interface */
283 DEVMETHOD(device_probe, fxp_probe),
284 DEVMETHOD(device_attach, fxp_attach),
285 DEVMETHOD(device_detach, fxp_detach),
286 DEVMETHOD(device_shutdown, fxp_shutdown),
287 DEVMETHOD(device_suspend, fxp_suspend),
288 DEVMETHOD(device_resume, fxp_resume),
289
290 /* MII interface */
291 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
292 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
293 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
294
295 DEVMETHOD_END
296 };
297
298 static driver_t fxp_driver = {
299 "fxp",
300 fxp_methods,
301 sizeof(struct fxp_softc),
302 };
303
304 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, NULL, NULL, SI_ORDER_ANY);
305 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table,
306 nitems(fxp_ident_table) - 1);
307 DRIVER_MODULE(miibus, fxp, miibus_driver, NULL, NULL);
308
309 static struct resource_spec fxp_res_spec_mem[] = {
310 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
312 { -1, 0 }
313 };
314
315 static struct resource_spec fxp_res_spec_io[] = {
316 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
318 { -1, 0 }
319 };
320
321 /*
322 * Wait for the previous command to be accepted (but not necessarily
323 * completed).
324 */
325 static void
fxp_scb_wait(struct fxp_softc * sc)326 fxp_scb_wait(struct fxp_softc *sc)
327 {
328 union {
329 uint16_t w;
330 uint8_t b[2];
331 } flowctl;
332 int i = 10000;
333
334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
335 DELAY(2);
336 if (i == 0) {
337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
343 }
344 }
345
346 static void
fxp_scb_cmd(struct fxp_softc * sc,int cmd)347 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
348 {
349
350 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
352 fxp_scb_wait(sc);
353 }
354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
355 }
356
357 static void
fxp_dma_wait(struct fxp_softc * sc,volatile uint16_t * status,bus_dma_tag_t dmat,bus_dmamap_t map)358 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
359 bus_dma_tag_t dmat, bus_dmamap_t map)
360 {
361 int i;
362
363 for (i = 10000; i > 0; i--) {
364 DELAY(2);
365 bus_dmamap_sync(dmat, map,
366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
368 break;
369 }
370 if (i == 0)
371 device_printf(sc->dev, "DMA timeout\n");
372 }
373
374 static const struct fxp_ident *
fxp_find_ident(device_t dev)375 fxp_find_ident(device_t dev)
376 {
377 uint16_t vendor;
378 uint16_t device;
379 uint8_t revid;
380 const struct fxp_ident *ident;
381
382 vendor = pci_get_vendor(dev);
383 device = pci_get_device(dev);
384 revid = pci_get_revid(dev);
385 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
386 if (ident->vendor == vendor && ident->device == device &&
387 (ident->revid == revid || ident->revid == -1)) {
388 return (ident);
389 }
390 }
391 return (NULL);
392 }
393
394 /*
395 * Return identification string if this device is ours.
396 */
397 static int
fxp_probe(device_t dev)398 fxp_probe(device_t dev)
399 {
400 const struct fxp_ident *ident;
401
402 ident = fxp_find_ident(dev);
403 if (ident != NULL) {
404 device_set_desc(dev, ident->name);
405 return (BUS_PROBE_DEFAULT);
406 }
407 return (ENXIO);
408 }
409
410 static void
fxp_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)411 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
412 {
413 uint32_t *addr;
414
415 if (error)
416 return;
417
418 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
419 addr = arg;
420 *addr = segs->ds_addr;
421 }
422
423 static int
fxp_attach(device_t dev)424 fxp_attach(device_t dev)
425 {
426 struct fxp_softc *sc;
427 struct fxp_cb_tx *tcbp;
428 struct fxp_tx *txp;
429 struct fxp_rx *rxp;
430 if_t ifp;
431 uint32_t val;
432 uint16_t data;
433 u_char eaddr[ETHER_ADDR_LEN];
434 int error, flags, i, pmc, prefer_iomap;
435
436 error = 0;
437 sc = device_get_softc(dev);
438 sc->dev = dev;
439 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
440 MTX_DEF);
441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
443 fxp_serial_ifmedia_sts);
444
445 ifp = sc->ifp = if_gethandle(IFT_ETHER);
446 if (ifp == (void *)NULL) {
447 device_printf(dev, "can not if_alloc()\n");
448 error = ENOSPC;
449 goto fail;
450 }
451
452 /*
453 * Enable bus mastering.
454 */
455 pci_enable_busmaster(dev);
456
457 /*
458 * Figure out which we should try first - memory mapping or i/o mapping?
459 * We default to memory mapping. Then we accept an override from the
460 * command line. Then we check to see which one is enabled.
461 */
462 prefer_iomap = 0;
463 resource_int_value(device_get_name(dev), device_get_unit(dev),
464 "prefer_iomap", &prefer_iomap);
465 if (prefer_iomap)
466 sc->fxp_spec = fxp_res_spec_io;
467 else
468 sc->fxp_spec = fxp_res_spec_mem;
469
470 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
471 if (error) {
472 if (sc->fxp_spec == fxp_res_spec_mem)
473 sc->fxp_spec = fxp_res_spec_io;
474 else
475 sc->fxp_spec = fxp_res_spec_mem;
476 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
477 }
478 if (error) {
479 device_printf(dev, "could not allocate resources\n");
480 error = ENXIO;
481 goto fail;
482 }
483
484 if (bootverbose) {
485 device_printf(dev, "using %s space register mapping\n",
486 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
487 }
488
489 /*
490 * Put CU/RU idle state and prepare full reset.
491 */
492 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
493 DELAY(10);
494 /* Full reset and disable interrupts. */
495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
496 DELAY(10);
497 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
498
499 /*
500 * Find out how large of an SEEPROM we have.
501 */
502 fxp_autosize_eeprom(sc);
503 fxp_load_eeprom(sc);
504
505 /*
506 * Find out the chip revision; lump all 82557 revs together.
507 */
508 sc->ident = fxp_find_ident(dev);
509 if (sc->ident->ich > 0) {
510 /* Assume ICH controllers are 82559. */
511 sc->revision = FXP_REV_82559_A0;
512 } else {
513 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
514 if ((data >> 8) == 1)
515 sc->revision = FXP_REV_82557;
516 else
517 sc->revision = pci_get_revid(dev);
518 }
519
520 /*
521 * Check availability of WOL. 82559ER does not support WOL.
522 */
523 if (sc->revision >= FXP_REV_82558_A4 &&
524 sc->revision != FXP_REV_82559S_A) {
525 data = sc->eeprom[FXP_EEPROM_MAP_ID];
526 if ((data & 0x20) != 0 &&
527 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
528 sc->flags |= FXP_FLAG_WOLCAP;
529 }
530
531 if (sc->revision == FXP_REV_82550_C) {
532 /*
533 * 82550C with server extension requires microcode to
534 * receive fragmented UDP datagrams. However if the
535 * microcode is used for client-only featured 82550C
536 * it locks up controller.
537 */
538 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
539 if ((data & 0x0400) == 0)
540 sc->flags |= FXP_FLAG_NO_UCODE;
541 }
542
543 /* Receiver lock-up workaround detection. */
544 if (sc->revision < FXP_REV_82558_A4) {
545 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
546 if ((data & 0x03) != 0x03) {
547 sc->flags |= FXP_FLAG_RXBUG;
548 device_printf(dev, "Enabling Rx lock-up workaround\n");
549 }
550 }
551
552 /*
553 * Determine whether we must use the 503 serial interface.
554 */
555 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
556 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
557 && (data & FXP_PHY_SERIAL_ONLY))
558 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
559
560 fxp_sysctl_node(sc);
561 /*
562 * Enable workarounds for certain chip revision deficiencies.
563 *
564 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
565 * some systems based a normal 82559 design, have a defect where
566 * the chip can cause a PCI protocol violation if it receives
567 * a CU_RESUME command when it is entering the IDLE state. The
568 * workaround is to disable Dynamic Standby Mode, so the chip never
569 * deasserts CLKRUN#, and always remains in an active state.
570 *
571 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
572 */
573 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
574 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
575 data = sc->eeprom[FXP_EEPROM_MAP_ID];
576 if (data & 0x02) { /* STB enable */
577 uint16_t cksum;
578 int i;
579
580 device_printf(dev,
581 "Disabling dynamic standby mode in EEPROM\n");
582 data &= ~0x02;
583 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
584 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
585 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
586 cksum = 0;
587 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
588 cksum += sc->eeprom[i];
589 i = (1 << sc->eeprom_size) - 1;
590 cksum = 0xBABA - cksum;
591 fxp_write_eeprom(sc, &cksum, i, 1);
592 device_printf(dev,
593 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
594 i, sc->eeprom[i], cksum);
595 sc->eeprom[i] = cksum;
596 /*
597 * If the user elects to continue, try the software
598 * workaround, as it is better than nothing.
599 */
600 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
601 }
602 }
603
604 /*
605 * If we are not a 82557 chip, we can enable extended features.
606 */
607 if (sc->revision != FXP_REV_82557) {
608 /*
609 * If MWI is enabled in the PCI configuration, and there
610 * is a valid cacheline size (8 or 16 dwords), then tell
611 * the board to turn on MWI.
612 */
613 val = pci_read_config(dev, PCIR_COMMAND, 2);
614 if (val & PCIM_CMD_MWRICEN &&
615 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
616 sc->flags |= FXP_FLAG_MWI_ENABLE;
617
618 /* turn on the extended TxCB feature */
619 sc->flags |= FXP_FLAG_EXT_TXCB;
620
621 /* enable reception of long frames for VLAN */
622 sc->flags |= FXP_FLAG_LONG_PKT_EN;
623 } else {
624 /* a hack to get long VLAN frames on a 82557 */
625 sc->flags |= FXP_FLAG_SAVE_BAD;
626 }
627
628 /* For 82559 or later chips, Rx checksum offload is supported. */
629 if (sc->revision >= FXP_REV_82559_A0) {
630 /* 82559ER does not support Rx checksum offloading. */
631 if (sc->ident->device != 0x1209)
632 sc->flags |= FXP_FLAG_82559_RXCSUM;
633 }
634 /*
635 * Enable use of extended RFDs and TCBs for 82550
636 * and later chips. Note: we need extended TXCB support
637 * too, but that's already enabled by the code above.
638 * Be careful to do this only on the right devices.
639 */
640 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
641 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
642 || sc->revision == FXP_REV_82551_10) {
643 sc->rfa_size = sizeof (struct fxp_rfa);
644 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
645 sc->flags |= FXP_FLAG_EXT_RFA;
646 /* Use extended RFA instead of 82559 checksum mode. */
647 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
648 } else {
649 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
650 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
651 }
652
653 /*
654 * Allocate DMA tags and DMA safe memory.
655 */
656 sc->maxtxseg = FXP_NTXSEG;
657 sc->maxsegsize = MCLBYTES;
658 if (sc->flags & FXP_FLAG_EXT_RFA) {
659 sc->maxtxseg--;
660 sc->maxsegsize = FXP_TSO_SEGSIZE;
661 }
662 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
663 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
664 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
665 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag);
666 if (error) {
667 device_printf(dev, "could not create TX DMA tag\n");
668 goto fail;
669 }
670
671 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
672 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
673 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag);
674 if (error) {
675 device_printf(dev, "could not create RX DMA tag\n");
676 goto fail;
677 }
678
679 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
680 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
681 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
682 NULL, NULL, &sc->fxp_stag);
683 if (error) {
684 device_printf(dev, "could not create stats DMA tag\n");
685 goto fail;
686 }
687
688 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
689 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
690 if (error) {
691 device_printf(dev, "could not allocate stats DMA memory\n");
692 goto fail;
693 }
694 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
695 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
696 BUS_DMA_NOWAIT);
697 if (error) {
698 device_printf(dev, "could not load the stats DMA buffer\n");
699 goto fail;
700 }
701
702 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
703 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
704 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag);
705 if (error) {
706 device_printf(dev, "could not create TxCB DMA tag\n");
707 goto fail;
708 }
709
710 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
711 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
712 if (error) {
713 device_printf(dev, "could not allocate TxCB DMA memory\n");
714 goto fail;
715 }
716
717 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
718 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
719 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
720 if (error) {
721 device_printf(dev, "could not load TxCB DMA buffer\n");
722 goto fail;
723 }
724
725 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
726 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
727 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
728 NULL, NULL, &sc->mcs_tag);
729 if (error) {
730 device_printf(dev,
731 "could not create multicast setup DMA tag\n");
732 goto fail;
733 }
734
735 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
736 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
737 if (error) {
738 device_printf(dev,
739 "could not allocate multicast setup DMA memory\n");
740 goto fail;
741 }
742 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
743 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
744 BUS_DMA_NOWAIT);
745 if (error) {
746 device_printf(dev,
747 "can't load the multicast setup DMA buffer\n");
748 goto fail;
749 }
750
751 /*
752 * Pre-allocate the TX DMA maps and setup the pointers to
753 * the TX command blocks.
754 */
755 txp = sc->fxp_desc.tx_list;
756 tcbp = sc->fxp_desc.cbl_list;
757 for (i = 0; i < FXP_NTXCB; i++) {
758 txp[i].tx_cb = tcbp + i;
759 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
760 if (error) {
761 device_printf(dev, "can't create DMA map for TX\n");
762 goto fail;
763 }
764 }
765 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
766 if (error) {
767 device_printf(dev, "can't create spare DMA map\n");
768 goto fail;
769 }
770
771 /*
772 * Pre-allocate our receive buffers.
773 */
774 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
775 for (i = 0; i < FXP_NRFABUFS; i++) {
776 rxp = &sc->fxp_desc.rx_list[i];
777 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
778 if (error) {
779 device_printf(dev, "can't create DMA map for RX\n");
780 goto fail;
781 }
782 if (fxp_new_rfabuf(sc, rxp) != 0) {
783 error = ENOMEM;
784 goto fail;
785 }
786 fxp_add_rfabuf(sc, rxp);
787 }
788
789 /*
790 * Read MAC address.
791 */
792 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
793 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
794 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
795 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
796 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
797 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
798 if (bootverbose) {
799 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
800 pci_get_vendor(dev), pci_get_device(dev),
801 pci_get_subvendor(dev), pci_get_subdevice(dev),
802 pci_get_revid(dev));
803 device_printf(dev, "Dynamic Standby mode is %s\n",
804 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
805 "disabled");
806 }
807
808 /*
809 * If this is only a 10Mbps device, then there is no MII, and
810 * the PHY will use a serial interface instead.
811 *
812 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
813 * doesn't have a programming interface of any sort. The
814 * media is sensed automatically based on how the link partner
815 * is configured. This is, in essence, manual configuration.
816 */
817 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
818 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
819 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
820 } else {
821 /*
822 * i82557 wedge when isolating all of their PHYs.
823 */
824 flags = MIIF_NOISOLATE;
825 if (sc->revision >= FXP_REV_82558_A4)
826 flags |= MIIF_DOPAUSE;
827 error = mii_attach(dev, &sc->miibus, ifp,
828 (ifm_change_cb_t)fxp_ifmedia_upd,
829 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK,
830 MII_PHY_ANY, MII_OFFSET_ANY, flags);
831 if (error != 0) {
832 device_printf(dev, "attaching PHYs failed\n");
833 goto fail;
834 }
835 }
836
837 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
838 if_setdev(ifp, dev);
839 if_setinitfn(ifp, fxp_init);
840 if_setsoftc(ifp, sc);
841 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
842 if_setioctlfn(ifp, fxp_ioctl);
843 if_setstartfn(ifp, fxp_start);
844
845 if_setcapabilities(ifp, 0);
846 if_setcapenable(ifp, 0);
847
848 /* Enable checksum offload/TSO for 82550 or better chips */
849 if (sc->flags & FXP_FLAG_EXT_RFA) {
850 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO);
851 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
852 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
853 }
854
855 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
856 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
857 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
858 }
859
860 if (sc->flags & FXP_FLAG_WOLCAP) {
861 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
862 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
863 }
864
865 #ifdef DEVICE_POLLING
866 /* Inform the world we support polling. */
867 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
868 #endif
869
870 /*
871 * Attach the interface.
872 */
873 ether_ifattach(ifp, eaddr);
874
875 /*
876 * Tell the upper layer(s) we support long frames.
877 * Must appear after the call to ether_ifattach() because
878 * ether_ifattach() sets ifi_hdrlen to the default value.
879 */
880 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
881 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
882 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
883 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
884 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING |
885 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
886 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING |
887 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
888 }
889
890 /*
891 * Let the system queue as many packets as we have available
892 * TX descriptors.
893 */
894 if_setsendqlen(ifp, FXP_NTXCB - 1);
895 if_setsendqready(ifp);
896
897 /*
898 * Hook our interrupt after all initialization is complete.
899 */
900 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
901 NULL, fxp_intr, sc, &sc->ih);
902 if (error) {
903 device_printf(dev, "could not setup irq\n");
904 ether_ifdetach(sc->ifp);
905 goto fail;
906 }
907
908 /*
909 * Configure hardware to reject magic frames otherwise
910 * system will hang on recipt of magic frames.
911 */
912 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
913 FXP_LOCK(sc);
914 /* Clear wakeup events. */
915 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
916 fxp_init_body(sc, 0);
917 fxp_stop(sc);
918 FXP_UNLOCK(sc);
919 }
920
921 fail:
922 if (error)
923 fxp_release(sc);
924 return (error);
925 }
926
927 /*
928 * Release all resources. The softc lock should not be held and the
929 * interrupt should already be torn down.
930 */
931 static void
fxp_release(struct fxp_softc * sc)932 fxp_release(struct fxp_softc *sc)
933 {
934 struct fxp_rx *rxp;
935 struct fxp_tx *txp;
936 int i;
937
938 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
939 KASSERT(sc->ih == NULL,
940 ("fxp_release() called with intr handle still active"));
941 if (sc->miibus)
942 device_delete_child(sc->dev, sc->miibus);
943 bus_generic_detach(sc->dev);
944 ifmedia_removeall(&sc->sc_media);
945 if (sc->fxp_desc.cbl_list) {
946 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
947 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
948 sc->cbl_map);
949 }
950 if (sc->fxp_stats) {
951 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
952 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
953 }
954 if (sc->mcsp) {
955 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
956 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
957 }
958 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
959 if (sc->fxp_rxmtag) {
960 for (i = 0; i < FXP_NRFABUFS; i++) {
961 rxp = &sc->fxp_desc.rx_list[i];
962 if (rxp->rx_mbuf != NULL) {
963 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
964 BUS_DMASYNC_POSTREAD);
965 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
966 m_freem(rxp->rx_mbuf);
967 }
968 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
969 }
970 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
971 bus_dma_tag_destroy(sc->fxp_rxmtag);
972 }
973 if (sc->fxp_txmtag) {
974 for (i = 0; i < FXP_NTXCB; i++) {
975 txp = &sc->fxp_desc.tx_list[i];
976 if (txp->tx_mbuf != NULL) {
977 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
978 BUS_DMASYNC_POSTWRITE);
979 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
980 m_freem(txp->tx_mbuf);
981 }
982 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
983 }
984 bus_dma_tag_destroy(sc->fxp_txmtag);
985 }
986 if (sc->fxp_stag)
987 bus_dma_tag_destroy(sc->fxp_stag);
988 if (sc->cbl_tag)
989 bus_dma_tag_destroy(sc->cbl_tag);
990 if (sc->mcs_tag)
991 bus_dma_tag_destroy(sc->mcs_tag);
992 if (sc->ifp)
993 if_free(sc->ifp);
994
995 mtx_destroy(&sc->sc_mtx);
996 }
997
998 /*
999 * Detach interface.
1000 */
1001 static int
fxp_detach(device_t dev)1002 fxp_detach(device_t dev)
1003 {
1004 struct fxp_softc *sc = device_get_softc(dev);
1005
1006 #ifdef DEVICE_POLLING
1007 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1008 ether_poll_deregister(sc->ifp);
1009 #endif
1010
1011 FXP_LOCK(sc);
1012 /*
1013 * Stop DMA and drop transmit queue, but disable interrupts first.
1014 */
1015 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1016 fxp_stop(sc);
1017 FXP_UNLOCK(sc);
1018 callout_drain(&sc->stat_ch);
1019
1020 /*
1021 * Close down routes etc.
1022 */
1023 ether_ifdetach(sc->ifp);
1024
1025 /*
1026 * Unhook interrupt before dropping lock. This is to prevent
1027 * races with fxp_intr().
1028 */
1029 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1030 sc->ih = NULL;
1031
1032 /* Release our allocated resources. */
1033 fxp_release(sc);
1034 return (0);
1035 }
1036
1037 /*
1038 * Device shutdown routine. Called at system shutdown after sync. The
1039 * main purpose of this routine is to shut off receiver DMA so that
1040 * kernel memory doesn't get clobbered during warmboot.
1041 */
1042 static int
fxp_shutdown(device_t dev)1043 fxp_shutdown(device_t dev)
1044 {
1045
1046 /*
1047 * Make sure that DMA is disabled prior to reboot. Not doing
1048 * do could allow DMA to corrupt kernel memory during the
1049 * reboot before the driver initializes.
1050 */
1051 return (fxp_suspend(dev));
1052 }
1053
1054 /*
1055 * Device suspend routine. Stop the interface and save some PCI
1056 * settings in case the BIOS doesn't restore them properly on
1057 * resume.
1058 */
1059 static int
fxp_suspend(device_t dev)1060 fxp_suspend(device_t dev)
1061 {
1062 struct fxp_softc *sc = device_get_softc(dev);
1063 if_t ifp;
1064 int pmc;
1065 uint16_t pmstat;
1066
1067 FXP_LOCK(sc);
1068
1069 ifp = sc->ifp;
1070 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1071 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1072 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1073 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1074 /* Request PME. */
1075 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1076 sc->flags |= FXP_FLAG_WOL;
1077 /* Reconfigure hardware to accept magic frames. */
1078 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1079 fxp_init_body(sc, 0);
1080 }
1081 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1082 }
1083 fxp_stop(sc);
1084
1085 sc->suspended = 1;
1086
1087 FXP_UNLOCK(sc);
1088 return (0);
1089 }
1090
1091 /*
1092 * Device resume routine. re-enable busmastering, and restart the interface if
1093 * appropriate.
1094 */
1095 static int
fxp_resume(device_t dev)1096 fxp_resume(device_t dev)
1097 {
1098 struct fxp_softc *sc = device_get_softc(dev);
1099 if_t ifp = sc->ifp;
1100 int pmc;
1101 uint16_t pmstat;
1102
1103 FXP_LOCK(sc);
1104
1105 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1106 sc->flags &= ~FXP_FLAG_WOL;
1107 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1108 /* Disable PME and clear PME status. */
1109 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1110 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1111 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1112 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1113 CSR_READ_1(sc, FXP_CSR_PMDR));
1114 }
1115
1116 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1117 DELAY(10);
1118
1119 /* reinitialize interface if necessary */
1120 if (if_getflags(ifp) & IFF_UP)
1121 fxp_init_body(sc, 1);
1122
1123 sc->suspended = 0;
1124
1125 FXP_UNLOCK(sc);
1126 return (0);
1127 }
1128
1129 static void
fxp_eeprom_shiftin(struct fxp_softc * sc,int data,int length)1130 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1131 {
1132 uint16_t reg;
1133 int x;
1134
1135 /*
1136 * Shift in data.
1137 */
1138 for (x = 1 << (length - 1); x; x >>= 1) {
1139 if (data & x)
1140 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1141 else
1142 reg = FXP_EEPROM_EECS;
1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1144 DELAY(1);
1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1146 DELAY(1);
1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1148 DELAY(1);
1149 }
1150 }
1151
1152 /*
1153 * Read from the serial EEPROM. Basically, you manually shift in
1154 * the read opcode (one bit at a time) and then shift in the address,
1155 * and then you shift out the data (all of this one bit at a time).
1156 * The word size is 16 bits, so you have to provide the address for
1157 * every 16 bits of data.
1158 */
1159 static uint16_t
fxp_eeprom_getword(struct fxp_softc * sc,int offset,int autosize)1160 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1161 {
1162 uint16_t reg, data;
1163 int x;
1164
1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1166 /*
1167 * Shift in read opcode.
1168 */
1169 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1170 /*
1171 * Shift in address.
1172 */
1173 data = 0;
1174 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1175 if (offset & x)
1176 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1177 else
1178 reg = FXP_EEPROM_EECS;
1179 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1180 DELAY(1);
1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1182 DELAY(1);
1183 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1184 DELAY(1);
1185 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1186 data++;
1187 if (autosize && reg == 0) {
1188 sc->eeprom_size = data;
1189 break;
1190 }
1191 }
1192 /*
1193 * Shift out data.
1194 */
1195 data = 0;
1196 reg = FXP_EEPROM_EECS;
1197 for (x = 1 << 15; x; x >>= 1) {
1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1199 DELAY(1);
1200 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1201 data |= x;
1202 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1203 DELAY(1);
1204 }
1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1206 DELAY(1);
1207
1208 return (data);
1209 }
1210
1211 static void
fxp_eeprom_putword(struct fxp_softc * sc,int offset,uint16_t data)1212 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1213 {
1214 int i;
1215
1216 /*
1217 * Erase/write enable.
1218 */
1219 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1220 fxp_eeprom_shiftin(sc, 0x4, 3);
1221 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1223 DELAY(1);
1224 /*
1225 * Shift in write opcode, address, data.
1226 */
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1228 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1229 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1230 fxp_eeprom_shiftin(sc, data, 16);
1231 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1232 DELAY(1);
1233 /*
1234 * Wait for EEPROM to finish up.
1235 */
1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1237 DELAY(1);
1238 for (i = 0; i < 1000; i++) {
1239 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1240 break;
1241 DELAY(50);
1242 }
1243 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1244 DELAY(1);
1245 /*
1246 * Erase/write disable.
1247 */
1248 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1249 fxp_eeprom_shiftin(sc, 0x4, 3);
1250 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1251 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1252 DELAY(1);
1253 }
1254
1255 /*
1256 * From NetBSD:
1257 *
1258 * Figure out EEPROM size.
1259 *
1260 * 559's can have either 64-word or 256-word EEPROMs, the 558
1261 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1262 * talks about the existence of 16 to 256 word EEPROMs.
1263 *
1264 * The only known sizes are 64 and 256, where the 256 version is used
1265 * by CardBus cards to store CIS information.
1266 *
1267 * The address is shifted in msb-to-lsb, and after the last
1268 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1269 * after which follows the actual data. We try to detect this zero, by
1270 * probing the data-out bit in the EEPROM control register just after
1271 * having shifted in a bit. If the bit is zero, we assume we've
1272 * shifted enough address bits. The data-out should be tri-state,
1273 * before this, which should translate to a logical one.
1274 */
1275 static void
fxp_autosize_eeprom(struct fxp_softc * sc)1276 fxp_autosize_eeprom(struct fxp_softc *sc)
1277 {
1278
1279 /* guess maximum size of 256 words */
1280 sc->eeprom_size = 8;
1281
1282 /* autosize */
1283 (void) fxp_eeprom_getword(sc, 0, 1);
1284 }
1285
1286 static void
fxp_read_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1287 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1288 {
1289 int i;
1290
1291 for (i = 0; i < words; i++)
1292 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1293 }
1294
1295 static void
fxp_write_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1296 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1297 {
1298 int i;
1299
1300 for (i = 0; i < words; i++)
1301 fxp_eeprom_putword(sc, offset + i, data[i]);
1302 }
1303
1304 static void
fxp_load_eeprom(struct fxp_softc * sc)1305 fxp_load_eeprom(struct fxp_softc *sc)
1306 {
1307 int i;
1308 uint16_t cksum;
1309
1310 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1311 cksum = 0;
1312 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1313 cksum += sc->eeprom[i];
1314 cksum = 0xBABA - cksum;
1315 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1316 device_printf(sc->dev,
1317 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1318 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1319 }
1320
1321 /*
1322 * Grab the softc lock and call the real fxp_start_body() routine
1323 */
1324 static void
fxp_start(if_t ifp)1325 fxp_start(if_t ifp)
1326 {
1327 struct fxp_softc *sc = if_getsoftc(ifp);
1328
1329 FXP_LOCK(sc);
1330 fxp_start_body(ifp);
1331 FXP_UNLOCK(sc);
1332 }
1333
1334 /*
1335 * Start packet transmission on the interface.
1336 * This routine must be called with the softc lock held, and is an
1337 * internal entry point only.
1338 */
1339 static void
fxp_start_body(if_t ifp)1340 fxp_start_body(if_t ifp)
1341 {
1342 struct fxp_softc *sc = if_getsoftc(ifp);
1343 struct mbuf *mb_head;
1344 int txqueued;
1345
1346 FXP_LOCK_ASSERT(sc, MA_OWNED);
1347
1348 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1349 IFF_DRV_RUNNING)
1350 return;
1351
1352 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1353 fxp_txeof(sc);
1354 /*
1355 * We're finished if there is nothing more to add to the list or if
1356 * we're all filled up with buffers to transmit.
1357 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1358 * a NOP command when needed.
1359 */
1360 txqueued = 0;
1361 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) {
1362
1363 /*
1364 * Grab a packet to transmit.
1365 */
1366 mb_head = if_dequeue(ifp);
1367 if (mb_head == NULL)
1368 break;
1369
1370 if (fxp_encap(sc, &mb_head)) {
1371 if (mb_head == NULL)
1372 break;
1373 if_sendq_prepend(ifp, mb_head);
1374 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1375 }
1376 txqueued++;
1377 /*
1378 * Pass packet to bpf if there is a listener.
1379 */
1380 bpf_mtap_if(ifp, mb_head);
1381 }
1382
1383 /*
1384 * We're finished. If we added to the list, issue a RESUME to get DMA
1385 * going again if suspended.
1386 */
1387 if (txqueued > 0) {
1388 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1390 fxp_scb_wait(sc);
1391 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1392 /*
1393 * Set a 5 second timer just in case we don't hear
1394 * from the card again.
1395 */
1396 sc->watchdog_timer = 5;
1397 }
1398 }
1399
1400 static int
fxp_encap(struct fxp_softc * sc,struct mbuf ** m_head)1401 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1402 {
1403 struct mbuf *m;
1404 struct fxp_tx *txp;
1405 struct fxp_cb_tx *cbp;
1406 struct tcphdr *tcp;
1407 bus_dma_segment_t segs[FXP_NTXSEG];
1408 int error, i, nseg, tcp_payload;
1409
1410 FXP_LOCK_ASSERT(sc, MA_OWNED);
1411
1412 tcp_payload = 0;
1413 tcp = NULL;
1414 /*
1415 * Get pointer to next available tx desc.
1416 */
1417 txp = sc->fxp_desc.tx_last->tx_next;
1418
1419 /*
1420 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1421 * Ethernet Controller Family Open Source Software
1422 * Developer Manual says:
1423 * Using software parsing is only allowed with legal
1424 * TCP/IP or UDP/IP packets.
1425 * ...
1426 * For all other datagrams, hardware parsing must
1427 * be used.
1428 * Software parsing appears to truncate ICMP and
1429 * fragmented UDP packets that contain one to three
1430 * bytes in the second (and final) mbuf of the packet.
1431 */
1432 if (sc->flags & FXP_FLAG_EXT_RFA)
1433 txp->tx_cb->ipcb_ip_activation_high =
1434 FXP_IPCB_HARDWAREPARSING_ENABLE;
1435
1436 m = *m_head;
1437 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1438 /*
1439 * 82550/82551 requires ethernet/IP/TCP headers must be
1440 * contained in the first active transmit buffer.
1441 */
1442 struct ether_header *eh;
1443 struct ip *ip;
1444 uint32_t ip_off, poff;
1445
1446 if (M_WRITABLE(*m_head) == 0) {
1447 /* Get a writable copy. */
1448 m = m_dup(*m_head, M_NOWAIT);
1449 m_freem(*m_head);
1450 if (m == NULL) {
1451 *m_head = NULL;
1452 return (ENOBUFS);
1453 }
1454 *m_head = m;
1455 }
1456 ip_off = sizeof(struct ether_header);
1457 m = m_pullup(*m_head, ip_off);
1458 if (m == NULL) {
1459 *m_head = NULL;
1460 return (ENOBUFS);
1461 }
1462 eh = mtod(m, struct ether_header *);
1463 /* Check the existence of VLAN tag. */
1464 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1465 ip_off = sizeof(struct ether_vlan_header);
1466 m = m_pullup(m, ip_off);
1467 if (m == NULL) {
1468 *m_head = NULL;
1469 return (ENOBUFS);
1470 }
1471 }
1472 m = m_pullup(m, ip_off + sizeof(struct ip));
1473 if (m == NULL) {
1474 *m_head = NULL;
1475 return (ENOBUFS);
1476 }
1477 ip = (struct ip *)(mtod(m, char *) + ip_off);
1478 poff = ip_off + (ip->ip_hl << 2);
1479 m = m_pullup(m, poff + sizeof(struct tcphdr));
1480 if (m == NULL) {
1481 *m_head = NULL;
1482 return (ENOBUFS);
1483 }
1484 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1485 m = m_pullup(m, poff + (tcp->th_off << 2));
1486 if (m == NULL) {
1487 *m_head = NULL;
1488 return (ENOBUFS);
1489 }
1490
1491 /*
1492 * Since 82550/82551 doesn't modify IP length and pseudo
1493 * checksum in the first frame driver should compute it.
1494 */
1495 ip = (struct ip *)(mtod(m, char *) + ip_off);
1496 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1497 ip->ip_sum = 0;
1498 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1499 (tcp->th_off << 2));
1500 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1501 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1502 m->m_pkthdr.tso_segsz));
1503 /* Compute total TCP payload. */
1504 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1505 tcp_payload -= tcp->th_off << 2;
1506 *m_head = m;
1507 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1508 /*
1509 * Deal with TCP/IP checksum offload. Note that
1510 * in order for TCP checksum offload to work,
1511 * the pseudo header checksum must have already
1512 * been computed and stored in the checksum field
1513 * in the TCP header. The stack should have
1514 * already done this for us.
1515 */
1516 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1517 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1518 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1519
1520 #ifdef FXP_IP_CSUM_WAR
1521 /*
1522 * XXX The 82550 chip appears to have trouble
1523 * dealing with IP header checksums in very small
1524 * datagrams, namely fragments from 1 to 3 bytes
1525 * in size. For example, say you want to transmit
1526 * a UDP packet of 1473 bytes. The packet will be
1527 * fragmented over two IP datagrams, the latter
1528 * containing only one byte of data. The 82550 will
1529 * botch the header checksum on the 1-byte fragment.
1530 * As long as the datagram contains 4 or more bytes
1531 * of data, you're ok.
1532 *
1533 * The following code attempts to work around this
1534 * problem: if the datagram is less than 38 bytes
1535 * in size (14 bytes ether header, 20 bytes IP header,
1536 * plus 4 bytes of data), we punt and compute the IP
1537 * header checksum by hand. This workaround doesn't
1538 * work very well, however, since it can be fooled
1539 * by things like VLAN tags and IP options that make
1540 * the header sizes/offsets vary.
1541 */
1542
1543 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1544 if (m->m_pkthdr.len < 38) {
1545 struct ip *ip;
1546 m->m_data += ETHER_HDR_LEN;
1547 ip = mtod(m, struct ip *);
1548 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1549 m->m_data -= ETHER_HDR_LEN;
1550 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1551 } else {
1552 txp->tx_cb->ipcb_ip_activation_high =
1553 FXP_IPCB_HARDWAREPARSING_ENABLE;
1554 txp->tx_cb->ipcb_ip_schedule |=
1555 FXP_IPCB_IP_CHECKSUM_ENABLE;
1556 }
1557 }
1558 #endif
1559 }
1560
1561 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1562 segs, &nseg, 0);
1563 if (error == EFBIG) {
1564 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1565 if (m == NULL) {
1566 m_freem(*m_head);
1567 *m_head = NULL;
1568 return (ENOMEM);
1569 }
1570 *m_head = m;
1571 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1572 *m_head, segs, &nseg, 0);
1573 if (error != 0) {
1574 m_freem(*m_head);
1575 *m_head = NULL;
1576 return (ENOMEM);
1577 }
1578 } else if (error != 0)
1579 return (error);
1580 if (nseg == 0) {
1581 m_freem(*m_head);
1582 *m_head = NULL;
1583 return (EIO);
1584 }
1585
1586 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1587 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1588
1589 cbp = txp->tx_cb;
1590 for (i = 0; i < nseg; i++) {
1591 /*
1592 * If this is an 82550/82551, then we're using extended
1593 * TxCBs _and_ we're using checksum offload. This means
1594 * that the TxCB is really an IPCB. One major difference
1595 * between the two is that with plain extended TxCBs,
1596 * the bottom half of the TxCB contains two entries from
1597 * the TBD array, whereas IPCBs contain just one entry:
1598 * one entry (8 bytes) has been sacrificed for the TCP/IP
1599 * checksum offload control bits. So to make things work
1600 * right, we have to start filling in the TBD array
1601 * starting from a different place depending on whether
1602 * the chip is an 82550/82551 or not.
1603 */
1604 if (sc->flags & FXP_FLAG_EXT_RFA) {
1605 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1606 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1607 } else {
1608 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1609 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1610 }
1611 }
1612 if (sc->flags & FXP_FLAG_EXT_RFA) {
1613 /* Configure dynamic TBD for 82550/82551. */
1614 cbp->tbd_number = 0xFF;
1615 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1616 } else
1617 cbp->tbd_number = nseg;
1618 /* Configure TSO. */
1619 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1620 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1621 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1622 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1623 FXP_IPCB_IP_CHECKSUM_ENABLE |
1624 FXP_IPCB_TCP_PACKET |
1625 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1626 }
1627 /* Configure VLAN hardware tag insertion. */
1628 if ((m->m_flags & M_VLANTAG) != 0) {
1629 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1630 txp->tx_cb->ipcb_ip_activation_high |=
1631 FXP_IPCB_INSERTVLAN_ENABLE;
1632 }
1633
1634 txp->tx_mbuf = m;
1635 txp->tx_cb->cb_status = 0;
1636 txp->tx_cb->byte_count = 0;
1637 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1638 txp->tx_cb->cb_command =
1639 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1640 FXP_CB_COMMAND_S);
1641 else
1642 txp->tx_cb->cb_command =
1643 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1644 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1645 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1646 txp->tx_cb->tx_threshold = tx_threshold;
1647
1648 /*
1649 * Advance the end of list forward.
1650 */
1651 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1652 sc->fxp_desc.tx_last = txp;
1653
1654 /*
1655 * Advance the beginning of the list forward if there are
1656 * no other packets queued (when nothing is queued, tx_first
1657 * sits on the last TxCB that was sent out).
1658 */
1659 if (sc->tx_queued == 0)
1660 sc->fxp_desc.tx_first = txp;
1661
1662 sc->tx_queued++;
1663
1664 return (0);
1665 }
1666
1667 #ifdef DEVICE_POLLING
1668 static poll_handler_t fxp_poll;
1669
1670 static int
fxp_poll(if_t ifp,enum poll_cmd cmd,int count)1671 fxp_poll(if_t ifp, enum poll_cmd cmd, int count)
1672 {
1673 struct fxp_softc *sc = if_getsoftc(ifp);
1674 uint8_t statack;
1675 int rx_npkts = 0;
1676
1677 FXP_LOCK(sc);
1678 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1679 FXP_UNLOCK(sc);
1680 return (rx_npkts);
1681 }
1682
1683 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1684 FXP_SCB_STATACK_FR;
1685 if (cmd == POLL_AND_CHECK_STATUS) {
1686 uint8_t tmp;
1687
1688 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1689 if (tmp == 0xff || tmp == 0) {
1690 FXP_UNLOCK(sc);
1691 return (rx_npkts); /* nothing to do */
1692 }
1693 tmp &= ~statack;
1694 /* ack what we can */
1695 if (tmp != 0)
1696 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1697 statack |= tmp;
1698 }
1699 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1700 FXP_UNLOCK(sc);
1701 return (rx_npkts);
1702 }
1703 #endif /* DEVICE_POLLING */
1704
1705 /*
1706 * Process interface interrupts.
1707 */
1708 static void
fxp_intr(void * xsc)1709 fxp_intr(void *xsc)
1710 {
1711 struct fxp_softc *sc = xsc;
1712 if_t ifp = sc->ifp;
1713 uint8_t statack;
1714
1715 FXP_LOCK(sc);
1716 if (sc->suspended) {
1717 FXP_UNLOCK(sc);
1718 return;
1719 }
1720
1721 #ifdef DEVICE_POLLING
1722 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1723 FXP_UNLOCK(sc);
1724 return;
1725 }
1726 #endif
1727 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1728 /*
1729 * It should not be possible to have all bits set; the
1730 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1731 * all bits are set, this may indicate that the card has
1732 * been physically ejected, so ignore it.
1733 */
1734 if (statack == 0xff) {
1735 FXP_UNLOCK(sc);
1736 return;
1737 }
1738
1739 /*
1740 * First ACK all the interrupts in this pass.
1741 */
1742 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1743 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1744 fxp_intr_body(sc, ifp, statack, -1);
1745 }
1746 FXP_UNLOCK(sc);
1747 }
1748
1749 static void
fxp_txeof(struct fxp_softc * sc)1750 fxp_txeof(struct fxp_softc *sc)
1751 {
1752 if_t ifp;
1753 struct fxp_tx *txp;
1754
1755 ifp = sc->ifp;
1756 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1757 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1758 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1759 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1760 txp = txp->tx_next) {
1761 if (txp->tx_mbuf != NULL) {
1762 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1763 BUS_DMASYNC_POSTWRITE);
1764 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1765 m_freem(txp->tx_mbuf);
1766 txp->tx_mbuf = NULL;
1767 /* clear this to reset csum offload bits */
1768 txp->tx_cb->tbd[0].tb_addr = 0;
1769 }
1770 sc->tx_queued--;
1771 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1772 }
1773 sc->fxp_desc.tx_first = txp;
1774 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1775 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1776 if (sc->tx_queued == 0)
1777 sc->watchdog_timer = 0;
1778 }
1779
1780 static void
fxp_rxcsum(struct fxp_softc * sc,if_t ifp,struct mbuf * m,uint16_t status,int pos)1781 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m,
1782 uint16_t status, int pos)
1783 {
1784 struct ether_header *eh;
1785 struct ip *ip;
1786 struct udphdr *uh;
1787 int32_t hlen, len, pktlen, temp32;
1788 uint16_t csum, *opts;
1789
1790 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1791 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1792 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1793 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1794 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1795 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1796 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1797 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1798 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1799 CSUM_PSEUDO_HDR;
1800 m->m_pkthdr.csum_data = 0xffff;
1801 }
1802 }
1803 return;
1804 }
1805
1806 pktlen = m->m_pkthdr.len;
1807 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1808 return;
1809 eh = mtod(m, struct ether_header *);
1810 if (eh->ether_type != htons(ETHERTYPE_IP))
1811 return;
1812 ip = (struct ip *)(eh + 1);
1813 if (ip->ip_v != IPVERSION)
1814 return;
1815
1816 hlen = ip->ip_hl << 2;
1817 pktlen -= sizeof(struct ether_header);
1818 if (hlen < sizeof(struct ip))
1819 return;
1820 if (ntohs(ip->ip_len) < hlen)
1821 return;
1822 if (ntohs(ip->ip_len) != pktlen)
1823 return;
1824 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1825 return; /* can't handle fragmented packet */
1826
1827 switch (ip->ip_p) {
1828 case IPPROTO_TCP:
1829 if (pktlen < (hlen + sizeof(struct tcphdr)))
1830 return;
1831 break;
1832 case IPPROTO_UDP:
1833 if (pktlen < (hlen + sizeof(struct udphdr)))
1834 return;
1835 uh = (struct udphdr *)((caddr_t)ip + hlen);
1836 if (uh->uh_sum == 0)
1837 return; /* no checksum */
1838 break;
1839 default:
1840 return;
1841 }
1842 /* Extract computed checksum. */
1843 csum = be16dec(mtod(m, char *) + pos);
1844 /* checksum fixup for IP options */
1845 len = hlen - sizeof(struct ip);
1846 if (len > 0) {
1847 opts = (uint16_t *)(ip + 1);
1848 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1849 temp32 = csum - *opts;
1850 temp32 = (temp32 >> 16) + (temp32 & 65535);
1851 csum = temp32 & 65535;
1852 }
1853 }
1854 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1855 m->m_pkthdr.csum_data = csum;
1856 }
1857
1858 static int
fxp_intr_body(struct fxp_softc * sc,if_t ifp,uint8_t statack,int count)1859 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack,
1860 int count)
1861 {
1862 struct mbuf *m;
1863 struct fxp_rx *rxp;
1864 struct fxp_rfa *rfa;
1865 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1866 int rx_npkts;
1867 uint16_t status;
1868
1869 rx_npkts = 0;
1870 FXP_LOCK_ASSERT(sc, MA_OWNED);
1871
1872 if (rnr)
1873 sc->rnr++;
1874 #ifdef DEVICE_POLLING
1875 /* Pick up a deferred RNR condition if `count' ran out last time. */
1876 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1877 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1878 rnr = 1;
1879 }
1880 #endif
1881
1882 /*
1883 * Free any finished transmit mbuf chains.
1884 *
1885 * Handle the CNA event likt a CXTNO event. It used to
1886 * be that this event (control unit not ready) was not
1887 * encountered, but it is now with the SMPng modifications.
1888 * The exact sequence of events that occur when the interface
1889 * is brought up are different now, and if this event
1890 * goes unhandled, the configuration/rxfilter setup sequence
1891 * can stall for several seconds. The result is that no
1892 * packets go out onto the wire for about 5 to 10 seconds
1893 * after the interface is ifconfig'ed for the first time.
1894 */
1895 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1896 fxp_txeof(sc);
1897
1898 /*
1899 * Try to start more packets transmitting.
1900 */
1901 if (!if_sendq_empty(ifp))
1902 fxp_start_body(ifp);
1903
1904 /*
1905 * Just return if nothing happened on the receive side.
1906 */
1907 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1908 return (rx_npkts);
1909
1910 /*
1911 * Process receiver interrupts. If a no-resource (RNR)
1912 * condition exists, get whatever packets we can and
1913 * re-start the receiver.
1914 *
1915 * When using polling, we do not process the list to completion,
1916 * so when we get an RNR interrupt we must defer the restart
1917 * until we hit the last buffer with the C bit set.
1918 * If we run out of cycles and rfa_headm has the C bit set,
1919 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1920 * that the info will be used in the subsequent polling cycle.
1921 */
1922 for (;;) {
1923 rxp = sc->fxp_desc.rx_head;
1924 m = rxp->rx_mbuf;
1925 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1926 RFA_ALIGNMENT_FUDGE);
1927 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1928 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1929
1930 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1931 if (count >= 0 && count-- == 0) {
1932 if (rnr) {
1933 /* Defer RNR processing until the next time. */
1934 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1935 rnr = 0;
1936 }
1937 break;
1938 }
1939 #endif /* DEVICE_POLLING */
1940
1941 status = le16toh(rfa->rfa_status);
1942 if ((status & FXP_RFA_STATUS_C) == 0)
1943 break;
1944
1945 if ((status & FXP_RFA_STATUS_RNR) != 0)
1946 rnr++;
1947 /*
1948 * Advance head forward.
1949 */
1950 sc->fxp_desc.rx_head = rxp->rx_next;
1951
1952 /*
1953 * Add a new buffer to the receive chain.
1954 * If this fails, the old buffer is recycled
1955 * instead.
1956 */
1957 if (fxp_new_rfabuf(sc, rxp) == 0) {
1958 int total_len;
1959
1960 /*
1961 * Fetch packet length (the top 2 bits of
1962 * actual_size are flags set by the controller
1963 * upon completion), and drop the packet in case
1964 * of bogus length or CRC errors.
1965 */
1966 total_len = le16toh(rfa->actual_size) & 0x3fff;
1967 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1968 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1969 /* Adjust for appended checksum bytes. */
1970 total_len -= 2;
1971 }
1972 if (total_len < (int)sizeof(struct ether_header) ||
1973 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1974 sc->rfa_size) ||
1975 status & (FXP_RFA_STATUS_CRC |
1976 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1977 m_freem(m);
1978 fxp_add_rfabuf(sc, rxp);
1979 continue;
1980 }
1981
1982 m->m_pkthdr.len = m->m_len = total_len;
1983 if_setrcvif(m, ifp);
1984
1985 /* Do IP checksum checking. */
1986 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1987 fxp_rxcsum(sc, ifp, m, status, total_len);
1988 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1989 (status & FXP_RFA_STATUS_VLAN) != 0) {
1990 m->m_pkthdr.ether_vtag =
1991 ntohs(rfa->rfax_vlan_id);
1992 m->m_flags |= M_VLANTAG;
1993 }
1994 /*
1995 * Drop locks before calling if_input() since it
1996 * may re-enter fxp_start() in the netisr case.
1997 * This would result in a lock reversal. Better
1998 * performance might be obtained by chaining all
1999 * packets received, dropping the lock, and then
2000 * calling if_input() on each one.
2001 */
2002 FXP_UNLOCK(sc);
2003 if_input(ifp, m);
2004 FXP_LOCK(sc);
2005 rx_npkts++;
2006 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2007 return (rx_npkts);
2008 } else {
2009 /* Reuse RFA and loaded DMA map. */
2010 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2011 fxp_discard_rfabuf(sc, rxp);
2012 }
2013 fxp_add_rfabuf(sc, rxp);
2014 }
2015 if (rnr) {
2016 fxp_scb_wait(sc);
2017 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2018 sc->fxp_desc.rx_head->rx_addr);
2019 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2020 }
2021 return (rx_npkts);
2022 }
2023
2024 static void
fxp_update_stats(struct fxp_softc * sc)2025 fxp_update_stats(struct fxp_softc *sc)
2026 {
2027 if_t ifp = sc->ifp;
2028 struct fxp_stats *sp = sc->fxp_stats;
2029 struct fxp_hwstats *hsp;
2030 uint32_t *status;
2031
2032 FXP_LOCK_ASSERT(sc, MA_OWNED);
2033
2034 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2035 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2036 /* Update statistical counters. */
2037 if (sc->revision >= FXP_REV_82559_A0)
2038 status = &sp->completion_status;
2039 else if (sc->revision >= FXP_REV_82558_A4)
2040 status = (uint32_t *)&sp->tx_tco;
2041 else
2042 status = &sp->tx_pause;
2043 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2044 hsp = &sc->fxp_hwstats;
2045 hsp->tx_good += le32toh(sp->tx_good);
2046 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2047 hsp->tx_latecols += le32toh(sp->tx_latecols);
2048 hsp->tx_underruns += le32toh(sp->tx_underruns);
2049 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2050 hsp->tx_deffered += le32toh(sp->tx_deffered);
2051 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2052 hsp->tx_multiple_collisions +=
2053 le32toh(sp->tx_multiple_collisions);
2054 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2055 hsp->rx_good += le32toh(sp->rx_good);
2056 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2057 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2058 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2059 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2060 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2061 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2062 hsp->tx_pause += le32toh(sp->tx_pause);
2063 hsp->rx_pause += le32toh(sp->rx_pause);
2064 hsp->rx_controls += le32toh(sp->rx_controls);
2065 hsp->tx_tco += le16toh(sp->tx_tco);
2066 hsp->rx_tco += le16toh(sp->rx_tco);
2067
2068 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good));
2069 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2070 le32toh(sp->tx_total_collisions));
2071 if (sp->rx_good) {
2072 if_inc_counter(ifp, IFCOUNTER_IPACKETS,
2073 le32toh(sp->rx_good));
2074 sc->rx_idle_secs = 0;
2075 } else if (sc->flags & FXP_FLAG_RXBUG) {
2076 /*
2077 * Receiver's been idle for another second.
2078 */
2079 sc->rx_idle_secs++;
2080 }
2081 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2082 le32toh(sp->rx_crc_errors) +
2083 le32toh(sp->rx_alignment_errors) +
2084 le32toh(sp->rx_rnr_errors) +
2085 le32toh(sp->rx_overrun_errors));
2086 /*
2087 * If any transmit underruns occurred, bump up the transmit
2088 * threshold by another 512 bytes (64 * 8).
2089 */
2090 if (sp->tx_underruns) {
2091 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2092 le32toh(sp->tx_underruns));
2093 if (tx_threshold < 192)
2094 tx_threshold += 64;
2095 }
2096 *status = 0;
2097 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2098 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2099 }
2100 }
2101
2102 /*
2103 * Update packet in/out/collision statistics. The i82557 doesn't
2104 * allow you to access these counters without doing a fairly
2105 * expensive DMA to get _all_ of the statistics it maintains, so
2106 * we do this operation here only once per second. The statistics
2107 * counters in the kernel are updated from the previous dump-stats
2108 * DMA and then a new dump-stats DMA is started. The on-chip
2109 * counters are zeroed when the DMA completes. If we can't start
2110 * the DMA immediately, we don't wait - we just prepare to read
2111 * them again next time.
2112 */
2113 static void
fxp_tick(void * xsc)2114 fxp_tick(void *xsc)
2115 {
2116 struct fxp_softc *sc = xsc;
2117 if_t ifp = sc->ifp;
2118
2119 FXP_LOCK_ASSERT(sc, MA_OWNED);
2120
2121 /* Update statistical counters. */
2122 fxp_update_stats(sc);
2123
2124 /*
2125 * Release any xmit buffers that have completed DMA. This isn't
2126 * strictly necessary to do here, but it's advantagous for mbufs
2127 * with external storage to be released in a timely manner rather
2128 * than being defered for a potentially long time. This limits
2129 * the delay to a maximum of one second.
2130 */
2131 fxp_txeof(sc);
2132
2133 /*
2134 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2135 * then assume the receiver has locked up and attempt to clear
2136 * the condition by reprogramming the multicast filter. This is
2137 * a work-around for a bug in the 82557 where the receiver locks
2138 * up if it gets certain types of garbage in the synchronization
2139 * bits prior to the packet header. This bug is supposed to only
2140 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2141 * mode as well (perhaps due to a 10/100 speed transition).
2142 */
2143 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2144 sc->rx_idle_secs = 0;
2145 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2146 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2147 fxp_init_body(sc, 1);
2148 }
2149 return;
2150 }
2151 /*
2152 * If there is no pending command, start another stats
2153 * dump. Otherwise punt for now.
2154 */
2155 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2156 /*
2157 * Start another stats dump.
2158 */
2159 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2160 }
2161 if (sc->miibus != NULL)
2162 mii_tick(device_get_softc(sc->miibus));
2163
2164 /*
2165 * Check that chip hasn't hung.
2166 */
2167 fxp_watchdog(sc);
2168
2169 /*
2170 * Schedule another timeout one second from now.
2171 */
2172 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2173 }
2174
2175 /*
2176 * Stop the interface. Cancels the statistics updater and resets
2177 * the interface.
2178 */
2179 static void
fxp_stop(struct fxp_softc * sc)2180 fxp_stop(struct fxp_softc *sc)
2181 {
2182 if_t ifp = sc->ifp;
2183 struct fxp_tx *txp;
2184 int i;
2185
2186 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2187 sc->watchdog_timer = 0;
2188
2189 /*
2190 * Cancel stats updater.
2191 */
2192 callout_stop(&sc->stat_ch);
2193
2194 /*
2195 * Preserve PCI configuration, configure, IA/multicast
2196 * setup and put RU and CU into idle state.
2197 */
2198 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2199 DELAY(50);
2200 /* Disable interrupts. */
2201 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2202
2203 fxp_update_stats(sc);
2204
2205 /*
2206 * Release any xmit buffers.
2207 */
2208 txp = sc->fxp_desc.tx_list;
2209 for (i = 0; i < FXP_NTXCB; i++) {
2210 if (txp[i].tx_mbuf != NULL) {
2211 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2212 BUS_DMASYNC_POSTWRITE);
2213 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map);
2214 m_freem(txp[i].tx_mbuf);
2215 txp[i].tx_mbuf = NULL;
2216 /* clear this to reset csum offload bits */
2217 txp[i].tx_cb->tbd[0].tb_addr = 0;
2218 }
2219 }
2220 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2222 sc->tx_queued = 0;
2223 }
2224
2225 /*
2226 * Watchdog/transmission transmit timeout handler. Called when a
2227 * transmission is started on the interface, but no interrupt is
2228 * received before the timeout. This usually indicates that the
2229 * card has wedged for some reason.
2230 */
2231 static void
fxp_watchdog(struct fxp_softc * sc)2232 fxp_watchdog(struct fxp_softc *sc)
2233 {
2234 if_t ifp = sc->ifp;
2235
2236 FXP_LOCK_ASSERT(sc, MA_OWNED);
2237
2238 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2239 return;
2240
2241 device_printf(sc->dev, "device timeout\n");
2242 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2243
2244 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2245 fxp_init_body(sc, 1);
2246 }
2247
2248 /*
2249 * Acquire locks and then call the real initialization function. This
2250 * is necessary because ether_ioctl() calls if_init() and this would
2251 * result in mutex recursion if the mutex was held.
2252 */
2253 static void
fxp_init(void * xsc)2254 fxp_init(void *xsc)
2255 {
2256 struct fxp_softc *sc = xsc;
2257
2258 FXP_LOCK(sc);
2259 fxp_init_body(sc, 1);
2260 FXP_UNLOCK(sc);
2261 }
2262
2263 /*
2264 * Perform device initialization. This routine must be called with the
2265 * softc lock held.
2266 */
2267 static void
fxp_init_body(struct fxp_softc * sc,int setmedia)2268 fxp_init_body(struct fxp_softc *sc, int setmedia)
2269 {
2270 if_t ifp = sc->ifp;
2271 struct mii_data *mii;
2272 struct fxp_cb_config *cbp;
2273 struct fxp_cb_ias *cb_ias;
2274 struct fxp_cb_tx *tcbp;
2275 struct fxp_tx *txp;
2276 int i, prm;
2277
2278 FXP_LOCK_ASSERT(sc, MA_OWNED);
2279
2280 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2281 return;
2282
2283 /*
2284 * Cancel any pending I/O
2285 */
2286 fxp_stop(sc);
2287
2288 /*
2289 * Issue software reset, which also unloads the microcode.
2290 */
2291 sc->flags &= ~FXP_FLAG_UCODE;
2292 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2293 DELAY(50);
2294
2295 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2296
2297 /*
2298 * Initialize base of CBL and RFA memory. Loading with zero
2299 * sets it up for regular linear addressing.
2300 */
2301 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2302 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2303
2304 fxp_scb_wait(sc);
2305 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2306
2307 /*
2308 * Initialize base of dump-stats buffer.
2309 */
2310 fxp_scb_wait(sc);
2311 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2312 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2313 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2314 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2315 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2316
2317 /*
2318 * Attempt to load microcode if requested.
2319 * For ICH based controllers do not load microcode.
2320 */
2321 if (sc->ident->ich == 0) {
2322 if (if_getflags(ifp) & IFF_LINK0 &&
2323 (sc->flags & FXP_FLAG_UCODE) == 0)
2324 fxp_load_ucode(sc);
2325 }
2326
2327 /*
2328 * Set IFF_ALLMULTI status. It's needed in configure action
2329 * command.
2330 */
2331 fxp_mc_addrs(sc);
2332
2333 /*
2334 * We temporarily use memory that contains the TxCB list to
2335 * construct the config CB. The TxCB list memory is rebuilt
2336 * later.
2337 */
2338 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2339
2340 /*
2341 * This bcopy is kind of disgusting, but there are a bunch of must be
2342 * zero and must be one bits in this structure and this is the easiest
2343 * way to initialize them all to proper values.
2344 */
2345 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2346
2347 cbp->cb_status = 0;
2348 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2349 FXP_CB_COMMAND_EL);
2350 cbp->link_addr = 0xffffffff; /* (no) next command */
2351 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2352 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2353 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2354 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2355 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2356 cbp->type_enable = 0; /* actually reserved */
2357 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2358 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2359 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2360 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2361 cbp->dma_mbce = 0; /* (disable) dma max counters */
2362 cbp->late_scb = 0; /* (don't) defer SCB update */
2363 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2364 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2365 cbp->ci_int = 1; /* interrupt on CU idle */
2366 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2367 cbp->ext_stats_dis = 1; /* disable extended counters */
2368 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2369 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2370 cbp->disc_short_rx = !prm; /* discard short packets */
2371 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2372 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2373 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2374 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2375 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2376 cbp->csma_dis = 0; /* (don't) disable link */
2377 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2378 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2379 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2380 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2381 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2382 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2383 cbp->nsai = 1; /* (don't) disable source addr insert */
2384 cbp->preamble_length = 2; /* (7 byte) preamble */
2385 cbp->loopback = 0; /* (don't) loopback */
2386 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2387 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2388 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2389 cbp->promiscuous = prm; /* promiscuous mode */
2390 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2391 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2392 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2393 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2394 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2395
2396 cbp->stripping = !prm; /* truncate rx packet to byte count */
2397 cbp->padding = 1; /* (do) pad short tx packets */
2398 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2399 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2400 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2401 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2402 cbp->force_fdx = 0; /* (don't) force full duplex */
2403 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2404 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2405 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm;
2406 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2407 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2408 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2409
2410 if (sc->revision == FXP_REV_82557) {
2411 /*
2412 * The 82557 has no hardware flow control, the values
2413 * below are the defaults for the chip.
2414 */
2415 cbp->fc_delay_lsb = 0;
2416 cbp->fc_delay_msb = 0x40;
2417 cbp->pri_fc_thresh = 3;
2418 cbp->tx_fc_dis = 0;
2419 cbp->rx_fc_restop = 0;
2420 cbp->rx_fc_restart = 0;
2421 cbp->fc_filter = 0;
2422 cbp->pri_fc_loc = 1;
2423 } else {
2424 /* Set pause RX FIFO threshold to 1KB. */
2425 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2426 /* Set pause time. */
2427 cbp->fc_delay_lsb = 0xff;
2428 cbp->fc_delay_msb = 0xff;
2429 cbp->pri_fc_thresh = 3;
2430 mii = device_get_softc(sc->miibus);
2431 if ((IFM_OPTIONS(mii->mii_media_active) &
2432 IFM_ETH_TXPAUSE) != 0)
2433 /* enable transmit FC */
2434 cbp->tx_fc_dis = 0;
2435 else
2436 /* disable transmit FC */
2437 cbp->tx_fc_dis = 1;
2438 if ((IFM_OPTIONS(mii->mii_media_active) &
2439 IFM_ETH_RXPAUSE) != 0) {
2440 /* enable FC restart/restop frames */
2441 cbp->rx_fc_restart = 1;
2442 cbp->rx_fc_restop = 1;
2443 } else {
2444 /* disable FC restart/restop frames */
2445 cbp->rx_fc_restart = 0;
2446 cbp->rx_fc_restop = 0;
2447 }
2448 cbp->fc_filter = !prm; /* drop FC frames to host */
2449 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2450 }
2451
2452 /* Enable 82558 and 82559 extended statistics functionality. */
2453 if (sc->revision >= FXP_REV_82558_A4) {
2454 if (sc->revision >= FXP_REV_82559_A0) {
2455 /*
2456 * Extend configuration table size to 32
2457 * to include TCO configuration.
2458 */
2459 cbp->byte_count = 32;
2460 cbp->ext_stats_dis = 1;
2461 /* Enable TCO stats. */
2462 cbp->tno_int_or_tco_en = 1;
2463 cbp->gamla_rx = 1;
2464 } else
2465 cbp->ext_stats_dis = 0;
2466 }
2467
2468 /*
2469 * Start the config command/DMA.
2470 */
2471 fxp_scb_wait(sc);
2472 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2474 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2475 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2476 /* ...and wait for it to complete. */
2477 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2478
2479 /*
2480 * Now initialize the station address. Temporarily use the TxCB
2481 * memory area like we did above for the config CB.
2482 */
2483 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2484 cb_ias->cb_status = 0;
2485 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2486 cb_ias->link_addr = 0xffffffff;
2487 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2488
2489 /*
2490 * Start the IAS (Individual Address Setup) command/DMA.
2491 */
2492 fxp_scb_wait(sc);
2493 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2495 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2496 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2497 /* ...and wait for it to complete. */
2498 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2499
2500 /*
2501 * Initialize the multicast address list.
2502 */
2503 fxp_mc_setup(sc);
2504
2505 /*
2506 * Initialize transmit control block (TxCB) list.
2507 */
2508 txp = sc->fxp_desc.tx_list;
2509 tcbp = sc->fxp_desc.cbl_list;
2510 bzero(tcbp, FXP_TXCB_SZ);
2511 for (i = 0; i < FXP_NTXCB; i++) {
2512 txp[i].tx_mbuf = NULL;
2513 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2514 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2515 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2516 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2517 if (sc->flags & FXP_FLAG_EXT_TXCB)
2518 tcbp[i].tbd_array_addr =
2519 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2520 else
2521 tcbp[i].tbd_array_addr =
2522 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2523 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2524 }
2525 /*
2526 * Set the suspend flag on the first TxCB and start the control
2527 * unit. It will execute the NOP and then suspend.
2528 */
2529 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2530 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2531 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2532 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2533 sc->tx_queued = 1;
2534
2535 fxp_scb_wait(sc);
2536 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2537 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2538
2539 /*
2540 * Initialize receiver buffer area - RFA.
2541 */
2542 fxp_scb_wait(sc);
2543 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2544 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2545
2546 if (sc->miibus != NULL && setmedia != 0)
2547 mii_mediachg(device_get_softc(sc->miibus));
2548
2549 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2550
2551 /*
2552 * Enable interrupts.
2553 */
2554 #ifdef DEVICE_POLLING
2555 /*
2556 * ... but only do that if we are not polling. And because (presumably)
2557 * the default is interrupts on, we need to disable them explicitly!
2558 */
2559 if (if_getcapenable(ifp) & IFCAP_POLLING )
2560 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2561 else
2562 #endif /* DEVICE_POLLING */
2563 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2564
2565 /*
2566 * Start stats updater.
2567 */
2568 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2569 }
2570
2571 static int
fxp_serial_ifmedia_upd(if_t ifp)2572 fxp_serial_ifmedia_upd(if_t ifp)
2573 {
2574
2575 return (0);
2576 }
2577
2578 static void
fxp_serial_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2579 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2580 {
2581
2582 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2583 }
2584
2585 /*
2586 * Change media according to request.
2587 */
2588 static int
fxp_ifmedia_upd(if_t ifp)2589 fxp_ifmedia_upd(if_t ifp)
2590 {
2591 struct fxp_softc *sc = if_getsoftc(ifp);
2592 struct mii_data *mii;
2593 struct mii_softc *miisc;
2594
2595 mii = device_get_softc(sc->miibus);
2596 FXP_LOCK(sc);
2597 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2598 PHY_RESET(miisc);
2599 mii_mediachg(mii);
2600 FXP_UNLOCK(sc);
2601 return (0);
2602 }
2603
2604 /*
2605 * Notify the world which media we're using.
2606 */
2607 static void
fxp_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2608 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2609 {
2610 struct fxp_softc *sc = if_getsoftc(ifp);
2611 struct mii_data *mii;
2612
2613 mii = device_get_softc(sc->miibus);
2614 FXP_LOCK(sc);
2615 mii_pollstat(mii);
2616 ifmr->ifm_active = mii->mii_media_active;
2617 ifmr->ifm_status = mii->mii_media_status;
2618 FXP_UNLOCK(sc);
2619 }
2620
2621 /*
2622 * Add a buffer to the end of the RFA buffer list.
2623 * Return 0 if successful, 1 for failure. A failure results in
2624 * reusing the RFA buffer.
2625 * The RFA struct is stuck at the beginning of mbuf cluster and the
2626 * data pointer is fixed up to point just past it.
2627 */
2628 static int
fxp_new_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2629 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2630 {
2631 struct mbuf *m;
2632 struct fxp_rfa *rfa;
2633 bus_dmamap_t tmp_map;
2634 int error;
2635
2636 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2637 if (m == NULL)
2638 return (ENOBUFS);
2639
2640 /*
2641 * Move the data pointer up so that the incoming data packet
2642 * will be 32-bit aligned.
2643 */
2644 m->m_data += RFA_ALIGNMENT_FUDGE;
2645
2646 /*
2647 * Get a pointer to the base of the mbuf cluster and move
2648 * data start past it.
2649 */
2650 rfa = mtod(m, struct fxp_rfa *);
2651 m->m_data += sc->rfa_size;
2652 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2653
2654 rfa->rfa_status = 0;
2655 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2656 rfa->actual_size = 0;
2657 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2658 sc->rfa_size;
2659
2660 /*
2661 * Initialize the rest of the RFA. Note that since the RFA
2662 * is misaligned, we cannot store values directly. We're thus
2663 * using the le32enc() function which handles endianness and
2664 * is also alignment-safe.
2665 */
2666 le32enc(&rfa->link_addr, 0xffffffff);
2667 le32enc(&rfa->rbd_addr, 0xffffffff);
2668
2669 /* Map the RFA into DMA memory. */
2670 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2671 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2672 &rxp->rx_addr, BUS_DMA_NOWAIT);
2673 if (error) {
2674 m_freem(m);
2675 return (error);
2676 }
2677
2678 if (rxp->rx_mbuf != NULL)
2679 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2680 tmp_map = sc->spare_map;
2681 sc->spare_map = rxp->rx_map;
2682 rxp->rx_map = tmp_map;
2683 rxp->rx_mbuf = m;
2684
2685 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2686 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2687 return (0);
2688 }
2689
2690 static void
fxp_add_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2691 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2692 {
2693 struct fxp_rfa *p_rfa;
2694 struct fxp_rx *p_rx;
2695
2696 /*
2697 * If there are other buffers already on the list, attach this
2698 * one to the end by fixing up the tail to point to this one.
2699 */
2700 if (sc->fxp_desc.rx_head != NULL) {
2701 p_rx = sc->fxp_desc.rx_tail;
2702 p_rfa = (struct fxp_rfa *)
2703 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2704 p_rx->rx_next = rxp;
2705 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2706 p_rfa->rfa_control = 0;
2707 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2709 } else {
2710 rxp->rx_next = NULL;
2711 sc->fxp_desc.rx_head = rxp;
2712 }
2713 sc->fxp_desc.rx_tail = rxp;
2714 }
2715
2716 static void
fxp_discard_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2717 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2718 {
2719 struct mbuf *m;
2720 struct fxp_rfa *rfa;
2721
2722 m = rxp->rx_mbuf;
2723 m->m_data = m->m_ext.ext_buf;
2724 /*
2725 * Move the data pointer up so that the incoming data packet
2726 * will be 32-bit aligned.
2727 */
2728 m->m_data += RFA_ALIGNMENT_FUDGE;
2729
2730 /*
2731 * Get a pointer to the base of the mbuf cluster and move
2732 * data start past it.
2733 */
2734 rfa = mtod(m, struct fxp_rfa *);
2735 m->m_data += sc->rfa_size;
2736 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2737
2738 rfa->rfa_status = 0;
2739 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2740 rfa->actual_size = 0;
2741
2742 /*
2743 * Initialize the rest of the RFA. Note that since the RFA
2744 * is misaligned, we cannot store values directly. We're thus
2745 * using the le32enc() function which handles endianness and
2746 * is also alignment-safe.
2747 */
2748 le32enc(&rfa->link_addr, 0xffffffff);
2749 le32enc(&rfa->rbd_addr, 0xffffffff);
2750
2751 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2753 }
2754
2755 static int
fxp_miibus_readreg(device_t dev,int phy,int reg)2756 fxp_miibus_readreg(device_t dev, int phy, int reg)
2757 {
2758 struct fxp_softc *sc = device_get_softc(dev);
2759 int count = 10000;
2760 int value;
2761
2762 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2763 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2764
2765 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2766 && count--)
2767 DELAY(10);
2768
2769 if (count <= 0)
2770 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2771
2772 return (value & 0xffff);
2773 }
2774
2775 static int
fxp_miibus_writereg(device_t dev,int phy,int reg,int value)2776 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2777 {
2778 struct fxp_softc *sc = device_get_softc(dev);
2779 int count = 10000;
2780
2781 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2782 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2783 (value & 0xffff));
2784
2785 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2786 count--)
2787 DELAY(10);
2788
2789 if (count <= 0)
2790 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2791 return (0);
2792 }
2793
2794 static void
fxp_miibus_statchg(device_t dev)2795 fxp_miibus_statchg(device_t dev)
2796 {
2797 struct fxp_softc *sc;
2798 struct mii_data *mii;
2799 if_t ifp;
2800
2801 sc = device_get_softc(dev);
2802 mii = device_get_softc(sc->miibus);
2803 ifp = sc->ifp;
2804 if (mii == NULL || ifp == (void *)NULL ||
2805 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2806 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2807 (IFM_AVALID | IFM_ACTIVE))
2808 return;
2809
2810 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2811 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2812 sc->cu_resume_bug = 1;
2813 else
2814 sc->cu_resume_bug = 0;
2815 /*
2816 * Call fxp_init_body in order to adjust the flow control settings.
2817 * Note that the 82557 doesn't support hardware flow control.
2818 */
2819 if (sc->revision == FXP_REV_82557)
2820 return;
2821 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2822 fxp_init_body(sc, 0);
2823 }
2824
2825 static int
fxp_ioctl(if_t ifp,u_long command,caddr_t data)2826 fxp_ioctl(if_t ifp, u_long command, caddr_t data)
2827 {
2828 struct fxp_softc *sc = if_getsoftc(ifp);
2829 struct ifreq *ifr = (struct ifreq *)data;
2830 struct mii_data *mii;
2831 int flag, mask, error = 0, reinit;
2832
2833 switch (command) {
2834 case SIOCSIFFLAGS:
2835 FXP_LOCK(sc);
2836 /*
2837 * If interface is marked up and not running, then start it.
2838 * If it is marked down and running, stop it.
2839 * XXX If it's up then re-initialize it. This is so flags
2840 * such as IFF_PROMISC are handled.
2841 */
2842 if (if_getflags(ifp) & IFF_UP) {
2843 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2844 ((if_getflags(ifp) ^ sc->if_flags) &
2845 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2846 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2847 fxp_init_body(sc, 0);
2848 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2849 fxp_init_body(sc, 1);
2850 } else {
2851 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2852 fxp_stop(sc);
2853 }
2854 sc->if_flags = if_getflags(ifp);
2855 FXP_UNLOCK(sc);
2856 break;
2857
2858 case SIOCADDMULTI:
2859 case SIOCDELMULTI:
2860 FXP_LOCK(sc);
2861 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2862 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2863 fxp_init_body(sc, 0);
2864 }
2865 FXP_UNLOCK(sc);
2866 break;
2867
2868 case SIOCSIFMEDIA:
2869 case SIOCGIFMEDIA:
2870 if (sc->miibus != NULL) {
2871 mii = device_get_softc(sc->miibus);
2872 error = ifmedia_ioctl(ifp, ifr,
2873 &mii->mii_media, command);
2874 } else {
2875 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2876 }
2877 break;
2878
2879 case SIOCSIFCAP:
2880 reinit = 0;
2881 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
2882 #ifdef DEVICE_POLLING
2883 if (mask & IFCAP_POLLING) {
2884 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2885 error = ether_poll_register(fxp_poll, ifp);
2886 if (error)
2887 return(error);
2888 FXP_LOCK(sc);
2889 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2890 FXP_SCB_INTR_DISABLE);
2891 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2892 FXP_UNLOCK(sc);
2893 } else {
2894 error = ether_poll_deregister(ifp);
2895 /* Enable interrupts in any case */
2896 FXP_LOCK(sc);
2897 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2898 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2899 FXP_UNLOCK(sc);
2900 }
2901 }
2902 #endif
2903 FXP_LOCK(sc);
2904 if ((mask & IFCAP_TXCSUM) != 0 &&
2905 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2906 if_togglecapenable(ifp, IFCAP_TXCSUM);
2907 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2908 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2909 else
2910 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2911 }
2912 if ((mask & IFCAP_RXCSUM) != 0 &&
2913 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2914 if_togglecapenable(ifp, IFCAP_RXCSUM);
2915 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2916 reinit++;
2917 }
2918 if ((mask & IFCAP_TSO4) != 0 &&
2919 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2920 if_togglecapenable(ifp, IFCAP_TSO4);
2921 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2922 if_sethwassistbits(ifp, CSUM_TSO, 0);
2923 else
2924 if_sethwassistbits(ifp, 0, CSUM_TSO);
2925 }
2926 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2927 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2928 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2929 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2930 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2931 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2932 if (sc->revision != FXP_REV_82557)
2933 flag = FXP_FLAG_LONG_PKT_EN;
2934 else /* a hack to get long frames on the old chip */
2935 flag = FXP_FLAG_SAVE_BAD;
2936 sc->flags ^= flag;
2937 if (if_getflags(ifp) & IFF_UP)
2938 reinit++;
2939 }
2940 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2941 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2942 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2943 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2944 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2945 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2946 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2947 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2948 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2949 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2950 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2951 IFCAP_VLAN_HWCSUM);
2952 reinit++;
2953 }
2954 if (reinit > 0 &&
2955 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2956 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2957 fxp_init_body(sc, 0);
2958 }
2959 FXP_UNLOCK(sc);
2960 if_vlancap(ifp);
2961 break;
2962
2963 default:
2964 error = ether_ioctl(ifp, command, data);
2965 }
2966 return (error);
2967 }
2968
2969 static u_int
fxp_setup_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2970 fxp_setup_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2971 {
2972 struct fxp_softc *sc = arg;
2973 struct fxp_cb_mcs *mcsp = sc->mcsp;
2974
2975 if (mcsp->mc_cnt < MAXMCADDR)
2976 bcopy(LLADDR(sdl), mcsp->mc_addr[mcsp->mc_cnt * ETHER_ADDR_LEN],
2977 ETHER_ADDR_LEN);
2978 mcsp->mc_cnt++;
2979 return (1);
2980 }
2981
2982 /*
2983 * Fill in the multicast address list and return number of entries.
2984 */
2985 static void
fxp_mc_addrs(struct fxp_softc * sc)2986 fxp_mc_addrs(struct fxp_softc *sc)
2987 {
2988 struct fxp_cb_mcs *mcsp = sc->mcsp;
2989 if_t ifp = sc->ifp;
2990
2991 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2992 mcsp->mc_cnt = 0;
2993 if_foreach_llmaddr(sc->ifp, fxp_setup_maddr, sc);
2994 if (mcsp->mc_cnt >= MAXMCADDR) {
2995 if_setflagbits(ifp, IFF_ALLMULTI, 0);
2996 mcsp->mc_cnt = 0;
2997 }
2998 }
2999 mcsp->mc_cnt = htole16(mcsp->mc_cnt * ETHER_ADDR_LEN);
3000 }
3001
3002 /*
3003 * Program the multicast filter.
3004 *
3005 * We have an artificial restriction that the multicast setup command
3006 * must be the first command in the chain, so we take steps to ensure
3007 * this. By requiring this, it allows us to keep up the performance of
3008 * the pre-initialized command ring (esp. link pointers) by not actually
3009 * inserting the mcsetup command in the ring - i.e. its link pointer
3010 * points to the TxCB ring, but the mcsetup descriptor itself is not part
3011 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3012 * lead into the regular TxCB ring when it completes.
3013 */
3014 static void
fxp_mc_setup(struct fxp_softc * sc)3015 fxp_mc_setup(struct fxp_softc *sc)
3016 {
3017 struct fxp_cb_mcs *mcsp;
3018 int count;
3019
3020 FXP_LOCK_ASSERT(sc, MA_OWNED);
3021
3022 mcsp = sc->mcsp;
3023 mcsp->cb_status = 0;
3024 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3025 mcsp->link_addr = 0xffffffff;
3026 fxp_mc_addrs(sc);
3027
3028 /*
3029 * Wait until command unit is idle. This should never be the
3030 * case when nothing is queued, but make sure anyway.
3031 */
3032 count = 100;
3033 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3034 FXP_SCB_CUS_IDLE && --count)
3035 DELAY(10);
3036 if (count == 0) {
3037 device_printf(sc->dev, "command queue timeout\n");
3038 return;
3039 }
3040
3041 /*
3042 * Start the multicast setup command.
3043 */
3044 fxp_scb_wait(sc);
3045 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3047 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3048 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3049 /* ...and wait for it to complete. */
3050 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3051 }
3052
3053 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3054 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3055 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3056 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3057 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3058 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3059 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3060
3061 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3062
3063 static const struct ucode {
3064 uint32_t revision;
3065 uint32_t *ucode;
3066 int length;
3067 u_short int_delay_offset;
3068 u_short bundle_max_offset;
3069 } ucode_table[] = {
3070 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3071 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3072 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3073 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3074 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3075 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3076 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3077 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3078 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3079 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3080 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3081 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3082 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3083 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3084 { 0, NULL, 0, 0, 0 }
3085 };
3086
3087 static void
fxp_load_ucode(struct fxp_softc * sc)3088 fxp_load_ucode(struct fxp_softc *sc)
3089 {
3090 const struct ucode *uc;
3091 struct fxp_cb_ucode *cbp;
3092 int i;
3093
3094 if (sc->flags & FXP_FLAG_NO_UCODE)
3095 return;
3096
3097 for (uc = ucode_table; uc->ucode != NULL; uc++)
3098 if (sc->revision == uc->revision)
3099 break;
3100 if (uc->ucode == NULL)
3101 return;
3102 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3103 cbp->cb_status = 0;
3104 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3105 cbp->link_addr = 0xffffffff; /* (no) next command */
3106 for (i = 0; i < uc->length; i++)
3107 cbp->ucode[i] = htole32(uc->ucode[i]);
3108 if (uc->int_delay_offset)
3109 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3110 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3111 if (uc->bundle_max_offset)
3112 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3113 htole16(sc->tunable_bundle_max);
3114 /*
3115 * Download the ucode to the chip.
3116 */
3117 fxp_scb_wait(sc);
3118 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3119 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3120 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3121 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3122 /* ...and wait for it to complete. */
3123 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3124 device_printf(sc->dev,
3125 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3126 sc->tunable_int_delay,
3127 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3128 sc->flags |= FXP_FLAG_UCODE;
3129 bzero(cbp, FXP_TXCB_SZ);
3130 }
3131
3132 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3133 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3134
3135 static void
fxp_sysctl_node(struct fxp_softc * sc)3136 fxp_sysctl_node(struct fxp_softc *sc)
3137 {
3138 struct sysctl_ctx_list *ctx;
3139 struct sysctl_oid_list *child, *parent;
3140 struct sysctl_oid *tree;
3141 struct fxp_hwstats *hsp;
3142
3143 ctx = device_get_sysctl_ctx(sc->dev);
3144 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3145
3146 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_delay",
3147 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3148 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3149 "FXP driver receive interrupt microcode bundling delay");
3150 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "bundle_max",
3151 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3152 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3153 "FXP driver receive interrupt microcode bundle size limit");
3154 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3155 "FXP RNR events");
3156
3157 /*
3158 * Pull in device tunables.
3159 */
3160 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3161 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3162 (void) resource_int_value(device_get_name(sc->dev),
3163 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3164 (void) resource_int_value(device_get_name(sc->dev),
3165 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3166 sc->rnr = 0;
3167
3168 hsp = &sc->fxp_hwstats;
3169 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
3170 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "FXP statistics");
3171 parent = SYSCTL_CHILDREN(tree);
3172
3173 /* Rx MAC statistics. */
3174 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
3175 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
3176 child = SYSCTL_CHILDREN(tree);
3177 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3178 &hsp->rx_good, "Good frames");
3179 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3180 &hsp->rx_crc_errors, "CRC errors");
3181 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3182 &hsp->rx_alignment_errors, "Alignment errors");
3183 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3184 &hsp->rx_rnr_errors, "RNR errors");
3185 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3186 &hsp->rx_overrun_errors, "Overrun errors");
3187 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3188 &hsp->rx_cdt_errors, "Collision detect errors");
3189 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3190 &hsp->rx_shortframes, "Short frame errors");
3191 if (sc->revision >= FXP_REV_82558_A4) {
3192 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3193 &hsp->rx_pause, "Pause frames");
3194 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3195 &hsp->rx_controls, "Unsupported control frames");
3196 }
3197 if (sc->revision >= FXP_REV_82559_A0)
3198 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3199 &hsp->rx_tco, "TCO frames");
3200
3201 /* Tx MAC statistics. */
3202 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
3203 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
3204 child = SYSCTL_CHILDREN(tree);
3205 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3206 &hsp->tx_good, "Good frames");
3207 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3208 &hsp->tx_maxcols, "Maximum collisions errors");
3209 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3210 &hsp->tx_latecols, "Late collisions errors");
3211 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3212 &hsp->tx_underruns, "Underrun errors");
3213 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3214 &hsp->tx_lostcrs, "Lost carrier sense");
3215 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3216 &hsp->tx_deffered, "Deferred");
3217 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3218 &hsp->tx_single_collisions, "Single collisions");
3219 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3220 &hsp->tx_multiple_collisions, "Multiple collisions");
3221 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3222 &hsp->tx_total_collisions, "Total collisions");
3223 if (sc->revision >= FXP_REV_82558_A4)
3224 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3225 &hsp->tx_pause, "Pause frames");
3226 if (sc->revision >= FXP_REV_82559_A0)
3227 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3228 &hsp->tx_tco, "TCO frames");
3229 }
3230
3231 #undef FXP_SYSCTL_STAT_ADD
3232
3233 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3234 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3235 {
3236 int error, value;
3237
3238 value = *(int *)arg1;
3239 error = sysctl_handle_int(oidp, &value, 0, req);
3240 if (error || !req->newptr)
3241 return (error);
3242 if (value < low || value > high)
3243 return (EINVAL);
3244 *(int *)arg1 = value;
3245 return (0);
3246 }
3247
3248 /*
3249 * Interrupt delay is expressed in microseconds, a multiplier is used
3250 * to convert this to the appropriate clock ticks before using.
3251 */
3252 static int
sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)3253 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3254 {
3255
3256 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3257 }
3258
3259 static int
sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)3260 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3261 {
3262
3263 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3264 }
3265