1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Justin Hibbits
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 #include <sys/param.h>
31 #include <sys/pmc.h>
32 #include <sys/pmckern.h>
33 #include <sys/systm.h>
34
35 #include <machine/pmc_mdep.h>
36 #include <machine/spr.h>
37 #include <machine/cpu.h>
38
39 #include "hwpmc_powerpc.h"
40
41 #define PPC970_MAX_PMCS 8
42 #define PMC_PPC970_FLAG_PMCS 0x000000ff
43
44 /* MMCR0, PMC1 is 8 bytes in, PMC2 is 1 byte in. */
45 #define PPC970_SET_MMCR0_PMCSEL(r, x, i) \
46 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
47 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
48 #define PPC970_SET_MMCR1_PMCSEL(r, x, i) \
49 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
50
51 /* How PMC works on PPC970:
52 *
53 * Any PMC can count a direct event. Indirect events are handled specially.
54 * Direct events: As published.
55 *
56 * Encoding 00 000 -- Add byte lane bit counters
57 * MMCR1[24:31] -- select bit matching PMC being an adder.
58 * Bus events:
59 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
60 * lane (2/3).
61 * PMCxSEL[2:4] -- bit in the byte lane selected.
62 *
63 * PMC[1,2,5,6] == lane 0/lane 2
64 * PMC[3,4,7,8] == lane 1,3
65 *
66 *
67 * Lanes:
68 * Lane 0 -- TTM0(FPU,ISU,IFU,VPU)
69 * TTM1(IDU,ISU,STS)
70 * LSU0 byte 0
71 * LSU1 byte 0
72 * Lane 1 -- TTM0
73 * TTM1
74 * LSU0 byte 1
75 * LSU1 byte 1
76 * Lane 2 -- TTM0
77 * TTM1
78 * LSU0 byte 2
79 * LSU1 byte 2 or byte 6
80 * Lane 3 -- TTM0
81 * TTM1
82 * LSU0 byte 3
83 * LSU1 byte 3 or byte 7
84 *
85 * Adders:
86 * Add byte lane for PMC (above), bit 0+4, 1+5, 2+6, 3+7
87 */
88
89 static struct pmc_ppc_event ppc970_event_codes[] = {
90 {PMC_EV_PPC970_INSTR_COMPLETED,
91 .pe_flags = PMC_PPC970_FLAG_PMCS,
92 .pe_code = 0x09
93 },
94 {PMC_EV_PPC970_MARKED_GROUP_DISPATCH,
95 .pe_flags = PMC_FLAG_PMC1,
96 .pe_code = 0x2
97 },
98 {PMC_EV_PPC970_MARKED_STORE_COMPLETED,
99 .pe_flags = PMC_FLAG_PMC1,
100 .pe_code = 0x03
101 },
102 {PMC_EV_PPC970_GCT_EMPTY,
103 .pe_flags = PMC_FLAG_PMC1,
104 .pe_code = 0x04
105 },
106 {PMC_EV_PPC970_RUN_CYCLES,
107 .pe_flags = PMC_FLAG_PMC1,
108 .pe_code = 0x05
109 },
110 {PMC_EV_PPC970_OVERFLOW,
111 .pe_flags = PMC_PPC970_FLAG_PMCS,
112 .pe_code = 0x0a
113 },
114 {PMC_EV_PPC970_CYCLES,
115 .pe_flags = PMC_PPC970_FLAG_PMCS,
116 .pe_code = 0x0f
117 },
118 {PMC_EV_PPC970_THRESHOLD_TIMEOUT,
119 .pe_flags = PMC_FLAG_PMC2,
120 .pe_code = 0x3
121 },
122 {PMC_EV_PPC970_GROUP_DISPATCH,
123 .pe_flags = PMC_FLAG_PMC2,
124 .pe_code = 0x4
125 },
126 {PMC_EV_PPC970_BR_MARKED_INSTR_FINISH,
127 .pe_flags = PMC_FLAG_PMC2,
128 .pe_code = 0x5
129 },
130 {PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL,
131 .pe_flags = PMC_FLAG_PMC2,
132 .pe_code = 0xb
133 },
134 {PMC_EV_PPC970_STOP_COMPLETION,
135 .pe_flags = PMC_FLAG_PMC3,
136 .pe_code = 0x1
137 },
138 {PMC_EV_PPC970_LSU_EMPTY,
139 .pe_flags = PMC_FLAG_PMC3,
140 .pe_code = 0x2
141 },
142 {PMC_EV_PPC970_MARKED_STORE_WITH_INTR,
143 .pe_flags = PMC_FLAG_PMC3,
144 .pe_code = 0x3
145 },
146 {PMC_EV_PPC970_CYCLES_IN_SUPER,
147 .pe_flags = PMC_FLAG_PMC3,
148 .pe_code = 0x4
149 },
150 {PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED,
151 .pe_flags = PMC_FLAG_PMC3,
152 .pe_code = 0x5
153 },
154 {PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY,
155 .pe_flags = PMC_FLAG_PMC4,
156 .pe_code = 0x2
157 },
158 {PMC_EV_PPC970_SRQ_EMPTY,
159 .pe_flags = PMC_FLAG_PMC4,
160 .pe_code = 0x3
161 },
162 {PMC_EV_PPC970_MARKED_GROUP_COMPLETED,
163 .pe_flags = PMC_FLAG_PMC4,
164 .pe_code = 0x4
165 },
166 {PMC_EV_PPC970_CR_MARKED_INSTR_FINISH,
167 .pe_flags = PMC_FLAG_PMC4,
168 .pe_code = 0x5
169 },
170 {PMC_EV_PPC970_DISPATCH_SUCCESS,
171 .pe_flags = PMC_FLAG_PMC5,
172 .pe_code = 0x1
173 },
174 {PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE,
175 .pe_flags = PMC_FLAG_PMC5,
176 .pe_code = 0x2
177 },
178 {PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED,
179 .pe_flags = PMC_FLAG_PMC5,
180 .pe_code = 0x3
181 },
182 {PMC_EV_PPC970_GROUP_MARKED_IDU,
183 .pe_flags = PMC_FLAG_PMC5,
184 .pe_code = 0x4
185 },
186 {PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT,
187 .pe_flags = PMC_FLAG_PMC5,
188 .pe_code = 0x5
189 },
190 {PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY,
191 .pe_flags = PMC_FLAG_PMC6,
192 .pe_code = 0x2
193 },
194 {PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS,
195 .pe_flags = PMC_FLAG_PMC6,
196 .pe_code = 0x3
197 },
198 {PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED,
199 .pe_flags = PMC_FLAG_PMC6,
200 .pe_code = 0x4
201 },
202 {PMC_EV_PPC970_MARKED_GROUP_ISSUED,
203 .pe_flags = PMC_FLAG_PMC6,
204 .pe_code = 0x5
205 },
206 {PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE,
207 .pe_flags = PMC_FLAG_PMC7,
208 .pe_code = 0x2
209 },
210 {PMC_EV_PPC970_GROUP_COMPLETED,
211 .pe_flags = PMC_FLAG_PMC7,
212 .pe_code = 0x3
213 },
214 {PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED,
215 .pe_flags = PMC_FLAG_PMC7,
216 .pe_code = 0x4
217 },
218 {PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT,
219 .pe_flags = PMC_FLAG_PMC7,
220 .pe_code = 0x5
221 },
222 {PMC_EV_PPC970_EXTERNAL_INTERRUPT,
223 .pe_flags = PMC_FLAG_PMC8,
224 .pe_code = 0x2
225 },
226 {PMC_EV_PPC970_GROUP_DISPATCH_REJECT,
227 .pe_flags = PMC_FLAG_PMC8,
228 .pe_code = 0x3
229 },
230 {PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH,
231 .pe_flags = PMC_FLAG_PMC8,
232 .pe_code = 0x4
233 },
234 {PMC_EV_PPC970_TIMEBASE_EVENT,
235 .pe_flags = PMC_FLAG_PMC8,
236 .pe_code = 0x5
237 },
238 #if 0
239 {PMC_EV_PPC970_LSU_COMPLETION_STALL, },
240 {PMC_EV_PPC970_FXU_COMPLETION_STALL, },
241 {PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL, },
242 {PMC_EV_PPC970_FPU_COMPLETION_STALL, },
243 {PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL, },
244 {PMC_EV_PPC970_REJECT_COMPLETION_STALL, },
245 {PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL, },
246 {PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS, },
247 {PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS, },
248 {PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT, },
249 #endif
250 };
251 static size_t ppc970_event_codes_size = nitems(ppc970_event_codes);
252
253 static void
ppc970_set_pmc(int cpu,int ri,int config)254 ppc970_set_pmc(int cpu, int ri, int config)
255 {
256 register_t pmc_mmcr;
257 int config_mask;
258
259 if (config == PMCN_NONE)
260 config = PMC970N_NONE;
261
262 /*
263 * The mask is inverted (enable is 1) compared to the flags in MMCR0,
264 * which are Freeze flags.
265 */
266 config_mask = ~config & POWERPC_PMC_ENABLE;
267 config &= ~POWERPC_PMC_ENABLE;
268
269 /*
270 * Disable the PMCs.
271 */
272 switch (ri) {
273 case 0:
274 case 1:
275 pmc_mmcr = mfspr(SPR_MMCR0);
276 pmc_mmcr = PPC970_SET_MMCR0_PMCSEL(pmc_mmcr, config, ri);
277 mtspr(SPR_MMCR0, pmc_mmcr);
278 break;
279 case 2:
280 case 3:
281 case 4:
282 case 5:
283 case 6:
284 case 7:
285 pmc_mmcr = mfspr(SPR_MMCR1);
286 pmc_mmcr = PPC970_SET_MMCR1_PMCSEL(pmc_mmcr, config, ri);
287 mtspr(SPR_MMCR1, pmc_mmcr);
288 break;
289 }
290
291 if (config != PMC970N_NONE) {
292 pmc_mmcr = mfspr(SPR_MMCR0);
293 pmc_mmcr &= ~SPR_MMCR0_FC;
294 pmc_mmcr |= config_mask;
295 mtspr(SPR_MMCR0, pmc_mmcr);
296 }
297 }
298
299 static int
ppc970_pcpu_init(struct pmc_mdep * md,int cpu)300 ppc970_pcpu_init(struct pmc_mdep *md, int cpu)
301 {
302 powerpc_pcpu_init(md, cpu);
303
304 /* Clear the MMCRs, and set FC, to disable all PMCs. */
305 /* 970 PMC is not counted when set to 0x08 */
306 mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE |
307 SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE |
308 SPR_MMCR0_PMC1SEL(0x8) | SPR_MMCR0_PMC2SEL(0x8));
309 mtspr(SPR_MMCR1, 0x4218420);
310
311 return (0);
312 }
313
314 static int
ppc970_pcpu_fini(struct pmc_mdep * md,int cpu)315 ppc970_pcpu_fini(struct pmc_mdep *md, int cpu)
316 {
317 register_t mmcr0;
318
319 /* Freeze counters, disable interrupts */
320 mmcr0 = mfspr(SPR_MMCR0);
321 mmcr0 &= ~SPR_MMCR0_PMXE;
322 mmcr0 |= SPR_MMCR0_FC;
323 mtspr(SPR_MMCR0, mmcr0);
324
325 return (powerpc_pcpu_fini(md, cpu));
326 }
327
328 static void
ppc970_resume_pmc(bool ie)329 ppc970_resume_pmc(bool ie)
330 {
331 register_t mmcr0;
332
333 /* Unfreeze counters and re-enable PERF exceptions if requested. */
334 mmcr0 = mfspr(SPR_MMCR0);
335 mmcr0 &= ~(SPR_MMCR0_FC | SPR_MMCR0_PMXE);
336 if (ie)
337 mmcr0 |= SPR_MMCR0_PMXE;
338 mtspr(SPR_MMCR0, mmcr0);
339 }
340
341 int
pmc_ppc970_initialize(struct pmc_mdep * pmc_mdep)342 pmc_ppc970_initialize(struct pmc_mdep *pmc_mdep)
343 {
344 struct pmc_classdep *pcd;
345
346 pmc_mdep->pmd_cputype = PMC_CPU_PPC_970;
347
348 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
349 pcd->pcd_caps = POWERPC_PMC_CAPS;
350 pcd->pcd_class = PMC_CLASS_PPC970;
351 pcd->pcd_num = PPC970_MAX_PMCS;
352 pcd->pcd_ri = pmc_mdep->pmd_npmc;
353 pcd->pcd_width = 32;
354
355 pcd->pcd_allocate_pmc = powerpc_allocate_pmc;
356 pcd->pcd_config_pmc = powerpc_config_pmc;
357 pcd->pcd_pcpu_fini = ppc970_pcpu_fini;
358 pcd->pcd_pcpu_init = ppc970_pcpu_init;
359 pcd->pcd_describe = powerpc_describe;
360 pcd->pcd_get_config = powerpc_get_config;
361 pcd->pcd_read_pmc = powerpc_read_pmc;
362 pcd->pcd_release_pmc = powerpc_release_pmc;
363 pcd->pcd_start_pmc = powerpc_start_pmc;
364 pcd->pcd_stop_pmc = powerpc_stop_pmc;
365 pcd->pcd_write_pmc = powerpc_write_pmc;
366
367 pmc_mdep->pmd_npmc += PPC970_MAX_PMCS;
368 pmc_mdep->pmd_intr = powerpc_pmc_intr;
369
370 ppc_event_codes = ppc970_event_codes;
371 ppc_event_codes_size = ppc970_event_codes_size;
372 ppc_event_first = PMC_EV_PPC970_FIRST;
373 ppc_event_last = PMC_EV_PPC970_LAST;
374 ppc_max_pmcs = PPC970_MAX_PMCS;
375 ppc_class = pcd->pcd_class;
376
377 powerpc_set_pmc = ppc970_set_pmc;
378 powerpc_pmcn_read = powerpc_pmcn_read_default;
379 powerpc_pmcn_write = powerpc_pmcn_write_default;
380 powerpc_resume_pmc = ppc970_resume_pmc;
381
382 return (0);
383 }
384