1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2024, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "ice_common.h"
33
34 #define GL_MNG_DEF_DEVID 0x000B611C
35
36 /**
37 * ice_aq_read_nvm
38 * @hw: pointer to the HW struct
39 * @module_typeid: module pointer location in words from the NVM beginning
40 * @offset: byte offset from the module beginning
41 * @length: length of the section to be read (in bytes from the offset)
42 * @data: command buffer (size [bytes] = length)
43 * @last_command: tells if this is the last command in a series
44 * @read_shadow_ram: tell if this is a shadow RAM read
45 * @cd: pointer to command details structure or NULL
46 *
47 * Read the NVM using the admin queue commands (0x0701)
48 */
49 enum ice_status
ice_aq_read_nvm(struct ice_hw * hw,u16 module_typeid,u32 offset,u16 length,void * data,bool last_command,bool read_shadow_ram,struct ice_sq_cd * cd)50 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
51 void *data, bool last_command, bool read_shadow_ram,
52 struct ice_sq_cd *cd)
53 {
54 struct ice_aq_desc desc;
55 struct ice_aqc_nvm *cmd;
56
57 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
58
59 cmd = &desc.params.nvm;
60
61 if (offset > ICE_AQC_NVM_MAX_OFFSET)
62 return ICE_ERR_PARAM;
63
64 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
65
66 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
67 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
68
69 /* If this is the last command in a series, set the proper flag. */
70 if (last_command)
71 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
72 cmd->module_typeid = CPU_TO_LE16(module_typeid);
73 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
74 cmd->offset_high = (offset >> 16) & 0xFF;
75 cmd->length = CPU_TO_LE16(length);
76
77 return ice_aq_send_cmd(hw, &desc, data, length, cd);
78 }
79
80 /**
81 * ice_read_flat_nvm - Read portion of NVM by flat offset
82 * @hw: pointer to the HW struct
83 * @offset: offset from beginning of NVM
84 * @length: (in) number of bytes to read; (out) number of bytes actually read
85 * @data: buffer to return data in (sized to fit the specified length)
86 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
87 *
88 * Reads a portion of the NVM, as a flat memory space. This function correctly
89 * breaks read requests across Shadow RAM sectors and ensures that no single
90 * read request exceeds the maximum 4KB read for a single AdminQ command.
91 *
92 * Returns a status code on failure. Note that the data pointer may be
93 * partially updated if some reads succeed before a failure.
94 */
95 enum ice_status
ice_read_flat_nvm(struct ice_hw * hw,u32 offset,u32 * length,u8 * data,bool read_shadow_ram)96 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
97 bool read_shadow_ram)
98 {
99 enum ice_status status;
100 u32 inlen = *length;
101 u32 bytes_read = 0;
102 bool last_cmd;
103
104 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
105
106 *length = 0;
107
108 /* Verify the length of the read if this is for the Shadow RAM */
109 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
110 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
111 return ICE_ERR_PARAM;
112 }
113
114 do {
115 u32 read_size, sector_offset;
116
117 /* ice_aq_read_nvm cannot read more than 4KB at a time.
118 * Additionally, a read from the Shadow RAM may not cross over
119 * a sector boundary. Conveniently, the sector size is also
120 * 4KB.
121 */
122 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
123 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
124 inlen - bytes_read);
125
126 last_cmd = !(bytes_read + read_size < inlen);
127
128 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
129 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
130 * size guarantees that it will fit within the 2 bytes.
131 */
132 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
133 offset, (u16)read_size,
134 data + bytes_read, last_cmd,
135 read_shadow_ram, NULL);
136 if (status)
137 break;
138
139 bytes_read += read_size;
140 offset += read_size;
141 } while (!last_cmd);
142
143 *length = bytes_read;
144 return status;
145 }
146
147 /**
148 * ice_aq_update_nvm
149 * @hw: pointer to the HW struct
150 * @module_typeid: module pointer location in words from the NVM beginning
151 * @offset: byte offset from the module beginning
152 * @length: length of the section to be written (in bytes from the offset)
153 * @data: command buffer (size [bytes] = length)
154 * @last_command: tells if this is the last command in a series
155 * @command_flags: command parameters
156 * @cd: pointer to command details structure or NULL
157 *
158 * Update the NVM using the admin queue commands (0x0703)
159 */
160 enum ice_status
ice_aq_update_nvm(struct ice_hw * hw,u16 module_typeid,u32 offset,u16 length,void * data,bool last_command,u8 command_flags,struct ice_sq_cd * cd)161 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
162 u16 length, void *data, bool last_command, u8 command_flags,
163 struct ice_sq_cd *cd)
164 {
165 struct ice_aq_desc desc;
166 struct ice_aqc_nvm *cmd;
167
168 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
169
170 cmd = &desc.params.nvm;
171
172 /* In offset the highest byte must be zeroed. */
173 if (offset & 0xFF000000)
174 return ICE_ERR_PARAM;
175
176 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
177
178 cmd->cmd_flags |= command_flags;
179
180 /* If this is the last command in a series, set the proper flag. */
181 if (last_command)
182 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
183 cmd->module_typeid = CPU_TO_LE16(module_typeid);
184 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
185 cmd->offset_high = (offset >> 16) & 0xFF;
186 cmd->length = CPU_TO_LE16(length);
187
188 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
189
190 return ice_aq_send_cmd(hw, &desc, data, length, cd);
191 }
192
193 /**
194 * ice_aq_erase_nvm
195 * @hw: pointer to the HW struct
196 * @module_typeid: module pointer location in words from the NVM beginning
197 * @cd: pointer to command details structure or NULL
198 *
199 * Erase the NVM sector using the admin queue commands (0x0702)
200 */
201 enum ice_status
ice_aq_erase_nvm(struct ice_hw * hw,u16 module_typeid,struct ice_sq_cd * cd)202 ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
203 {
204 struct ice_aq_desc desc;
205 struct ice_aqc_nvm *cmd;
206 enum ice_status status;
207 __le16 len;
208
209 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
210
211 /* read a length value from SR, so module_typeid is equal to 0 */
212 /* calculate offset where module size is placed from bytes to words */
213 /* set last command and read from SR values to true */
214 status = ice_aq_read_nvm(hw, 0, 2 * module_typeid + 2, 2, &len, true,
215 true, NULL);
216 if (status)
217 return status;
218
219 cmd = &desc.params.nvm;
220
221 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
222
223 cmd->module_typeid = CPU_TO_LE16(module_typeid);
224 cmd->length = len;
225 cmd->offset_low = 0;
226 cmd->offset_high = 0;
227
228 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
229 }
230
231 /**
232 * ice_aq_read_nvm_cfg - read an NVM config block
233 * @hw: pointer to the HW struct
234 * @cmd_flags: NVM access admin command bits
235 * @field_id: field or feature ID
236 * @data: buffer for result
237 * @buf_size: buffer size
238 * @elem_count: pointer to count of elements read by FW
239 * @cd: pointer to command details structure or NULL
240 *
241 * Reads single or multiple feature/field ID and data (0x0704)
242 */
243 enum ice_status
ice_aq_read_nvm_cfg(struct ice_hw * hw,u8 cmd_flags,u16 field_id,void * data,u16 buf_size,u16 * elem_count,struct ice_sq_cd * cd)244 ice_aq_read_nvm_cfg(struct ice_hw *hw, u8 cmd_flags, u16 field_id, void *data,
245 u16 buf_size, u16 *elem_count, struct ice_sq_cd *cd)
246 {
247 struct ice_aqc_nvm_cfg *cmd;
248 struct ice_aq_desc desc;
249 enum ice_status status;
250
251 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
252
253 cmd = &desc.params.nvm_cfg;
254
255 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_cfg_read);
256
257 cmd->cmd_flags = cmd_flags;
258 cmd->id = CPU_TO_LE16(field_id);
259
260 status = ice_aq_send_cmd(hw, &desc, data, buf_size, cd);
261 if (!status && elem_count)
262 *elem_count = LE16_TO_CPU(cmd->count);
263
264 return status;
265 }
266
267 /**
268 * ice_aq_write_nvm_cfg - write an NVM config block
269 * @hw: pointer to the HW struct
270 * @cmd_flags: NVM access admin command bits
271 * @data: buffer for result
272 * @buf_size: buffer size
273 * @elem_count: count of elements to be written
274 * @cd: pointer to command details structure or NULL
275 *
276 * Writes single or multiple feature/field ID and data (0x0705)
277 */
278 enum ice_status
ice_aq_write_nvm_cfg(struct ice_hw * hw,u8 cmd_flags,void * data,u16 buf_size,u16 elem_count,struct ice_sq_cd * cd)279 ice_aq_write_nvm_cfg(struct ice_hw *hw, u8 cmd_flags, void *data, u16 buf_size,
280 u16 elem_count, struct ice_sq_cd *cd)
281 {
282 struct ice_aqc_nvm_cfg *cmd;
283 struct ice_aq_desc desc;
284
285 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
286
287 cmd = &desc.params.nvm_cfg;
288
289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_cfg_write);
290 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
291
292 cmd->count = CPU_TO_LE16(elem_count);
293 cmd->cmd_flags = cmd_flags;
294
295 return ice_aq_send_cmd(hw, &desc, data, buf_size, cd);
296 }
297
298 /**
299 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations
300 * @hw: pointer to the HW structure
301 * @offset: offset in words from module start
302 * @words: number of words to access
303 */
304 static enum ice_status
ice_check_sr_access_params(struct ice_hw * hw,u32 offset,u16 words)305 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
306 {
307 if ((offset + words) > hw->flash.sr_words) {
308 ice_debug(hw, ICE_DBG_NVM, "NVM error: offset beyond SR lmt.\n");
309 return ICE_ERR_PARAM;
310 }
311
312 if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
313 /* We can access only up to 4KB (one sector), in one AQ write */
314 ice_debug(hw, ICE_DBG_NVM, "NVM error: tried to access %d words, limit is %d.\n",
315 words, ICE_SR_SECTOR_SIZE_IN_WORDS);
316 return ICE_ERR_PARAM;
317 }
318
319 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
320 (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
321 /* A single access cannot spread over two sectors */
322 ice_debug(hw, ICE_DBG_NVM, "NVM error: cannot spread over two sectors.\n");
323 return ICE_ERR_PARAM;
324 }
325
326 return ICE_SUCCESS;
327 }
328
329 /**
330 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
331 * @hw: pointer to the HW structure
332 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
333 * @data: word read from the Shadow RAM
334 *
335 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
336 */
ice_read_sr_word_aq(struct ice_hw * hw,u16 offset,u16 * data)337 enum ice_status ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
338 {
339 u32 bytes = sizeof(u16);
340 enum ice_status status;
341 __le16 data_local;
342
343 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
344
345 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
346 * RAM size, and ensures we don't read across a Shadow RAM sector
347 * boundary
348 */
349 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
350 (_FORCE_ u8 *)&data_local, true);
351 if (status)
352 return status;
353
354 *data = LE16_TO_CPU(data_local);
355 return ICE_SUCCESS;
356 }
357
358 /**
359 * ice_write_sr_aq - Writes Shadow RAM
360 * @hw: pointer to the HW structure
361 * @offset: offset in words from module start
362 * @words: number of words to write
363 * @data: buffer with words to write to the Shadow RAM
364 * @last_command: tells the AdminQ that this is the last command
365 *
366 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
367 */
368 static enum ice_status
ice_write_sr_aq(struct ice_hw * hw,u32 offset,u16 words,__le16 * data,bool last_command)369 ice_write_sr_aq(struct ice_hw *hw, u32 offset, u16 words, __le16 *data,
370 bool last_command)
371 {
372 enum ice_status status;
373
374 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
375
376 status = ice_check_sr_access_params(hw, offset, words);
377 if (!status)
378 status = ice_aq_update_nvm(hw, 0, 2 * offset, 2 * words, data,
379 last_command, 0, NULL);
380
381 return status;
382 }
383
384 /**
385 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
386 * @hw: pointer to the HW structure
387 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
388 * @words: (in) number of words to read; (out) number of words actually read
389 * @data: words read from the Shadow RAM
390 *
391 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
392 * taken before reading the buffer and later released.
393 */
394 static enum ice_status
ice_read_sr_buf_aq(struct ice_hw * hw,u16 offset,u16 * words,u16 * data)395 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
396 {
397 u32 bytes = *words * 2, i;
398 enum ice_status status;
399
400 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
401
402 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
403 * sector restrictions necessary when reading from the NVM.
404 */
405 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
406
407 /* Report the number of words successfully read */
408 *words = (u16)(bytes / 2);
409
410 /* Byte swap the words up to the amount we actually read */
411 for (i = 0; i < *words; i++)
412 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
413
414 return status;
415 }
416
417 /**
418 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
419 * @hw: pointer to the HW structure
420 * @access: NVM access type (read or write)
421 *
422 * This function will request NVM ownership.
423 */
424 enum ice_status
ice_acquire_nvm(struct ice_hw * hw,enum ice_aq_res_access_type access)425 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
426 {
427 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
428 if (hw->flash.blank_nvm_mode)
429 return ICE_SUCCESS;
430
431 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
432 }
433
434 /**
435 * ice_release_nvm - Generic request for releasing the NVM ownership
436 * @hw: pointer to the HW structure
437 *
438 * This function will release NVM ownership.
439 */
ice_release_nvm(struct ice_hw * hw)440 void ice_release_nvm(struct ice_hw *hw)
441 {
442 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
443
444 if (hw->flash.blank_nvm_mode)
445 return;
446
447 ice_release_res(hw, ICE_NVM_RES_ID);
448 }
449
450 /**
451 * ice_get_flash_bank_offset - Get offset into requested flash bank
452 * @hw: pointer to the HW structure
453 * @bank: whether to read from the active or inactive flash bank
454 * @module: the module to read from
455 *
456 * Based on the module, lookup the module offset from the beginning of the
457 * flash.
458 *
459 * Returns the flash offset. Note that a value of zero is invalid and must be
460 * treated as an error.
461 */
ice_get_flash_bank_offset(struct ice_hw * hw,enum ice_bank_select bank,u16 module)462 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
463 {
464 struct ice_bank_info *banks = &hw->flash.banks;
465 enum ice_flash_bank active_bank;
466 bool second_bank_active;
467 u32 offset, size;
468
469 switch (module) {
470 case ICE_SR_1ST_NVM_BANK_PTR:
471 offset = banks->nvm_ptr;
472 size = banks->nvm_size;
473 active_bank = banks->nvm_bank;
474 break;
475 case ICE_SR_1ST_OROM_BANK_PTR:
476 offset = banks->orom_ptr;
477 size = banks->orom_size;
478 active_bank = banks->orom_bank;
479 break;
480 case ICE_SR_NETLIST_BANK_PTR:
481 offset = banks->netlist_ptr;
482 size = banks->netlist_size;
483 active_bank = banks->netlist_bank;
484 break;
485 default:
486 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
487 return 0;
488 }
489
490 switch (active_bank) {
491 case ICE_1ST_FLASH_BANK:
492 second_bank_active = false;
493 break;
494 case ICE_2ND_FLASH_BANK:
495 second_bank_active = true;
496 break;
497 default:
498 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
499 active_bank);
500 return 0;
501 }
502
503 /* The second flash bank is stored immediately following the first
504 * bank. Based on whether the 1st or 2nd bank is active, and whether
505 * we want the active or inactive bank, calculate the desired offset.
506 */
507 switch (bank) {
508 case ICE_ACTIVE_FLASH_BANK:
509 return offset + (second_bank_active ? size : 0);
510 case ICE_INACTIVE_FLASH_BANK:
511 return offset + (second_bank_active ? 0 : size);
512 }
513
514 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
515 return 0;
516 }
517
518 /**
519 * ice_read_flash_module - Read a word from one of the main NVM modules
520 * @hw: pointer to the HW structure
521 * @bank: which bank of the module to read
522 * @module: the module to read
523 * @offset: the offset into the module in bytes
524 * @data: storage for the word read from the flash
525 * @length: bytes of data to read
526 *
527 * Read data from the specified flash module. The bank parameter indicates
528 * whether or not to read from the active bank or the inactive bank of that
529 * module.
530 *
531 * The word will be read using flat NVM access, and relies on the
532 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
533 * during initialization.
534 */
535 static enum ice_status
ice_read_flash_module(struct ice_hw * hw,enum ice_bank_select bank,u16 module,u32 offset,u8 * data,u32 length)536 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
537 u32 offset, u8 *data, u32 length)
538 {
539 enum ice_status status;
540 u32 start;
541
542 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
543
544 start = ice_get_flash_bank_offset(hw, bank, module);
545 if (!start) {
546 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
547 module);
548 return ICE_ERR_PARAM;
549 }
550
551 status = ice_acquire_nvm(hw, ICE_RES_READ);
552 if (status)
553 return status;
554
555 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
556
557 ice_release_nvm(hw);
558
559 return status;
560 }
561
562 /**
563 * ice_read_nvm_module - Read from the active main NVM module
564 * @hw: pointer to the HW structure
565 * @bank: whether to read from active or inactive NVM module
566 * @offset: offset into the NVM module to read, in words
567 * @data: storage for returned word value
568 *
569 * Read the specified word from the active NVM module. This includes the CSS
570 * header at the start of the NVM module.
571 */
572 static enum ice_status
ice_read_nvm_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)573 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
574 {
575 enum ice_status status;
576 __le16 data_local;
577
578 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
579 (_FORCE_ u8 *)&data_local, sizeof(u16));
580 if (!status)
581 *data = LE16_TO_CPU(data_local);
582
583 return status;
584 }
585
586 /**
587 * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header
588 * @hw: pointer to the HW struct
589 * @bank: whether to read from the active or inactive flash bank
590 * @hdr_len: storage for header length in words
591 *
592 * Read the CSS header length from the NVM CSS header and add the Authentication
593 * header size, and then convert to words.
594 */
595 static enum ice_status
ice_get_nvm_css_hdr_len(struct ice_hw * hw,enum ice_bank_select bank,u32 * hdr_len)596 ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,
597 u32 *hdr_len)
598 {
599 u16 hdr_len_l, hdr_len_h;
600 enum ice_status status;
601 u32 hdr_len_dword;
602
603 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,
604 &hdr_len_l);
605 if (status)
606 return status;
607
608 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,
609 &hdr_len_h);
610 if (status)
611 return status;
612
613 /* CSS header length is in DWORD, so convert to words and add
614 * authentication header size
615 */
616 hdr_len_dword = hdr_len_h << 16 | hdr_len_l;
617 *hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN;
618
619 return ICE_SUCCESS;
620 }
621
622 /**
623 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
624 * @hw: pointer to the HW structure
625 * @bank: whether to read from the active or inactive NVM module
626 * @offset: offset into the Shadow RAM copy to read, in words
627 * @data: storage for returned word value
628 *
629 * Read the specified word from the copy of the Shadow RAM found in the
630 * specified NVM module.
631 */
632 static enum ice_status
ice_read_nvm_sr_copy(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)633 ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
634 {
635 enum ice_status status;
636 u32 hdr_len;
637
638 status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
639 if (status)
640 return status;
641
642 hdr_len = ROUND_UP(hdr_len, 32);
643
644 return ice_read_nvm_module(hw, bank, hdr_len + offset, data);
645 }
646
647 /**
648 * ice_read_orom_module - Read from the active Option ROM module
649 * @hw: pointer to the HW structure
650 * @bank: whether to read from active or inactive OROM module
651 * @offset: offset into the OROM module to read, in words
652 * @data: storage for returned word value
653 *
654 * Read the specified word from the active Option ROM module of the flash.
655 * Note that unlike the NVM module, the CSS data is stored at the end of the
656 * module instead of at the beginning.
657 */
658 static enum ice_status
ice_read_orom_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)659 ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
660 {
661 enum ice_status status;
662 __le16 data_local;
663
664 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset * sizeof(u16),
665 (_FORCE_ u8 *)&data_local, sizeof(u16));
666 if (!status)
667 *data = LE16_TO_CPU(data_local);
668
669 return status;
670 }
671
672 /**
673 * ice_read_netlist_module - Read data from the netlist module area
674 * @hw: pointer to the HW structure
675 * @bank: whether to read from the active or inactive module
676 * @offset: offset into the netlist to read from
677 * @data: storage for returned word value
678 *
679 * Read a word from the specified netlist bank.
680 */
681 static enum ice_status
ice_read_netlist_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)682 ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
683 {
684 enum ice_status status;
685 __le16 data_local;
686
687 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
688 (_FORCE_ u8 *)&data_local, sizeof(u16));
689 if (!status)
690 *data = LE16_TO_CPU(data_local);
691
692 return status;
693 }
694
695 /**
696 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
697 * @hw: pointer to the HW structure
698 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
699 * @data: word read from the Shadow RAM
700 *
701 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
702 */
ice_read_sr_word(struct ice_hw * hw,u16 offset,u16 * data)703 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
704 {
705 enum ice_status status;
706
707 status = ice_acquire_nvm(hw, ICE_RES_READ);
708 if (!status) {
709 status = ice_read_sr_word_aq(hw, offset, data);
710 ice_release_nvm(hw);
711 }
712
713 return status;
714 }
715
716 /**
717 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
718 * @hw: pointer to hardware structure
719 * @module_tlv: pointer to module TLV to return
720 * @module_tlv_len: pointer to module TLV length to return
721 * @module_type: module type requested
722 *
723 * Finds the requested sub module TLV type from the Preserved Field
724 * Area (PFA) and returns the TLV pointer and length. The caller can
725 * use these to read the variable length TLV value.
726 */
727 enum ice_status
ice_get_pfa_module_tlv(struct ice_hw * hw,u16 * module_tlv,u16 * module_tlv_len,u16 module_type)728 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
729 u16 module_type)
730 {
731 enum ice_status status;
732 u16 pfa_len, pfa_ptr;
733 u16 next_tlv;
734
735 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
736 if (status != ICE_SUCCESS) {
737 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
738 return status;
739 }
740 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
741 if (status != ICE_SUCCESS) {
742 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
743 return status;
744 }
745 /* Starting with first TLV after PFA length, iterate through the list
746 * of TLVs to find the requested one.
747 */
748 next_tlv = pfa_ptr + 1;
749 while (next_tlv < pfa_ptr + pfa_len) {
750 u16 tlv_sub_module_type;
751 u16 tlv_len;
752
753 /* Read TLV type */
754 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
755 if (status != ICE_SUCCESS) {
756 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
757 break;
758 }
759 /* Read TLV length */
760 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
761 if (status != ICE_SUCCESS) {
762 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
763 break;
764 }
765 if (tlv_sub_module_type == module_type) {
766 if (tlv_len) {
767 *module_tlv = next_tlv;
768 *module_tlv_len = tlv_len;
769 return ICE_SUCCESS;
770 }
771 return ICE_ERR_INVAL_SIZE;
772 }
773 /* Check next TLV, i.e. current TLV pointer + length + 2 words
774 * (for current TLV's type and length)
775 */
776 next_tlv = next_tlv + tlv_len + 2;
777 }
778 /* Module does not exist */
779 return ICE_ERR_DOES_NOT_EXIST;
780 }
781
782 /**
783 * ice_read_pba_string - Reads part number string from NVM
784 * @hw: pointer to hardware structure
785 * @pba_num: stores the part number string from the NVM
786 * @pba_num_size: part number string buffer length
787 *
788 * Reads the part number string from the NVM.
789 */
790 enum ice_status
ice_read_pba_string(struct ice_hw * hw,u8 * pba_num,u32 pba_num_size)791 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
792 {
793 u16 pba_tlv, pba_tlv_len;
794 enum ice_status status;
795 u16 pba_word, pba_size;
796 u16 i;
797
798 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
799 ICE_SR_PBA_BLOCK_PTR);
800 if (status != ICE_SUCCESS) {
801 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
802 return status;
803 }
804
805 /* pba_size is the next word */
806 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
807 if (status != ICE_SUCCESS) {
808 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
809 return status;
810 }
811
812 if (pba_tlv_len < pba_size) {
813 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
814 return ICE_ERR_INVAL_SIZE;
815 }
816
817 /* Subtract one to get PBA word count (PBA Size word is included in
818 * total size)
819 */
820 pba_size--;
821 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
822 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
823 return ICE_ERR_PARAM;
824 }
825
826 for (i = 0; i < pba_size; i++) {
827 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
828 if (status != ICE_SUCCESS) {
829 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
830 return status;
831 }
832
833 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
834 pba_num[(i * 2) + 1] = pba_word & 0xFF;
835 }
836 pba_num[(pba_size * 2)] = '\0';
837
838 return status;
839 }
840
841 /**
842 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
843 * @hw: pointer to the HW struct
844 * @bank: whether to read from the active or inactive flash bank
845 * @srev: storage for security revision
846 *
847 * Read the security revision out of the CSS header of the active NVM module
848 * bank.
849 */
ice_get_nvm_srev(struct ice_hw * hw,enum ice_bank_select bank,u32 * srev)850 static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
851 {
852 enum ice_status status;
853 u16 srev_l, srev_h;
854
855 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l);
856 if (status)
857 return status;
858
859 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h);
860 if (status)
861 return status;
862
863 *srev = srev_h << 16 | srev_l;
864
865 return ICE_SUCCESS;
866 }
867
868 /**
869 * ice_get_nvm_ver_info - Read NVM version information
870 * @hw: pointer to the HW struct
871 * @bank: whether to read from the active or inactive flash bank
872 * @nvm: pointer to NVM info structure
873 *
874 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
875 * in the NVM info structure.
876 */
877 static enum ice_status
ice_get_nvm_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_nvm_info * nvm)878 ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
879 {
880 u16 eetrack_lo, eetrack_hi, ver;
881 enum ice_status status;
882
883 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
884 if (status) {
885 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
886 return status;
887 }
888
889 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
890 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
891
892 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
893 if (status) {
894 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
895 return status;
896 }
897 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
898 if (status) {
899 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
900 return status;
901 }
902
903 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
904
905 status = ice_get_nvm_srev(hw, bank, &nvm->srev);
906 if (status)
907 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
908
909 return ICE_SUCCESS;
910 }
911
912 /**
913 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
914 * @hw: pointer to the HW structure
915 * @nvm: storage for Option ROM version information
916 *
917 * Reads the NVM EETRACK ID, Map version, and security revision of the
918 * inactive NVM bank. Used to access version data for a pending update that
919 * has not yet been activated.
920 */
ice_get_inactive_nvm_ver(struct ice_hw * hw,struct ice_nvm_info * nvm)921 enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
922 {
923 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
924 }
925
926 /**
927 * ice_get_orom_srev - Read the security revision from the OROM CSS header
928 * @hw: pointer to the HW struct
929 * @bank: whether to read from active or inactive flash module
930 * @srev: storage for security revision
931 *
932 * Read the security revision out of the CSS header of the active OROM module
933 * bank.
934 */
ice_get_orom_srev(struct ice_hw * hw,enum ice_bank_select bank,u32 * srev)935 static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
936 {
937 u32 orom_size_word = hw->flash.banks.orom_size / 2;
938 enum ice_status status;
939 u16 srev_l, srev_h;
940 u32 css_start;
941 u32 hdr_len;
942
943 status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
944 if (status)
945 return status;
946
947 if (orom_size_word < hdr_len) {
948 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
949 hw->flash.banks.orom_size);
950 return ICE_ERR_CFG;
951 }
952
953 /* calculate how far into the Option ROM the CSS header starts. Note
954 * that ice_read_orom_module takes a word offset
955 */
956 css_start = orom_size_word - hdr_len;
957 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
958 if (status)
959 return status;
960
961 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
962 if (status)
963 return status;
964
965 *srev = srev_h << 16 | srev_l;
966
967 return ICE_SUCCESS;
968 }
969
970 /**
971 * ice_get_orom_civd_data - Get the combo version information from Option ROM
972 * @hw: pointer to the HW struct
973 * @bank: whether to read from the active or inactive flash module
974 * @civd: storage for the Option ROM CIVD data.
975 *
976 * Searches through the Option ROM flash contents to locate the CIVD data for
977 * the image.
978 */
979 static enum ice_status
ice_get_orom_civd_data(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_civd_info * civd)980 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
981 struct ice_orom_civd_info *civd)
982 {
983 u8 *orom_data;
984 enum ice_status status;
985 u32 offset;
986
987 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
988 * The first 4 bytes must contain the ASCII characters "$CIV".
989 * A simple modulo 256 sum of all of the bytes of the structure must
990 * equal 0.
991 *
992 * The exact location is unknown and varies between images but is
993 * usually somewhere in the middle of the bank. We need to scan the
994 * Option ROM bank to locate it.
995 *
996 * It's significantly faster to read the entire Option ROM up front
997 * using the maximum page size, than to read each possible location
998 * with a separate firmware command.
999 */
1000 orom_data = (u8 *)ice_calloc(hw, hw->flash.banks.orom_size, sizeof(u8));
1001 if (!orom_data)
1002 return ICE_ERR_NO_MEMORY;
1003
1004 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,
1005 orom_data, hw->flash.banks.orom_size);
1006 if (status) {
1007 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
1008 goto exit_error;
1009 }
1010
1011 /* Scan the memory buffer to locate the CIVD data section */
1012 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
1013 struct ice_orom_civd_info *tmp;
1014 u8 sum = 0, i;
1015
1016 tmp = (struct ice_orom_civd_info *)&orom_data[offset];
1017
1018 /* Skip forward until we find a matching signature */
1019 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
1020 continue;
1021
1022 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
1023 offset);
1024
1025 /* Verify that the simple checksum is zero */
1026 for (i = 0; i < sizeof(*tmp); i++)
1027 sum += ((u8 *)tmp)[i];
1028
1029 if (sum) {
1030 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
1031 sum);
1032 status = ICE_ERR_NVM;
1033 goto exit_error;
1034 }
1035
1036 *civd = *tmp;
1037 ice_free(hw, orom_data);
1038 return ICE_SUCCESS;
1039 }
1040
1041 status = ICE_ERR_NVM;
1042 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
1043
1044 exit_error:
1045 ice_free(hw, orom_data);
1046 return status;
1047 }
1048
1049 /**
1050 * ice_get_orom_ver_info - Read Option ROM version information
1051 * @hw: pointer to the HW struct
1052 * @bank: whether to read from the active or inactive flash module
1053 * @orom: pointer to Option ROM info structure
1054 *
1055 * Read Option ROM version and security revision from the Option ROM flash
1056 * section.
1057 */
1058 static enum ice_status
ice_get_orom_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_info * orom)1059 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
1060 {
1061 struct ice_orom_civd_info civd;
1062 enum ice_status status;
1063 u32 combo_ver;
1064
1065 status = ice_get_orom_civd_data(hw, bank, &civd);
1066 if (status) {
1067 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
1068 return status;
1069 }
1070
1071 combo_ver = LE32_TO_CPU(civd.combo_ver);
1072
1073 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
1074 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
1075 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
1076
1077 status = ice_get_orom_srev(hw, bank, &orom->srev);
1078 if (status) {
1079 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
1080 return status;
1081 }
1082
1083 return ICE_SUCCESS;
1084 }
1085
1086 /**
1087 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
1088 * @hw: pointer to the HW structure
1089 * @orom: storage for Option ROM version information
1090 *
1091 * Reads the Option ROM version and security revision data for the inactive
1092 * section of flash. Used to access version data for a pending update that has
1093 * not yet been activated.
1094 */
ice_get_inactive_orom_ver(struct ice_hw * hw,struct ice_orom_info * orom)1095 enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
1096 {
1097 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
1098 }
1099
1100 /**
1101 * ice_get_netlist_info
1102 * @hw: pointer to the HW struct
1103 * @bank: whether to read from the active or inactive flash bank
1104 * @netlist: pointer to netlist version info structure
1105 *
1106 * Get the netlist version information from the requested bank. Reads the Link
1107 * Topology section to find the Netlist ID block and extract the relevant
1108 * information into the netlist version structure.
1109 */
1110 static enum ice_status
ice_get_netlist_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_netlist_info * netlist)1111 ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
1112 struct ice_netlist_info *netlist)
1113 {
1114 u16 module_id, length, node_count, i;
1115 enum ice_status status;
1116 u16 *id_blk;
1117
1118 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
1119 if (status)
1120 return status;
1121
1122 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) {
1123 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
1124 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id);
1125 return ICE_ERR_NVM;
1126 }
1127
1128 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
1129 if (status)
1130 return status;
1131
1132 /* sanity check that we have at least enough words to store the netlist ID block */
1133 if (length < ICE_NETLIST_ID_BLK_SIZE) {
1134 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
1135 ICE_NETLIST_ID_BLK_SIZE, length);
1136 return ICE_ERR_NVM;
1137 }
1138
1139 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
1140 if (status)
1141 return status;
1142 node_count &= ICE_LINK_TOPO_NODE_COUNT_M;
1143
1144 id_blk = (u16 *)ice_calloc(hw, ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk));
1145 if (!id_blk)
1146 return ICE_ERR_NO_MEMORY;
1147
1148 /* Read out the entire Netlist ID Block at once. */
1149 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
1150 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16),
1151 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16));
1152 if (status)
1153 goto exit_error;
1154
1155 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++)
1156 id_blk[i] = LE16_TO_CPU(((_FORCE_ __le16 *)id_blk)[i]);
1157
1158 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
1159 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW];
1160 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
1161 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW];
1162 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
1163 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW];
1164 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
1165 id_blk[ICE_NETLIST_ID_BLK_REV_LOW];
1166 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
1167 /* Read the left most 4 bytes of SHA */
1168 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
1169 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)];
1170
1171 exit_error:
1172 ice_free(hw, id_blk);
1173
1174 return status;
1175 }
1176
1177 /**
1178 * ice_get_netlist_ver_info
1179 * @hw: pointer to the HW struct
1180 * @netlist: pointer to netlist version info structure
1181 *
1182 * Get the netlist version information
1183 */
ice_get_netlist_ver_info(struct ice_hw * hw,struct ice_netlist_info * netlist)1184 enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *netlist)
1185 {
1186 return ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, netlist);
1187 }
1188
1189 /**
1190 * ice_get_inactive_netlist_ver
1191 * @hw: pointer to the HW struct
1192 * @netlist: pointer to netlist version info structure
1193 *
1194 * Read the netlist version data from the inactive netlist bank. Used to
1195 * extract version data of a pending flash update in order to display the
1196 * version data.
1197 */
ice_get_inactive_netlist_ver(struct ice_hw * hw,struct ice_netlist_info * netlist)1198 enum ice_status ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
1199 {
1200 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
1201 }
1202
1203 /**
1204 * ice_discover_flash_size - Discover the available flash size
1205 * @hw: pointer to the HW struct
1206 *
1207 * The device flash could be up to 16MB in size. However, it is possible that
1208 * the actual size is smaller. Use bisection to determine the accessible size
1209 * of flash memory.
1210 */
ice_discover_flash_size(struct ice_hw * hw)1211 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
1212 {
1213 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
1214 enum ice_status status;
1215
1216 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1217
1218 status = ice_acquire_nvm(hw, ICE_RES_READ);
1219 if (status)
1220 return status;
1221
1222 while ((max_size - min_size) > 1) {
1223 u32 offset = (max_size + min_size) / 2;
1224 u32 len = 1;
1225 u8 data;
1226
1227 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
1228 if (status == ICE_ERR_AQ_ERROR &&
1229 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
1230 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
1231 __func__, offset);
1232 status = ICE_SUCCESS;
1233 max_size = offset;
1234 } else if (!status) {
1235 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
1236 __func__, offset);
1237 min_size = offset;
1238 } else {
1239 /* an unexpected error occurred */
1240 goto err_read_flat_nvm;
1241 }
1242 }
1243
1244 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
1245
1246 hw->flash.flash_size = max_size;
1247
1248 err_read_flat_nvm:
1249 ice_release_nvm(hw);
1250
1251 return status;
1252 }
1253
1254 /**
1255 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
1256 * @hw: pointer to the HW structure
1257 * @offset: the word offset of the Shadow RAM word to read
1258 * @pointer: pointer value read from Shadow RAM
1259 *
1260 * Read the given Shadow RAM word, and convert it to a pointer value specified
1261 * in bytes. This function assumes the specified offset is a valid pointer
1262 * word.
1263 *
1264 * Each pointer word specifies whether it is stored in word size or 4KB
1265 * sector size by using the highest bit. The reported pointer value will be in
1266 * bytes, intended for flat NVM reads.
1267 */
1268 static enum ice_status
ice_read_sr_pointer(struct ice_hw * hw,u16 offset,u32 * pointer)1269 ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
1270 {
1271 enum ice_status status;
1272 u16 value;
1273
1274 status = ice_read_sr_word(hw, offset, &value);
1275 if (status)
1276 return status;
1277
1278 /* Determine if the pointer is in 4KB or word units */
1279 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
1280 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
1281 else
1282 *pointer = value * 2;
1283
1284 return ICE_SUCCESS;
1285 }
1286
1287 /**
1288 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
1289 * @hw: pointer to the HW structure
1290 * @offset: the word offset of the Shadow RAM to read
1291 * @size: size value read from the Shadow RAM
1292 *
1293 * Read the given Shadow RAM word, and convert it to an area size value
1294 * specified in bytes. This function assumes the specified offset is a valid
1295 * area size word.
1296 *
1297 * Each area size word is specified in 4KB sector units. This function reports
1298 * the size in bytes, intended for flat NVM reads.
1299 */
1300 static enum ice_status
ice_read_sr_area_size(struct ice_hw * hw,u16 offset,u32 * size)1301 ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
1302 {
1303 enum ice_status status;
1304 u16 value;
1305
1306 status = ice_read_sr_word(hw, offset, &value);
1307 if (status)
1308 return status;
1309
1310 /* Area sizes are always specified in 4KB units */
1311 *size = value * 4 * 1024;
1312
1313 return ICE_SUCCESS;
1314 }
1315
1316 /**
1317 * ice_determine_active_flash_banks - Discover active bank for each module
1318 * @hw: pointer to the HW struct
1319 *
1320 * Read the Shadow RAM control word and determine which banks are active for
1321 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
1322 * pointer and size. These values are then cached into the ice_flash_info
1323 * structure for later use in order to calculate the correct offset to read
1324 * from the active module.
1325 */
1326 static enum ice_status
ice_determine_active_flash_banks(struct ice_hw * hw)1327 ice_determine_active_flash_banks(struct ice_hw *hw)
1328 {
1329 struct ice_bank_info *banks = &hw->flash.banks;
1330 enum ice_status status;
1331 u16 ctrl_word;
1332
1333 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
1334 if (status) {
1335 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
1336 return status;
1337 }
1338
1339 /* Check that the control word indicates validity */
1340 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
1341 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
1342 return ICE_ERR_CFG;
1343 }
1344
1345 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
1346 banks->nvm_bank = ICE_1ST_FLASH_BANK;
1347 else
1348 banks->nvm_bank = ICE_2ND_FLASH_BANK;
1349
1350 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
1351 banks->orom_bank = ICE_1ST_FLASH_BANK;
1352 else
1353 banks->orom_bank = ICE_2ND_FLASH_BANK;
1354
1355 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
1356 banks->netlist_bank = ICE_1ST_FLASH_BANK;
1357 else
1358 banks->netlist_bank = ICE_2ND_FLASH_BANK;
1359
1360 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
1361 if (status) {
1362 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
1363 return status;
1364 }
1365
1366 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
1367 if (status) {
1368 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
1369 return status;
1370 }
1371
1372 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
1373 if (status) {
1374 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
1375 return status;
1376 }
1377
1378 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
1379 if (status) {
1380 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
1381 return status;
1382 }
1383
1384 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
1385 if (status) {
1386 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1387 return status;
1388 }
1389
1390 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1391 if (status) {
1392 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1393 return status;
1394 }
1395
1396 return ICE_SUCCESS;
1397 }
1398
1399 /**
1400 * ice_init_nvm - initializes NVM setting
1401 * @hw: pointer to the HW struct
1402 *
1403 * This function reads and populates NVM settings such as Shadow RAM size,
1404 * max_timeout, and blank_nvm_mode
1405 */
ice_init_nvm(struct ice_hw * hw)1406 enum ice_status ice_init_nvm(struct ice_hw *hw)
1407 {
1408 struct ice_flash_info *flash = &hw->flash;
1409 enum ice_status status;
1410 u32 fla, gens_stat;
1411 u8 sr_size;
1412
1413 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1414
1415 /* The SR size is stored regardless of the NVM programming mode
1416 * as the blank mode may be used in the factory line.
1417 */
1418 gens_stat = rd32(hw, GLNVM_GENS);
1419 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
1420
1421 /* Switching to words (sr_size contains power of 2) */
1422 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1423
1424 /* Check if we are in the normal or blank NVM programming mode */
1425 fla = rd32(hw, GLNVM_FLA);
1426 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
1427 flash->blank_nvm_mode = false;
1428 } else {
1429 /* Blank programming mode */
1430 flash->blank_nvm_mode = true;
1431 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1432 return ICE_ERR_NVM_BLANK_MODE;
1433 }
1434
1435 status = ice_discover_flash_size(hw);
1436 if (status) {
1437 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1438 return status;
1439 }
1440
1441 status = ice_determine_active_flash_banks(hw);
1442 if (status) {
1443 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1444 return status;
1445 }
1446
1447 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1448 if (status) {
1449 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1450 return status;
1451 }
1452
1453 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1454 if (status)
1455 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1456
1457 /* read the netlist version information */
1458 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1459 if (status)
1460 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1461
1462 return ICE_SUCCESS;
1463 }
1464
1465 /**
1466 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
1467 * @hw: pointer to the HW structure
1468 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
1469 * @words: (in) number of words to read; (out) number of words actually read
1470 * @data: words read from the Shadow RAM
1471 *
1472 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
1473 * method. The buf read is preceded by the NVM ownership take
1474 * and followed by the release.
1475 */
1476 enum ice_status
ice_read_sr_buf(struct ice_hw * hw,u16 offset,u16 * words,u16 * data)1477 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
1478 {
1479 enum ice_status status;
1480
1481 status = ice_acquire_nvm(hw, ICE_RES_READ);
1482 if (!status) {
1483 status = ice_read_sr_buf_aq(hw, offset, words, data);
1484 ice_release_nvm(hw);
1485 }
1486
1487 return status;
1488 }
1489
1490 /**
1491 * __ice_write_sr_word - Writes Shadow RAM word
1492 * @hw: pointer to the HW structure
1493 * @offset: offset of the Shadow RAM word to write
1494 * @data: word to write to the Shadow RAM
1495 *
1496 * Writes a 16 bit word to the SR using the ice_write_sr_aq method.
1497 * NVM ownership have to be acquired and released (on ARQ completion event
1498 * reception) by caller. To commit SR to NVM update checksum function
1499 * should be called.
1500 */
1501 enum ice_status
__ice_write_sr_word(struct ice_hw * hw,u32 offset,const u16 * data)1502 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data)
1503 {
1504 __le16 data_local = CPU_TO_LE16(*data);
1505
1506 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1507
1508 /* Value 0x00 below means that we treat SR as a flat mem */
1509 return ice_write_sr_aq(hw, offset, 1, &data_local, false);
1510 }
1511
1512 /**
1513 * __ice_write_sr_buf - Writes Shadow RAM buf
1514 * @hw: pointer to the HW structure
1515 * @offset: offset of the Shadow RAM buffer to write
1516 * @words: number of words to write
1517 * @data: words to write to the Shadow RAM
1518 *
1519 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
1520 * NVM ownership must be acquired before calling this function and released
1521 * on ARQ completion event reception by caller. To commit SR to NVM update
1522 * checksum function should be called.
1523 */
1524 enum ice_status
__ice_write_sr_buf(struct ice_hw * hw,u32 offset,u16 words,const u16 * data)1525 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data)
1526 {
1527 enum ice_status status;
1528 __le16 *data_local;
1529 void *vmem;
1530 u32 i;
1531
1532 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1533
1534 vmem = ice_calloc(hw, words, sizeof(u16));
1535 if (!vmem)
1536 return ICE_ERR_NO_MEMORY;
1537 data_local = (_FORCE_ __le16 *)vmem;
1538
1539 for (i = 0; i < words; i++)
1540 data_local[i] = CPU_TO_LE16(data[i]);
1541
1542 /* Here we will only write one buffer as the size of the modules
1543 * mirrored in the Shadow RAM is always less than 4K.
1544 */
1545 status = ice_write_sr_aq(hw, offset, words, data_local, false);
1546
1547 ice_free(hw, vmem);
1548
1549 return status;
1550 }
1551
1552 /**
1553 * ice_calc_sr_checksum - Calculates and returns Shadow RAM SW checksum
1554 * @hw: pointer to hardware structure
1555 * @checksum: pointer to the checksum
1556 *
1557 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
1558 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
1559 * is customer specific and unknown. Therefore, this function skips all maximum
1560 * possible size of VPD (1kB).
1561 */
ice_calc_sr_checksum(struct ice_hw * hw,u16 * checksum)1562 static enum ice_status ice_calc_sr_checksum(struct ice_hw *hw, u16 *checksum)
1563 {
1564 enum ice_status status = ICE_SUCCESS;
1565 u16 pcie_alt_module = 0;
1566 u16 checksum_local = 0;
1567 u16 vpd_module;
1568 void *vmem;
1569 u16 *data;
1570 u16 i;
1571
1572 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1573
1574 vmem = ice_calloc(hw, ICE_SR_SECTOR_SIZE_IN_WORDS, sizeof(u16));
1575 if (!vmem)
1576 return ICE_ERR_NO_MEMORY;
1577 data = (u16 *)vmem;
1578
1579 /* read pointer to VPD area */
1580 status = ice_read_sr_word_aq(hw, ICE_SR_VPD_PTR, &vpd_module);
1581 if (status)
1582 goto ice_calc_sr_checksum_exit;
1583
1584 /* read pointer to PCIe Alt Auto-load module */
1585 status = ice_read_sr_word_aq(hw, ICE_SR_PCIE_ALT_AUTO_LOAD_PTR,
1586 &pcie_alt_module);
1587 if (status)
1588 goto ice_calc_sr_checksum_exit;
1589
1590 /* Calculate SW checksum that covers the whole 64kB shadow RAM
1591 * except the VPD and PCIe ALT Auto-load modules
1592 */
1593 for (i = 0; i < hw->flash.sr_words; i++) {
1594 /* Read SR page */
1595 if ((i % ICE_SR_SECTOR_SIZE_IN_WORDS) == 0) {
1596 u16 words = ICE_SR_SECTOR_SIZE_IN_WORDS;
1597
1598 status = ice_read_sr_buf_aq(hw, i, &words, data);
1599 if (status != ICE_SUCCESS)
1600 goto ice_calc_sr_checksum_exit;
1601 }
1602
1603 /* Skip Checksum word */
1604 if (i == ICE_SR_SW_CHECKSUM_WORD)
1605 continue;
1606 /* Skip VPD module (convert byte size to word count) */
1607 if (i >= (u32)vpd_module &&
1608 i < ((u32)vpd_module + ICE_SR_VPD_SIZE_WORDS))
1609 continue;
1610 /* Skip PCIe ALT module (convert byte size to word count) */
1611 if (i >= (u32)pcie_alt_module &&
1612 i < ((u32)pcie_alt_module + ICE_SR_PCIE_ALT_SIZE_WORDS))
1613 continue;
1614
1615 checksum_local += data[i % ICE_SR_SECTOR_SIZE_IN_WORDS];
1616 }
1617
1618 *checksum = (u16)ICE_SR_SW_CHECKSUM_BASE - checksum_local;
1619
1620 ice_calc_sr_checksum_exit:
1621 ice_free(hw, vmem);
1622 return status;
1623 }
1624
1625 /**
1626 * ice_update_sr_checksum - Updates the Shadow RAM SW checksum
1627 * @hw: pointer to hardware structure
1628 *
1629 * NVM ownership must be acquired before calling this function and released
1630 * on ARQ completion event reception by caller.
1631 * This function will commit SR to NVM.
1632 */
ice_update_sr_checksum(struct ice_hw * hw)1633 enum ice_status ice_update_sr_checksum(struct ice_hw *hw)
1634 {
1635 enum ice_status status;
1636 __le16 le_sum;
1637 u16 checksum;
1638
1639 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1640
1641 status = ice_calc_sr_checksum(hw, &checksum);
1642 if (!status) {
1643 le_sum = CPU_TO_LE16(checksum);
1644 status = ice_write_sr_aq(hw, ICE_SR_SW_CHECKSUM_WORD, 1,
1645 &le_sum, true);
1646 }
1647 return status;
1648 }
1649
1650 /**
1651 * ice_validate_sr_checksum - Validate Shadow RAM SW checksum
1652 * @hw: pointer to hardware structure
1653 * @checksum: calculated checksum
1654 *
1655 * Performs checksum calculation and validates the Shadow RAM SW checksum.
1656 * If the caller does not need checksum, the value can be NULL.
1657 */
ice_validate_sr_checksum(struct ice_hw * hw,u16 * checksum)1658 enum ice_status ice_validate_sr_checksum(struct ice_hw *hw, u16 *checksum)
1659 {
1660 enum ice_status status;
1661 u16 checksum_local;
1662 u16 checksum_sr;
1663
1664 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1665
1666 status = ice_acquire_nvm(hw, ICE_RES_READ);
1667 if (!status) {
1668 status = ice_calc_sr_checksum(hw, &checksum_local);
1669 ice_release_nvm(hw);
1670 if (status)
1671 return status;
1672 } else {
1673 return status;
1674 }
1675
1676 ice_read_sr_word(hw, ICE_SR_SW_CHECKSUM_WORD, &checksum_sr);
1677
1678 /* Verify read checksum from EEPROM is the same as
1679 * calculated checksum
1680 */
1681 if (checksum_local != checksum_sr)
1682 status = ICE_ERR_NVM_CHECKSUM;
1683
1684 /* If the user cares, return the calculated checksum */
1685 if (checksum)
1686 *checksum = checksum_local;
1687
1688 return status;
1689 }
1690
1691 /**
1692 * ice_nvm_validate_checksum
1693 * @hw: pointer to the HW struct
1694 *
1695 * Verify NVM PFA checksum validity (0x0706)
1696 */
ice_nvm_validate_checksum(struct ice_hw * hw)1697 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
1698 {
1699 struct ice_aqc_nvm_checksum *cmd;
1700 struct ice_aq_desc desc;
1701 enum ice_status status;
1702
1703 status = ice_acquire_nvm(hw, ICE_RES_READ);
1704 if (status)
1705 return status;
1706
1707 cmd = &desc.params.nvm_checksum;
1708
1709 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1710 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1711
1712 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1713 ice_release_nvm(hw);
1714
1715 if (!status)
1716 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1717 status = ICE_ERR_NVM_CHECKSUM;
1718
1719 return status;
1720 }
1721
1722 /**
1723 * ice_nvm_recalculate_checksum
1724 * @hw: pointer to the HW struct
1725 *
1726 * Recalculate NVM PFA checksum (0x0706)
1727 */
ice_nvm_recalculate_checksum(struct ice_hw * hw)1728 enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw)
1729 {
1730 struct ice_aqc_nvm_checksum *cmd;
1731 struct ice_aq_desc desc;
1732 enum ice_status status;
1733
1734 status = ice_acquire_nvm(hw, ICE_RES_READ);
1735 if (status)
1736 return status;
1737
1738 cmd = &desc.params.nvm_checksum;
1739
1740 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1741 cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC;
1742
1743 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1744
1745 ice_release_nvm(hw);
1746
1747 return status;
1748 }
1749
1750 /**
1751 * ice_nvm_write_activate
1752 * @hw: pointer to the HW struct
1753 * @cmd_flags: flags for write activate command
1754 * @response_flags: response indicators from firmware
1755 *
1756 * Update the control word with the required banks' validity bits
1757 * and dumps the Shadow RAM to flash (0x0707)
1758 *
1759 * cmd_flags controls which banks to activate, the preservation level to use
1760 * when activating the NVM bank, and whether an EMP reset is required for
1761 * activation.
1762 *
1763 * Note that the 16bit cmd_flags value is split between two separate 1 byte
1764 * flag values in the descriptor.
1765 *
1766 * On successful return of the firmware command, the response_flags variable
1767 * is updated with the flags reported by firmware indicating certain status,
1768 * such as whether EMP reset is enabled.
1769 */
1770 enum ice_status
ice_nvm_write_activate(struct ice_hw * hw,u16 cmd_flags,u8 * response_flags)1771 ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
1772 {
1773 struct ice_aqc_nvm *cmd;
1774 struct ice_aq_desc desc;
1775 enum ice_status err;
1776
1777 cmd = &desc.params.nvm;
1778 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
1779
1780 cmd->cmd_flags = (u8)(cmd_flags & 0xFF);
1781 cmd->offset_high = (u8)((cmd_flags >> 8) & 0xFF);
1782
1783 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1784 if (!err && response_flags)
1785 *response_flags = cmd->cmd_flags;
1786
1787 return err;
1788 }
1789
1790 /**
1791 * ice_get_nvm_minsrevs - Get the Minimum Security Revision values from flash
1792 * @hw: pointer to the HW struct
1793 * @minsrevs: structure to store NVM and OROM minsrev values
1794 *
1795 * Read the Minimum Security Revision TLV and extract the revision values from
1796 * the flash image into a readable structure for processing.
1797 */
1798 enum ice_status
ice_get_nvm_minsrevs(struct ice_hw * hw,struct ice_minsrev_info * minsrevs)1799 ice_get_nvm_minsrevs(struct ice_hw *hw, struct ice_minsrev_info *minsrevs)
1800 {
1801 struct ice_aqc_nvm_minsrev data;
1802 enum ice_status status;
1803 u16 valid;
1804
1805 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1806
1807 status = ice_acquire_nvm(hw, ICE_RES_READ);
1808 if (status)
1809 return status;
1810
1811 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_MINSREV_MOD_ID, 0, sizeof(data),
1812 &data, true, false, NULL);
1813
1814 ice_release_nvm(hw);
1815
1816 if (status)
1817 return status;
1818
1819 valid = LE16_TO_CPU(data.validity);
1820
1821 /* Extract NVM minimum security revision */
1822 if (valid & ICE_AQC_NVM_MINSREV_NVM_VALID) {
1823 u16 minsrev_l, minsrev_h;
1824
1825 minsrev_l = LE16_TO_CPU(data.nvm_minsrev_l);
1826 minsrev_h = LE16_TO_CPU(data.nvm_minsrev_h);
1827
1828 minsrevs->nvm = minsrev_h << 16 | minsrev_l;
1829 minsrevs->nvm_valid = true;
1830 }
1831
1832 /* Extract the OROM minimum security revision */
1833 if (valid & ICE_AQC_NVM_MINSREV_OROM_VALID) {
1834 u16 minsrev_l, minsrev_h;
1835
1836 minsrev_l = LE16_TO_CPU(data.orom_minsrev_l);
1837 minsrev_h = LE16_TO_CPU(data.orom_minsrev_h);
1838
1839 minsrevs->orom = minsrev_h << 16 | minsrev_l;
1840 minsrevs->orom_valid = true;
1841 }
1842
1843 return ICE_SUCCESS;
1844 }
1845
1846 /**
1847 * ice_update_nvm_minsrevs - Update minimum security revision TLV data in flash
1848 * @hw: pointer to the HW struct
1849 * @minsrevs: minimum security revision information
1850 *
1851 * Update the NVM or Option ROM minimum security revision fields in the PFA
1852 * area of the flash. Reads the minsrevs->nvm_valid and minsrevs->orom_valid
1853 * fields to determine what update is being requested. If the valid bit is not
1854 * set for that module, then the associated minsrev will be left as is.
1855 */
1856 enum ice_status
ice_update_nvm_minsrevs(struct ice_hw * hw,struct ice_minsrev_info * minsrevs)1857 ice_update_nvm_minsrevs(struct ice_hw *hw, struct ice_minsrev_info *minsrevs)
1858 {
1859 struct ice_aqc_nvm_minsrev data;
1860 enum ice_status status;
1861
1862 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1863
1864 if (!minsrevs->nvm_valid && !minsrevs->orom_valid) {
1865 ice_debug(hw, ICE_DBG_NVM, "At least one of NVM and OROM MinSrev must be valid");
1866 return ICE_ERR_PARAM;
1867 }
1868
1869 status = ice_acquire_nvm(hw, ICE_RES_WRITE);
1870 if (status)
1871 return status;
1872
1873 /* Get current data */
1874 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_MINSREV_MOD_ID, 0, sizeof(data),
1875 &data, true, false, NULL);
1876 if (status)
1877 goto exit_release_res;
1878
1879 if (minsrevs->nvm_valid) {
1880 data.nvm_minsrev_l = CPU_TO_LE16(minsrevs->nvm & 0xFFFF);
1881 data.nvm_minsrev_h = CPU_TO_LE16(minsrevs->nvm >> 16);
1882 data.validity |= CPU_TO_LE16(ICE_AQC_NVM_MINSREV_NVM_VALID);
1883 }
1884
1885 if (minsrevs->orom_valid) {
1886 data.orom_minsrev_l = CPU_TO_LE16(minsrevs->orom & 0xFFFF);
1887 data.orom_minsrev_h = CPU_TO_LE16(minsrevs->orom >> 16);
1888 data.validity |= CPU_TO_LE16(ICE_AQC_NVM_MINSREV_OROM_VALID);
1889 }
1890
1891 /* Update flash data */
1892 status = ice_aq_update_nvm(hw, ICE_AQC_NVM_MINSREV_MOD_ID, 0, sizeof(data), &data,
1893 false, ICE_AQC_NVM_SPECIAL_UPDATE, NULL);
1894 if (status)
1895 goto exit_release_res;
1896
1897 /* Dump the Shadow RAM to the flash */
1898 status = ice_nvm_write_activate(hw, 0, NULL);
1899
1900 exit_release_res:
1901 ice_release_nvm(hw);
1902
1903 return status;
1904 }
1905
1906 /**
1907 * ice_nvm_access_get_features - Return the NVM access features structure
1908 * @cmd: NVM access command to process
1909 * @data: storage for the driver NVM features
1910 *
1911 * Fill in the data section of the NVM access request with a copy of the NVM
1912 * features structure.
1913 */
1914 enum ice_status
ice_nvm_access_get_features(struct ice_nvm_access_cmd * cmd,union ice_nvm_access_data * data)1915 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
1916 union ice_nvm_access_data *data)
1917 {
1918 /* The provided data_size must be at least as large as our NVM
1919 * features structure. A larger size should not be treated as an
1920 * error, to allow future extensions to the features structure to
1921 * work on older drivers.
1922 */
1923 if (cmd->data_size < sizeof(struct ice_nvm_features))
1924 return ICE_ERR_NO_MEMORY;
1925
1926 /* Initialize the data buffer to zeros */
1927 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1928
1929 /* Fill in the features data */
1930 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
1931 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
1932 data->drv_features.size = sizeof(struct ice_nvm_features);
1933 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
1934
1935 return ICE_SUCCESS;
1936 }
1937
1938 /**
1939 * ice_nvm_access_get_module - Helper function to read module value
1940 * @cmd: NVM access command structure
1941 *
1942 * Reads the module value out of the NVM access config field.
1943 */
ice_nvm_access_get_module(struct ice_nvm_access_cmd * cmd)1944 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
1945 {
1946 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
1947 }
1948
1949 /**
1950 * ice_nvm_access_get_flags - Helper function to read flags value
1951 * @cmd: NVM access command structure
1952 *
1953 * Reads the flags value out of the NVM access config field.
1954 */
ice_nvm_access_get_flags(struct ice_nvm_access_cmd * cmd)1955 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
1956 {
1957 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
1958 }
1959
1960 /**
1961 * ice_nvm_access_get_adapter - Helper function to read adapter info
1962 * @cmd: NVM access command structure
1963 *
1964 * Read the adapter info value out of the NVM access config field.
1965 */
ice_nvm_access_get_adapter(struct ice_nvm_access_cmd * cmd)1966 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
1967 {
1968 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1969 ICE_NVM_CFG_ADAPTER_INFO_S);
1970 }
1971
1972 /**
1973 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1974 * @cmd: NVM access command structure
1975 *
1976 * Validates that an NVM access structure is request to read or write a valid
1977 * register offset. First validates that the module and flags are correct, and
1978 * then ensures that the register offset is one of the accepted registers.
1979 */
1980 static enum ice_status
ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd * cmd)1981 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
1982 {
1983 u32 module, flags, offset;
1984 u16 i;
1985
1986 module = ice_nvm_access_get_module(cmd);
1987 flags = ice_nvm_access_get_flags(cmd);
1988 offset = cmd->offset;
1989
1990 /* Make sure the module and flags indicate a read/write request */
1991 if (module != ICE_NVM_REG_RW_MODULE ||
1992 flags != ICE_NVM_REG_RW_FLAGS ||
1993 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
1994 return ICE_ERR_PARAM;
1995
1996 switch (offset) {
1997 case GL_HICR:
1998 case GL_HICR_EN: /* Note, this register is read only */
1999 case GL_FWSTS:
2000 case GL_MNG_FWSM:
2001 case GLGEN_CSR_DEBUG_C:
2002 case GLGEN_RSTAT:
2003 case GLPCI_LBARCTRL:
2004 case GL_MNG_DEF_DEVID:
2005 case GLNVM_GENS:
2006 case GLNVM_FLA:
2007 case PF_FUNC_RID:
2008 return ICE_SUCCESS;
2009 default:
2010 break;
2011 }
2012
2013 for (i = 0; i <= GL_HIDA_MAX_INDEX; i++)
2014 if (offset == (u32)GL_HIDA(i))
2015 return ICE_SUCCESS;
2016
2017 for (i = 0; i <= GL_HIBA_MAX_INDEX; i++)
2018 if (offset == (u32)GL_HIBA(i))
2019 return ICE_SUCCESS;
2020
2021 /* All other register offsets are not valid */
2022 return ICE_ERR_OUT_OF_RANGE;
2023 }
2024
2025 /**
2026 * ice_nvm_access_read - Handle an NVM read request
2027 * @hw: pointer to the HW struct
2028 * @cmd: NVM access command to process
2029 * @data: storage for the register value read
2030 *
2031 * Process an NVM access request to read a register.
2032 */
2033 enum ice_status
ice_nvm_access_read(struct ice_hw * hw,struct ice_nvm_access_cmd * cmd,union ice_nvm_access_data * data)2034 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
2035 union ice_nvm_access_data *data)
2036 {
2037 enum ice_status status;
2038
2039 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2040
2041 /* Always initialize the output data, even on failure */
2042 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
2043
2044 /* Make sure this is a valid read/write access request */
2045 status = ice_validate_nvm_rw_reg(cmd);
2046 if (status)
2047 return status;
2048
2049 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
2050 cmd->offset);
2051
2052 /* Read the register and store the contents in the data field */
2053 data->regval = rd32(hw, cmd->offset);
2054
2055 return ICE_SUCCESS;
2056 }
2057
2058 /**
2059 * ice_nvm_access_write - Handle an NVM write request
2060 * @hw: pointer to the HW struct
2061 * @cmd: NVM access command to process
2062 * @data: NVM access data to write
2063 *
2064 * Process an NVM access request to write a register.
2065 */
2066 enum ice_status
ice_nvm_access_write(struct ice_hw * hw,struct ice_nvm_access_cmd * cmd,union ice_nvm_access_data * data)2067 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
2068 union ice_nvm_access_data *data)
2069 {
2070 enum ice_status status;
2071
2072 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2073
2074 /* Make sure this is a valid read/write access request */
2075 status = ice_validate_nvm_rw_reg(cmd);
2076 if (status)
2077 return status;
2078
2079 /* Reject requests to write to read-only registers */
2080 switch (cmd->offset) {
2081 case GL_HICR_EN:
2082 case GLGEN_RSTAT:
2083 return ICE_ERR_OUT_OF_RANGE;
2084 default:
2085 break;
2086 }
2087
2088 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
2089 cmd->offset, data->regval);
2090
2091 /* Write the data field to the specified register */
2092 wr32(hw, cmd->offset, data->regval);
2093
2094 return ICE_SUCCESS;
2095 }
2096
2097 /**
2098 * ice_handle_nvm_access - Handle an NVM access request
2099 * @hw: pointer to the HW struct
2100 * @cmd: NVM access command info
2101 * @data: pointer to read or return data
2102 *
2103 * Process an NVM access request. Read the command structure information and
2104 * determine if it is valid. If not, report an error indicating the command
2105 * was invalid.
2106 *
2107 * For valid commands, perform the necessary function, copying the data into
2108 * the provided data buffer.
2109 */
2110 enum ice_status
ice_handle_nvm_access(struct ice_hw * hw,struct ice_nvm_access_cmd * cmd,union ice_nvm_access_data * data)2111 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
2112 union ice_nvm_access_data *data)
2113 {
2114 u32 module, flags, adapter_info;
2115
2116 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2117
2118 /* Extended flags are currently reserved and must be zero */
2119 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
2120 return ICE_ERR_PARAM;
2121
2122 /* Adapter info must match the HW device ID */
2123 adapter_info = ice_nvm_access_get_adapter(cmd);
2124 if (adapter_info != hw->device_id)
2125 return ICE_ERR_PARAM;
2126
2127 switch (cmd->command) {
2128 case ICE_NVM_CMD_READ:
2129 module = ice_nvm_access_get_module(cmd);
2130 flags = ice_nvm_access_get_flags(cmd);
2131
2132 /* Getting the driver's NVM features structure shares the same
2133 * command type as reading a register. Read the config field
2134 * to determine if this is a request to get features.
2135 */
2136 if (module == ICE_NVM_GET_FEATURES_MODULE &&
2137 flags == ICE_NVM_GET_FEATURES_FLAGS &&
2138 cmd->offset == 0)
2139 return ice_nvm_access_get_features(cmd, data);
2140 else
2141 return ice_nvm_access_read(hw, cmd, data);
2142 case ICE_NVM_CMD_WRITE:
2143 return ice_nvm_access_write(hw, cmd, data);
2144 default:
2145 return ICE_ERR_PARAM;
2146 }
2147 }
2148
2149