1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io>
5 * All rights reserved.
6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate)
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "if_igc.h"
32
33 #ifdef RSS
34 #include <net/rss_config.h>
35 #include <netinet/in_rss.h>
36 #endif
37
38 #ifdef VERBOSE_DEBUG
39 #define DPRINTF device_printf
40 #else
41 #define DPRINTF(...)
42 #endif
43
44 /*********************************************************************
45 * Local Function prototypes
46 *********************************************************************/
47 static int igc_isc_txd_encap(void *arg, if_pkt_info_t pi);
48 static void igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx);
49 static int igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear);
50
51 static void igc_isc_rxd_refill(void *arg, if_rxd_update_t iru);
52
53 static void igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused,
54 qidx_t pidx);
55 static int igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx,
56 qidx_t budget);
57
58 static int igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri);
59
60 static int igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi,
61 uint32_t *cmd_type_len, uint32_t *olinfo_status);
62 static int igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi,
63 uint32_t *cmd_type_len, uint32_t *olinfo_status);
64
65 static void igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype);
66 static int igc_determine_rsstype(uint16_t pkt_info);
67
68 extern void igc_if_enable_intr(if_ctx_t ctx);
69 extern int igc_intr(void *arg);
70
71 struct if_txrx igc_txrx = {
72 .ift_txd_encap = igc_isc_txd_encap,
73 .ift_txd_flush = igc_isc_txd_flush,
74 .ift_txd_credits_update = igc_isc_txd_credits_update,
75 .ift_rxd_available = igc_isc_rxd_available,
76 .ift_rxd_pkt_get = igc_isc_rxd_pkt_get,
77 .ift_rxd_refill = igc_isc_rxd_refill,
78 .ift_rxd_flush = igc_isc_rxd_flush,
79 .ift_legacy_intr = igc_intr
80 };
81
82 void
igc_dump_rs(struct igc_adapter * adapter)83 igc_dump_rs(struct igc_adapter *adapter)
84 {
85 if_softc_ctx_t scctx = adapter->shared;
86 struct igc_tx_queue *que;
87 struct tx_ring *txr;
88 qidx_t i, ntxd, qid, cur;
89 int16_t rs_cidx;
90 uint8_t status;
91
92 printf("\n");
93 ntxd = scctx->isc_ntxd[0];
94 for (qid = 0; qid < adapter->tx_num_queues; qid++) {
95 que = &adapter->tx_queues[qid];
96 txr = &que->txr;
97 rs_cidx = txr->tx_rs_cidx;
98 if (rs_cidx != txr->tx_rs_pidx) {
99 cur = txr->tx_rsq[rs_cidx];
100 status = txr->tx_base[cur].upper.fields.status;
101 if (!(status & IGC_TXD_STAT_DD))
102 printf("qid[%d]->tx_rsq[%d]: %d clear ", qid, rs_cidx, cur);
103 } else {
104 rs_cidx = (rs_cidx-1)&(ntxd-1);
105 cur = txr->tx_rsq[rs_cidx];
106 printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ", qid, rs_cidx, cur);
107 }
108 printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed, txr->tx_rs_pidx);
109 for (i = 0; i < ntxd; i++) {
110 if (txr->tx_base[i].upper.fields.status & IGC_TXD_STAT_DD)
111 printf("%d set ", i);
112 }
113 printf("\n");
114 }
115 }
116
117 /**********************************************************************
118 *
119 * Setup work for hardware segmentation offload (TSO) on
120 * adapters using advanced tx descriptors
121 *
122 **********************************************************************/
123 static int
igc_tso_setup(struct tx_ring * txr,if_pkt_info_t pi,uint32_t * cmd_type_len,uint32_t * olinfo_status)124 igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
125 uint32_t *olinfo_status)
126 {
127 struct igc_adv_tx_context_desc *TXD;
128 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0;
129 uint32_t mss_l4len_idx = 0;
130 uint32_t paylen;
131
132 switch(pi->ipi_etype) {
133 case ETHERTYPE_IPV6:
134 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6;
135 break;
136 case ETHERTYPE_IP:
137 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4;
138 /* Tell transmit desc to also do IPv4 checksum. */
139 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8;
140 break;
141 default:
142 panic("%s: CSUM_TSO but no supported IP version (0x%04x)",
143 __func__, ntohs(pi->ipi_etype));
144 break;
145 }
146
147 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
148
149 /* This is used in the transmit desc in encap */
150 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen;
151
152 /* VLAN MACLEN IPLEN */
153 if (pi->ipi_mflags & M_VLANTAG) {
154 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT);
155 }
156
157 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT;
158 vlan_macip_lens |= pi->ipi_ip_hlen;
159 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
160
161 /* ADV DTYPE TUCMD */
162 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
163 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP;
164 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
165
166 /* MSS L4LEN IDX */
167 mss_l4len_idx |= (pi->ipi_tso_segsz << IGC_ADVTXD_MSS_SHIFT);
168 mss_l4len_idx |= (pi->ipi_tcp_hlen << IGC_ADVTXD_L4LEN_SHIFT);
169 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
170
171 TXD->seqnum_seed = htole32(0);
172 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE;
173 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
174 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT;
175
176 return (1);
177 }
178
179 /*********************************************************************
180 *
181 * Advanced Context Descriptor setup for VLAN, CSUM or TSO
182 *
183 **********************************************************************/
184 static int
igc_tx_ctx_setup(struct tx_ring * txr,if_pkt_info_t pi,uint32_t * cmd_type_len,uint32_t * olinfo_status)185 igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
186 uint32_t *olinfo_status)
187 {
188 struct igc_adv_tx_context_desc *TXD;
189 uint32_t vlan_macip_lens, type_tucmd_mlhl;
190 uint32_t mss_l4len_idx;
191 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0;
192
193 /* First check if TSO is to be used */
194 if (pi->ipi_csum_flags & CSUM_TSO)
195 return (igc_tso_setup(txr, pi, cmd_type_len, olinfo_status));
196
197 /* Indicate the whole packet as payload when not doing TSO */
198 *olinfo_status |= pi->ipi_len << IGC_ADVTXD_PAYLEN_SHIFT;
199
200 /* Now ready a context descriptor */
201 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
202
203 /*
204 ** In advanced descriptors the vlan tag must
205 ** be placed into the context descriptor. Hence
206 ** we need to make one even if not doing offloads.
207 */
208 if (pi->ipi_mflags & M_VLANTAG) {
209 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT);
210 } else if ((pi->ipi_csum_flags & IGC_CSUM_OFFLOAD) == 0) {
211 return (0);
212 }
213
214 /* Set the ether header length */
215 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT;
216
217 switch(pi->ipi_etype) {
218 case ETHERTYPE_IP:
219 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4;
220 break;
221 case ETHERTYPE_IPV6:
222 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6;
223 break;
224 default:
225 break;
226 }
227
228 vlan_macip_lens |= pi->ipi_ip_hlen;
229 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
230
231 switch (pi->ipi_ipproto) {
232 case IPPROTO_TCP:
233 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) {
234 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP;
235 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
236 }
237 break;
238 case IPPROTO_UDP:
239 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) {
240 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP;
241 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
242 }
243 break;
244 case IPPROTO_SCTP:
245 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) {
246 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_SCTP;
247 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
248 }
249 break;
250 default:
251 break;
252 }
253
254 /* Now copy bits into descriptor */
255 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
256 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
257 TXD->seqnum_seed = htole32(0);
258 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
259
260 return (1);
261 }
262
263 static int
igc_isc_txd_encap(void * arg,if_pkt_info_t pi)264 igc_isc_txd_encap(void *arg, if_pkt_info_t pi)
265 {
266 struct igc_adapter *sc = arg;
267 if_softc_ctx_t scctx = sc->shared;
268 struct igc_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx];
269 struct tx_ring *txr = &que->txr;
270 int nsegs = pi->ipi_nsegs;
271 bus_dma_segment_t *segs = pi->ipi_segs;
272 union igc_adv_tx_desc *txd = NULL;
273 int i, j, pidx_last;
274 uint32_t olinfo_status, cmd_type_len, txd_flags;
275 qidx_t ntxd;
276
277 pidx_last = olinfo_status = 0;
278 /* Basic descriptor defines */
279 cmd_type_len = (IGC_ADVTXD_DTYP_DATA |
280 IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DCMD_DEXT);
281
282 if (pi->ipi_mflags & M_VLANTAG)
283 cmd_type_len |= IGC_ADVTXD_DCMD_VLE;
284
285 i = pi->ipi_pidx;
286 ntxd = scctx->isc_ntxd[0];
287 txd_flags = pi->ipi_flags & IPI_TX_INTR ? IGC_ADVTXD_DCMD_RS : 0;
288 /* Consume the first descriptor */
289 i += igc_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status);
290 if (i == scctx->isc_ntxd[0])
291 i = 0;
292
293 for (j = 0; j < nsegs; j++) {
294 bus_size_t seglen;
295 bus_addr_t segaddr;
296
297 txd = (union igc_adv_tx_desc *)&txr->tx_base[i];
298 seglen = segs[j].ds_len;
299 segaddr = htole64(segs[j].ds_addr);
300
301 txd->read.buffer_addr = segaddr;
302 txd->read.cmd_type_len = htole32(IGC_ADVTXD_DCMD_IFCS |
303 cmd_type_len | seglen);
304 txd->read.olinfo_status = htole32(olinfo_status);
305 pidx_last = i;
306 if (++i == scctx->isc_ntxd[0]) {
307 i = 0;
308 }
309 }
310 if (txd_flags) {
311 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last;
312 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1);
313 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx);
314 }
315
316 txd->read.cmd_type_len |= htole32(IGC_ADVTXD_DCMD_EOP | txd_flags);
317 pi->ipi_new_pidx = i;
318
319 return (0);
320 }
321
322 static void
igc_isc_txd_flush(void * arg,uint16_t txqid,qidx_t pidx)323 igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
324 {
325 struct igc_adapter *adapter = arg;
326 struct igc_tx_queue *que = &adapter->tx_queues[txqid];
327 struct tx_ring *txr = &que->txr;
328
329 IGC_WRITE_REG(&adapter->hw, IGC_TDT(txr->me), pidx);
330 }
331
332 static int
igc_isc_txd_credits_update(void * arg,uint16_t txqid,bool clear)333 igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
334 {
335 struct igc_adapter *adapter = arg;
336 if_softc_ctx_t scctx = adapter->shared;
337 struct igc_tx_queue *que = &adapter->tx_queues[txqid];
338 struct tx_ring *txr = &que->txr;
339
340 qidx_t processed = 0;
341 int updated;
342 qidx_t cur, prev, ntxd, rs_cidx;
343 int32_t delta;
344 uint8_t status;
345
346 rs_cidx = txr->tx_rs_cidx;
347 if (rs_cidx == txr->tx_rs_pidx)
348 return (0);
349 cur = txr->tx_rsq[rs_cidx];
350 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
351 updated = !!(status & IGC_TXD_STAT_DD);
352
353 if (!updated)
354 return (0);
355
356 /* If clear is false just let caller know that there
357 * are descriptors to reclaim */
358 if (!clear)
359 return (1);
360
361 prev = txr->tx_cidx_processed;
362 ntxd = scctx->isc_ntxd[0];
363 do {
364 MPASS(prev != cur);
365 delta = (int32_t)cur - (int32_t)prev;
366 if (delta < 0)
367 delta += ntxd;
368 MPASS(delta > 0);
369
370 processed += delta;
371 prev = cur;
372 rs_cidx = (rs_cidx + 1) & (ntxd-1);
373 if (rs_cidx == txr->tx_rs_pidx)
374 break;
375 cur = txr->tx_rsq[rs_cidx];
376 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
377 } while ((status & IGC_TXD_STAT_DD));
378
379 txr->tx_rs_cidx = rs_cidx;
380 txr->tx_cidx_processed = prev;
381 return (processed);
382 }
383
384 static void
igc_isc_rxd_refill(void * arg,if_rxd_update_t iru)385 igc_isc_rxd_refill(void *arg, if_rxd_update_t iru)
386 {
387 struct igc_adapter *sc = arg;
388 if_softc_ctx_t scctx = sc->shared;
389 uint16_t rxqid = iru->iru_qsidx;
390 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
391 union igc_adv_rx_desc *rxd;
392 struct rx_ring *rxr = &que->rxr;
393 uint64_t *paddrs;
394 uint32_t next_pidx, pidx;
395 uint16_t count;
396 int i;
397
398 paddrs = iru->iru_paddrs;
399 pidx = iru->iru_pidx;
400 count = iru->iru_count;
401
402 for (i = 0, next_pidx = pidx; i < count; i++) {
403 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[next_pidx];
404
405 rxd->read.pkt_addr = htole64(paddrs[i]);
406 if (++next_pidx == scctx->isc_nrxd[0])
407 next_pidx = 0;
408 }
409 }
410
411 static void
igc_isc_rxd_flush(void * arg,uint16_t rxqid,uint8_t flid __unused,qidx_t pidx)412 igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx)
413 {
414 struct igc_adapter *sc = arg;
415 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
416 struct rx_ring *rxr = &que->rxr;
417
418 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), pidx);
419 }
420
421 static int
igc_isc_rxd_available(void * arg,uint16_t rxqid,qidx_t idx,qidx_t budget)422 igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget)
423 {
424 struct igc_adapter *sc = arg;
425 if_softc_ctx_t scctx = sc->shared;
426 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
427 struct rx_ring *rxr = &que->rxr;
428 union igc_adv_rx_desc *rxd;
429 uint32_t staterr = 0;
430 int cnt, i;
431
432 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) {
433 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[i];
434 staterr = le32toh(rxd->wb.upper.status_error);
435
436 if ((staterr & IGC_RXD_STAT_DD) == 0)
437 break;
438 if (++i == scctx->isc_nrxd[0])
439 i = 0;
440 if (staterr & IGC_RXD_STAT_EOP)
441 cnt++;
442 }
443 return (cnt);
444 }
445
446 /****************************************************************
447 * Routine sends data which has been dma'ed into host memory
448 * to upper layer. Initialize ri structure.
449 *
450 * Returns 0 upon success, errno on failure
451 ***************************************************************/
452
453 static int
igc_isc_rxd_pkt_get(void * arg,if_rxd_info_t ri)454 igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
455 {
456 struct igc_adapter *adapter = arg;
457 if_softc_ctx_t scctx = adapter->shared;
458 struct igc_rx_queue *que = &adapter->rx_queues[ri->iri_qsidx];
459 struct rx_ring *rxr = &que->rxr;
460 union igc_adv_rx_desc *rxd;
461
462 uint16_t pkt_info, len;
463 uint32_t ptype, staterr;
464 int i, cidx;
465 bool eop;
466
467 staterr = i = 0;
468 cidx = ri->iri_cidx;
469
470 do {
471 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[cidx];
472 staterr = le32toh(rxd->wb.upper.status_error);
473 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info);
474
475 MPASS ((staterr & IGC_RXD_STAT_DD) != 0);
476
477 len = le16toh(rxd->wb.upper.length);
478 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGC_PKTTYPE_MASK;
479
480 ri->iri_len += len;
481 rxr->rx_bytes += ri->iri_len;
482
483 rxd->wb.upper.status_error = 0;
484 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP);
485
486 /* Make sure bad packets are discarded */
487 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) {
488 adapter->dropped_pkts++;
489 ++rxr->rx_discarded;
490 return (EBADMSG);
491 }
492 ri->iri_frags[i].irf_flid = 0;
493 ri->iri_frags[i].irf_idx = cidx;
494 ri->iri_frags[i].irf_len = len;
495
496 if (++cidx == scctx->isc_nrxd[0])
497 cidx = 0;
498 #ifdef notyet
499 if (rxr->hdr_split == true) {
500 ri->iri_frags[i].irf_flid = 1;
501 ri->iri_frags[i].irf_idx = cidx;
502 if (++cidx == scctx->isc_nrxd[0])
503 cidx = 0;
504 }
505 #endif
506 i++;
507 } while (!eop);
508
509 rxr->rx_packets++;
510
511 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0)
512 igc_rx_checksum(staterr, ri, ptype);
513
514 if (staterr & IGC_RXD_STAT_VP) {
515 ri->iri_vtag = le16toh(rxd->wb.upper.vlan);
516 ri->iri_flags |= M_VLANTAG;
517 }
518
519 ri->iri_flowid =
520 le32toh(rxd->wb.lower.hi_dword.rss);
521 ri->iri_rsstype = igc_determine_rsstype(pkt_info);
522 ri->iri_nfrags = i;
523
524 return (0);
525 }
526
527 /*********************************************************************
528 *
529 * Verify that the hardware indicated that the checksum is valid.
530 * Inform the stack about the status of checksum so that stack
531 * doesn't spend time verifying the checksum.
532 *
533 *********************************************************************/
534 static void
igc_rx_checksum(uint32_t staterr,if_rxd_info_t ri,uint32_t ptype)535 igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype)
536 {
537 uint16_t status = (uint16_t)staterr;
538 uint8_t errors = (uint8_t)(staterr >> 24);
539
540 if (__predict_false(status & IGC_RXD_STAT_IXSM))
541 return;
542
543 /* If there is a layer 3 or 4 error we are done */
544 if (__predict_false(errors & (IGC_RXD_ERR_IPE | IGC_RXD_ERR_TCPE)))
545 return;
546
547 /* IP Checksum Good */
548 if (status & IGC_RXD_STAT_IPCS)
549 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
550
551 /* Valid L4E checksum */
552 if (__predict_true(status &
553 (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS))) {
554 /* SCTP header present */
555 if (__predict_false((ptype & IGC_RXDADV_PKTTYPE_ETQF) == 0 &&
556 (ptype & IGC_RXDADV_PKTTYPE_SCTP) != 0)) {
557 ri->iri_csum_flags |= CSUM_SCTP_VALID;
558 } else {
559 ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
560 ri->iri_csum_data = htons(0xffff);
561 }
562 }
563 }
564
565 /********************************************************************
566 *
567 * Parse the packet type to determine the appropriate hash
568 *
569 ******************************************************************/
570 static int
igc_determine_rsstype(uint16_t pkt_info)571 igc_determine_rsstype(uint16_t pkt_info)
572 {
573 switch (pkt_info & IGC_RXDADV_RSSTYPE_MASK) {
574 case IGC_RXDADV_RSSTYPE_IPV4_TCP:
575 return M_HASHTYPE_RSS_TCP_IPV4;
576 case IGC_RXDADV_RSSTYPE_IPV4:
577 return M_HASHTYPE_RSS_IPV4;
578 case IGC_RXDADV_RSSTYPE_IPV6_TCP:
579 return M_HASHTYPE_RSS_TCP_IPV6;
580 case IGC_RXDADV_RSSTYPE_IPV6_EX:
581 return M_HASHTYPE_RSS_IPV6_EX;
582 case IGC_RXDADV_RSSTYPE_IPV6:
583 return M_HASHTYPE_RSS_IPV6;
584 case IGC_RXDADV_RSSTYPE_IPV6_TCP_EX:
585 return M_HASHTYPE_RSS_TCP_IPV6_EX;
586 default:
587 return M_HASHTYPE_OPAQUE;
588 }
589 }
590