1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3 *
4 * Copyright (c) 2015 - 2023 Intel Corporation
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenFabrics.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include "irdma_main.h"
36
37 static struct irdma_rsrc_limits rsrc_limits_table[] = {
38 [0] = {
39 .qplimit = SZ_128,
40 },
41 [1] = {
42 .qplimit = SZ_1K,
43 },
44 [2] = {
45 .qplimit = SZ_2K,
46 },
47 [3] = {
48 .qplimit = SZ_4K,
49 },
50 [4] = {
51 .qplimit = SZ_16K,
52 },
53 [5] = {
54 .qplimit = SZ_64K,
55 },
56 [6] = {
57 .qplimit = SZ_128K,
58 },
59 [7] = {
60 .qplimit = SZ_256K,
61 },
62 };
63
64 /* types of hmc objects */
65 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = {
66 IRDMA_HMC_IW_QP,
67 IRDMA_HMC_IW_CQ,
68 IRDMA_HMC_IW_HTE,
69 IRDMA_HMC_IW_ARP,
70 IRDMA_HMC_IW_APBVT_ENTRY,
71 IRDMA_HMC_IW_MR,
72 IRDMA_HMC_IW_XF,
73 IRDMA_HMC_IW_XFFL,
74 IRDMA_HMC_IW_Q1,
75 IRDMA_HMC_IW_Q1FL,
76 IRDMA_HMC_IW_PBLE,
77 IRDMA_HMC_IW_TIMER,
78 IRDMA_HMC_IW_FSIMC,
79 IRDMA_HMC_IW_FSIAV,
80 IRDMA_HMC_IW_RRF,
81 IRDMA_HMC_IW_RRFFL,
82 IRDMA_HMC_IW_HDR,
83 IRDMA_HMC_IW_MD,
84 IRDMA_HMC_IW_OOISC,
85 IRDMA_HMC_IW_OOISCFFL,
86 };
87
88 /**
89 * irdma_iwarp_ce_handler - handle iwarp completions
90 * @iwcq: iwarp cq receiving event
91 */
92 static void
irdma_iwarp_ce_handler(struct irdma_sc_cq * iwcq)93 irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
94 {
95 struct irdma_cq *cq = iwcq->back_cq;
96
97 if (!cq->user_mode)
98 atomic_set(&cq->armed, 0);
99 if (cq->ibcq.comp_handler)
100 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
101 }
102
103 /**
104 * irdma_puda_ce_handler - handle puda completion events
105 * @rf: RDMA PCI function
106 * @cq: puda completion q for event
107 */
108 static void
irdma_puda_ce_handler(struct irdma_pci_f * rf,struct irdma_sc_cq * cq)109 irdma_puda_ce_handler(struct irdma_pci_f *rf,
110 struct irdma_sc_cq *cq)
111 {
112 struct irdma_sc_dev *dev = &rf->sc_dev;
113 u32 compl_error;
114 int status;
115
116 do {
117 status = irdma_puda_poll_cmpl(dev, cq, &compl_error);
118 if (status == -ENOENT)
119 break;
120 if (status) {
121 irdma_debug(dev, IRDMA_DEBUG_ERR, "puda status = %d\n", status);
122 break;
123 }
124 if (compl_error) {
125 irdma_debug(dev, IRDMA_DEBUG_ERR,
126 "puda compl_err = 0x%x\n", compl_error);
127 break;
128 }
129 } while (1);
130
131 irdma_sc_ccq_arm(cq);
132 }
133
134 /**
135 * irdma_process_ceq - handle ceq for completions
136 * @rf: RDMA PCI function
137 * @ceq: ceq having cq for completion
138 */
139 static void
irdma_process_ceq(struct irdma_pci_f * rf,struct irdma_ceq * ceq)140 irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq)
141 {
142 struct irdma_sc_dev *dev = &rf->sc_dev;
143 struct irdma_sc_ceq *sc_ceq;
144 struct irdma_sc_cq *cq;
145 unsigned long flags;
146
147 sc_ceq = &ceq->sc_ceq;
148 do {
149 spin_lock_irqsave(&ceq->ce_lock, flags);
150 cq = irdma_sc_process_ceq(dev, sc_ceq);
151 if (!cq) {
152 spin_unlock_irqrestore(&ceq->ce_lock, flags);
153 break;
154 }
155
156 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP)
157 irdma_iwarp_ce_handler(cq);
158
159 spin_unlock_irqrestore(&ceq->ce_lock, flags);
160
161 if (cq->cq_type == IRDMA_CQ_TYPE_CQP)
162 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);
163 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ ||
164 cq->cq_type == IRDMA_CQ_TYPE_IEQ)
165 irdma_puda_ce_handler(rf, cq);
166 } while (1);
167 }
168
169 static void
irdma_set_flush_fields(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)170 irdma_set_flush_fields(struct irdma_sc_qp *qp,
171 struct irdma_aeqe_info *info)
172 {
173 struct qp_err_code qp_err;
174
175 qp->sq_flush_code = info->sq;
176 qp->rq_flush_code = info->rq;
177 qp_err = irdma_ae_to_qp_err_code(info->ae_id);
178
179 qp->flush_code = qp_err.flush_code;
180 qp->event_type = qp_err.event_type;
181 }
182
183 /**
184 * irdma_complete_cqp_request - perform post-completion cleanup
185 * @cqp: device CQP
186 * @cqp_request: CQP request
187 *
188 * Mark CQP request as done, wake up waiting thread or invoke
189 * callback function and release/free CQP request.
190 */
191 static void
irdma_complete_cqp_request(struct irdma_cqp * cqp,struct irdma_cqp_request * cqp_request)192 irdma_complete_cqp_request(struct irdma_cqp *cqp,
193 struct irdma_cqp_request *cqp_request)
194 {
195 WRITE_ONCE(cqp_request->request_done, true);
196 if (cqp_request->waiting)
197 wake_up(&cqp_request->waitq);
198 else if (cqp_request->callback_fcn)
199 cqp_request->callback_fcn(cqp_request);
200 irdma_put_cqp_request(cqp, cqp_request);
201 }
202
203 /**
204 * irdma_process_aeq - handle aeq events
205 * @rf: RDMA PCI function
206 */
207 static void
irdma_process_aeq(struct irdma_pci_f * rf)208 irdma_process_aeq(struct irdma_pci_f *rf)
209 {
210 struct irdma_sc_dev *dev = &rf->sc_dev;
211 struct irdma_aeq *aeq = &rf->aeq;
212 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq;
213 struct irdma_aeqe_info aeinfo;
214 struct irdma_aeqe_info *info = &aeinfo;
215 int ret;
216 struct irdma_qp *iwqp = NULL;
217 struct irdma_cq *iwcq = NULL;
218 struct irdma_sc_qp *qp = NULL;
219 struct irdma_device *iwdev = rf->iwdev;
220 struct irdma_qp_host_ctx_info *ctx_info = NULL;
221 unsigned long flags;
222
223 u32 aeqcnt = 0;
224
225 if (!sc_aeq->size)
226 return;
227
228 do {
229 memset(info, 0, sizeof(*info));
230 ret = irdma_sc_get_next_aeqe(sc_aeq, info);
231 if (ret)
232 break;
233
234 aeqcnt++;
235 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ,
236 "ae_id = 0x%x (%s), is_qp = %d, qp_id = %d, tcp_state = %d, iwarp_state = %d, ae_src = %d\n",
237 info->ae_id, irdma_get_ae_desc(info->ae_id),
238 info->qp, info->qp_cq_id, info->tcp_state,
239 info->iwarp_state, info->ae_src);
240
241 if (info->qp) {
242 spin_lock_irqsave(&rf->qptable_lock, flags);
243 iwqp = rf->qp_table[info->qp_cq_id];
244 if (!iwqp) {
245 spin_unlock_irqrestore(&rf->qptable_lock,
246 flags);
247 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) {
248 struct irdma_device *iwdev = rf->iwdev;
249
250 if (!iwdev->vsi.tc_change_pending)
251 continue;
252
253 atomic_dec(&iwdev->vsi.qp_suspend_reqs);
254 wake_up(&iwdev->suspend_wq);
255 continue;
256 }
257 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ,
258 "qp_id %d is already freed\n",
259 info->qp_cq_id);
260 continue;
261 }
262 irdma_qp_add_ref(&iwqp->ibqp);
263 spin_unlock_irqrestore(&rf->qptable_lock, flags);
264 qp = &iwqp->sc_qp;
265 spin_lock_irqsave(&iwqp->lock, flags);
266 iwqp->hw_tcp_state = info->tcp_state;
267 iwqp->hw_iwarp_state = info->iwarp_state;
268 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE)
269 iwqp->last_aeq = info->ae_id;
270 spin_unlock_irqrestore(&iwqp->lock, flags);
271 ctx_info = &iwqp->ctx_info;
272 } else {
273 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR)
274 continue;
275 }
276
277 switch (info->ae_id) {
278 struct irdma_cm_node *cm_node;
279
280 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
281 cm_node = iwqp->cm_node;
282 if (cm_node->accept_pend) {
283 atomic_dec(&cm_node->listener->pend_accepts_cnt);
284 cm_node->accept_pend = 0;
285 }
286 iwqp->rts_ae_rcvd = 1;
287 wake_up_interruptible(&iwqp->waitq);
288 break;
289 case IRDMA_AE_LLP_FIN_RECEIVED:
290 if (qp->term_flags)
291 break;
292 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
293 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT;
294 if (iwqp->ibqp_state == IB_QPS_RTS) {
295 irdma_next_iw_state(iwqp,
296 IRDMA_QP_STATE_CLOSING,
297 0, 0, 0);
298 irdma_cm_disconn(iwqp);
299 }
300 irdma_schedule_cm_timer(iwqp->cm_node,
301 (struct irdma_puda_buf *)iwqp,
302 IRDMA_TIMER_TYPE_CLOSE,
303 1, 0);
304 }
305 break;
306 case IRDMA_AE_LLP_CLOSE_COMPLETE:
307 if (qp->term_flags)
308 irdma_terminate_done(qp, 0);
309 else
310 irdma_cm_disconn(iwqp);
311 break;
312 case IRDMA_AE_BAD_CLOSE:
313 case IRDMA_AE_RESET_SENT:
314 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0,
315 0);
316 irdma_cm_disconn(iwqp);
317 break;
318 case IRDMA_AE_LLP_CONNECTION_RESET:
319 if (atomic_read(&iwqp->close_timer_started))
320 break;
321 irdma_cm_disconn(iwqp);
322 break;
323 case IRDMA_AE_QP_SUSPEND_COMPLETE:
324 if (iwqp->iwdev->vsi.tc_change_pending) {
325 if (!atomic_dec_return(&iwqp->sc_qp.vsi->qp_suspend_reqs))
326 wake_up(&iwqp->iwdev->suspend_wq);
327 }
328 if (iwqp->suspend_pending) {
329 iwqp->suspend_pending = false;
330 wake_up(&iwqp->iwdev->suspend_wq);
331 }
332 break;
333 case IRDMA_AE_TERMINATE_SENT:
334 irdma_terminate_send_fin(qp);
335 break;
336 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
337 irdma_terminate_received(qp, info);
338 break;
339 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
340 case IRDMA_AE_CQ_OPERATION_ERROR:
341 irdma_dev_err(&iwdev->ibdev,
342 "Processing CQ[0x%x] op error, AE 0x%04X\n",
343 info->qp_cq_id, info->ae_id);
344 spin_lock_irqsave(&rf->cqtable_lock, flags);
345 iwcq = rf->cq_table[info->qp_cq_id];
346 if (!iwcq) {
347 spin_unlock_irqrestore(&rf->cqtable_lock,
348 flags);
349 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ,
350 "cq_id %d is already freed\n",
351 info->qp_cq_id);
352 continue;
353 }
354 irdma_cq_add_ref(&iwcq->ibcq);
355 spin_unlock_irqrestore(&rf->cqtable_lock, flags);
356 if (iwcq->ibcq.event_handler) {
357 struct ib_event ibevent;
358
359 ibevent.device = iwcq->ibcq.device;
360 ibevent.event = IB_EVENT_CQ_ERR;
361 ibevent.element.cq = &iwcq->ibcq;
362 iwcq->ibcq.event_handler(&ibevent,
363 iwcq->ibcq.cq_context);
364 }
365 irdma_cq_rem_ref(&iwcq->ibcq);
366 break;
367 case IRDMA_AE_RESET_NOT_SENT:
368 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
369 break;
370 case IRDMA_AE_RESOURCE_EXHAUSTION:
371 irdma_dev_err(&iwdev->ibdev,
372 "Resource exhaustion reason: q1 = %d xmit or rreq = %d\n",
373 info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_Q1,
374 info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR);
375 break;
376 case IRDMA_AE_PRIV_OPERATION_DENIED:
377 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
378 case IRDMA_AE_STAG_ZERO_INVALID:
379 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
380 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
381 case IRDMA_AE_DDP_UBE_INVALID_MO:
382 case IRDMA_AE_DDP_UBE_INVALID_QN:
383 case IRDMA_AE_DDP_NO_L_BIT:
384 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
385 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
386 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
387 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
388 case IRDMA_AE_INVALID_ARP_ENTRY:
389 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
390 case IRDMA_AE_STALE_ARP_ENTRY:
391 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
392 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
393 case IRDMA_AE_LLP_SYN_RECEIVED:
394 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
395 case IRDMA_AE_LCE_QP_CATASTROPHIC:
396 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC:
397 case IRDMA_AE_LLP_TOO_MANY_RNRS:
398 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
399 default:
400 irdma_dev_err(&iwdev->ibdev,
401 "AEQ: abnormal ae_id = 0x%x (%s), is_qp = %d, qp_id = %d, ae_source = %d\n",
402 info->ae_id, irdma_get_ae_desc(info->ae_id),
403 info->qp, info->qp_cq_id, info->ae_src);
404 if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) {
405 ctx_info->roce_info->err_rq_idx_valid = info->err_rq_idx_valid;
406 if (info->rq) {
407 ctx_info->roce_info->err_rq_idx = info->wqe_idx;
408 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va,
409 ctx_info);
410 }
411 irdma_set_flush_fields(qp, info);
412 irdma_cm_disconn(iwqp);
413 break;
414 }
415 ctx_info->iwarp_info->err_rq_idx_valid = info->err_rq_idx_valid;
416 if (info->rq) {
417 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx;
418 ctx_info->tcp_info_valid = false;
419 ctx_info->iwarp_info_valid = true;
420 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va,
421 ctx_info);
422 }
423 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS &&
424 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) {
425 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0);
426 irdma_cm_disconn(iwqp);
427 } else {
428 irdma_terminate_connection(qp, info);
429 }
430 break;
431 }
432 if (info->qp)
433 irdma_qp_rem_ref(&iwqp->ibqp);
434 } while (1);
435
436 if (aeqcnt)
437 irdma_sc_repost_aeq_entries(dev, aeqcnt);
438 }
439
440 /**
441 * irdma_ena_intr - set up device interrupts
442 * @dev: hardware control device structure
443 * @msix_id: id of the interrupt to be enabled
444 */
445 static void
irdma_ena_intr(struct irdma_sc_dev * dev,u32 msix_id)446 irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id)
447 {
448 dev->irq_ops->irdma_en_irq(dev, msix_id);
449 }
450
451 /**
452 * irdma_dpc - tasklet for aeq and ceq 0
453 * @t: tasklet_struct ptr
454 */
455 static void
irdma_dpc(unsigned long t)456 irdma_dpc(unsigned long t)
457 {
458 struct irdma_pci_f *rf = from_tasklet(rf, (struct tasklet_struct *)t,
459 dpc_tasklet);
460
461 if (rf->msix_shared)
462 irdma_process_ceq(rf, rf->ceqlist);
463 irdma_process_aeq(rf);
464 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx);
465 }
466
467 /**
468 * irdma_ceq_dpc - dpc handler for CEQ
469 * @t: tasklet_struct ptr
470 */
471 static void
irdma_ceq_dpc(unsigned long t)472 irdma_ceq_dpc(unsigned long t)
473 {
474 struct irdma_ceq *iwceq = from_tasklet(iwceq, (struct tasklet_struct *)t,
475 dpc_tasklet);
476 struct irdma_pci_f *rf = iwceq->rf;
477
478 irdma_process_ceq(rf, iwceq);
479 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx);
480 }
481
482 /**
483 * irdma_save_msix_info - copy msix vector information to iwarp device
484 * @rf: RDMA PCI function
485 *
486 * Allocate iwdev msix table and copy the msix info to the table
487 * Return 0 if successful, otherwise return error
488 */
489 static int
irdma_save_msix_info(struct irdma_pci_f * rf)490 irdma_save_msix_info(struct irdma_pci_f *rf)
491 {
492 struct irdma_qvlist_info *iw_qvlist;
493 struct irdma_qv_info *iw_qvinfo;
494 u16 ceq_idx;
495 u32 i;
496 u32 size;
497
498 if (!rf->msix_count) {
499 irdma_dev_err(to_ibdev(&rf->sc_dev), "No MSI-X vectors reserved for RDMA.\n");
500 return -EINVAL;
501 }
502
503 size = sizeof(struct irdma_msix_vector) * rf->msix_count;
504 size += sizeof(*iw_qvlist);
505 size += sizeof(*iw_qvinfo) * rf->msix_count - 1;
506 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL);
507 if (!rf->iw_msixtbl)
508 return -ENOMEM;
509
510 rf->iw_qvlist = (struct irdma_qvlist_info *)
511 (&rf->iw_msixtbl[rf->msix_count]);
512 iw_qvlist = rf->iw_qvlist;
513 iw_qvinfo = iw_qvlist->qv_info;
514 iw_qvlist->num_vectors = rf->msix_count;
515 if (rf->msix_count <= num_online_cpus())
516 rf->msix_shared = true;
517 else if (rf->msix_count > num_online_cpus() + 1)
518 rf->msix_count = num_online_cpus() + 1;
519
520 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) {
521 rf->iw_msixtbl[i].idx = rf->msix_info.entry + i;
522 rf->iw_msixtbl[i].cpu_affinity = ceq_idx;
523 if (!i) {
524 iw_qvinfo->aeq_idx = 0;
525 if (rf->msix_shared)
526 iw_qvinfo->ceq_idx = ceq_idx++;
527 else
528 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX;
529 } else {
530 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX;
531 iw_qvinfo->ceq_idx = ceq_idx++;
532 }
533 iw_qvinfo->itr_idx = IRDMA_IDX_NOITR;
534 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx;
535 }
536
537 return 0;
538 }
539
540 /**
541 * irdma_irq_handler - interrupt handler for aeq and ceq0
542 * @data: RDMA PCI function
543 */
544 static void
irdma_irq_handler(void * data)545 irdma_irq_handler(void *data)
546 {
547 struct irdma_pci_f *rf = data;
548
549 tasklet_schedule(&rf->dpc_tasklet);
550 }
551
552 /**
553 * irdma_ceq_handler - interrupt handler for ceq
554 * @data: ceq pointer
555 */
556 static void
irdma_ceq_handler(void * data)557 irdma_ceq_handler(void *data)
558 {
559 struct irdma_ceq *iwceq = data;
560
561 tasklet_schedule(&iwceq->dpc_tasklet);
562 }
563
564 /**
565 * irdma_free_irq - free device interrupts in FreeBSD manner
566 * @rf: RDMA PCI function
567 * @msix_vec: msix vector to disable irq
568 *
569 * The function is called when destroying irq. It tearsdown
570 * the interrupt and release resources.
571 */
572 static void
irdma_free_irq(struct irdma_pci_f * rf,struct irdma_msix_vector * msix_vec)573 irdma_free_irq(struct irdma_pci_f *rf, struct irdma_msix_vector *msix_vec)
574 {
575 if (msix_vec->tag) {
576 bus_teardown_intr(rf->dev_ctx.dev, msix_vec->res,
577 msix_vec->tag);
578 msix_vec->tag = NULL;
579 }
580 if (msix_vec->res) {
581 bus_release_resource(rf->dev_ctx.dev, SYS_RES_IRQ,
582 msix_vec->idx + 1,
583 msix_vec->res);
584 msix_vec->res = NULL;
585 }
586 }
587
588 /**
589 * irdma_destroy_irq - destroy device interrupts
590 * @rf: RDMA PCI function
591 * @msix_vec: msix vector to disable irq
592 * @dev_id: parameter to pass to free_irq (used during irq setup)
593 *
594 * The function is called when destroying aeq/ceq
595 */
596 static void
irdma_destroy_irq(struct irdma_pci_f * rf,struct irdma_msix_vector * msix_vec,void * dev_id)597 irdma_destroy_irq(struct irdma_pci_f *rf,
598 struct irdma_msix_vector *msix_vec, void *dev_id)
599 {
600 struct irdma_sc_dev *dev = &rf->sc_dev;
601
602 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx);
603 irdma_free_irq(rf, msix_vec);
604 if (rf == dev_id) {
605 tasklet_kill(&rf->dpc_tasklet);
606 } else {
607 struct irdma_ceq *iwceq = (struct irdma_ceq *)dev_id;
608
609 tasklet_kill(&iwceq->dpc_tasklet);
610 }
611 }
612
613 /**
614 * irdma_destroy_cqp - destroy control qp
615 * @rf: RDMA PCI function
616 * @free_hwcqp: 1 if hw cqp should be freed
617 *
618 * Issue destroy cqp request and
619 * free the resources associated with the cqp
620 */
621 static void
irdma_destroy_cqp(struct irdma_pci_f * rf,bool free_hwcqp)622 irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp)
623 {
624 struct irdma_sc_dev *dev = &rf->sc_dev;
625 struct irdma_cqp *cqp = &rf->cqp;
626 int status = 0;
627
628 if (rf->cqp_cmpl_wq)
629 destroy_workqueue(rf->cqp_cmpl_wq);
630 status = irdma_sc_cqp_destroy(dev->cqp, free_hwcqp);
631 if (status)
632 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy CQP failed %d\n", status);
633
634 irdma_cleanup_pending_cqp_op(rf);
635 irdma_free_dma_mem(dev->hw, &cqp->sq);
636 kfree(cqp->scratch_array);
637 cqp->scratch_array = NULL;
638 kfree(cqp->cqp_requests);
639 cqp->cqp_requests = NULL;
640 }
641
642 static void
irdma_destroy_virt_aeq(struct irdma_pci_f * rf)643 irdma_destroy_virt_aeq(struct irdma_pci_f *rf)
644 {
645 struct irdma_aeq *aeq = &rf->aeq;
646 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
647 dma_addr_t *pg_arr = (dma_addr_t *) aeq->palloc.level1.addr;
648
649 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt);
650 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
651 vfree(aeq->mem.va);
652 }
653
654 /**
655 * irdma_destroy_aeq - destroy aeq
656 * @rf: RDMA PCI function
657 *
658 * Issue a destroy aeq request and
659 * free the resources associated with the aeq
660 * The function is called during driver unload
661 */
662 static void
irdma_destroy_aeq(struct irdma_pci_f * rf)663 irdma_destroy_aeq(struct irdma_pci_f *rf)
664 {
665 struct irdma_sc_dev *dev = &rf->sc_dev;
666 struct irdma_aeq *aeq = &rf->aeq;
667 int status = -EBUSY;
668
669 if (!rf->msix_shared) {
670 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false);
671 irdma_destroy_irq(rf, rf->iw_msixtbl, rf);
672 }
673 if (rf->reset)
674 goto exit;
675
676 aeq->sc_aeq.size = 0;
677 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY);
678 if (status)
679 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy AEQ failed %d\n", status);
680
681 exit:
682 if (aeq->virtual_map)
683 irdma_destroy_virt_aeq(rf);
684 else
685 irdma_free_dma_mem(dev->hw, &aeq->mem);
686 }
687
688 /**
689 * irdma_destroy_ceq - destroy ceq
690 * @rf: RDMA PCI function
691 * @iwceq: ceq to be destroyed
692 *
693 * Issue a destroy ceq request and
694 * free the resources associated with the ceq
695 */
696 static void
irdma_destroy_ceq(struct irdma_pci_f * rf,struct irdma_ceq * iwceq)697 irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq)
698 {
699 struct irdma_sc_dev *dev = &rf->sc_dev;
700 int status;
701
702 if (rf->reset)
703 goto exit;
704
705 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1);
706 if (status) {
707 irdma_debug(dev, IRDMA_DEBUG_ERR, "CEQ destroy command failed %d\n", status);
708 goto exit;
709 }
710
711 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq);
712 if (status)
713 irdma_debug(dev, IRDMA_DEBUG_ERR,
714 "CEQ destroy completion failed %d\n", status);
715 exit:
716 spin_lock_destroy(&iwceq->ce_lock);
717 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock);
718 kfree(iwceq->sc_ceq.reg_cq);
719 irdma_free_dma_mem(dev->hw, &iwceq->mem);
720 }
721
722 /**
723 * irdma_del_ceq_0 - destroy ceq 0
724 * @rf: RDMA PCI function
725 *
726 * Disable the ceq 0 interrupt and destroy the ceq 0
727 */
728 static void
irdma_del_ceq_0(struct irdma_pci_f * rf)729 irdma_del_ceq_0(struct irdma_pci_f *rf)
730 {
731 struct irdma_ceq *iwceq = rf->ceqlist;
732 struct irdma_msix_vector *msix_vec;
733
734 if (rf->msix_shared) {
735 msix_vec = &rf->iw_msixtbl[0];
736 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev,
737 msix_vec->ceq_id,
738 msix_vec->idx, false);
739 irdma_destroy_irq(rf, msix_vec, rf);
740 } else {
741 msix_vec = &rf->iw_msixtbl[1];
742 irdma_destroy_irq(rf, msix_vec, iwceq);
743 }
744
745 irdma_destroy_ceq(rf, iwceq);
746 rf->sc_dev.ceq_valid = false;
747 rf->ceqs_count = 0;
748 }
749
750 /**
751 * irdma_del_ceqs - destroy all ceq's except CEQ 0
752 * @rf: RDMA PCI function
753 *
754 * Go through all of the device ceq's, except 0, and for each
755 * ceq disable the ceq interrupt and destroy the ceq
756 */
757 static void
irdma_del_ceqs(struct irdma_pci_f * rf)758 irdma_del_ceqs(struct irdma_pci_f *rf)
759 {
760 struct irdma_ceq *iwceq = &rf->ceqlist[1];
761 struct irdma_msix_vector *msix_vec;
762 u32 i = 0;
763
764 if (rf->msix_shared)
765 msix_vec = &rf->iw_msixtbl[1];
766 else
767 msix_vec = &rf->iw_msixtbl[2];
768
769 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) {
770 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id,
771 msix_vec->idx, false);
772 irdma_destroy_irq(rf, msix_vec, iwceq);
773 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
774 IRDMA_OP_CEQ_DESTROY);
775 spin_lock_destroy(&iwceq->ce_lock);
776 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock);
777 kfree(iwceq->sc_ceq.reg_cq);
778 irdma_free_dma_mem(rf->sc_dev.hw, &iwceq->mem);
779 }
780 rf->ceqs_count = 1;
781 }
782
783 /**
784 * irdma_destroy_ccq - destroy control cq
785 * @rf: RDMA PCI function
786 *
787 * Issue destroy ccq request and
788 * free the resources associated with the ccq
789 */
790 static void
irdma_destroy_ccq(struct irdma_pci_f * rf)791 irdma_destroy_ccq(struct irdma_pci_f *rf)
792 {
793 struct irdma_sc_dev *dev = &rf->sc_dev;
794 struct irdma_ccq *ccq = &rf->ccq;
795 int status = 0;
796
797 if (!rf->reset)
798 status = irdma_sc_ccq_destroy(dev->ccq, 0, true);
799 if (status)
800 irdma_debug(dev, IRDMA_DEBUG_ERR, "CCQ destroy failed %d\n", status);
801 irdma_free_dma_mem(dev->hw, &ccq->mem_cq);
802 }
803
804 /**
805 * irdma_close_hmc_objects_type - delete hmc objects of a given type
806 * @dev: iwarp device
807 * @obj_type: the hmc object type to be deleted
808 * @hmc_info: host memory info struct
809 * @privileged: permission to close HMC objects
810 * @reset: true if called before reset
811 */
812 static void
irdma_close_hmc_objects_type(struct irdma_sc_dev * dev,enum irdma_hmc_rsrc_type obj_type,struct irdma_hmc_info * hmc_info,bool privileged,bool reset)813 irdma_close_hmc_objects_type(struct irdma_sc_dev *dev,
814 enum irdma_hmc_rsrc_type obj_type,
815 struct irdma_hmc_info *hmc_info,
816 bool privileged, bool reset)
817 {
818 struct irdma_hmc_del_obj_info info = {0};
819
820 info.hmc_info = hmc_info;
821 info.rsrc_type = obj_type;
822 info.count = hmc_info->hmc_obj[obj_type].cnt;
823 info.privileged = privileged;
824 if (irdma_sc_del_hmc_obj(dev, &info, reset))
825 irdma_debug(dev, IRDMA_DEBUG_ERR,
826 "del HMC obj of type %d failed\n", obj_type);
827 }
828
829 /**
830 * irdma_del_hmc_objects - remove all device hmc objects
831 * @dev: iwarp device
832 * @hmc_info: hmc_info to free
833 * @privileged: permission to delete HMC objects
834 * @reset: true if called before reset
835 * @vers: hardware version
836 */
837 void
irdma_del_hmc_objects(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,bool privileged,bool reset,enum irdma_vers vers)838 irdma_del_hmc_objects(struct irdma_sc_dev *dev,
839 struct irdma_hmc_info *hmc_info, bool privileged,
840 bool reset, enum irdma_vers vers)
841 {
842 unsigned int i;
843
844 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
845 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
846 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
847 hmc_info, privileged, reset);
848 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
849 break;
850 }
851 }
852
853 /**
854 * irdma_create_hmc_obj_type - create hmc object of a given type
855 * @dev: hardware control device structure
856 * @info: information for the hmc object to create
857 */
858 static int
irdma_create_hmc_obj_type(struct irdma_sc_dev * dev,struct irdma_hmc_create_obj_info * info)859 irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
860 struct irdma_hmc_create_obj_info *info)
861 {
862 return irdma_sc_create_hmc_obj(dev, info);
863 }
864
865 /**
866 * irdma_create_hmc_objs - create all hmc objects for the device
867 * @rf: RDMA PCI function
868 * @privileged: permission to create HMC objects
869 * @vers: HW version
870 *
871 * Create the device hmc objects and allocate hmc pages
872 * Return 0 if successful, otherwise clean up and return error
873 */
874 static int
irdma_create_hmc_objs(struct irdma_pci_f * rf,bool privileged,enum irdma_vers vers)875 irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged,
876 enum irdma_vers vers)
877 {
878 struct irdma_sc_dev *dev = &rf->sc_dev;
879 struct irdma_hmc_create_obj_info info = {0};
880 int i, status = 0;
881
882 info.hmc_info = dev->hmc_info;
883 info.privileged = privileged;
884 info.entry_type = rf->sd_type;
885
886 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
887 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE)
888 continue;
889 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) {
890 info.rsrc_type = iw_hmc_obj_types[i];
891 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
892 info.add_sd_cnt = 0;
893 status = irdma_create_hmc_obj_type(dev, &info);
894 if (status) {
895 irdma_debug(dev, IRDMA_DEBUG_ERR,
896 "create obj type %d status = %d\n",
897 iw_hmc_obj_types[i], status);
898 break;
899 }
900 }
901 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
902 break;
903 }
904
905 if (!status)
906 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id,
907 true, true);
908
909 while (i) {
910 i--;
911 /* destroy the hmc objects of a given type */
912 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
913 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
914 dev->hmc_info, privileged,
915 false);
916 }
917
918 return status;
919 }
920
921 /**
922 * irdma_obj_aligned_mem - get aligned memory from device allocated memory
923 * @rf: RDMA PCI function
924 * @memptr: points to the memory addresses
925 * @size: size of memory needed
926 * @mask: mask for the aligned memory
927 *
928 * Get aligned memory of the requested size and
929 * update the memptr to point to the new aligned memory
930 * Return 0 if successful, otherwise return no memory error
931 */
932 static int
irdma_obj_aligned_mem(struct irdma_pci_f * rf,struct irdma_dma_mem * memptr,u32 size,u32 mask)933 irdma_obj_aligned_mem(struct irdma_pci_f *rf,
934 struct irdma_dma_mem *memptr, u32 size,
935 u32 mask)
936 {
937 unsigned long va, newva;
938 unsigned long extra;
939
940 va = (unsigned long)rf->obj_next.va;
941 newva = va;
942 if (mask)
943 newva = ALIGN(va, (unsigned long)mask + 1ULL);
944 extra = newva - va;
945 memptr->va = (u8 *)va + extra;
946 memptr->pa = rf->obj_next.pa + extra;
947 memptr->size = size;
948 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size))
949 return -ENOMEM;
950
951 rf->obj_next.va = (u8 *)memptr->va + size;
952 rf->obj_next.pa = memptr->pa + size;
953
954 return 0;
955 }
956
957 /**
958 * irdma_create_cqp - create control qp
959 * @rf: RDMA PCI function
960 *
961 * Return 0, if the cqp and all the resources associated with it
962 * are successfully created, otherwise return error
963 */
964 static int
irdma_create_cqp(struct irdma_pci_f * rf)965 irdma_create_cqp(struct irdma_pci_f *rf)
966 {
967 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048;
968 struct irdma_dma_mem mem;
969 struct irdma_sc_dev *dev = &rf->sc_dev;
970 struct irdma_cqp_init_info cqp_init_info = {0};
971 struct irdma_cqp *cqp = &rf->cqp;
972 u16 maj_err, min_err;
973 int i, status;
974
975 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests),
976 GFP_KERNEL);
977 if (!cqp->cqp_requests)
978 return -ENOMEM;
979
980 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array),
981 GFP_KERNEL);
982 if (!cqp->scratch_array) {
983 status = -ENOMEM;
984 goto err_scratch;
985 }
986
987 dev->cqp = &cqp->sc_cqp;
988 dev->cqp->dev = dev;
989 cqp->sq.size = sizeof(struct irdma_cqp_sq_wqe) * sqsize;
990 cqp->sq.va = irdma_allocate_dma_mem(dev->hw, &cqp->sq, cqp->sq.size,
991 IRDMA_CQP_ALIGNMENT);
992 if (!cqp->sq.va) {
993 status = -ENOMEM;
994 goto err_sq;
995 }
996
997 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx),
998 IRDMA_HOST_CTX_ALIGNMENT_M);
999 if (status)
1000 goto err_ctx;
1001
1002 dev->cqp->host_ctx_pa = mem.pa;
1003 dev->cqp->host_ctx = mem.va;
1004 /* populate the cqp init info */
1005 cqp_init_info.dev = dev;
1006 cqp_init_info.sq_size = sqsize;
1007 cqp_init_info.sq = cqp->sq.va;
1008 cqp_init_info.sq_pa = cqp->sq.pa;
1009 cqp_init_info.host_ctx_pa = mem.pa;
1010 cqp_init_info.host_ctx = mem.va;
1011 cqp_init_info.hmc_profile = rf->rsrc_profile;
1012 cqp_init_info.scratch_array = cqp->scratch_array;
1013 cqp_init_info.protocol_used = rf->protocol_used;
1014 cqp_init_info.en_rem_endpoint_trk = rf->en_rem_endpoint_trk;
1015 memcpy(&cqp_init_info.dcqcn_params, &rf->dcqcn_params,
1016 sizeof(cqp_init_info.dcqcn_params));
1017
1018 switch (rf->rdma_ver) {
1019 case IRDMA_GEN_1:
1020 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1;
1021 break;
1022 case IRDMA_GEN_2:
1023 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2;
1024 break;
1025 }
1026 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info);
1027 if (status) {
1028 irdma_debug(dev, IRDMA_DEBUG_ERR, "cqp init status %d\n", status);
1029 goto err_ctx;
1030 }
1031
1032 spin_lock_init(&cqp->req_lock);
1033 spin_lock_init(&cqp->compl_lock);
1034
1035 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err);
1036 if (status) {
1037 irdma_debug(dev, IRDMA_DEBUG_ERR,
1038 "cqp create failed - status %d maj_err %d min_err %d\n",
1039 status, maj_err, min_err);
1040 goto err_ctx;
1041 }
1042
1043 INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
1044 INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
1045
1046 /* init the waitqueue of the cqp_requests and add them to the list */
1047 for (i = 0; i < sqsize; i++) {
1048 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
1049 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
1050 }
1051 init_waitqueue_head(&cqp->remove_wq);
1052 return 0;
1053
1054 err_ctx:
1055 irdma_free_dma_mem(dev->hw, &cqp->sq);
1056 err_sq:
1057 kfree(cqp->scratch_array);
1058 cqp->scratch_array = NULL;
1059 err_scratch:
1060 kfree(cqp->cqp_requests);
1061 cqp->cqp_requests = NULL;
1062
1063 return status;
1064 }
1065
1066 /**
1067 * irdma_create_ccq - create control cq
1068 * @rf: RDMA PCI function
1069 *
1070 * Return 0, if the ccq and the resources associated with it
1071 * are successfully created, otherwise return error
1072 */
1073 static int
irdma_create_ccq(struct irdma_pci_f * rf)1074 irdma_create_ccq(struct irdma_pci_f *rf)
1075 {
1076 struct irdma_sc_dev *dev = &rf->sc_dev;
1077 struct irdma_ccq_init_info info = {0};
1078 struct irdma_ccq *ccq = &rf->ccq;
1079 int status;
1080
1081 dev->ccq = &ccq->sc_cq;
1082 dev->ccq->dev = dev;
1083 info.dev = dev;
1084 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area);
1085 ccq->mem_cq.size = sizeof(struct irdma_cqe) * IW_CCQ_SIZE;
1086 ccq->mem_cq.va = irdma_allocate_dma_mem(dev->hw, &ccq->mem_cq,
1087 ccq->mem_cq.size,
1088 IRDMA_CQ0_ALIGNMENT);
1089 if (!ccq->mem_cq.va)
1090 return -ENOMEM;
1091
1092 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area,
1093 ccq->shadow_area.size,
1094 IRDMA_SHADOWAREA_M);
1095 if (status)
1096 goto exit;
1097
1098 ccq->sc_cq.back_cq = ccq;
1099 /* populate the ccq init info */
1100 info.cq_base = ccq->mem_cq.va;
1101 info.cq_pa = ccq->mem_cq.pa;
1102 info.num_elem = IW_CCQ_SIZE;
1103 info.shadow_area = ccq->shadow_area.va;
1104 info.shadow_area_pa = ccq->shadow_area.pa;
1105 info.ceqe_mask = false;
1106 info.ceq_id_valid = true;
1107 info.shadow_read_threshold = 16;
1108 info.vsi = &rf->default_vsi;
1109 status = irdma_sc_ccq_init(dev->ccq, &info);
1110 if (!status)
1111 status = irdma_sc_ccq_create(dev->ccq, 0, true, true);
1112 exit:
1113 if (status)
1114 irdma_free_dma_mem(dev->hw, &ccq->mem_cq);
1115
1116 return status;
1117 }
1118
1119 /**
1120 * irdma_alloc_set_mac - set up a mac address table entry
1121 * @iwdev: irdma device
1122 *
1123 * Allocate a mac ip entry and add it to the hw table Return 0
1124 * if successful, otherwise return error
1125 */
1126 static int
irdma_alloc_set_mac(struct irdma_device * iwdev)1127 irdma_alloc_set_mac(struct irdma_device *iwdev)
1128 {
1129 int status;
1130
1131 status = irdma_alloc_local_mac_entry(iwdev->rf,
1132 &iwdev->mac_ip_table_idx);
1133 if (!status) {
1134 status = irdma_add_local_mac_entry(iwdev->rf,
1135 (const u8 *)if_getlladdr(iwdev->netdev),
1136 (u8)iwdev->mac_ip_table_idx);
1137 if (status)
1138 irdma_del_local_mac_entry(iwdev->rf,
1139 (u8)iwdev->mac_ip_table_idx);
1140 }
1141 return status;
1142 }
1143
1144 /**
1145 * irdma_irq_request - set up the msix interrupt vector
1146 * @rf: RDMA PCI function
1147 * @msix_vec: interrupt vector information
1148 * @handler: function pointer to associate with interrupt
1149 * @argument: argument passed to the handler
1150 *
1151 * Allocate interrupt resources and setup interrupt
1152 * Return 0 if successful, otherwise return error
1153 * Note that after this function bus_describe_intr shall
1154 * be called.
1155 */
1156 static int
irdma_irq_request(struct irdma_pci_f * rf,struct irdma_msix_vector * msix_vec,driver_intr_t handler,void * argument)1157 irdma_irq_request(struct irdma_pci_f *rf,
1158 struct irdma_msix_vector *msix_vec,
1159 driver_intr_t handler, void *argument)
1160 {
1161 device_t dev = rf->dev_ctx.dev;
1162 int rid = msix_vec->idx + 1;
1163 int err, status;
1164
1165 msix_vec->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE);
1166 if (!msix_vec->res) {
1167 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR,
1168 "Unable to allocate bus resource int[%d]\n", rid);
1169 return -EINVAL;
1170 }
1171 err = bus_setup_intr(dev, msix_vec->res, INTR_TYPE_NET | INTR_MPSAFE,
1172 NULL, handler, argument, &msix_vec->tag);
1173 if (err) {
1174 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR,
1175 "Unable to register handler with %x status\n", err);
1176 status = -EINVAL;
1177 goto fail_intr;
1178 }
1179 return 0;
1180
1181 fail_intr:
1182 bus_release_resource(dev, SYS_RES_IRQ, rid, msix_vec->res);
1183 msix_vec->res = NULL;
1184
1185 return status;
1186 }
1187
1188 /**
1189 * irdma_cfg_ceq_vector - set up the msix interrupt vector for
1190 * ceq
1191 * @rf: RDMA PCI function
1192 * @iwceq: ceq associated with the vector
1193 * @ceq_id: the id number of the iwceq
1194 * @msix_vec: interrupt vector information
1195 *
1196 * Allocate interrupt resources and enable irq handling
1197 * Return 0 if successful, otherwise return error
1198 */
1199 static int
irdma_cfg_ceq_vector(struct irdma_pci_f * rf,struct irdma_ceq * iwceq,u16 ceq_id,struct irdma_msix_vector * msix_vec)1200 irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1201 u16 ceq_id, struct irdma_msix_vector *msix_vec)
1202 {
1203 int status;
1204
1205 if (rf->msix_shared && !ceq_id) {
1206 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1207 "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev));
1208 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1209 status = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf);
1210 if (status)
1211 return status;
1212 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name);
1213 } else {
1214 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1215 "irdma-%s-CEQ-%d",
1216 dev_name(&rf->pcidev->dev), ceq_id);
1217 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc);
1218
1219 status = irdma_irq_request(rf, msix_vec, irdma_ceq_handler, iwceq);
1220 if (status)
1221 return status;
1222 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name);
1223 }
1224 msix_vec->ceq_id = ceq_id;
1225 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true);
1226
1227 return 0;
1228 }
1229
1230 /**
1231 * irdma_cfg_aeq_vector - set up the msix vector for aeq
1232 * @rf: RDMA PCI function
1233 *
1234 * Allocate interrupt resources and enable irq handling
1235 * Return 0 if successful, otherwise return error
1236 */
1237 static int
irdma_cfg_aeq_vector(struct irdma_pci_f * rf)1238 irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
1239 {
1240 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl;
1241 int status = 0;
1242
1243 if (!rf->msix_shared) {
1244 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1245 "irdma-%s-AEQ", dev_name(&rf->pcidev->dev));
1246 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1247 status = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf);
1248 if (status)
1249 return status;
1250 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name);
1251 }
1252
1253 if (status) {
1254 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, "aeq irq config fail\n");
1255 return status;
1256 }
1257
1258 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true);
1259
1260 return 0;
1261 }
1262
1263 /**
1264 * irdma_create_ceq - create completion event queue
1265 * @rf: RDMA PCI function
1266 * @iwceq: pointer to the ceq resources to be created
1267 * @ceq_id: the id number of the iwceq
1268 * @vsi: SC vsi struct
1269 *
1270 * Return 0, if the ceq and the resources associated with it
1271 * are successfully created, otherwise return error
1272 */
1273 static int
irdma_create_ceq(struct irdma_pci_f * rf,struct irdma_ceq * iwceq,u16 ceq_id,struct irdma_sc_vsi * vsi)1274 irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1275 u16 ceq_id, struct irdma_sc_vsi *vsi)
1276 {
1277 int status;
1278 struct irdma_ceq_init_info info = {0};
1279 struct irdma_sc_dev *dev = &rf->sc_dev;
1280 u64 scratch;
1281 u32 ceq_size;
1282
1283 info.ceq_id = ceq_id;
1284 iwceq->rf = rf;
1285 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
1286 dev->hw_attrs.max_hw_ceq_size);
1287 iwceq->mem.size = sizeof(struct irdma_ceqe) * ceq_size;
1288 iwceq->mem.va = irdma_allocate_dma_mem(dev->hw, &iwceq->mem,
1289 iwceq->mem.size,
1290 IRDMA_CEQ_ALIGNMENT);
1291 if (!iwceq->mem.va)
1292 return -ENOMEM;
1293
1294 info.ceq_id = ceq_id;
1295 info.ceqe_base = iwceq->mem.va;
1296 info.ceqe_pa = iwceq->mem.pa;
1297 info.elem_cnt = ceq_size;
1298 info.reg_cq = kzalloc(sizeof(struct irdma_sc_cq *) * info.elem_cnt, GFP_KERNEL);
1299
1300 iwceq->sc_ceq.ceq_id = ceq_id;
1301 info.dev = dev;
1302 info.vsi = vsi;
1303 scratch = (uintptr_t)&rf->cqp.sc_cqp;
1304 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info);
1305 if (!status) {
1306 if (dev->ceq_valid)
1307 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
1308 IRDMA_OP_CEQ_CREATE);
1309 else
1310 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch);
1311 }
1312
1313 if (status) {
1314 kfree(info.reg_cq);
1315 irdma_free_dma_mem(dev->hw, &iwceq->mem);
1316 }
1317
1318 return status;
1319 }
1320
1321 /**
1322 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource
1323 * @rf: RDMA PCI function
1324 *
1325 * Allocate a list for all device completion event queues
1326 * Create the ceq 0 and configure it's msix interrupt vector
1327 * Return 0, if successfully set up, otherwise return error
1328 */
1329 static int
irdma_setup_ceq_0(struct irdma_pci_f * rf)1330 irdma_setup_ceq_0(struct irdma_pci_f *rf)
1331 {
1332 struct irdma_ceq *iwceq;
1333 struct irdma_msix_vector *msix_vec;
1334 u32 i;
1335 int status = 0;
1336 u32 num_ceqs;
1337
1338 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1339 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL);
1340 memset(rf->ceqlist, 0, num_ceqs * sizeof(*rf->ceqlist));
1341 if (!rf->ceqlist) {
1342 status = -ENOMEM;
1343 goto exit;
1344 }
1345
1346 iwceq = &rf->ceqlist[0];
1347 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi);
1348 if (status) {
1349 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR,
1350 "create ceq status = %d\n", status);
1351 goto exit;
1352 }
1353
1354 spin_lock_init(&iwceq->ce_lock);
1355 i = rf->msix_shared ? 0 : 1;
1356 msix_vec = &rf->iw_msixtbl[i];
1357 iwceq->irq = msix_vec->irq;
1358 iwceq->msix_idx = msix_vec->idx;
1359 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec);
1360 if (status) {
1361 irdma_destroy_ceq(rf, iwceq);
1362 goto exit;
1363 }
1364
1365 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1366 rf->ceqs_count++;
1367
1368 exit:
1369 if (status && !rf->ceqs_count) {
1370 kfree(rf->ceqlist);
1371 rf->ceqlist = NULL;
1372 return status;
1373 }
1374 rf->sc_dev.ceq_valid = true;
1375
1376 return 0;
1377 }
1378
1379 /**
1380 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources
1381 * @rf: RDMA PCI function
1382 * @vsi: VSI structure for this CEQ
1383 *
1384 * Allocate a list for all device completion event queues
1385 * Create the ceq's and configure their msix interrupt vectors
1386 * Return 0, if ceqs are successfully set up, otherwise return error
1387 */
1388 static int
irdma_setup_ceqs(struct irdma_pci_f * rf,struct irdma_sc_vsi * vsi)1389 irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi)
1390 {
1391 u32 i;
1392 u16 ceq_id;
1393 struct irdma_ceq *iwceq;
1394 struct irdma_msix_vector *msix_vec;
1395 int status;
1396 u32 num_ceqs;
1397
1398 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1399 i = (rf->msix_shared) ? 1 : 2;
1400 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) {
1401 iwceq = &rf->ceqlist[ceq_id];
1402 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi);
1403 if (status) {
1404 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR,
1405 "create ceq status = %d\n", status);
1406 goto del_ceqs;
1407 }
1408 spin_lock_init(&iwceq->ce_lock);
1409 msix_vec = &rf->iw_msixtbl[i];
1410 iwceq->irq = msix_vec->irq;
1411 iwceq->msix_idx = msix_vec->idx;
1412 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec);
1413 if (status) {
1414 irdma_destroy_ceq(rf, iwceq);
1415 goto del_ceqs;
1416 }
1417 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1418 rf->ceqs_count++;
1419 }
1420
1421 return 0;
1422
1423 del_ceqs:
1424 irdma_del_ceqs(rf);
1425
1426 return status;
1427 }
1428
1429 static int
irdma_create_virt_aeq(struct irdma_pci_f * rf,u32 size)1430 irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size)
1431 {
1432 struct irdma_aeq *aeq = &rf->aeq;
1433 dma_addr_t *pg_arr;
1434 u32 pg_cnt;
1435 int status;
1436
1437 if (rf->rdma_ver < IRDMA_GEN_2)
1438 return -EOPNOTSUPP;
1439
1440 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size;
1441 aeq->mem.va = vzalloc(aeq->mem.size);
1442
1443 if (!aeq->mem.va)
1444 return -ENOMEM;
1445
1446 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
1447 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true);
1448 if (status) {
1449 vfree(aeq->mem.va);
1450 return status;
1451 }
1452
1453 pg_arr = (dma_addr_t *) aeq->palloc.level1.addr;
1454 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt);
1455 if (status) {
1456 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
1457 vfree(aeq->mem.va);
1458 return status;
1459 }
1460
1461 return 0;
1462 }
1463
1464 /**
1465 * irdma_create_aeq - create async event queue
1466 * @rf: RDMA PCI function
1467 *
1468 * Return 0, if the aeq and the resources associated with it
1469 * are successfully created, otherwise return error
1470 */
1471 static int
irdma_create_aeq(struct irdma_pci_f * rf)1472 irdma_create_aeq(struct irdma_pci_f *rf)
1473 {
1474 struct irdma_aeq_init_info info = {0};
1475 struct irdma_sc_dev *dev = &rf->sc_dev;
1476 struct irdma_aeq *aeq = &rf->aeq;
1477 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info;
1478 u32 aeq_size;
1479 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1;
1480 int status;
1481
1482 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt +
1483 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
1484 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size);
1485
1486 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * aeq_size;
1487 aeq->mem.va = irdma_allocate_dma_mem(dev->hw, &aeq->mem, aeq->mem.size,
1488 IRDMA_AEQ_ALIGNMENT);
1489 if (aeq->mem.va)
1490 goto skip_virt_aeq;
1491
1492 /* physically mapped aeq failed. setup virtual aeq */
1493 status = irdma_create_virt_aeq(rf, aeq_size);
1494 if (status)
1495 return status;
1496
1497 info.virtual_map = true;
1498 aeq->virtual_map = info.virtual_map;
1499 info.pbl_chunk_size = 1;
1500 info.first_pm_pbl_idx = aeq->palloc.level1.idx;
1501
1502 skip_virt_aeq:
1503 info.aeqe_base = aeq->mem.va;
1504 info.aeq_elem_pa = aeq->mem.pa;
1505 info.elem_cnt = aeq_size;
1506 info.dev = dev;
1507 info.msix_idx = rf->iw_msixtbl->idx;
1508 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info);
1509 if (status)
1510 goto err;
1511
1512 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE);
1513 if (status)
1514 goto err;
1515
1516 return 0;
1517
1518 err:
1519 if (aeq->virtual_map)
1520 irdma_destroy_virt_aeq(rf);
1521 else
1522 irdma_free_dma_mem(dev->hw, &aeq->mem);
1523
1524 return status;
1525 }
1526
1527 /**
1528 * irdma_setup_aeq - set up the device aeq
1529 * @rf: RDMA PCI function
1530 *
1531 * Create the aeq and configure its msix interrupt vector
1532 * Return 0 if successful, otherwise return error
1533 */
1534 static int
irdma_setup_aeq(struct irdma_pci_f * rf)1535 irdma_setup_aeq(struct irdma_pci_f *rf)
1536 {
1537 struct irdma_sc_dev *dev = &rf->sc_dev;
1538 int status;
1539
1540 status = irdma_create_aeq(rf);
1541 if (status)
1542 return status;
1543
1544 status = irdma_cfg_aeq_vector(rf);
1545 if (status) {
1546 irdma_destroy_aeq(rf);
1547 return status;
1548 }
1549
1550 if (!rf->msix_shared)
1551 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx);
1552
1553 return 0;
1554 }
1555
1556 /**
1557 * irdma_initialize_ilq - create iwarp local queue for cm
1558 * @iwdev: irdma device
1559 *
1560 * Return 0 if successful, otherwise return error
1561 */
1562 static int
irdma_initialize_ilq(struct irdma_device * iwdev)1563 irdma_initialize_ilq(struct irdma_device *iwdev)
1564 {
1565 struct irdma_puda_rsrc_info info = {0};
1566 int status;
1567
1568 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ;
1569 info.cq_id = 1;
1570 info.qp_id = 1;
1571 info.count = 1;
1572 info.pd_id = 1;
1573 info.abi_ver = IRDMA_ABI_VER;
1574 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1575 info.rq_size = info.sq_size;
1576 info.buf_size = 1024;
1577 info.tx_buf_cnt = 2 * info.sq_size;
1578 info.receive = irdma_receive_ilq;
1579 info.xmit_complete = irdma_free_sqbuf;
1580 status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1581 if (status)
1582 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, "ilq create fail\n");
1583
1584 return status;
1585 }
1586
1587 /**
1588 * irdma_initialize_ieq - create iwarp exception queue
1589 * @iwdev: irdma device
1590 *
1591 * Return 0 if successful, otherwise return error
1592 */
1593 static int
irdma_initialize_ieq(struct irdma_device * iwdev)1594 irdma_initialize_ieq(struct irdma_device *iwdev)
1595 {
1596 struct irdma_puda_rsrc_info info = {0};
1597 int status;
1598
1599 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ;
1600 info.cq_id = 2;
1601 info.qp_id = iwdev->vsi.exception_lan_q;
1602 info.count = 1;
1603 info.pd_id = 2;
1604 info.abi_ver = IRDMA_ABI_VER;
1605 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1606 info.rq_size = info.sq_size;
1607 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD;
1608 info.tx_buf_cnt = 4096;
1609 status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1610 if (status)
1611 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, "ieq create fail\n");
1612
1613 return status;
1614 }
1615
1616 /**
1617 * irdma_reinitialize_ieq - destroy and re-create ieq
1618 * @vsi: VSI structure
1619 */
1620 void
irdma_reinitialize_ieq(struct irdma_sc_vsi * vsi)1621 irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi)
1622 {
1623 struct irdma_device *iwdev = vsi->back_vsi;
1624 struct irdma_pci_f *rf = iwdev->rf;
1625
1626 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false);
1627 if (irdma_initialize_ieq(iwdev)) {
1628 iwdev->rf->reset = true;
1629 rf->gen_ops.request_reset(rf);
1630 }
1631 }
1632
1633 /**
1634 * irdma_hmc_setup - create hmc objects for the device
1635 * @rf: RDMA PCI function
1636 *
1637 * Set up the device private memory space for the number and size of
1638 * the hmc objects and create the objects
1639 * Return 0 if successful, otherwise return error
1640 */
1641 static int
irdma_hmc_setup(struct irdma_pci_f * rf)1642 irdma_hmc_setup(struct irdma_pci_f *rf)
1643 {
1644 struct irdma_sc_dev *dev = &rf->sc_dev;
1645 int status;
1646 u32 qpcnt;
1647
1648 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit;
1649
1650 rf->sd_type = IRDMA_SD_TYPE_DIRECT;
1651 status = irdma_cfg_fpm_val(dev, qpcnt);
1652 if (status)
1653 return status;
1654
1655 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver);
1656
1657 return status;
1658 }
1659
1660 /**
1661 * irdma_del_init_mem - deallocate memory resources
1662 * @rf: RDMA PCI function
1663 */
1664 static void
irdma_del_init_mem(struct irdma_pci_f * rf)1665 irdma_del_init_mem(struct irdma_pci_f *rf)
1666 {
1667 struct irdma_sc_dev *dev = &rf->sc_dev;
1668
1669 kfree(dev->hmc_info->sd_table.sd_entry);
1670 dev->hmc_info->sd_table.sd_entry = NULL;
1671 vfree(rf->mem_rsrc);
1672 rf->mem_rsrc = NULL;
1673 irdma_free_dma_mem(&rf->hw, &rf->obj_mem);
1674 if (rf->rdma_ver != IRDMA_GEN_1) {
1675 kfree(rf->allocated_ws_nodes);
1676 rf->allocated_ws_nodes = NULL;
1677 }
1678 mutex_destroy(&dev->ws_mutex);
1679 kfree(rf->ceqlist);
1680 rf->ceqlist = NULL;
1681 kfree(rf->iw_msixtbl);
1682 rf->iw_msixtbl = NULL;
1683 kfree(rf->hmc_info_mem);
1684 rf->hmc_info_mem = NULL;
1685 }
1686 /**
1687 * irdma_initialize_dev - initialize device
1688 * @rf: RDMA PCI function
1689 *
1690 * Allocate memory for the hmc objects and initialize iwdev
1691 * Return 0 if successful, otherwise clean up the resources
1692 * and return error
1693 */
1694 static int
irdma_initialize_dev(struct irdma_pci_f * rf)1695 irdma_initialize_dev(struct irdma_pci_f *rf)
1696 {
1697 int status;
1698 struct irdma_sc_dev *dev = &rf->sc_dev;
1699 struct irdma_device_init_info info = {0};
1700 struct irdma_dma_mem mem;
1701 u32 size;
1702
1703 size = sizeof(struct irdma_hmc_pble_rsrc) +
1704 sizeof(struct irdma_hmc_info) +
1705 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX);
1706
1707 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1708 if (!rf->hmc_info_mem)
1709 return -ENOMEM;
1710
1711 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem;
1712 dev->hmc_info = &rf->hw.hmc;
1713 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *)
1714 (rf->pble_rsrc + 1);
1715
1716 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE,
1717 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M);
1718 if (status)
1719 goto error;
1720
1721 info.fpm_query_buf_pa = mem.pa;
1722 info.fpm_query_buf = mem.va;
1723
1724 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE,
1725 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M);
1726 if (status)
1727 goto error;
1728
1729 info.fpm_commit_buf_pa = mem.pa;
1730 info.fpm_commit_buf = mem.va;
1731
1732 info.bar0 = rf->hw.hw_addr;
1733 info.hmc_fn_id = rf->peer_info->pf_id;
1734 /*
1735 * the debug_mask is already assigned at this point through sysctl and so the value shouldn't be overwritten
1736 */
1737 info.debug_mask = rf->sc_dev.debug_mask;
1738 info.hw = &rf->hw;
1739 status = irdma_sc_dev_init(&rf->sc_dev, &info);
1740 if (status)
1741 goto error;
1742
1743 return status;
1744 error:
1745 kfree(rf->hmc_info_mem);
1746 rf->hmc_info_mem = NULL;
1747
1748 return status;
1749 }
1750
1751 /**
1752 * irdma_rt_deinit_hw - clean up the irdma device resources
1753 * @iwdev: irdma device
1754 *
1755 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the
1756 * device queues and free the pble and the hmc objects
1757 */
1758 void
irdma_rt_deinit_hw(struct irdma_device * iwdev)1759 irdma_rt_deinit_hw(struct irdma_device *iwdev)
1760 {
1761 struct irdma_sc_qp qp = {{0}};
1762
1763 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_INIT, "state = %d\n", iwdev->init_state);
1764
1765 switch (iwdev->init_state) {
1766 case IP_ADDR_REGISTERED:
1767 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1768 irdma_del_local_mac_entry(iwdev->rf,
1769 (u8)iwdev->mac_ip_table_idx);
1770 /* fallthrough */
1771 case AEQ_CREATED:
1772 case PBLE_CHUNK_MEM:
1773 case CEQS_CREATED:
1774 case REM_ENDPOINT_TRK_CREATED:
1775 if (iwdev->rf->en_rem_endpoint_trk) {
1776 qp.dev = &iwdev->rf->sc_dev;
1777 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID;
1778 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP;
1779 irdma_cqp_qp_destroy_cmd(qp.dev, &qp);
1780 }
1781 /* fallthrough */
1782 case IEQ_CREATED:
1783 if (!iwdev->roce_mode)
1784 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ,
1785 iwdev->rf->reset);
1786 /* fallthrough */
1787 case ILQ_CREATED:
1788 if (!iwdev->roce_mode)
1789 irdma_puda_dele_rsrc(&iwdev->vsi,
1790 IRDMA_PUDA_RSRC_TYPE_ILQ,
1791 iwdev->rf->reset);
1792 break;
1793 default:
1794 irdma_dev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state);
1795 break;
1796 }
1797
1798 irdma_cleanup_cm_core(&iwdev->cm_core);
1799 if (iwdev->vsi.pestat) {
1800 irdma_vsi_stats_free(&iwdev->vsi);
1801 kfree(iwdev->vsi.pestat);
1802 }
1803 if (iwdev->cleanup_wq)
1804 destroy_workqueue(iwdev->cleanup_wq);
1805 }
1806
1807 static int
irdma_setup_init_state(struct irdma_pci_f * rf)1808 irdma_setup_init_state(struct irdma_pci_f *rf)
1809 {
1810 int status;
1811
1812 status = irdma_save_msix_info(rf);
1813 if (status)
1814 return status;
1815
1816 rf->obj_mem.size = 8192;
1817 rf->obj_mem.va = irdma_allocate_dma_mem(&rf->hw, &rf->obj_mem,
1818 rf->obj_mem.size,
1819 IRDMA_HW_PAGE_SIZE);
1820 if (!rf->obj_mem.va) {
1821 status = -ENOMEM;
1822 goto clean_msixtbl;
1823 }
1824
1825 rf->obj_next = rf->obj_mem;
1826 status = irdma_initialize_dev(rf);
1827 if (status)
1828 goto clean_obj_mem;
1829
1830 return 0;
1831
1832 clean_obj_mem:
1833 irdma_free_dma_mem(&rf->hw, &rf->obj_mem);
1834 clean_msixtbl:
1835 kfree(rf->iw_msixtbl);
1836 rf->iw_msixtbl = NULL;
1837 return status;
1838 }
1839
1840 /**
1841 * irdma_get_used_rsrc - determine resources used internally
1842 * @iwdev: irdma device
1843 *
1844 * Called at the end of open to get all internal allocations
1845 */
1846 static void
irdma_get_used_rsrc(struct irdma_device * iwdev)1847 irdma_get_used_rsrc(struct irdma_device *iwdev)
1848 {
1849 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds,
1850 iwdev->rf->max_pd);
1851 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps,
1852 iwdev->rf->max_qp);
1853 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs,
1854 iwdev->rf->max_cq);
1855 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs,
1856 iwdev->rf->max_mr);
1857 }
1858
1859 void
irdma_ctrl_deinit_hw(struct irdma_pci_f * rf)1860 irdma_ctrl_deinit_hw(struct irdma_pci_f *rf)
1861 {
1862 enum init_completion_state state = rf->init_state;
1863
1864 rf->init_state = INVALID_STATE;
1865 if (rf->rsrc_created) {
1866 irdma_destroy_aeq(rf);
1867 irdma_destroy_pble_prm(rf->pble_rsrc);
1868 irdma_del_ceqs(rf);
1869 rf->rsrc_created = false;
1870 }
1871
1872 switch (state) {
1873 case CEQ0_CREATED:
1874 irdma_del_ceq_0(rf);
1875 /* fallthrough */
1876 case CCQ_CREATED:
1877 irdma_destroy_ccq(rf);
1878 /* fallthrough */
1879 case HW_RSRC_INITIALIZED:
1880 case HMC_OBJS_CREATED:
1881 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true,
1882 rf->reset, rf->rdma_ver);
1883 /* fallthrough */
1884 case CQP_CREATED:
1885 irdma_destroy_cqp(rf, !rf->reset);
1886 /* fallthrough */
1887 case INITIAL_STATE:
1888 irdma_del_init_mem(rf);
1889 break;
1890 case INVALID_STATE:
1891 default:
1892 irdma_dev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state);
1893 break;
1894 }
1895 }
1896
1897 /**
1898 * irdma_rt_init_hw - Initializes runtime portion of HW
1899 * @iwdev: irdma device
1900 * @l2params: qos, tc, mtu info from netdev driver
1901 *
1902 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma
1903 * device resource objects.
1904 */
1905 int
irdma_rt_init_hw(struct irdma_device * iwdev,struct irdma_l2params * l2params)1906 irdma_rt_init_hw(struct irdma_device *iwdev,
1907 struct irdma_l2params *l2params)
1908 {
1909 struct irdma_pci_f *rf = iwdev->rf;
1910 struct irdma_sc_dev *dev = &rf->sc_dev;
1911 struct irdma_sc_qp qp = {{0}};
1912 struct irdma_vsi_init_info vsi_info = {0};
1913 struct irdma_vsi_stats_info stats_info = {0};
1914 int status;
1915
1916 vsi_info.dev = dev;
1917 vsi_info.back_vsi = iwdev;
1918 vsi_info.params = l2params;
1919 vsi_info.pf_data_vsi_num = iwdev->vsi_num;
1920 vsi_info.register_qset = rf->gen_ops.register_qset;
1921 vsi_info.unregister_qset = rf->gen_ops.unregister_qset;
1922 vsi_info.exception_lan_q = 2;
1923 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info);
1924
1925 status = irdma_setup_cm_core(iwdev, rf->rdma_ver);
1926 if (status)
1927 return status;
1928
1929 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1930 if (!stats_info.pestat) {
1931 irdma_cleanup_cm_core(&iwdev->cm_core);
1932 return -ENOMEM;
1933 }
1934 stats_info.fcn_id = dev->hmc_fn_id;
1935 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info);
1936 if (status) {
1937 irdma_cleanup_cm_core(&iwdev->cm_core);
1938 kfree(stats_info.pestat);
1939 return status;
1940 }
1941
1942 do {
1943 if (!iwdev->roce_mode) {
1944 status = irdma_initialize_ilq(iwdev);
1945 if (status)
1946 break;
1947 iwdev->init_state = ILQ_CREATED;
1948 status = irdma_initialize_ieq(iwdev);
1949 if (status)
1950 break;
1951 iwdev->init_state = IEQ_CREATED;
1952 }
1953 if (iwdev->rf->en_rem_endpoint_trk) {
1954 qp.dev = dev;
1955 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID;
1956 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP;
1957 status = irdma_cqp_qp_create_cmd(dev, &qp);
1958 if (status)
1959 break;
1960 iwdev->init_state = REM_ENDPOINT_TRK_CREATED;
1961 }
1962 if (!rf->rsrc_created) {
1963 status = irdma_setup_ceqs(rf, &iwdev->vsi);
1964 if (status)
1965 break;
1966
1967 iwdev->init_state = CEQS_CREATED;
1968
1969 status = irdma_hmc_init_pble(&rf->sc_dev,
1970 rf->pble_rsrc);
1971 if (status) {
1972 irdma_del_ceqs(rf);
1973 break;
1974 }
1975
1976 iwdev->init_state = PBLE_CHUNK_MEM;
1977
1978 status = irdma_setup_aeq(rf);
1979 if (status) {
1980 irdma_destroy_pble_prm(rf->pble_rsrc);
1981 irdma_del_ceqs(rf);
1982 break;
1983 }
1984 iwdev->init_state = AEQ_CREATED;
1985 rf->rsrc_created = true;
1986 }
1987
1988 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1989 irdma_alloc_set_mac(iwdev);
1990 irdma_add_ip(iwdev);
1991 iwdev->init_state = IP_ADDR_REGISTERED;
1992
1993 /*
1994 * handles asynch cleanup tasks - disconnect CM , free qp, free cq bufs
1995 */
1996 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq",
1997 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
1998 if (!iwdev->cleanup_wq)
1999 return -ENOMEM;
2000 irdma_get_used_rsrc(iwdev);
2001 init_waitqueue_head(&iwdev->suspend_wq);
2002
2003 return 0;
2004 } while (0);
2005
2006 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n",
2007 status, iwdev->init_state);
2008 irdma_rt_deinit_hw(iwdev);
2009
2010 return status;
2011 }
2012
2013 /**
2014 * irdma_ctrl_init_hw - Initializes control portion of HW
2015 * @rf: RDMA PCI function
2016 *
2017 * Create admin queues, HMC obejcts and RF resource objects
2018 */
2019 int
irdma_ctrl_init_hw(struct irdma_pci_f * rf)2020 irdma_ctrl_init_hw(struct irdma_pci_f *rf)
2021 {
2022 struct irdma_sc_dev *dev = &rf->sc_dev;
2023 int status;
2024
2025 do {
2026 status = irdma_setup_init_state(rf);
2027 if (status)
2028 break;
2029 rf->init_state = INITIAL_STATE;
2030
2031 status = irdma_create_cqp(rf);
2032 if (status)
2033 break;
2034 rf->init_state = CQP_CREATED;
2035
2036 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT;
2037 if (rf->rdma_ver != IRDMA_GEN_1) {
2038 status = irdma_get_rdma_features(dev);
2039 if (status)
2040 break;
2041 }
2042
2043 status = irdma_hmc_setup(rf);
2044 if (status)
2045 break;
2046 rf->init_state = HMC_OBJS_CREATED;
2047
2048 status = irdma_initialize_hw_rsrc(rf);
2049 if (status)
2050 break;
2051 rf->init_state = HW_RSRC_INITIALIZED;
2052
2053 status = irdma_create_ccq(rf);
2054 if (status)
2055 break;
2056 rf->init_state = CCQ_CREATED;
2057
2058 status = irdma_setup_ceq_0(rf);
2059 if (status)
2060 break;
2061 rf->init_state = CEQ0_CREATED;
2062 /* Handles processing of CQP completions */
2063 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq",
2064 WQ_HIGHPRI | WQ_UNBOUND);
2065 if (!rf->cqp_cmpl_wq) {
2066 status = -ENOMEM;
2067 break;
2068 }
2069 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker);
2070 irdma_sc_ccq_arm(dev->ccq);
2071 return 0;
2072 } while (0);
2073
2074 pr_err("IRDMA hardware initialization FAILED init_state=%d status=%d\n",
2075 rf->init_state, status);
2076 irdma_ctrl_deinit_hw(rf);
2077 return status;
2078 }
2079
2080 /**
2081 * irdma_set_hw_rsrc - set hw memory resources.
2082 * @rf: RDMA PCI function
2083 */
2084 static void
irdma_set_hw_rsrc(struct irdma_pci_f * rf)2085 irdma_set_hw_rsrc(struct irdma_pci_f *rf)
2086 {
2087 rf->allocated_qps = (void *)(rf->mem_rsrc +
2088 (sizeof(struct irdma_arp_entry) * rf->arp_table_size));
2089 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)];
2090 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];
2091 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)];
2092 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)];
2093 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)];
2094 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)];
2095
2096 rf->qp_table = (struct irdma_qp **)
2097 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]);
2098 rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]);
2099
2100 spin_lock_init(&rf->rsrc_lock);
2101 spin_lock_init(&rf->arp_lock);
2102 spin_lock_init(&rf->qptable_lock);
2103 spin_lock_init(&rf->cqtable_lock);
2104 spin_lock_init(&rf->qh_list_lock);
2105 }
2106
2107 /**
2108 * irdma_calc_mem_rsrc_size - calculate memory resources size.
2109 * @rf: RDMA PCI function
2110 */
irdma_calc_mem_rsrc_size(struct irdma_pci_f * rf)2111 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf){
2112 u32 rsrc_size;
2113
2114 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size;
2115 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp);
2116 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr);
2117 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq);
2118 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd);
2119 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size);
2120 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah);
2121 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg);
2122 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp;
2123 rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq;
2124
2125 return rsrc_size;
2126 }
2127
2128 /**
2129 * irdma_initialize_hw_rsrc - initialize hw resource tracking array
2130 * @rf: RDMA PCI function
2131 */
2132 u32
irdma_initialize_hw_rsrc(struct irdma_pci_f * rf)2133 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf)
2134 {
2135 u32 rsrc_size;
2136 u32 mrdrvbits;
2137 u32 ret;
2138
2139 if (rf->rdma_ver != IRDMA_GEN_1) {
2140 rf->allocated_ws_nodes =
2141 kcalloc(BITS_TO_LONGS(IRDMA_MAX_WS_NODES),
2142 sizeof(unsigned long), GFP_KERNEL);
2143 if (!rf->allocated_ws_nodes)
2144 return -ENOMEM;
2145
2146 set_bit(0, rf->allocated_ws_nodes);
2147 rf->max_ws_node_id = IRDMA_MAX_WS_NODES;
2148 }
2149 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size;
2150 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt;
2151 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt;
2152 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
2153 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds;
2154 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt;
2155 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt;
2156 rf->max_mcg = rf->max_qp;
2157
2158 rsrc_size = irdma_calc_mem_rsrc_size(rf);
2159 rf->mem_rsrc = vzalloc(rsrc_size);
2160 if (!rf->mem_rsrc) {
2161 ret = -ENOMEM;
2162 goto mem_rsrc_vmalloc_fail;
2163 }
2164
2165 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc;
2166
2167 irdma_set_hw_rsrc(rf);
2168
2169 set_bit(0, rf->allocated_mrs);
2170 set_bit(0, rf->allocated_qps);
2171 set_bit(0, rf->allocated_cqs);
2172 set_bit(0, rf->allocated_pds);
2173 set_bit(0, rf->allocated_arps);
2174 set_bit(0, rf->allocated_ahs);
2175 set_bit(0, rf->allocated_mcgs);
2176 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */
2177 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */
2178 set_bit(IRDMA_REM_ENDPOINT_TRK_QPID, rf->allocated_qps); /* qp 3 Remote Endpt trk */
2179 set_bit(1, rf->allocated_cqs);
2180 set_bit(1, rf->allocated_pds);
2181 set_bit(2, rf->allocated_cqs);
2182 set_bit(2, rf->allocated_pds);
2183
2184 INIT_LIST_HEAD(&rf->mc_qht_list.list);
2185 /* stag index mask has a minimum of 14 bits */
2186 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
2187 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
2188
2189 return 0;
2190
2191 mem_rsrc_vmalloc_fail:
2192 kfree(rf->allocated_ws_nodes);
2193 rf->allocated_ws_nodes = NULL;
2194
2195 return ret;
2196 }
2197
2198 /**
2199 * irdma_cqp_ce_handler - handle cqp completions
2200 * @rf: RDMA PCI function
2201 * @cq: cq for cqp completions
2202 */
2203 void
irdma_cqp_ce_handler(struct irdma_pci_f * rf,struct irdma_sc_cq * cq)2204 irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
2205 {
2206 struct irdma_cqp_request *cqp_request;
2207 struct irdma_sc_dev *dev = &rf->sc_dev;
2208 u32 cqe_count = 0;
2209 struct irdma_ccq_cqe_info info;
2210 unsigned long flags;
2211 int ret;
2212
2213 do {
2214 memset(&info, 0, sizeof(info));
2215 spin_lock_irqsave(&rf->cqp.compl_lock, flags);
2216 ret = irdma_sc_ccq_get_cqe_info(cq, &info);
2217 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags);
2218 if (ret)
2219 break;
2220
2221 cqp_request = (struct irdma_cqp_request *)
2222 (uintptr_t)info.scratch;
2223 if (info.error && irdma_cqp_crit_err(dev,
2224 cqp_request->info.cqp_cmd,
2225 info.maj_err_code,
2226 info.min_err_code))
2227 irdma_dev_err(&rf->iwdev->ibdev,
2228 "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
2229 info.op_code, info.maj_err_code,
2230 info.min_err_code);
2231 if (cqp_request) {
2232 cqp_request->compl_info.maj_err_code =
2233 info.maj_err_code;
2234 cqp_request->compl_info.min_err_code =
2235 info.min_err_code;
2236 cqp_request->compl_info.op_ret_val = info.op_ret_val;
2237 cqp_request->compl_info.error = info.error;
2238 irdma_complete_cqp_request(&rf->cqp, cqp_request);
2239 }
2240
2241 cqe_count++;
2242 } while (1);
2243
2244 if (cqe_count) {
2245 irdma_process_bh(dev);
2246 irdma_sc_ccq_arm(dev->ccq);
2247 }
2248 }
2249
2250 /**
2251 * cqp_compl_worker - Handle cqp completions
2252 * @work: Pointer to work structure
2253 */
2254 void
cqp_compl_worker(struct work_struct * work)2255 cqp_compl_worker(struct work_struct *work)
2256 {
2257 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f,
2258 cqp_cmpl_work);
2259 struct irdma_sc_cq *cq = &rf->ccq.sc_cq;
2260
2261 irdma_cqp_ce_handler(rf, cq);
2262 }
2263
2264 /**
2265 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port
2266 * @cm_core: cm's core
2267 * @port: port to identify apbvt entry
2268 */
2269 static struct irdma_apbvt_entry *
irdma_lookup_apbvt_entry(struct irdma_cm_core * cm_core,u16 port)2270 irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core,
2271 u16 port)
2272 {
2273 struct irdma_apbvt_entry *entry;
2274
2275 HASH_FOR_EACH_POSSIBLE(cm_core->apbvt_hash_tbl, entry, hlist, port) {
2276 if (entry->port == port) {
2277 entry->use_cnt++;
2278 return entry;
2279 }
2280 }
2281
2282 return NULL;
2283 }
2284
2285 /**
2286 * irdma_next_iw_state - modify qp state
2287 * @iwqp: iwarp qp to modify
2288 * @state: next state for qp
2289 * @del_hash: del hash
2290 * @term: term message
2291 * @termlen: length of term message
2292 */
2293 void
irdma_next_iw_state(struct irdma_qp * iwqp,u8 state,u8 del_hash,u8 term,u8 termlen)2294 irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
2295 u8 termlen)
2296 {
2297 struct irdma_modify_qp_info info = {0};
2298
2299 info.next_iwarp_state = state;
2300 info.remove_hash_idx = del_hash;
2301 info.cq_num_valid = true;
2302 info.arp_cache_idx_valid = true;
2303 info.dont_send_term = true;
2304 info.dont_send_fin = true;
2305 info.termlen = termlen;
2306
2307 if (term & IRDMAQP_TERM_SEND_TERM_ONLY)
2308 info.dont_send_term = false;
2309 if (term & IRDMAQP_TERM_SEND_FIN_ONLY)
2310 info.dont_send_fin = false;
2311 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR)
2312 info.reset_tcp_conn = true;
2313 iwqp->hw_iwarp_state = state;
2314 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
2315 iwqp->iwarp_state = info.next_iwarp_state;
2316 }
2317
2318 /**
2319 * irdma_del_local_mac_entry - remove a mac entry from the hw
2320 * table
2321 * @rf: RDMA PCI function
2322 * @idx: the index of the mac ip address to delete
2323 */
2324 void
irdma_del_local_mac_entry(struct irdma_pci_f * rf,u16 idx)2325 irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx)
2326 {
2327 struct irdma_cqp *iwcqp = &rf->cqp;
2328 struct irdma_cqp_request *cqp_request;
2329 struct cqp_cmds_info *cqp_info;
2330
2331 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2332 if (!cqp_request)
2333 return;
2334
2335 cqp_info = &cqp_request->info;
2336 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY;
2337 cqp_info->post_sq = 1;
2338 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp;
2339 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request;
2340 cqp_info->in.u.del_local_mac_entry.entry_idx = idx;
2341 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0;
2342
2343 irdma_handle_cqp_op(rf, cqp_request);
2344 irdma_put_cqp_request(iwcqp, cqp_request);
2345 }
2346
2347 /**
2348 * irdma_add_local_mac_entry - add a mac ip address entry to the
2349 * hw table
2350 * @rf: RDMA PCI function
2351 * @mac_addr: pointer to mac address
2352 * @idx: the index of the mac ip address to add
2353 */
2354 int
irdma_add_local_mac_entry(struct irdma_pci_f * rf,const u8 * mac_addr,u16 idx)2355 irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx)
2356 {
2357 struct irdma_local_mac_entry_info *info;
2358 struct irdma_cqp *iwcqp = &rf->cqp;
2359 struct irdma_cqp_request *cqp_request;
2360 struct cqp_cmds_info *cqp_info;
2361 int status;
2362
2363 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2364 if (!cqp_request)
2365 return -ENOMEM;
2366
2367 cqp_info = &cqp_request->info;
2368 cqp_info->post_sq = 1;
2369 info = &cqp_info->in.u.add_local_mac_entry.info;
2370 ether_addr_copy(info->mac_addr, mac_addr);
2371 info->entry_idx = idx;
2372 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2373 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY;
2374 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp;
2375 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2376
2377 status = irdma_handle_cqp_op(rf, cqp_request);
2378 irdma_put_cqp_request(iwcqp, cqp_request);
2379
2380 return status;
2381 }
2382
2383 /**
2384 * irdma_alloc_local_mac_entry - allocate a mac entry
2385 * @rf: RDMA PCI function
2386 * @mac_tbl_idx: the index of the new mac address
2387 *
2388 * Allocate a mac address entry and update the mac_tbl_idx
2389 * to hold the index of the newly created mac address
2390 * Return 0 if successful, otherwise return error
2391 */
2392 int
irdma_alloc_local_mac_entry(struct irdma_pci_f * rf,u16 * mac_tbl_idx)2393 irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx)
2394 {
2395 struct irdma_cqp *iwcqp = &rf->cqp;
2396 struct irdma_cqp_request *cqp_request;
2397 struct cqp_cmds_info *cqp_info;
2398 int status = 0;
2399
2400 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2401 if (!cqp_request)
2402 return -ENOMEM;
2403
2404 cqp_info = &cqp_request->info;
2405 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY;
2406 cqp_info->post_sq = 1;
2407 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp;
2408 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request;
2409 status = irdma_handle_cqp_op(rf, cqp_request);
2410 if (!status)
2411 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val;
2412
2413 irdma_put_cqp_request(iwcqp, cqp_request);
2414
2415 return status;
2416 }
2417
2418 /**
2419 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt
2420 * @iwdev: irdma device
2421 * @accel_local_port: port for apbvt
2422 * @add_port: add ordelete port
2423 */
2424 static int
irdma_cqp_manage_apbvt_cmd(struct irdma_device * iwdev,u16 accel_local_port,bool add_port)2425 irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev,
2426 u16 accel_local_port, bool add_port)
2427 {
2428 struct irdma_apbvt_info *info;
2429 struct irdma_cqp_request *cqp_request;
2430 struct cqp_cmds_info *cqp_info;
2431 int status;
2432
2433 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port);
2434 if (!cqp_request)
2435 return -ENOMEM;
2436
2437 cqp_info = &cqp_request->info;
2438 info = &cqp_info->in.u.manage_apbvt_entry.info;
2439 memset(info, 0, sizeof(*info));
2440 info->add = add_port;
2441 info->port = accel_local_port;
2442 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY;
2443 cqp_info->post_sq = 1;
2444 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2445 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
2446 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_DEV,
2447 "%s: port=0x%04x\n", (!add_port) ? "DELETE" : "ADD",
2448 accel_local_port);
2449
2450 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2451 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2452
2453 return status;
2454 }
2455
2456 /**
2457 * irdma_add_apbvt - add tcp port to HW apbvt table
2458 * @iwdev: irdma device
2459 * @port: port for apbvt
2460 */
2461 struct irdma_apbvt_entry *
irdma_add_apbvt(struct irdma_device * iwdev,u16 port)2462 irdma_add_apbvt(struct irdma_device *iwdev, u16 port)
2463 {
2464 struct irdma_cm_core *cm_core = &iwdev->cm_core;
2465 struct irdma_apbvt_entry *entry;
2466 unsigned long flags;
2467
2468 spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2469 entry = irdma_lookup_apbvt_entry(cm_core, port);
2470 if (entry) {
2471 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2472 return entry;
2473 }
2474
2475 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2476 if (!entry) {
2477 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2478 return NULL;
2479 }
2480
2481 entry->port = port;
2482 entry->use_cnt = 1;
2483 HASH_ADD(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port);
2484 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2485
2486 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) {
2487 kfree(entry);
2488 return NULL;
2489 }
2490
2491 return entry;
2492 }
2493
2494 /**
2495 * irdma_del_apbvt - delete tcp port from HW apbvt table
2496 * @iwdev: irdma device
2497 * @entry: apbvt entry object
2498 */
2499 void
irdma_del_apbvt(struct irdma_device * iwdev,struct irdma_apbvt_entry * entry)2500 irdma_del_apbvt(struct irdma_device *iwdev,
2501 struct irdma_apbvt_entry *entry)
2502 {
2503 struct irdma_cm_core *cm_core = &iwdev->cm_core;
2504 unsigned long flags;
2505
2506 spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2507 if (--entry->use_cnt) {
2508 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2509 return;
2510 }
2511
2512 HASH_DEL(cm_core->apbvt_hash_tbl, &entry->hlist);
2513 /*
2514 * apbvt_lock is held across CQP delete APBVT OP (non-waiting) to protect against race where add APBVT CQP can
2515 * race ahead of the delete APBVT for same port.
2516 */
2517 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false);
2518 kfree(entry);
2519 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2520 }
2521
2522 /**
2523 * irdma_manage_arp_cache - manage hw arp cache
2524 * @rf: RDMA PCI function
2525 * @mac_addr: mac address ptr
2526 * @ip_addr: ip addr for arp cache
2527 * @action: add, delete or modify
2528 */
2529 void
irdma_manage_arp_cache(struct irdma_pci_f * rf,const unsigned char * mac_addr,u32 * ip_addr,u32 action)2530 irdma_manage_arp_cache(struct irdma_pci_f *rf, const unsigned char *mac_addr,
2531 u32 *ip_addr, u32 action)
2532 {
2533 struct irdma_add_arp_cache_entry_info *info;
2534 struct irdma_cqp_request *cqp_request;
2535 struct cqp_cmds_info *cqp_info;
2536 int arp_index;
2537
2538 arp_index = irdma_arp_table(rf, ip_addr, mac_addr, action);
2539 if (arp_index == -1)
2540 return;
2541
2542 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
2543 if (!cqp_request)
2544 return;
2545
2546 cqp_info = &cqp_request->info;
2547 if (action == IRDMA_ARP_ADD) {
2548 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY;
2549 info = &cqp_info->in.u.add_arp_cache_entry.info;
2550 memset(info, 0, sizeof(*info));
2551 info->arp_index = (u16)arp_index;
2552 info->permanent = true;
2553 ether_addr_copy(info->mac_addr, mac_addr);
2554 cqp_info->in.u.add_arp_cache_entry.scratch =
2555 (uintptr_t)cqp_request;
2556 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2557 } else {
2558 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY;
2559 cqp_info->in.u.del_arp_cache_entry.scratch =
2560 (uintptr_t)cqp_request;
2561 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2562 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
2563 }
2564
2565 cqp_info->post_sq = 1;
2566 irdma_handle_cqp_op(rf, cqp_request);
2567 irdma_put_cqp_request(&rf->cqp, cqp_request);
2568 }
2569
2570 /**
2571 * irdma_send_syn_cqp_callback - do syn/ack after qhash
2572 * @cqp_request: qhash cqp completion
2573 */
2574 static void
irdma_send_syn_cqp_callback(struct irdma_cqp_request * cqp_request)2575 irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request)
2576 {
2577 struct irdma_cm_node *cm_node = cqp_request->param;
2578
2579 irdma_send_syn(cm_node, 1);
2580 irdma_rem_ref_cm_node(cm_node);
2581 }
2582
2583 /**
2584 * irdma_manage_qhash - add or modify qhash
2585 * @iwdev: irdma device
2586 * @cminfo: cm info for qhash
2587 * @etype: type (syn or quad)
2588 * @mtype: type of qhash
2589 * @cmnode: cmnode associated with connection
2590 * @wait: wait for completion
2591 */
2592 int
irdma_manage_qhash(struct irdma_device * iwdev,struct irdma_cm_info * cminfo,enum irdma_quad_entry_type etype,enum irdma_quad_hash_manage_type mtype,void * cmnode,bool wait)2593 irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
2594 enum irdma_quad_entry_type etype,
2595 enum irdma_quad_hash_manage_type mtype, void *cmnode,
2596 bool wait)
2597 {
2598 struct irdma_qhash_table_info *info;
2599 struct irdma_cqp *iwcqp = &iwdev->rf->cqp;
2600 struct irdma_cqp_request *cqp_request;
2601 struct cqp_cmds_info *cqp_info;
2602 struct irdma_cm_node *cm_node = cmnode;
2603 int status;
2604
2605 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
2606 if (!cqp_request)
2607 return -ENOMEM;
2608
2609 cminfo->cqp_request = cqp_request;
2610 if (!wait)
2611 atomic_inc(&cqp_request->refcnt);
2612 cqp_info = &cqp_request->info;
2613 info = &cqp_info->in.u.manage_qhash_table_entry.info;
2614 memset(info, 0, sizeof(*info));
2615 info->vsi = &iwdev->vsi;
2616 info->manage = mtype;
2617 info->entry_type = etype;
2618 if (cminfo->vlan_id < VLAN_N_VID) {
2619 info->vlan_valid = true;
2620 info->vlan_id = cminfo->vlan_id;
2621 } else {
2622 info->vlan_valid = false;
2623 }
2624 info->ipv4_valid = cminfo->ipv4;
2625 info->user_pri = cminfo->user_pri;
2626 ether_addr_copy(info->mac_addr, if_getlladdr(iwdev->netdev));
2627 info->qp_num = cminfo->qh_qpid;
2628 info->dest_port = cminfo->loc_port;
2629 info->dest_ip[0] = cminfo->loc_addr[0];
2630 info->dest_ip[1] = cminfo->loc_addr[1];
2631 info->dest_ip[2] = cminfo->loc_addr[2];
2632 info->dest_ip[3] = cminfo->loc_addr[3];
2633 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED ||
2634 etype == IRDMA_QHASH_TYPE_UDP_UNICAST ||
2635 etype == IRDMA_QHASH_TYPE_UDP_MCAST ||
2636 etype == IRDMA_QHASH_TYPE_ROCE_MCAST ||
2637 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) {
2638 info->src_port = cminfo->rem_port;
2639 info->src_ip[0] = cminfo->rem_addr[0];
2640 info->src_ip[1] = cminfo->rem_addr[1];
2641 info->src_ip[2] = cminfo->rem_addr[2];
2642 info->src_ip[3] = cminfo->rem_addr[3];
2643 }
2644 if (cmnode) {
2645 cqp_request->callback_fcn = irdma_send_syn_cqp_callback;
2646 cqp_request->param = cmnode;
2647 if (!wait)
2648 atomic_inc(&cm_node->refcnt);
2649 }
2650 if (info->ipv4_valid)
2651 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_CM,
2652 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%x rem_addr=%x mac=%x:%x:%x:%x:%x:%x, vlan_id=%d cm_node=%p\n",
2653 (!mtype) ? "DELETE" : "ADD",
2654 __builtin_return_address(0), info->src_port,
2655 info->dest_port, info->src_ip[0], info->dest_ip[0],
2656 info->mac_addr[0], info->mac_addr[1],
2657 info->mac_addr[2], info->mac_addr[3],
2658 info->mac_addr[4], info->mac_addr[5],
2659 cminfo->vlan_id, cmnode ? cmnode : NULL);
2660 else
2661 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_CM,
2662 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%x:%x:%x:%x rem_addr=%x:%x:%x:%x mac=%x:%x:%x:%x:%x:%x, vlan_id=%d cm_node=%p\n",
2663 (!mtype) ? "DELETE" : "ADD",
2664 __builtin_return_address(0), info->src_port,
2665 info->dest_port, IRDMA_PRINT_IP6(info->src_ip),
2666 IRDMA_PRINT_IP6(info->dest_ip), info->mac_addr[0],
2667 info->mac_addr[1], info->mac_addr[2],
2668 info->mac_addr[3], info->mac_addr[4],
2669 info->mac_addr[5], cminfo->vlan_id,
2670 cmnode ? cmnode : NULL);
2671
2672 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2673 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
2674 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY;
2675 cqp_info->post_sq = 1;
2676 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2677 if (status && cm_node && !wait)
2678 irdma_rem_ref_cm_node(cm_node);
2679
2680 irdma_put_cqp_request(iwcqp, cqp_request);
2681
2682 return status;
2683 }
2684
2685 /**
2686 * irdma_hw_flush_wqes - flush qp's wqe
2687 * @rf: RDMA PCI function
2688 * @qp: hardware control qp
2689 * @info: info for flush
2690 * @wait: flag wait for completion
2691 */
2692 int
irdma_hw_flush_wqes(struct irdma_pci_f * rf,struct irdma_sc_qp * qp,struct irdma_qp_flush_info * info,bool wait)2693 irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2694 struct irdma_qp_flush_info *info, bool wait)
2695 {
2696 int status;
2697 struct irdma_qp_flush_info *hw_info;
2698 struct irdma_cqp_request *cqp_request;
2699 struct cqp_cmds_info *cqp_info;
2700 struct irdma_qp *iwqp = qp->qp_uk.back_qp;
2701
2702 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2703 if (!cqp_request)
2704 return -ENOMEM;
2705
2706 cqp_info = &cqp_request->info;
2707 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
2708 memcpy(hw_info, info, sizeof(*hw_info));
2709 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2710 cqp_info->post_sq = 1;
2711 cqp_info->in.u.qp_flush_wqes.qp = qp;
2712 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
2713 status = irdma_handle_cqp_op(rf, cqp_request);
2714 if (status) {
2715 qp->qp_uk.sq_flush_complete = true;
2716 qp->qp_uk.rq_flush_complete = true;
2717 irdma_put_cqp_request(&rf->cqp, cqp_request);
2718 return status;
2719 }
2720
2721 if (!wait || cqp_request->compl_info.maj_err_code)
2722 goto put_cqp;
2723
2724 if (info->rq) {
2725 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2726 cqp_request->compl_info.min_err_code == 0) {
2727 /* RQ WQE flush was requested but did not happen */
2728 qp->qp_uk.rq_flush_complete = true;
2729 }
2730 }
2731 if (info->sq) {
2732 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2733 cqp_request->compl_info.min_err_code == 0) {
2734 /* SQ WQE flush was requested but did not happen */
2735 qp->qp_uk.sq_flush_complete = true;
2736 }
2737 }
2738
2739 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_VERBS,
2740 "qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n",
2741 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state,
2742 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state,
2743 cqp_request->compl_info.maj_err_code,
2744 cqp_request->compl_info.min_err_code);
2745 put_cqp:
2746 irdma_put_cqp_request(&rf->cqp, cqp_request);
2747
2748 return status;
2749 }
2750
2751 /**
2752 * irdma_gen_ae - generate AE
2753 * @rf: RDMA PCI function
2754 * @qp: qp associated with AE
2755 * @info: info for ae
2756 * @wait: wait for completion
2757 */
2758 void
irdma_gen_ae(struct irdma_pci_f * rf,struct irdma_sc_qp * qp,struct irdma_gen_ae_info * info,bool wait)2759 irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2760 struct irdma_gen_ae_info *info, bool wait)
2761 {
2762 struct irdma_gen_ae_info *ae_info;
2763 struct irdma_cqp_request *cqp_request;
2764 struct cqp_cmds_info *cqp_info;
2765
2766 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2767 if (!cqp_request)
2768 return;
2769
2770 cqp_info = &cqp_request->info;
2771 ae_info = &cqp_request->info.in.u.gen_ae.info;
2772 memcpy(ae_info, info, sizeof(*ae_info));
2773 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE;
2774 cqp_info->post_sq = 1;
2775 cqp_info->in.u.gen_ae.qp = qp;
2776 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;
2777
2778 irdma_handle_cqp_op(rf, cqp_request);
2779 irdma_put_cqp_request(&rf->cqp, cqp_request);
2780 }
2781
2782 void
irdma_flush_wqes(struct irdma_qp * iwqp,u32 flush_mask)2783 irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask)
2784 {
2785 struct irdma_qp_flush_info info = {0};
2786 struct irdma_pci_f *rf = iwqp->iwdev->rf;
2787 u8 flush_code = iwqp->sc_qp.flush_code;
2788
2789 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ))
2790 return;
2791
2792 /* Set flush info fields */
2793 info.sq = flush_mask & IRDMA_FLUSH_SQ;
2794 info.rq = flush_mask & IRDMA_FLUSH_RQ;
2795
2796 /* Generate userflush errors in CQE */
2797 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2798 info.sq_minor_code = FLUSH_GENERAL_ERR;
2799 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2800 info.rq_minor_code = FLUSH_GENERAL_ERR;
2801 info.userflushcode = true;
2802
2803 if (flush_mask & IRDMA_REFLUSH) {
2804 if (info.sq)
2805 iwqp->sc_qp.flush_sq = false;
2806 if (info.rq)
2807 iwqp->sc_qp.flush_rq = false;
2808 } else {
2809 if (flush_code) {
2810 if (info.sq && iwqp->sc_qp.sq_flush_code)
2811 info.sq_minor_code = flush_code;
2812 if (info.rq && iwqp->sc_qp.rq_flush_code)
2813 info.rq_minor_code = flush_code;
2814 }
2815 if (irdma_upload_context && irdma_upload_qp_context(iwqp, 0, 1))
2816 irdma_dev_warn(&iwqp->iwdev->ibdev, "failed to upload QP context\n");
2817 if (!iwqp->user_mode)
2818 irdma_sched_qp_flush_work(iwqp);
2819 }
2820
2821 /* Issue flush */
2822 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2823 flush_mask & IRDMA_FLUSH_WAIT);
2824 iwqp->flush_issued = true;
2825 }
2826