1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #include "irdma_main.h" 37 38 static struct irdma_rsrc_limits rsrc_limits_table[] = { 39 [0] = { 40 .qplimit = SZ_128, 41 }, 42 [1] = { 43 .qplimit = SZ_1K, 44 }, 45 [2] = { 46 .qplimit = SZ_2K, 47 }, 48 [3] = { 49 .qplimit = SZ_4K, 50 }, 51 [4] = { 52 .qplimit = SZ_16K, 53 }, 54 [5] = { 55 .qplimit = SZ_64K, 56 }, 57 [6] = { 58 .qplimit = SZ_128K, 59 }, 60 [7] = { 61 .qplimit = SZ_256K, 62 }, 63 }; 64 65 /* types of hmc objects */ 66 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 67 IRDMA_HMC_IW_QP, 68 IRDMA_HMC_IW_CQ, 69 IRDMA_HMC_IW_HTE, 70 IRDMA_HMC_IW_ARP, 71 IRDMA_HMC_IW_APBVT_ENTRY, 72 IRDMA_HMC_IW_MR, 73 IRDMA_HMC_IW_XF, 74 IRDMA_HMC_IW_XFFL, 75 IRDMA_HMC_IW_Q1, 76 IRDMA_HMC_IW_Q1FL, 77 IRDMA_HMC_IW_PBLE, 78 IRDMA_HMC_IW_TIMER, 79 IRDMA_HMC_IW_FSIMC, 80 IRDMA_HMC_IW_FSIAV, 81 IRDMA_HMC_IW_RRF, 82 IRDMA_HMC_IW_RRFFL, 83 IRDMA_HMC_IW_HDR, 84 IRDMA_HMC_IW_MD, 85 IRDMA_HMC_IW_OOISC, 86 IRDMA_HMC_IW_OOISCFFL, 87 }; 88 89 /** 90 * irdma_iwarp_ce_handler - handle iwarp completions 91 * @iwcq: iwarp cq receiving event 92 */ 93 static void 94 irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 95 { 96 struct irdma_cq *cq = iwcq->back_cq; 97 98 if (!cq->user_mode) 99 atomic_set(&cq->armed, 0); 100 if (cq->ibcq.comp_handler) 101 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 102 } 103 104 /** 105 * irdma_puda_ce_handler - handle puda completion events 106 * @rf: RDMA PCI function 107 * @cq: puda completion q for event 108 */ 109 static void 110 irdma_puda_ce_handler(struct irdma_pci_f *rf, 111 struct irdma_sc_cq *cq) 112 { 113 struct irdma_sc_dev *dev = &rf->sc_dev; 114 u32 compl_error; 115 int status; 116 117 do { 118 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 119 if (status == -ENOENT) 120 break; 121 if (status) { 122 irdma_debug(dev, IRDMA_DEBUG_ERR, "puda status = %d\n", 123 status); 124 break; 125 } 126 if (compl_error) { 127 irdma_debug(dev, IRDMA_DEBUG_ERR, 128 "puda compl_err =0x%x\n", compl_error); 129 break; 130 } 131 } while (1); 132 133 irdma_sc_ccq_arm(cq); 134 } 135 136 /** 137 * irdma_process_ceq - handle ceq for completions 138 * @rf: RDMA PCI function 139 * @ceq: ceq having cq for completion 140 */ 141 static void 142 irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 143 { 144 struct irdma_sc_dev *dev = &rf->sc_dev; 145 struct irdma_sc_ceq *sc_ceq; 146 struct irdma_sc_cq *cq; 147 unsigned long flags; 148 149 sc_ceq = &ceq->sc_ceq; 150 do { 151 spin_lock_irqsave(&ceq->ce_lock, flags); 152 cq = irdma_sc_process_ceq(dev, sc_ceq); 153 if (!cq) { 154 spin_unlock_irqrestore(&ceq->ce_lock, flags); 155 break; 156 } 157 158 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 159 irdma_iwarp_ce_handler(cq); 160 161 spin_unlock_irqrestore(&ceq->ce_lock, flags); 162 163 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 164 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 165 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 166 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 167 irdma_puda_ce_handler(rf, cq); 168 } while (1); 169 } 170 171 static void 172 irdma_set_flush_fields(struct irdma_sc_qp *qp, 173 struct irdma_aeqe_info *info) 174 { 175 struct qp_err_code qp_err; 176 177 qp->sq_flush_code = info->sq; 178 qp->rq_flush_code = info->rq; 179 180 qp_err = irdma_ae_to_qp_err_code(info->ae_id); 181 182 qp->flush_code = qp_err.flush_code; 183 qp->event_type = qp_err.event_type; 184 } 185 186 /** 187 * irdma_complete_cqp_request - perform post-completion cleanup 188 * @cqp: device CQP 189 * @cqp_request: CQP request 190 * 191 * Mark CQP request as done, wake up waiting thread or invoke 192 * callback function and release/free CQP request. 193 */ 194 static void 195 irdma_complete_cqp_request(struct irdma_cqp *cqp, 196 struct irdma_cqp_request *cqp_request) 197 { 198 if (cqp_request->waiting) { 199 cqp_request->request_done = true; 200 wake_up(&cqp_request->waitq); 201 } else if (cqp_request->callback_fcn) { 202 cqp_request->callback_fcn(cqp_request); 203 } 204 irdma_put_cqp_request(cqp, cqp_request); 205 } 206 207 /** 208 * irdma_process_aeq - handle aeq events 209 * @rf: RDMA PCI function 210 */ 211 static void 212 irdma_process_aeq(struct irdma_pci_f *rf) 213 { 214 struct irdma_sc_dev *dev = &rf->sc_dev; 215 struct irdma_aeq *aeq = &rf->aeq; 216 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 217 struct irdma_aeqe_info aeinfo; 218 struct irdma_aeqe_info *info = &aeinfo; 219 int ret; 220 struct irdma_qp *iwqp = NULL; 221 struct irdma_cq *iwcq = NULL; 222 struct irdma_sc_qp *qp = NULL; 223 struct irdma_qp_host_ctx_info *ctx_info = NULL; 224 unsigned long flags; 225 226 u32 aeqcnt = 0; 227 228 if (!sc_aeq->size) 229 return; 230 231 do { 232 memset(info, 0, sizeof(*info)); 233 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 234 if (ret) 235 break; 236 237 aeqcnt++; 238 irdma_debug(dev, IRDMA_DEBUG_AEQ, 239 "ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 240 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, info->iwarp_state, info->ae_src); 241 242 if (info->qp) { 243 spin_lock_irqsave(&rf->qptable_lock, flags); 244 iwqp = rf->qp_table[info->qp_cq_id]; 245 if (!iwqp) { 246 spin_unlock_irqrestore(&rf->qptable_lock, 247 flags); 248 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 249 struct irdma_device *iwdev = rf->iwdev; 250 251 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 252 wake_up(&iwdev->suspend_wq); 253 continue; 254 } 255 irdma_debug(dev, IRDMA_DEBUG_AEQ, 256 "qp_id %d is already freed\n", 257 info->qp_cq_id); 258 continue; 259 } 260 irdma_qp_add_ref(&iwqp->ibqp); 261 spin_unlock_irqrestore(&rf->qptable_lock, flags); 262 qp = &iwqp->sc_qp; 263 spin_lock_irqsave(&iwqp->lock, flags); 264 iwqp->hw_tcp_state = info->tcp_state; 265 iwqp->hw_iwarp_state = info->iwarp_state; 266 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 267 iwqp->last_aeq = info->ae_id; 268 spin_unlock_irqrestore(&iwqp->lock, flags); 269 ctx_info = &iwqp->ctx_info; 270 } else { 271 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 272 continue; 273 } 274 275 switch (info->ae_id) { 276 struct irdma_cm_node *cm_node; 277 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 278 cm_node = iwqp->cm_node; 279 if (cm_node->accept_pend) { 280 atomic_dec(&cm_node->listener->pend_accepts_cnt); 281 cm_node->accept_pend = 0; 282 } 283 iwqp->rts_ae_rcvd = 1; 284 wake_up_interruptible(&iwqp->waitq); 285 break; 286 case IRDMA_AE_LLP_FIN_RECEIVED: 287 if (qp->term_flags) 288 break; 289 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 290 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 291 if (iwqp->ibqp_state == IB_QPS_RTS) { 292 irdma_next_iw_state(iwqp, 293 IRDMA_QP_STATE_CLOSING, 294 0, 0, 0); 295 irdma_cm_disconn(iwqp); 296 } 297 irdma_schedule_cm_timer(iwqp->cm_node, 298 (struct irdma_puda_buf *)iwqp, 299 IRDMA_TIMER_TYPE_CLOSE, 300 1, 0); 301 } 302 break; 303 case IRDMA_AE_LLP_CLOSE_COMPLETE: 304 if (qp->term_flags) 305 irdma_terminate_done(qp, 0); 306 else 307 irdma_cm_disconn(iwqp); 308 break; 309 case IRDMA_AE_BAD_CLOSE: 310 case IRDMA_AE_RESET_SENT: 311 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 312 0); 313 irdma_cm_disconn(iwqp); 314 break; 315 case IRDMA_AE_LLP_CONNECTION_RESET: 316 if (atomic_read(&iwqp->close_timer_started)) 317 break; 318 irdma_cm_disconn(iwqp); 319 break; 320 case IRDMA_AE_QP_SUSPEND_COMPLETE: 321 if (iwqp->iwdev->vsi.tc_change_pending) { 322 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 323 wake_up(&iwqp->iwdev->suspend_wq); 324 } 325 break; 326 case IRDMA_AE_TERMINATE_SENT: 327 irdma_terminate_send_fin(qp); 328 break; 329 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 330 irdma_terminate_received(qp, info); 331 break; 332 case IRDMA_AE_CQ_OPERATION_ERROR: 333 irdma_dev_err(dev, 334 "Processing CQ[0x%x] op error, AE 0x%04X\n", 335 info->qp_cq_id, info->ae_id); 336 spin_lock_irqsave(&rf->cqtable_lock, flags); 337 iwcq = rf->cq_table[info->qp_cq_id]; 338 if (!iwcq) { 339 spin_unlock_irqrestore(&rf->cqtable_lock, 340 flags); 341 irdma_debug(dev, IRDMA_DEBUG_AEQ, 342 "cq_id %d is already freed\n", 343 info->qp_cq_id); 344 continue; 345 } 346 irdma_cq_add_ref(&iwcq->ibcq); 347 spin_unlock_irqrestore(&rf->cqtable_lock, flags); 348 if (iwcq->ibcq.event_handler) { 349 struct ib_event ibevent; 350 351 ibevent.device = iwcq->ibcq.device; 352 ibevent.event = IB_EVENT_CQ_ERR; 353 ibevent.element.cq = &iwcq->ibcq; 354 iwcq->ibcq.event_handler(&ibevent, 355 iwcq->ibcq.cq_context); 356 } 357 irdma_cq_rem_ref(&iwcq->ibcq); 358 break; 359 case IRDMA_AE_RESET_NOT_SENT: 360 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 361 case IRDMA_AE_RESOURCE_EXHAUSTION: 362 break; 363 case IRDMA_AE_PRIV_OPERATION_DENIED: 364 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 365 case IRDMA_AE_STAG_ZERO_INVALID: 366 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 367 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 368 case IRDMA_AE_DDP_UBE_INVALID_MO: 369 case IRDMA_AE_DDP_UBE_INVALID_QN: 370 case IRDMA_AE_DDP_NO_L_BIT: 371 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 372 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 373 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 374 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 375 case IRDMA_AE_INVALID_ARP_ENTRY: 376 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 377 case IRDMA_AE_STALE_ARP_ENTRY: 378 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 379 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 380 case IRDMA_AE_LLP_SYN_RECEIVED: 381 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 382 case IRDMA_AE_LCE_QP_CATASTROPHIC: 383 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 384 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 385 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 386 default: 387 irdma_dev_err(dev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_source=%d\n", 388 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 389 if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) { 390 ctx_info->roce_info->err_rq_idx_valid = info->rq; 391 if (info->rq) { 392 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 393 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 394 ctx_info); 395 } 396 irdma_set_flush_fields(qp, info); 397 irdma_cm_disconn(iwqp); 398 break; 399 } 400 ctx_info->iwarp_info->err_rq_idx_valid = info->rq; 401 if (info->rq) { 402 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 403 ctx_info->tcp_info_valid = false; 404 ctx_info->iwarp_info_valid = true; 405 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 406 ctx_info); 407 } 408 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 409 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 410 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 411 irdma_cm_disconn(iwqp); 412 } else { 413 irdma_terminate_connection(qp, info); 414 } 415 break; 416 } 417 if (info->qp) 418 irdma_qp_rem_ref(&iwqp->ibqp); 419 } while (1); 420 421 if (aeqcnt) 422 irdma_sc_repost_aeq_entries(dev, aeqcnt); 423 } 424 425 /** 426 * irdma_ena_intr - set up device interrupts 427 * @dev: hardware control device structure 428 * @msix_id: id of the interrupt to be enabled 429 */ 430 static void 431 irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 432 { 433 dev->irq_ops->irdma_en_irq(dev, msix_id); 434 } 435 436 /** 437 * irdma_dpc - tasklet for aeq and ceq 0 438 * @t: tasklet_struct ptr 439 */ 440 static void 441 irdma_dpc(struct tasklet_struct *t) 442 { 443 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet); 444 445 if (rf->msix_shared) 446 irdma_process_ceq(rf, rf->ceqlist); 447 irdma_process_aeq(rf); 448 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 449 } 450 451 /** 452 * irdma_ceq_dpc - dpc handler for CEQ 453 * @t: tasklet_struct ptr 454 */ 455 static void 456 irdma_ceq_dpc(struct tasklet_struct *t) 457 { 458 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet); 459 struct irdma_pci_f *rf = iwceq->rf; 460 461 irdma_process_ceq(rf, iwceq); 462 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 463 } 464 465 /** 466 * irdma_save_msix_info - copy msix vector information to iwarp device 467 * @rf: RDMA PCI function 468 * 469 * Allocate iwdev msix table and copy the msix info to the table 470 * Return 0 if successful, otherwise return error 471 */ 472 static int 473 irdma_save_msix_info(struct irdma_pci_f *rf) 474 { 475 struct irdma_qvlist_info *iw_qvlist; 476 struct irdma_qv_info *iw_qvinfo; 477 u32 ceq_idx; 478 u32 i; 479 u32 size; 480 481 if (!rf->msix_count) { 482 irdma_dev_err(&rf->sc_dev, "No MSI-X vectors reserved for RDMA.\n"); 483 return -EINVAL; 484 } 485 486 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 487 size += sizeof(struct irdma_qvlist_info); 488 size += sizeof(struct irdma_qv_info) * rf->msix_count - 1; 489 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 490 if (!rf->iw_msixtbl) 491 return -ENOMEM; 492 493 rf->iw_qvlist = (struct irdma_qvlist_info *) 494 (&rf->iw_msixtbl[rf->msix_count]); 495 iw_qvlist = rf->iw_qvlist; 496 iw_qvinfo = iw_qvlist->qv_info; 497 iw_qvlist->num_vectors = rf->msix_count; 498 if (rf->msix_count <= num_online_cpus()) 499 rf->msix_shared = true; 500 else if (rf->msix_count > num_online_cpus() + 1) 501 rf->msix_count = num_online_cpus() + 1; 502 503 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 504 rf->iw_msixtbl[i].idx = rf->msix_info.entry + i; 505 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 506 if (!i) { 507 iw_qvinfo->aeq_idx = 0; 508 if (rf->msix_shared) 509 iw_qvinfo->ceq_idx = ceq_idx++; 510 else 511 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 512 } else { 513 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 514 iw_qvinfo->ceq_idx = ceq_idx++; 515 } 516 iw_qvinfo->itr_idx = IRDMA_IDX_NOITR; 517 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 518 } 519 520 return 0; 521 } 522 523 /** 524 * irdma_irq_handler - interrupt handler for aeq and ceq0 525 * @data: RDMA PCI function 526 */ 527 static void 528 irdma_irq_handler(void *data) 529 { 530 struct irdma_pci_f *rf = data; 531 532 tasklet_schedule(&rf->dpc_tasklet); 533 } 534 535 /** 536 * irdma_ceq_handler - interrupt handler for ceq 537 * @data: ceq pointer 538 */ 539 static void 540 irdma_ceq_handler(void *data) 541 { 542 struct irdma_ceq *iwceq = data; 543 544 tasklet_schedule(&iwceq->dpc_tasklet); 545 } 546 547 /** 548 * irdma_free_irq - free device interrupts in FreeBSD manner 549 * @rf: RDMA PCI function 550 * @msix_vec: msix vector to disable irq 551 * 552 * The function is called when destroying irq. It tearsdown 553 * the interrupt and release resources. 554 */ 555 static void 556 irdma_free_irq(struct irdma_pci_f *rf, struct irdma_msix_vector *msix_vec) 557 { 558 if (msix_vec->tag) { 559 bus_teardown_intr(rf->dev_ctx.dev, msix_vec->res, 560 msix_vec->tag); 561 msix_vec->tag = NULL; 562 } 563 if (msix_vec->res) { 564 bus_release_resource(rf->dev_ctx.dev, SYS_RES_IRQ, 565 msix_vec->idx + 1, 566 msix_vec->res); 567 msix_vec->res = NULL; 568 } 569 } 570 571 /** 572 * irdma_destroy_irq - destroy device interrupts 573 * @rf: RDMA PCI function 574 * @msix_vec: msix vector to disable irq 575 * @dev_id: parameter to pass to free_irq (used during irq setup) 576 * 577 * The function is called when destroying aeq/ceq 578 */ 579 static void 580 irdma_destroy_irq(struct irdma_pci_f *rf, 581 struct irdma_msix_vector *msix_vec, void *dev_id) 582 { 583 struct irdma_sc_dev *dev = &rf->sc_dev; 584 585 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 586 irdma_free_irq(rf, msix_vec); 587 } 588 589 /** 590 * irdma_destroy_cqp - destroy control qp 591 * @rf: RDMA PCI function 592 * @free_hwcqp: 1 if hw cqp should be freed 593 * 594 * Issue destroy cqp request and 595 * free the resources associated with the cqp 596 */ 597 static void 598 irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 599 { 600 struct irdma_sc_dev *dev = &rf->sc_dev; 601 struct irdma_cqp *cqp = &rf->cqp; 602 int status = 0; 603 604 if (rf->cqp_cmpl_wq) 605 destroy_workqueue(rf->cqp_cmpl_wq); 606 status = irdma_sc_cqp_destroy(dev->cqp, free_hwcqp); 607 if (status) 608 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy CQP failed %d\n", 609 status); 610 611 irdma_cleanup_pending_cqp_op(rf); 612 irdma_free_dma_mem(dev->hw, &cqp->sq); 613 kfree(cqp->scratch_array); 614 cqp->scratch_array = NULL; 615 kfree(cqp->cqp_requests); 616 cqp->cqp_requests = NULL; 617 } 618 619 static void 620 irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 621 { 622 struct irdma_aeq *aeq = &rf->aeq; 623 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 624 dma_addr_t *pg_arr = (dma_addr_t *) aeq->palloc.level1.addr; 625 626 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 627 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 628 vfree(aeq->mem.va); 629 } 630 631 /** 632 * irdma_destroy_aeq - destroy aeq 633 * @rf: RDMA PCI function 634 * 635 * Issue a destroy aeq request and 636 * free the resources associated with the aeq 637 * The function is called during driver unload 638 */ 639 static void 640 irdma_destroy_aeq(struct irdma_pci_f *rf) 641 { 642 struct irdma_sc_dev *dev = &rf->sc_dev; 643 struct irdma_aeq *aeq = &rf->aeq; 644 int status = -EBUSY; 645 646 if (!rf->msix_shared) { 647 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 648 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 649 } 650 if (rf->reset) 651 goto exit; 652 653 aeq->sc_aeq.size = 0; 654 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 655 if (status) 656 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy AEQ failed %d\n", 657 status); 658 659 exit: 660 if (aeq->virtual_map) 661 irdma_destroy_virt_aeq(rf); 662 else 663 irdma_free_dma_mem(dev->hw, &aeq->mem); 664 } 665 666 /** 667 * irdma_destroy_ceq - destroy ceq 668 * @rf: RDMA PCI function 669 * @iwceq: ceq to be destroyed 670 * 671 * Issue a destroy ceq request and 672 * free the resources associated with the ceq 673 */ 674 static void 675 irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 676 { 677 struct irdma_sc_dev *dev = &rf->sc_dev; 678 int status; 679 680 if (rf->reset) 681 goto exit; 682 683 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 684 if (status) { 685 irdma_debug(dev, IRDMA_DEBUG_ERR, 686 "CEQ destroy command failed %d\n", status); 687 goto exit; 688 } 689 690 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 691 if (status) 692 irdma_debug(dev, IRDMA_DEBUG_ERR, 693 "CEQ destroy completion failed %d\n", status); 694 exit: 695 spin_lock_destroy(&iwceq->ce_lock); 696 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock); 697 kfree(iwceq->sc_ceq.reg_cq); 698 irdma_free_dma_mem(dev->hw, &iwceq->mem); 699 } 700 701 /** 702 * irdma_del_ceq_0 - destroy ceq 0 703 * @rf: RDMA PCI function 704 * 705 * Disable the ceq 0 interrupt and destroy the ceq 0 706 */ 707 static void 708 irdma_del_ceq_0(struct irdma_pci_f *rf) 709 { 710 struct irdma_ceq *iwceq = rf->ceqlist; 711 struct irdma_msix_vector *msix_vec; 712 713 if (rf->msix_shared) { 714 msix_vec = &rf->iw_msixtbl[0]; 715 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 716 msix_vec->ceq_id, 717 msix_vec->idx, false); 718 irdma_destroy_irq(rf, msix_vec, rf); 719 } else { 720 msix_vec = &rf->iw_msixtbl[1]; 721 irdma_destroy_irq(rf, msix_vec, iwceq); 722 } 723 724 irdma_destroy_ceq(rf, iwceq); 725 rf->sc_dev.ceq_valid = false; 726 rf->ceqs_count = 0; 727 } 728 729 /** 730 * irdma_del_ceqs - destroy all ceq's except CEQ 0 731 * @rf: RDMA PCI function 732 * 733 * Go through all of the device ceq's, except 0, and for each 734 * ceq disable the ceq interrupt and destroy the ceq 735 */ 736 static void 737 irdma_del_ceqs(struct irdma_pci_f *rf) 738 { 739 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 740 struct irdma_msix_vector *msix_vec; 741 u32 i = 0; 742 743 if (rf->msix_shared) 744 msix_vec = &rf->iw_msixtbl[1]; 745 else 746 msix_vec = &rf->iw_msixtbl[2]; 747 748 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 749 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 750 msix_vec->idx, false); 751 irdma_destroy_irq(rf, msix_vec, iwceq); 752 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 753 IRDMA_OP_CEQ_DESTROY); 754 spin_lock_destroy(&iwceq->ce_lock); 755 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock); 756 kfree(iwceq->sc_ceq.reg_cq); 757 irdma_free_dma_mem(rf->sc_dev.hw, &iwceq->mem); 758 } 759 rf->ceqs_count = 1; 760 } 761 762 /** 763 * irdma_destroy_ccq - destroy control cq 764 * @rf: RDMA PCI function 765 * 766 * Issue destroy ccq request and 767 * free the resources associated with the ccq 768 */ 769 static void 770 irdma_destroy_ccq(struct irdma_pci_f *rf) 771 { 772 struct irdma_sc_dev *dev = &rf->sc_dev; 773 struct irdma_ccq *ccq = &rf->ccq; 774 int status = 0; 775 776 if (!rf->reset) 777 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 778 if (status) 779 irdma_debug(dev, IRDMA_DEBUG_ERR, "CCQ destroy failed %d\n", 780 status); 781 irdma_free_dma_mem(dev->hw, &ccq->mem_cq); 782 } 783 784 /** 785 * irdma_close_hmc_objects_type - delete hmc objects of a given type 786 * @dev: iwarp device 787 * @obj_type: the hmc object type to be deleted 788 * @hmc_info: host memory info struct 789 * @privileged: permission to close HMC objects 790 * @reset: true if called before reset 791 */ 792 static void 793 irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 794 enum irdma_hmc_rsrc_type obj_type, 795 struct irdma_hmc_info *hmc_info, 796 bool privileged, bool reset) 797 { 798 struct irdma_hmc_del_obj_info info = {0}; 799 800 info.hmc_info = hmc_info; 801 info.rsrc_type = obj_type; 802 info.count = hmc_info->hmc_obj[obj_type].cnt; 803 info.privileged = privileged; 804 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 805 irdma_debug(dev, IRDMA_DEBUG_ERR, 806 "del HMC obj of type %d failed\n", obj_type); 807 } 808 809 /** 810 * irdma_del_hmc_objects - remove all device hmc objects 811 * @dev: iwarp device 812 * @hmc_info: hmc_info to free 813 * @privileged: permission to delete HMC objects 814 * @reset: true if called before reset 815 * @vers: hardware version 816 */ 817 void 818 irdma_del_hmc_objects(struct irdma_sc_dev *dev, 819 struct irdma_hmc_info *hmc_info, bool privileged, 820 bool reset, enum irdma_vers vers) 821 { 822 unsigned int i; 823 824 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 825 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 826 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 827 hmc_info, privileged, reset); 828 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 829 break; 830 } 831 } 832 833 /** 834 * irdma_create_hmc_obj_type - create hmc object of a given type 835 * @dev: hardware control device structure 836 * @info: information for the hmc object to create 837 */ 838 static int 839 irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 840 struct irdma_hmc_create_obj_info *info) 841 { 842 return irdma_sc_create_hmc_obj(dev, info); 843 } 844 845 /** 846 * irdma_create_hmc_objs - create all hmc objects for the device 847 * @rf: RDMA PCI function 848 * @privileged: permission to create HMC objects 849 * @vers: HW version 850 * 851 * Create the device hmc objects and allocate hmc pages 852 * Return 0 if successful, otherwise clean up and return error 853 */ 854 static int 855 irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 856 enum irdma_vers vers) 857 { 858 struct irdma_sc_dev *dev = &rf->sc_dev; 859 struct irdma_hmc_create_obj_info info = {0}; 860 int i, status = 0; 861 862 info.hmc_info = dev->hmc_info; 863 info.privileged = privileged; 864 info.entry_type = rf->sd_type; 865 866 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 867 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE) 868 continue; 869 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 870 info.rsrc_type = iw_hmc_obj_types[i]; 871 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 872 info.add_sd_cnt = 0; 873 status = irdma_create_hmc_obj_type(dev, &info); 874 if (status) { 875 irdma_debug(dev, IRDMA_DEBUG_ERR, 876 "create obj type %d status = %d\n", 877 iw_hmc_obj_types[i], status); 878 break; 879 } 880 } 881 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 882 break; 883 } 884 885 if (!status) 886 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 887 true, true); 888 889 while (i) { 890 i--; 891 /* destroy the hmc objects of a given type */ 892 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 893 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 894 dev->hmc_info, privileged, 895 false); 896 } 897 898 return status; 899 } 900 901 /** 902 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 903 * @rf: RDMA PCI function 904 * @memptr: points to the memory addresses 905 * @size: size of memory needed 906 * @mask: mask for the aligned memory 907 * 908 * Get aligned memory of the requested size and 909 * update the memptr to point to the new aligned memory 910 * Return 0 if successful, otherwise return no memory error 911 */ 912 static int 913 irdma_obj_aligned_mem(struct irdma_pci_f *rf, 914 struct irdma_dma_mem *memptr, u32 size, 915 u32 mask) 916 { 917 unsigned long va, newva; 918 unsigned long extra; 919 920 va = (unsigned long)rf->obj_next.va; 921 newva = va; 922 if (mask) 923 newva = ALIGN(va, (unsigned long)mask + 1ULL); 924 extra = newva - va; 925 memptr->va = (u8 *)va + extra; 926 memptr->pa = rf->obj_next.pa + extra; 927 memptr->size = size; 928 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 929 return -ENOMEM; 930 931 rf->obj_next.va = (u8 *)memptr->va + size; 932 rf->obj_next.pa = memptr->pa + size; 933 934 return 0; 935 } 936 937 /** 938 * irdma_create_cqp - create control qp 939 * @rf: RDMA PCI function 940 * 941 * Return 0, if the cqp and all the resources associated with it 942 * are successfully created, otherwise return error 943 */ 944 static int 945 irdma_create_cqp(struct irdma_pci_f *rf) 946 { 947 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 948 struct irdma_dma_mem mem; 949 struct irdma_sc_dev *dev = &rf->sc_dev; 950 struct irdma_cqp_init_info cqp_init_info = {0}; 951 struct irdma_cqp *cqp = &rf->cqp; 952 u16 maj_err, min_err; 953 int i, status; 954 955 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 956 memset(cqp->cqp_requests, 0, sqsize * sizeof(*cqp->cqp_requests)); 957 if (!cqp->cqp_requests) 958 return -ENOMEM; 959 960 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 961 memset(cqp->scratch_array, 0, sqsize * sizeof(*cqp->scratch_array)); 962 if (!cqp->scratch_array) { 963 status = -ENOMEM; 964 goto err_scratch; 965 } 966 967 dev->cqp = &cqp->sc_cqp; 968 dev->cqp->dev = dev; 969 cqp->sq.size = sizeof(struct irdma_cqp_sq_wqe) * sqsize; 970 cqp->sq.va = irdma_allocate_dma_mem(dev->hw, &cqp->sq, cqp->sq.size, 971 IRDMA_CQP_ALIGNMENT); 972 if (!cqp->sq.va) { 973 status = -ENOMEM; 974 goto err_sq; 975 } 976 977 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 978 IRDMA_HOST_CTX_ALIGNMENT_M); 979 if (status) 980 goto err_ctx; 981 982 dev->cqp->host_ctx_pa = mem.pa; 983 dev->cqp->host_ctx = mem.va; 984 /* populate the cqp init info */ 985 cqp_init_info.dev = dev; 986 cqp_init_info.sq_size = sqsize; 987 cqp_init_info.sq = cqp->sq.va; 988 cqp_init_info.sq_pa = cqp->sq.pa; 989 cqp_init_info.host_ctx_pa = mem.pa; 990 cqp_init_info.host_ctx = mem.va; 991 cqp_init_info.hmc_profile = rf->rsrc_profile; 992 cqp_init_info.scratch_array = cqp->scratch_array; 993 cqp_init_info.protocol_used = rf->protocol_used; 994 cqp_init_info.en_rem_endpoint_trk = rf->en_rem_endpoint_trk; 995 memcpy(&cqp_init_info.dcqcn_params, &rf->dcqcn_params, 996 sizeof(cqp_init_info.dcqcn_params)); 997 998 switch (rf->rdma_ver) { 999 case IRDMA_GEN_1: 1000 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 1001 break; 1002 case IRDMA_GEN_2: 1003 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 1004 break; 1005 } 1006 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 1007 if (status) { 1008 irdma_debug(dev, IRDMA_DEBUG_ERR, "cqp init status %d\n", 1009 status); 1010 goto err_ctx; 1011 } 1012 1013 spin_lock_init(&cqp->req_lock); 1014 spin_lock_init(&cqp->compl_lock); 1015 1016 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 1017 if (status) { 1018 irdma_debug(dev, IRDMA_DEBUG_ERR, 1019 "cqp create failed - status %d maj_err %d min_err %d\n", 1020 status, maj_err, min_err); 1021 goto err_create; 1022 } 1023 1024 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 1025 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 1026 1027 /* init the waitqueue of the cqp_requests and add them to the list */ 1028 for (i = 0; i < sqsize; i++) { 1029 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 1030 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 1031 } 1032 init_waitqueue_head(&cqp->remove_wq); 1033 return 0; 1034 1035 err_create: 1036 err_ctx: 1037 irdma_free_dma_mem(dev->hw, &cqp->sq); 1038 err_sq: 1039 kfree(cqp->scratch_array); 1040 cqp->scratch_array = NULL; 1041 err_scratch: 1042 kfree(cqp->cqp_requests); 1043 cqp->cqp_requests = NULL; 1044 1045 return status; 1046 } 1047 1048 /** 1049 * irdma_create_ccq - create control cq 1050 * @rf: RDMA PCI function 1051 * 1052 * Return 0, if the ccq and the resources associated with it 1053 * are successfully created, otherwise return error 1054 */ 1055 static int 1056 irdma_create_ccq(struct irdma_pci_f *rf) 1057 { 1058 struct irdma_sc_dev *dev = &rf->sc_dev; 1059 struct irdma_ccq_init_info info = {0}; 1060 struct irdma_ccq *ccq = &rf->ccq; 1061 int status; 1062 1063 dev->ccq = &ccq->sc_cq; 1064 dev->ccq->dev = dev; 1065 info.dev = dev; 1066 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1067 ccq->mem_cq.size = sizeof(struct irdma_cqe) * IW_CCQ_SIZE; 1068 ccq->mem_cq.va = irdma_allocate_dma_mem(dev->hw, &ccq->mem_cq, 1069 ccq->mem_cq.size, 1070 IRDMA_CQ0_ALIGNMENT); 1071 if (!ccq->mem_cq.va) 1072 return -ENOMEM; 1073 1074 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1075 ccq->shadow_area.size, 1076 IRDMA_SHADOWAREA_M); 1077 if (status) 1078 goto exit; 1079 1080 ccq->sc_cq.back_cq = ccq; 1081 /* populate the ccq init info */ 1082 info.cq_base = ccq->mem_cq.va; 1083 info.cq_pa = ccq->mem_cq.pa; 1084 info.num_elem = IW_CCQ_SIZE; 1085 info.shadow_area = ccq->shadow_area.va; 1086 info.shadow_area_pa = ccq->shadow_area.pa; 1087 info.ceqe_mask = false; 1088 info.ceq_id_valid = true; 1089 info.shadow_read_threshold = 16; 1090 info.vsi = &rf->default_vsi; 1091 status = irdma_sc_ccq_init(dev->ccq, &info); 1092 if (!status) 1093 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1094 exit: 1095 if (status) 1096 irdma_free_dma_mem(dev->hw, &ccq->mem_cq); 1097 1098 return status; 1099 } 1100 1101 /** 1102 * irdma_alloc_set_mac - set up a mac address table entry 1103 * @iwdev: irdma device 1104 * 1105 * Allocate a mac ip entry and add it to the hw table Return 0 1106 * if successful, otherwise return error 1107 */ 1108 static int 1109 irdma_alloc_set_mac(struct irdma_device *iwdev) 1110 { 1111 int status; 1112 1113 status = irdma_alloc_local_mac_entry(iwdev->rf, 1114 &iwdev->mac_ip_table_idx); 1115 if (!status) { 1116 status = irdma_add_local_mac_entry(iwdev->rf, 1117 (u8 *)IF_LLADDR(iwdev->netdev), 1118 (u8)iwdev->mac_ip_table_idx); 1119 if (status) 1120 irdma_del_local_mac_entry(iwdev->rf, 1121 (u8)iwdev->mac_ip_table_idx); 1122 } 1123 return status; 1124 } 1125 1126 /** 1127 * irdma_irq_request - set up the msix interrupt vector 1128 * @rf: RDMA PCI function 1129 * @msix_vec: interrupt vector information 1130 * @handler: function pointer to associate with interrupt 1131 * @argument: argument passed to the handler 1132 * 1133 * Allocate interrupt resources and setup interrupt 1134 * Return 0 if successful, otherwise return error 1135 * Note that after this function bus_describe_intr shall 1136 * be called. 1137 */ 1138 static int 1139 irdma_irq_request(struct irdma_pci_f *rf, 1140 struct irdma_msix_vector *msix_vec, 1141 driver_intr_t handler, void *argument) 1142 { 1143 device_t dev = rf->dev_ctx.dev; 1144 int rid = msix_vec->idx + 1; 1145 int err, status; 1146 1147 msix_vec->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 1148 if (!msix_vec->res) { 1149 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1150 "Unable to allocate bus resource int[%d]\n", rid); 1151 return -EINVAL; 1152 } 1153 err = bus_setup_intr(dev, msix_vec->res, INTR_TYPE_NET | INTR_MPSAFE, 1154 NULL, handler, argument, &msix_vec->tag); 1155 if (err) { 1156 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1157 "Unable to register handler with %x status\n", err); 1158 status = -EINVAL; 1159 goto fail_intr; 1160 } 1161 return 0; 1162 1163 fail_intr: 1164 bus_release_resource(dev, SYS_RES_IRQ, rid, msix_vec->res); 1165 msix_vec->res = NULL; 1166 1167 return status; 1168 } 1169 1170 /** 1171 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1172 * ceq 1173 * @rf: RDMA PCI function 1174 * @iwceq: ceq associated with the vector 1175 * @ceq_id: the id number of the iwceq 1176 * @msix_vec: interrupt vector information 1177 * 1178 * Allocate interrupt resources and enable irq handling 1179 * Return 0 if successful, otherwise return error 1180 */ 1181 static int 1182 irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1183 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1184 { 1185 int status; 1186 1187 if (rf->msix_shared && !ceq_id) { 1188 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1189 status = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf); 1190 if (status) 1191 return status; 1192 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "AEQCEQ"); 1193 } else { 1194 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1195 1196 status = irdma_irq_request(rf, msix_vec, irdma_ceq_handler, iwceq); 1197 if (status) 1198 return status; 1199 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "CEQ"); 1200 } 1201 1202 msix_vec->ceq_id = ceq_id; 1203 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1204 1205 return 0; 1206 } 1207 1208 /** 1209 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1210 * @rf: RDMA PCI function 1211 * 1212 * Allocate interrupt resources and enable irq handling 1213 * Return 0 if successful, otherwise return error 1214 */ 1215 static int 1216 irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1217 { 1218 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1219 u32 ret = 0; 1220 1221 if (!rf->msix_shared) { 1222 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1223 ret = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf); 1224 if (ret) 1225 return ret; 1226 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "irdma"); 1227 } 1228 if (ret) { 1229 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1230 "aeq irq config fail\n"); 1231 return -EINVAL; 1232 } 1233 1234 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1235 1236 return 0; 1237 } 1238 1239 /** 1240 * irdma_create_ceq - create completion event queue 1241 * @rf: RDMA PCI function 1242 * @iwceq: pointer to the ceq resources to be created 1243 * @ceq_id: the id number of the iwceq 1244 * @vsi: SC vsi struct 1245 * 1246 * Return 0, if the ceq and the resources associated with it 1247 * are successfully created, otherwise return error 1248 */ 1249 static int 1250 irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1251 u32 ceq_id, struct irdma_sc_vsi *vsi) 1252 { 1253 int status; 1254 struct irdma_ceq_init_info info = {0}; 1255 struct irdma_sc_dev *dev = &rf->sc_dev; 1256 u64 scratch; 1257 u32 ceq_size; 1258 1259 info.ceq_id = ceq_id; 1260 iwceq->rf = rf; 1261 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1262 dev->hw_attrs.max_hw_ceq_size); 1263 iwceq->mem.size = sizeof(struct irdma_ceqe) * ceq_size; 1264 iwceq->mem.va = irdma_allocate_dma_mem(dev->hw, &iwceq->mem, 1265 iwceq->mem.size, 1266 IRDMA_CEQ_ALIGNMENT); 1267 if (!iwceq->mem.va) 1268 return -ENOMEM; 1269 1270 info.ceq_id = ceq_id; 1271 info.ceqe_base = iwceq->mem.va; 1272 info.ceqe_pa = iwceq->mem.pa; 1273 info.elem_cnt = ceq_size; 1274 info.reg_cq = kzalloc(sizeof(struct irdma_sc_cq *) * info.elem_cnt, GFP_KERNEL); 1275 1276 iwceq->sc_ceq.ceq_id = ceq_id; 1277 info.dev = dev; 1278 info.vsi = vsi; 1279 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1280 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1281 if (!status) { 1282 if (dev->ceq_valid) 1283 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1284 IRDMA_OP_CEQ_CREATE); 1285 else 1286 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1287 } 1288 1289 if (status) { 1290 kfree(info.reg_cq); 1291 irdma_free_dma_mem(dev->hw, &iwceq->mem); 1292 } 1293 1294 return status; 1295 } 1296 1297 /** 1298 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1299 * @rf: RDMA PCI function 1300 * 1301 * Allocate a list for all device completion event queues 1302 * Create the ceq 0 and configure it's msix interrupt vector 1303 * Return 0, if successfully set up, otherwise return error 1304 */ 1305 static int 1306 irdma_setup_ceq_0(struct irdma_pci_f *rf) 1307 { 1308 struct irdma_ceq *iwceq; 1309 struct irdma_msix_vector *msix_vec; 1310 u32 i; 1311 int status = 0; 1312 u32 num_ceqs; 1313 1314 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1315 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1316 memset(rf->ceqlist, 0, num_ceqs * sizeof(*rf->ceqlist)); 1317 if (!rf->ceqlist) { 1318 status = -ENOMEM; 1319 goto exit; 1320 } 1321 1322 iwceq = &rf->ceqlist[0]; 1323 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1324 if (status) { 1325 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1326 "create ceq status = %d\n", status); 1327 goto exit; 1328 } 1329 1330 spin_lock_init(&iwceq->ce_lock); 1331 i = rf->msix_shared ? 0 : 1; 1332 msix_vec = &rf->iw_msixtbl[i]; 1333 iwceq->irq = msix_vec->irq; 1334 iwceq->msix_idx = msix_vec->idx; 1335 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1336 if (status) { 1337 irdma_destroy_ceq(rf, iwceq); 1338 goto exit; 1339 } 1340 1341 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1342 rf->ceqs_count++; 1343 1344 exit: 1345 if (status && !rf->ceqs_count) { 1346 kfree(rf->ceqlist); 1347 rf->ceqlist = NULL; 1348 return status; 1349 } 1350 rf->sc_dev.ceq_valid = true; 1351 1352 return 0; 1353 } 1354 1355 /** 1356 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1357 * @rf: RDMA PCI function 1358 * @vsi: VSI structure for this CEQ 1359 * 1360 * Allocate a list for all device completion event queues 1361 * Create the ceq's and configure their msix interrupt vectors 1362 * Return 0, if ceqs are successfully set up, otherwise return error 1363 */ 1364 static int 1365 irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1366 { 1367 u32 i; 1368 u32 ceq_id; 1369 struct irdma_ceq *iwceq; 1370 struct irdma_msix_vector *msix_vec; 1371 int status; 1372 u32 num_ceqs; 1373 1374 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1375 i = (rf->msix_shared) ? 1 : 2; 1376 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1377 iwceq = &rf->ceqlist[ceq_id]; 1378 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1379 if (status) { 1380 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1381 "create ceq status = %d\n", status); 1382 goto del_ceqs; 1383 } 1384 spin_lock_init(&iwceq->ce_lock); 1385 msix_vec = &rf->iw_msixtbl[i]; 1386 iwceq->irq = msix_vec->irq; 1387 iwceq->msix_idx = msix_vec->idx; 1388 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1389 if (status) { 1390 irdma_destroy_ceq(rf, iwceq); 1391 goto del_ceqs; 1392 } 1393 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1394 rf->ceqs_count++; 1395 } 1396 1397 return 0; 1398 1399 del_ceqs: 1400 irdma_del_ceqs(rf); 1401 1402 return status; 1403 } 1404 1405 static int 1406 irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1407 { 1408 struct irdma_aeq *aeq = &rf->aeq; 1409 dma_addr_t *pg_arr; 1410 u32 pg_cnt; 1411 int status; 1412 1413 if (rf->rdma_ver < IRDMA_GEN_2) 1414 return -EOPNOTSUPP; 1415 1416 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1417 aeq->mem.va = vzalloc(aeq->mem.size); 1418 1419 if (!aeq->mem.va) 1420 return -ENOMEM; 1421 1422 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1423 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1424 if (status) { 1425 vfree(aeq->mem.va); 1426 return status; 1427 } 1428 1429 pg_arr = (dma_addr_t *) aeq->palloc.level1.addr; 1430 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1431 if (status) { 1432 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1433 vfree(aeq->mem.va); 1434 return status; 1435 } 1436 1437 return 0; 1438 } 1439 1440 /** 1441 * irdma_create_aeq - create async event queue 1442 * @rf: RDMA PCI function 1443 * 1444 * Return 0, if the aeq and the resources associated with it 1445 * are successfully created, otherwise return error 1446 */ 1447 static int 1448 irdma_create_aeq(struct irdma_pci_f *rf) 1449 { 1450 struct irdma_aeq_init_info info = {0}; 1451 struct irdma_sc_dev *dev = &rf->sc_dev; 1452 struct irdma_aeq *aeq = &rf->aeq; 1453 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1454 u32 aeq_size; 1455 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1456 int status; 1457 1458 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1459 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1460 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1461 1462 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * aeq_size; 1463 aeq->mem.va = irdma_allocate_dma_mem(dev->hw, &aeq->mem, aeq->mem.size, 1464 IRDMA_AEQ_ALIGNMENT); 1465 if (aeq->mem.va) 1466 goto skip_virt_aeq; 1467 1468 /* physically mapped aeq failed. setup virtual aeq */ 1469 status = irdma_create_virt_aeq(rf, aeq_size); 1470 if (status) 1471 return status; 1472 1473 info.virtual_map = true; 1474 aeq->virtual_map = info.virtual_map; 1475 info.pbl_chunk_size = 1; 1476 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1477 1478 skip_virt_aeq: 1479 info.aeqe_base = aeq->mem.va; 1480 info.aeq_elem_pa = aeq->mem.pa; 1481 info.elem_cnt = aeq_size; 1482 info.dev = dev; 1483 info.msix_idx = rf->iw_msixtbl->idx; 1484 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1485 if (status) 1486 goto err; 1487 1488 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1489 if (status) 1490 goto err; 1491 1492 return 0; 1493 1494 err: 1495 if (aeq->virtual_map) 1496 irdma_destroy_virt_aeq(rf); 1497 else 1498 irdma_free_dma_mem(dev->hw, &aeq->mem); 1499 1500 return status; 1501 } 1502 1503 /** 1504 * irdma_setup_aeq - set up the device aeq 1505 * @rf: RDMA PCI function 1506 * 1507 * Create the aeq and configure its msix interrupt vector 1508 * Return 0 if successful, otherwise return error 1509 */ 1510 static int 1511 irdma_setup_aeq(struct irdma_pci_f *rf) 1512 { 1513 struct irdma_sc_dev *dev = &rf->sc_dev; 1514 int status; 1515 1516 status = irdma_create_aeq(rf); 1517 if (status) 1518 return status; 1519 1520 status = irdma_cfg_aeq_vector(rf); 1521 if (status) { 1522 irdma_destroy_aeq(rf); 1523 return status; 1524 } 1525 1526 if (!rf->msix_shared) 1527 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1528 1529 return 0; 1530 } 1531 1532 /** 1533 * irdma_initialize_ilq - create iwarp local queue for cm 1534 * @iwdev: irdma device 1535 * 1536 * Return 0 if successful, otherwise return error 1537 */ 1538 static int 1539 irdma_initialize_ilq(struct irdma_device *iwdev) 1540 { 1541 struct irdma_puda_rsrc_info info = {0}; 1542 int status; 1543 1544 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1545 info.cq_id = 1; 1546 info.qp_id = 1; 1547 info.count = 1; 1548 info.pd_id = 1; 1549 info.abi_ver = IRDMA_ABI_VER; 1550 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1551 info.rq_size = info.sq_size; 1552 info.buf_size = 1024; 1553 info.tx_buf_cnt = 2 * info.sq_size; 1554 info.receive = irdma_receive_ilq; 1555 info.xmit_complete = irdma_free_sqbuf; 1556 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1557 if (status) 1558 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, 1559 "ilq create fail\n"); 1560 1561 return status; 1562 } 1563 1564 /** 1565 * irdma_initialize_ieq - create iwarp exception queue 1566 * @iwdev: irdma device 1567 * 1568 * Return 0 if successful, otherwise return error 1569 */ 1570 static int 1571 irdma_initialize_ieq(struct irdma_device *iwdev) 1572 { 1573 struct irdma_puda_rsrc_info info = {0}; 1574 int status; 1575 1576 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1577 info.cq_id = 2; 1578 info.qp_id = iwdev->vsi.exception_lan_q; 1579 info.count = 1; 1580 info.pd_id = 2; 1581 info.abi_ver = IRDMA_ABI_VER; 1582 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1583 info.rq_size = info.sq_size; 1584 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1585 info.tx_buf_cnt = 4096; 1586 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1587 if (status) 1588 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, 1589 "ieq create fail\n"); 1590 1591 return status; 1592 } 1593 1594 /** 1595 * irdma_reinitialize_ieq - destroy and re-create ieq 1596 * @vsi: VSI structure 1597 */ 1598 void 1599 irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1600 { 1601 struct irdma_device *iwdev = vsi->back_vsi; 1602 struct irdma_pci_f *rf = iwdev->rf; 1603 1604 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1605 if (irdma_initialize_ieq(iwdev)) { 1606 iwdev->rf->reset = true; 1607 rf->gen_ops.request_reset(rf); 1608 } 1609 } 1610 1611 /** 1612 * irdma_hmc_setup - create hmc objects for the device 1613 * @rf: RDMA PCI function 1614 * 1615 * Set up the device private memory space for the number and size of 1616 * the hmc objects and create the objects 1617 * Return 0 if successful, otherwise return error 1618 */ 1619 static int 1620 irdma_hmc_setup(struct irdma_pci_f *rf) 1621 { 1622 int status; 1623 struct irdma_sc_dev *dev = &rf->sc_dev; 1624 u32 qpcnt; 1625 1626 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1627 1628 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1629 status = irdma_cfg_fpm_val(dev, qpcnt); 1630 if (status) 1631 return status; 1632 1633 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1634 1635 return status; 1636 } 1637 1638 /** 1639 * irdma_del_init_mem - deallocate memory resources 1640 * @rf: RDMA PCI function 1641 */ 1642 static void 1643 irdma_del_init_mem(struct irdma_pci_f *rf) 1644 { 1645 struct irdma_sc_dev *dev = &rf->sc_dev; 1646 1647 kfree(dev->hmc_info->sd_table.sd_entry); 1648 dev->hmc_info->sd_table.sd_entry = NULL; 1649 vfree(rf->mem_rsrc); 1650 rf->mem_rsrc = NULL; 1651 irdma_free_dma_mem(&rf->hw, &rf->obj_mem); 1652 if (rf->rdma_ver != IRDMA_GEN_1) { 1653 kfree(rf->allocated_ws_nodes); 1654 rf->allocated_ws_nodes = NULL; 1655 } 1656 mutex_destroy(&dev->ws_mutex); 1657 kfree(rf->ceqlist); 1658 rf->ceqlist = NULL; 1659 kfree(rf->iw_msixtbl); 1660 rf->iw_msixtbl = NULL; 1661 kfree(rf->hmc_info_mem); 1662 rf->hmc_info_mem = NULL; 1663 } 1664 /** 1665 * irdma_initialize_dev - initialize device 1666 * @rf: RDMA PCI function 1667 * 1668 * Allocate memory for the hmc objects and initialize iwdev 1669 * Return 0 if successful, otherwise clean up the resources 1670 * and return error 1671 */ 1672 static int 1673 irdma_initialize_dev(struct irdma_pci_f *rf) 1674 { 1675 int status; 1676 struct irdma_sc_dev *dev = &rf->sc_dev; 1677 struct irdma_device_init_info info = {0}; 1678 struct irdma_dma_mem mem; 1679 u32 size; 1680 1681 size = sizeof(struct irdma_hmc_pble_rsrc) + 1682 sizeof(struct irdma_hmc_info) + 1683 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1684 1685 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1686 if (!rf->hmc_info_mem) 1687 return -ENOMEM; 1688 1689 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1690 dev->hmc_info = &rf->hw.hmc; 1691 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1692 (rf->pble_rsrc + 1); 1693 1694 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1695 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1696 if (status) 1697 goto error; 1698 1699 info.fpm_query_buf_pa = mem.pa; 1700 info.fpm_query_buf = mem.va; 1701 1702 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1703 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1704 if (status) 1705 goto error; 1706 1707 info.fpm_commit_buf_pa = mem.pa; 1708 info.fpm_commit_buf = mem.va; 1709 1710 info.bar0 = rf->hw.hw_addr; 1711 info.hmc_fn_id = rf->peer_info->pf_id; 1712 info.hw = &rf->hw; 1713 status = irdma_sc_dev_init(&rf->sc_dev, &info); 1714 if (status) 1715 goto error; 1716 1717 return status; 1718 error: 1719 kfree(rf->hmc_info_mem); 1720 rf->hmc_info_mem = NULL; 1721 1722 return status; 1723 } 1724 1725 /** 1726 * irdma_rt_deinit_hw - clean up the irdma device resources 1727 * @iwdev: irdma device 1728 * 1729 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1730 * device queues and free the pble and the hmc objects 1731 */ 1732 void 1733 irdma_rt_deinit_hw(struct irdma_device *iwdev) 1734 { 1735 struct irdma_sc_qp qp = {{0}}; 1736 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_INIT, "state = %d\n", 1737 iwdev->init_state); 1738 1739 switch (iwdev->init_state) { 1740 case IP_ADDR_REGISTERED: 1741 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1742 irdma_del_local_mac_entry(iwdev->rf, 1743 (u8)iwdev->mac_ip_table_idx); 1744 /* fallthrough */ 1745 case AEQ_CREATED: 1746 case PBLE_CHUNK_MEM: 1747 case CEQS_CREATED: 1748 case REM_ENDPOINT_TRK_CREATED: 1749 if (iwdev->rf->en_rem_endpoint_trk) { 1750 qp.dev = &iwdev->rf->sc_dev; 1751 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; 1752 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; 1753 irdma_cqp_qp_destroy_cmd(qp.dev, &qp); 1754 } 1755 /* fallthrough */ 1756 case IEQ_CREATED: 1757 if (!iwdev->roce_mode) 1758 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1759 iwdev->rf->reset); 1760 /* fallthrough */ 1761 case ILQ_CREATED: 1762 if (!iwdev->roce_mode) 1763 irdma_puda_dele_rsrc(&iwdev->vsi, 1764 IRDMA_PUDA_RSRC_TYPE_ILQ, 1765 iwdev->rf->reset); 1766 break; 1767 default: 1768 irdma_dev_warn(&iwdev->rf->sc_dev, "bad init_state = %d\n", 1769 iwdev->init_state); 1770 break; 1771 } 1772 1773 irdma_cleanup_cm_core(&iwdev->cm_core); 1774 if (iwdev->vsi.pestat) { 1775 irdma_vsi_stats_free(&iwdev->vsi); 1776 kfree(iwdev->vsi.pestat); 1777 } 1778 if (iwdev->cleanup_wq) 1779 destroy_workqueue(iwdev->cleanup_wq); 1780 } 1781 1782 static int 1783 irdma_setup_init_state(struct irdma_pci_f *rf) 1784 { 1785 int status; 1786 1787 status = irdma_save_msix_info(rf); 1788 if (status) 1789 return status; 1790 1791 rf->obj_mem.size = 8192; 1792 rf->obj_mem.va = irdma_allocate_dma_mem(&rf->hw, &rf->obj_mem, 1793 rf->obj_mem.size, 1794 IRDMA_HW_PAGE_SIZE); 1795 if (!rf->obj_mem.va) { 1796 status = -ENOMEM; 1797 goto clean_msixtbl; 1798 } 1799 1800 rf->obj_next = rf->obj_mem; 1801 status = irdma_initialize_dev(rf); 1802 if (status) 1803 goto clean_obj_mem; 1804 1805 return 0; 1806 1807 clean_obj_mem: 1808 irdma_free_dma_mem(&rf->hw, &rf->obj_mem); 1809 clean_msixtbl: 1810 kfree(rf->iw_msixtbl); 1811 rf->iw_msixtbl = NULL; 1812 return status; 1813 } 1814 1815 /** 1816 * irdma_get_used_rsrc - determine resources used internally 1817 * @iwdev: irdma device 1818 * 1819 * Called at the end of open to get all internal allocations 1820 */ 1821 static void 1822 irdma_get_used_rsrc(struct irdma_device *iwdev) 1823 { 1824 iwdev->rf->used_pds = find_next_zero_bit(iwdev->rf->allocated_pds, 1825 iwdev->rf->max_pd, 0); 1826 iwdev->rf->used_qps = find_next_zero_bit(iwdev->rf->allocated_qps, 1827 iwdev->rf->max_qp, 0); 1828 iwdev->rf->used_cqs = find_next_zero_bit(iwdev->rf->allocated_cqs, 1829 iwdev->rf->max_cq, 0); 1830 iwdev->rf->used_mrs = find_next_zero_bit(iwdev->rf->allocated_mrs, 1831 iwdev->rf->max_mr, 0); 1832 } 1833 1834 void 1835 irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1836 { 1837 enum init_completion_state state = rf->init_state; 1838 1839 rf->init_state = INVALID_STATE; 1840 if (rf->rsrc_created) { 1841 irdma_destroy_aeq(rf); 1842 irdma_destroy_pble_prm(rf->pble_rsrc); 1843 irdma_del_ceqs(rf); 1844 rf->rsrc_created = false; 1845 } 1846 1847 switch (state) { 1848 case CEQ0_CREATED: 1849 irdma_del_ceq_0(rf); 1850 /* fallthrough */ 1851 case CCQ_CREATED: 1852 irdma_destroy_ccq(rf); 1853 /* fallthrough */ 1854 case HW_RSRC_INITIALIZED: 1855 case HMC_OBJS_CREATED: 1856 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1857 rf->reset, rf->rdma_ver); 1858 /* fallthrough */ 1859 case CQP_CREATED: 1860 irdma_destroy_cqp(rf, !rf->reset); 1861 /* fallthrough */ 1862 case INITIAL_STATE: 1863 irdma_del_init_mem(rf); 1864 break; 1865 case INVALID_STATE: 1866 default: 1867 irdma_pr_warn("bad init_state = %d\n", rf->init_state); 1868 break; 1869 } 1870 } 1871 1872 /** 1873 * irdma_rt_init_hw - Initializes runtime portion of HW 1874 * @iwdev: irdma device 1875 * @l2params: qos, tc, mtu info from netdev driver 1876 * 1877 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1878 * device resource objects. 1879 */ 1880 int 1881 irdma_rt_init_hw(struct irdma_device *iwdev, 1882 struct irdma_l2params *l2params) 1883 { 1884 struct irdma_pci_f *rf = iwdev->rf; 1885 struct irdma_sc_dev *dev = &rf->sc_dev; 1886 struct irdma_sc_qp qp = {{0}}; 1887 struct irdma_vsi_init_info vsi_info = {0}; 1888 struct irdma_vsi_stats_info stats_info = {0}; 1889 int status; 1890 1891 vsi_info.dev = dev; 1892 vsi_info.back_vsi = iwdev; 1893 vsi_info.params = l2params; 1894 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1895 vsi_info.register_qset = rf->gen_ops.register_qset; 1896 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1897 vsi_info.exception_lan_q = 2; 1898 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1899 1900 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1901 if (status) 1902 return status; 1903 1904 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1905 if (!stats_info.pestat) { 1906 irdma_cleanup_cm_core(&iwdev->cm_core); 1907 return -ENOMEM; 1908 } 1909 stats_info.fcn_id = dev->hmc_fn_id; 1910 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1911 if (status) { 1912 irdma_cleanup_cm_core(&iwdev->cm_core); 1913 kfree(stats_info.pestat); 1914 return status; 1915 } 1916 1917 do { 1918 if (!iwdev->roce_mode) { 1919 status = irdma_initialize_ilq(iwdev); 1920 if (status) 1921 break; 1922 iwdev->init_state = ILQ_CREATED; 1923 status = irdma_initialize_ieq(iwdev); 1924 if (status) 1925 break; 1926 iwdev->init_state = IEQ_CREATED; 1927 } 1928 if (iwdev->rf->en_rem_endpoint_trk) { 1929 qp.dev = dev; 1930 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; 1931 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; 1932 status = irdma_cqp_qp_create_cmd(dev, &qp); 1933 if (status) 1934 break; 1935 iwdev->init_state = REM_ENDPOINT_TRK_CREATED; 1936 } 1937 if (!rf->rsrc_created) { 1938 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1939 if (status) 1940 break; 1941 1942 iwdev->init_state = CEQS_CREATED; 1943 1944 status = irdma_hmc_init_pble(&rf->sc_dev, 1945 rf->pble_rsrc); 1946 if (status) { 1947 irdma_del_ceqs(rf); 1948 break; 1949 } 1950 1951 iwdev->init_state = PBLE_CHUNK_MEM; 1952 1953 status = irdma_setup_aeq(rf); 1954 if (status) { 1955 irdma_destroy_pble_prm(rf->pble_rsrc); 1956 irdma_del_ceqs(rf); 1957 break; 1958 } 1959 iwdev->init_state = AEQ_CREATED; 1960 rf->rsrc_created = true; 1961 } 1962 1963 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1964 irdma_alloc_set_mac(iwdev); 1965 irdma_add_ip(iwdev); 1966 iwdev->init_state = IP_ADDR_REGISTERED; 1967 1968 /* 1969 * handles asynch cleanup tasks - disconnect CM , free qp, free cq bufs 1970 */ 1971 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1972 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1973 if (!iwdev->cleanup_wq) 1974 return -ENOMEM; 1975 irdma_get_used_rsrc(iwdev); 1976 init_waitqueue_head(&iwdev->suspend_wq); 1977 1978 return 0; 1979 } while (0); 1980 1981 irdma_dev_err(idev_to_dev(dev), "HW runtime init FAIL status = %d last cmpl = %d\n", 1982 status, iwdev->init_state); 1983 irdma_rt_deinit_hw(iwdev); 1984 1985 return status; 1986 } 1987 1988 /** 1989 * irdma_ctrl_init_hw - Initializes control portion of HW 1990 * @rf: RDMA PCI function 1991 * 1992 * Create admin queues, HMC obejcts and RF resource objects 1993 */ 1994 int 1995 irdma_ctrl_init_hw(struct irdma_pci_f *rf) 1996 { 1997 struct irdma_sc_dev *dev = &rf->sc_dev; 1998 int status; 1999 do { 2000 status = irdma_setup_init_state(rf); 2001 if (status) 2002 break; 2003 rf->init_state = INITIAL_STATE; 2004 2005 status = irdma_create_cqp(rf); 2006 if (status) 2007 break; 2008 rf->init_state = CQP_CREATED; 2009 2010 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 2011 if (rf->rdma_ver != IRDMA_GEN_1) { 2012 status = irdma_get_rdma_features(dev); 2013 if (status) 2014 break; 2015 } 2016 2017 status = irdma_hmc_setup(rf); 2018 if (status) 2019 break; 2020 rf->init_state = HMC_OBJS_CREATED; 2021 2022 status = irdma_initialize_hw_rsrc(rf); 2023 if (status) 2024 break; 2025 rf->init_state = HW_RSRC_INITIALIZED; 2026 2027 status = irdma_create_ccq(rf); 2028 if (status) 2029 break; 2030 rf->init_state = CCQ_CREATED; 2031 2032 status = irdma_setup_ceq_0(rf); 2033 if (status) 2034 break; 2035 rf->init_state = CEQ0_CREATED; 2036 /* Handles processing of CQP completions */ 2037 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", 2038 WQ_HIGHPRI | WQ_UNBOUND); 2039 if (!rf->cqp_cmpl_wq) { 2040 status = -ENOMEM; 2041 break; 2042 } 2043 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 2044 irdma_sc_ccq_arm(dev->ccq); 2045 return 0; 2046 } while (0); 2047 2048 pr_err("IRDMA hardware initialization FAILED init_state=%d status=%d\n", 2049 rf->init_state, status); 2050 irdma_ctrl_deinit_hw(rf); 2051 return status; 2052 } 2053 2054 /** 2055 * irdma_set_hw_rsrc - set hw memory resources. 2056 * @rf: RDMA PCI function 2057 */ 2058 static void 2059 irdma_set_hw_rsrc(struct irdma_pci_f *rf) 2060 { 2061 rf->allocated_qps = (void *)(rf->mem_rsrc + 2062 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 2063 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 2064 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 2065 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 2066 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 2067 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 2068 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 2069 2070 rf->qp_table = (struct irdma_qp **) 2071 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 2072 rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]); 2073 2074 spin_lock_init(&rf->rsrc_lock); 2075 spin_lock_init(&rf->arp_lock); 2076 spin_lock_init(&rf->qptable_lock); 2077 spin_lock_init(&rf->cqtable_lock); 2078 spin_lock_init(&rf->qh_list_lock); 2079 } 2080 2081 /** 2082 * irdma_calc_mem_rsrc_size - calculate memory resources size. 2083 * @rf: RDMA PCI function 2084 */ 2085 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf){ 2086 u32 rsrc_size; 2087 2088 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 2089 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 2090 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 2091 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 2092 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 2093 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 2094 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 2095 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 2096 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 2097 rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq; 2098 2099 return rsrc_size; 2100 } 2101 2102 /** 2103 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 2104 * @rf: RDMA PCI function 2105 */ 2106 u32 2107 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 2108 { 2109 u32 rsrc_size; 2110 u32 mrdrvbits; 2111 u32 ret; 2112 2113 if (rf->rdma_ver != IRDMA_GEN_1) { 2114 rf->allocated_ws_nodes = 2115 kcalloc(BITS_TO_LONGS(IRDMA_MAX_WS_NODES), 2116 sizeof(unsigned long), GFP_KERNEL); 2117 if (!rf->allocated_ws_nodes) 2118 return -ENOMEM; 2119 2120 set_bit(0, rf->allocated_ws_nodes); 2121 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 2122 } 2123 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 2124 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 2125 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 2126 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 2127 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 2128 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 2129 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 2130 rf->max_mcg = rf->max_qp; 2131 2132 rsrc_size = irdma_calc_mem_rsrc_size(rf); 2133 rf->mem_rsrc = vzalloc(rsrc_size); 2134 if (!rf->mem_rsrc) { 2135 ret = -ENOMEM; 2136 goto mem_rsrc_vmalloc_fail; 2137 } 2138 2139 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2140 2141 irdma_set_hw_rsrc(rf); 2142 2143 set_bit(0, rf->allocated_mrs); 2144 set_bit(0, rf->allocated_qps); 2145 set_bit(0, rf->allocated_cqs); 2146 set_bit(0, rf->allocated_pds); 2147 set_bit(0, rf->allocated_arps); 2148 set_bit(0, rf->allocated_ahs); 2149 set_bit(0, rf->allocated_mcgs); 2150 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2151 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2152 set_bit(IRDMA_REM_ENDPOINT_TRK_QPID, rf->allocated_qps); /* qp 3 Remote Endpt trk */ 2153 set_bit(1, rf->allocated_cqs); 2154 set_bit(1, rf->allocated_pds); 2155 set_bit(2, rf->allocated_cqs); 2156 set_bit(2, rf->allocated_pds); 2157 2158 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2159 /* stag index mask has a minimum of 14 bits */ 2160 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2161 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2162 2163 return 0; 2164 2165 mem_rsrc_vmalloc_fail: 2166 kfree(rf->allocated_ws_nodes); 2167 rf->allocated_ws_nodes = NULL; 2168 2169 return ret; 2170 } 2171 2172 /** 2173 * irdma_cqp_ce_handler - handle cqp completions 2174 * @rf: RDMA PCI function 2175 * @cq: cq for cqp completions 2176 */ 2177 void 2178 irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2179 { 2180 struct irdma_cqp_request *cqp_request; 2181 struct irdma_sc_dev *dev = &rf->sc_dev; 2182 u32 cqe_count = 0; 2183 struct irdma_ccq_cqe_info info; 2184 unsigned long flags; 2185 int ret; 2186 2187 do { 2188 memset(&info, 0, sizeof(info)); 2189 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2190 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2191 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2192 if (ret) 2193 break; 2194 2195 cqp_request = (struct irdma_cqp_request *) 2196 (uintptr_t)info.scratch; 2197 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2198 info.maj_err_code, 2199 info.min_err_code)) 2200 irdma_dev_err(dev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2201 info.op_code, info.maj_err_code, 2202 info.min_err_code); 2203 2204 if (cqp_request) { 2205 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2206 cqp_request->compl_info.min_err_code = info.min_err_code; 2207 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2208 cqp_request->compl_info.error = info.error; 2209 irdma_complete_cqp_request(&rf->cqp, cqp_request); 2210 } 2211 2212 cqe_count++; 2213 } while (1); 2214 2215 if (cqe_count) { 2216 irdma_process_bh(dev); 2217 irdma_sc_ccq_arm(dev->ccq); 2218 } 2219 } 2220 2221 /** 2222 * cqp_compl_worker - Handle cqp completions 2223 * @work: Pointer to work structure 2224 */ 2225 void 2226 cqp_compl_worker(struct work_struct *work) 2227 { 2228 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2229 cqp_cmpl_work); 2230 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2231 2232 irdma_cqp_ce_handler(rf, cq); 2233 } 2234 2235 /** 2236 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2237 * @cm_core: cm's core 2238 * @port: port to identify apbvt entry 2239 */ 2240 static struct irdma_apbvt_entry * 2241 irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2242 u16 port) 2243 { 2244 struct irdma_apbvt_entry *entry; 2245 2246 HASH_FOR_EACH_POSSIBLE(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2247 if (entry->port == port) { 2248 entry->use_cnt++; 2249 return entry; 2250 } 2251 } 2252 2253 return NULL; 2254 } 2255 2256 /** 2257 * irdma_next_iw_state - modify qp state 2258 * @iwqp: iwarp qp to modify 2259 * @state: next state for qp 2260 * @del_hash: del hash 2261 * @term: term message 2262 * @termlen: length of term message 2263 */ 2264 void 2265 irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2266 u8 termlen) 2267 { 2268 struct irdma_modify_qp_info info = {0}; 2269 2270 info.next_iwarp_state = state; 2271 info.remove_hash_idx = del_hash; 2272 info.cq_num_valid = true; 2273 info.arp_cache_idx_valid = true; 2274 info.dont_send_term = true; 2275 info.dont_send_fin = true; 2276 info.termlen = termlen; 2277 2278 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2279 info.dont_send_term = false; 2280 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2281 info.dont_send_fin = false; 2282 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2283 info.reset_tcp_conn = true; 2284 iwqp->hw_iwarp_state = state; 2285 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2286 iwqp->iwarp_state = info.next_iwarp_state; 2287 } 2288 2289 /** 2290 * irdma_del_local_mac_entry - remove a mac entry from the hw 2291 * table 2292 * @rf: RDMA PCI function 2293 * @idx: the index of the mac ip address to delete 2294 */ 2295 void 2296 irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2297 { 2298 struct irdma_cqp *iwcqp = &rf->cqp; 2299 struct irdma_cqp_request *cqp_request; 2300 struct cqp_cmds_info *cqp_info; 2301 2302 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2303 if (!cqp_request) 2304 return; 2305 2306 cqp_info = &cqp_request->info; 2307 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2308 cqp_info->post_sq = 1; 2309 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2310 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2311 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2312 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2313 2314 irdma_handle_cqp_op(rf, cqp_request); 2315 irdma_put_cqp_request(iwcqp, cqp_request); 2316 } 2317 2318 /** 2319 * irdma_add_local_mac_entry - add a mac ip address entry to the 2320 * hw table 2321 * @rf: RDMA PCI function 2322 * @mac_addr: pointer to mac address 2323 * @idx: the index of the mac ip address to add 2324 */ 2325 int 2326 irdma_add_local_mac_entry(struct irdma_pci_f *rf, u8 *mac_addr, u16 idx) 2327 { 2328 struct irdma_local_mac_entry_info *info; 2329 struct irdma_cqp *iwcqp = &rf->cqp; 2330 struct irdma_cqp_request *cqp_request; 2331 struct cqp_cmds_info *cqp_info; 2332 int status; 2333 2334 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2335 if (!cqp_request) 2336 return -ENOMEM; 2337 2338 cqp_info = &cqp_request->info; 2339 cqp_info->post_sq = 1; 2340 info = &cqp_info->in.u.add_local_mac_entry.info; 2341 ether_addr_copy(info->mac_addr, mac_addr); 2342 info->entry_idx = idx; 2343 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2344 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2345 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2346 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2347 2348 status = irdma_handle_cqp_op(rf, cqp_request); 2349 irdma_put_cqp_request(iwcqp, cqp_request); 2350 2351 return status; 2352 } 2353 2354 /** 2355 * irdma_alloc_local_mac_entry - allocate a mac entry 2356 * @rf: RDMA PCI function 2357 * @mac_tbl_idx: the index of the new mac address 2358 * 2359 * Allocate a mac address entry and update the mac_tbl_idx 2360 * to hold the index of the newly created mac address 2361 * Return 0 if successful, otherwise return error 2362 */ 2363 int 2364 irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2365 { 2366 struct irdma_cqp *iwcqp = &rf->cqp; 2367 struct irdma_cqp_request *cqp_request; 2368 struct cqp_cmds_info *cqp_info; 2369 int status = 0; 2370 2371 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2372 if (!cqp_request) 2373 return -ENOMEM; 2374 2375 cqp_info = &cqp_request->info; 2376 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2377 cqp_info->post_sq = 1; 2378 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2379 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2380 status = irdma_handle_cqp_op(rf, cqp_request); 2381 if (!status) 2382 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2383 2384 irdma_put_cqp_request(iwcqp, cqp_request); 2385 2386 return status; 2387 } 2388 2389 /** 2390 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2391 * @iwdev: irdma device 2392 * @accel_local_port: port for apbvt 2393 * @add_port: add ordelete port 2394 */ 2395 static int 2396 irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2397 u16 accel_local_port, bool add_port) 2398 { 2399 struct irdma_apbvt_info *info; 2400 struct irdma_cqp_request *cqp_request; 2401 struct cqp_cmds_info *cqp_info; 2402 int status; 2403 2404 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2405 if (!cqp_request) 2406 return -ENOMEM; 2407 2408 cqp_info = &cqp_request->info; 2409 info = &cqp_info->in.u.manage_apbvt_entry.info; 2410 memset(info, 0, sizeof(*info)); 2411 info->add = add_port; 2412 info->port = accel_local_port; 2413 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2414 cqp_info->post_sq = 1; 2415 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2416 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2417 irdma_debug(iwdev_to_idev(iwdev), IRDMA_DEBUG_DEV, "%s: port=0x%04x\n", 2418 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2419 2420 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2421 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2422 2423 return status; 2424 } 2425 2426 /** 2427 * irdma_add_apbvt - add tcp port to HW apbvt table 2428 * @iwdev: irdma device 2429 * @port: port for apbvt 2430 */ 2431 struct irdma_apbvt_entry * 2432 irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2433 { 2434 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2435 struct irdma_apbvt_entry *entry; 2436 unsigned long flags; 2437 2438 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2439 entry = irdma_lookup_apbvt_entry(cm_core, port); 2440 if (entry) { 2441 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2442 return entry; 2443 } 2444 2445 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2446 if (!entry) { 2447 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2448 return NULL; 2449 } 2450 2451 entry->port = port; 2452 entry->use_cnt = 1; 2453 HASH_ADD(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2454 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2455 2456 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2457 kfree(entry); 2458 return NULL; 2459 } 2460 2461 return entry; 2462 } 2463 2464 /** 2465 * irdma_del_apbvt - delete tcp port from HW apbvt table 2466 * @iwdev: irdma device 2467 * @entry: apbvt entry object 2468 */ 2469 void 2470 irdma_del_apbvt(struct irdma_device *iwdev, 2471 struct irdma_apbvt_entry *entry) 2472 { 2473 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2474 unsigned long flags; 2475 2476 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2477 if (--entry->use_cnt) { 2478 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2479 return; 2480 } 2481 2482 HASH_DEL(cm_core->apbvt_hash_tbl, &entry->hlist); 2483 /* 2484 * apbvt_lock is held across CQP delete APBVT OP (non-waiting) to protect against race where add APBVT CQP can 2485 * race ahead of the delete APBVT for same port. 2486 */ 2487 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2488 kfree(entry); 2489 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2490 } 2491 2492 /** 2493 * irdma_manage_arp_cache - manage hw arp cache 2494 * @rf: RDMA PCI function 2495 * @mac_addr: mac address ptr 2496 * @ip_addr: ip addr for arp cache 2497 * @action: add, delete or modify 2498 */ 2499 void 2500 irdma_manage_arp_cache(struct irdma_pci_f *rf, const unsigned char *mac_addr, 2501 u32 *ip_addr, u32 action) 2502 { 2503 struct irdma_add_arp_cache_entry_info *info; 2504 struct irdma_cqp_request *cqp_request; 2505 struct cqp_cmds_info *cqp_info; 2506 int arp_index; 2507 2508 arp_index = irdma_arp_table(rf, ip_addr, mac_addr, action); 2509 if (arp_index == -1) 2510 return; 2511 2512 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2513 if (!cqp_request) 2514 return; 2515 2516 cqp_info = &cqp_request->info; 2517 if (action == IRDMA_ARP_ADD) { 2518 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2519 info = &cqp_info->in.u.add_arp_cache_entry.info; 2520 memset(info, 0, sizeof(*info)); 2521 info->arp_index = (u16)arp_index; 2522 info->permanent = true; 2523 ether_addr_copy(info->mac_addr, mac_addr); 2524 cqp_info->in.u.add_arp_cache_entry.scratch = 2525 (uintptr_t)cqp_request; 2526 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2527 } else { 2528 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2529 cqp_info->in.u.del_arp_cache_entry.scratch = 2530 (uintptr_t)cqp_request; 2531 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2532 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2533 } 2534 2535 cqp_info->post_sq = 1; 2536 irdma_handle_cqp_op(rf, cqp_request); 2537 irdma_put_cqp_request(&rf->cqp, cqp_request); 2538 } 2539 2540 /** 2541 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2542 * @cqp_request: qhash cqp completion 2543 */ 2544 static void 2545 irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2546 { 2547 struct irdma_cm_node *cm_node = cqp_request->param; 2548 2549 irdma_send_syn(cm_node, 1); 2550 irdma_rem_ref_cm_node(cm_node); 2551 } 2552 2553 /** 2554 * irdma_manage_qhash - add or modify qhash 2555 * @iwdev: irdma device 2556 * @cminfo: cm info for qhash 2557 * @etype: type (syn or quad) 2558 * @mtype: type of qhash 2559 * @cmnode: cmnode associated with connection 2560 * @wait: wait for completion 2561 */ 2562 int 2563 irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2564 enum irdma_quad_entry_type etype, 2565 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2566 bool wait) 2567 { 2568 struct irdma_qhash_table_info *info; 2569 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; 2570 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2571 struct irdma_cqp_request *cqp_request; 2572 struct cqp_cmds_info *cqp_info; 2573 struct irdma_cm_node *cm_node = cmnode; 2574 int status; 2575 2576 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2577 if (!cqp_request) 2578 return -ENOMEM; 2579 2580 cqp_info = &cqp_request->info; 2581 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2582 memset(info, 0, sizeof(*info)); 2583 info->vsi = &iwdev->vsi; 2584 info->manage = mtype; 2585 info->entry_type = etype; 2586 if (cminfo->vlan_id < VLAN_N_VID) { 2587 info->vlan_valid = true; 2588 info->vlan_id = cminfo->vlan_id; 2589 } else { 2590 info->vlan_valid = false; 2591 } 2592 info->ipv4_valid = cminfo->ipv4; 2593 info->user_pri = cminfo->user_pri; 2594 ether_addr_copy(info->mac_addr, IF_LLADDR(iwdev->netdev)); 2595 info->qp_num = cminfo->qh_qpid; 2596 info->dest_port = cminfo->loc_port; 2597 info->dest_ip[0] = cminfo->loc_addr[0]; 2598 info->dest_ip[1] = cminfo->loc_addr[1]; 2599 info->dest_ip[2] = cminfo->loc_addr[2]; 2600 info->dest_ip[3] = cminfo->loc_addr[3]; 2601 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2602 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2603 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2604 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2605 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2606 info->src_port = cminfo->rem_port; 2607 info->src_ip[0] = cminfo->rem_addr[0]; 2608 info->src_ip[1] = cminfo->rem_addr[1]; 2609 info->src_ip[2] = cminfo->rem_addr[2]; 2610 info->src_ip[3] = cminfo->rem_addr[3]; 2611 } 2612 if (cmnode) { 2613 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2614 cqp_request->param = cmnode; 2615 if (!wait) 2616 atomic_inc(&cm_node->refcnt); 2617 } 2618 if (info->ipv4_valid) 2619 irdma_debug(dev, IRDMA_DEBUG_CM, 2620 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2621 (!mtype) ? "DELETE" : "ADD", __builtin_return_address(0), 2622 info->dest_port, info->src_port, info->dest_ip, info->src_ip, 2623 info->mac_addr, cminfo->vlan_id, cmnode ? cmnode : NULL); 2624 else 2625 irdma_debug(dev, IRDMA_DEBUG_CM, 2626 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2627 (!mtype) ? "DELETE" : "ADD", __builtin_return_address(0), 2628 info->dest_port, info->src_port, info->dest_ip, info->src_ip, 2629 info->mac_addr, cminfo->vlan_id, cmnode ? cmnode : NULL); 2630 2631 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2632 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2633 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2634 cqp_info->post_sq = 1; 2635 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2636 if (status && cm_node && !wait) 2637 irdma_rem_ref_cm_node(cm_node); 2638 2639 irdma_put_cqp_request(iwcqp, cqp_request); 2640 2641 return status; 2642 } 2643 2644 /** 2645 * irdma_hw_flush_wqes - flush qp's wqe 2646 * @rf: RDMA PCI function 2647 * @qp: hardware control qp 2648 * @info: info for flush 2649 * @wait: flag wait for completion 2650 */ 2651 int 2652 irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2653 struct irdma_qp_flush_info *info, bool wait) 2654 { 2655 int status; 2656 struct irdma_qp_flush_info *hw_info; 2657 struct irdma_cqp_request *cqp_request; 2658 struct cqp_cmds_info *cqp_info; 2659 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2660 2661 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2662 if (!cqp_request) 2663 return -ENOMEM; 2664 2665 cqp_info = &cqp_request->info; 2666 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2667 memcpy(hw_info, info, sizeof(*hw_info)); 2668 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2669 cqp_info->post_sq = 1; 2670 cqp_info->in.u.qp_flush_wqes.qp = qp; 2671 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2672 status = irdma_handle_cqp_op(rf, cqp_request); 2673 if (status) { 2674 qp->qp_uk.sq_flush_complete = true; 2675 qp->qp_uk.rq_flush_complete = true; 2676 irdma_put_cqp_request(&rf->cqp, cqp_request); 2677 return status; 2678 } 2679 2680 if (!wait || cqp_request->compl_info.maj_err_code) 2681 goto put_cqp; 2682 2683 if (info->rq) { 2684 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2685 cqp_request->compl_info.min_err_code == 0) { 2686 /* RQ WQE flush was requested but did not happen */ 2687 qp->qp_uk.rq_flush_complete = true; 2688 } 2689 } 2690 if (info->sq) { 2691 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2692 cqp_request->compl_info.min_err_code == 0) { 2693 /* SQ WQE flush was requested but did not happen */ 2694 qp->qp_uk.sq_flush_complete = true; 2695 } 2696 } 2697 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_VERBS, 2698 "qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2699 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2700 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2701 cqp_request->compl_info.maj_err_code, cqp_request->compl_info.min_err_code); 2702 put_cqp: 2703 irdma_put_cqp_request(&rf->cqp, cqp_request); 2704 2705 return status; 2706 } 2707 2708 /** 2709 * irdma_gen_ae - generate AE 2710 * @rf: RDMA PCI function 2711 * @qp: qp associated with AE 2712 * @info: info for ae 2713 * @wait: wait for completion 2714 */ 2715 void 2716 irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2717 struct irdma_gen_ae_info *info, bool wait) 2718 { 2719 struct irdma_gen_ae_info *ae_info; 2720 struct irdma_cqp_request *cqp_request; 2721 struct cqp_cmds_info *cqp_info; 2722 2723 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2724 if (!cqp_request) 2725 return; 2726 2727 cqp_info = &cqp_request->info; 2728 ae_info = &cqp_request->info.in.u.gen_ae.info; 2729 memcpy(ae_info, info, sizeof(*ae_info)); 2730 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2731 cqp_info->post_sq = 1; 2732 cqp_info->in.u.gen_ae.qp = qp; 2733 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2734 2735 irdma_handle_cqp_op(rf, cqp_request); 2736 irdma_put_cqp_request(&rf->cqp, cqp_request); 2737 } 2738 2739 void 2740 irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2741 { 2742 struct irdma_qp_flush_info info = {0}; 2743 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2744 u8 flush_code = iwqp->sc_qp.flush_code; 2745 2746 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2747 return; 2748 2749 /* Set flush info fields */ 2750 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2751 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2752 2753 /* Generate userflush errors in CQE */ 2754 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2755 info.sq_minor_code = FLUSH_GENERAL_ERR; 2756 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2757 info.rq_minor_code = FLUSH_GENERAL_ERR; 2758 info.userflushcode = true; 2759 2760 if (flush_mask & IRDMA_REFLUSH) { 2761 if (info.sq) 2762 iwqp->sc_qp.flush_sq = false; 2763 if (info.rq) 2764 iwqp->sc_qp.flush_rq = false; 2765 } else { 2766 if (flush_code) { 2767 if (info.sq && iwqp->sc_qp.sq_flush_code) 2768 info.sq_minor_code = flush_code; 2769 if (info.rq && iwqp->sc_qp.rq_flush_code) 2770 info.rq_minor_code = flush_code; 2771 } 2772 if (irdma_upload_context && irdma_upload_qp_context(iwqp, 0, 1)) 2773 irdma_print("failed to upload QP context\n"); 2774 if (!iwqp->user_mode) 2775 irdma_sched_qp_flush_work(iwqp); 2776 } 2777 2778 /* Issue flush */ 2779 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2780 flush_mask & IRDMA_FLUSH_WAIT); 2781 iwqp->flush_issued = true; 2782 } 2783