1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #include "irdma_main.h" 37 38 static struct irdma_rsrc_limits rsrc_limits_table[] = { 39 [0] = { 40 .qplimit = SZ_128, 41 }, 42 [1] = { 43 .qplimit = SZ_1K, 44 }, 45 [2] = { 46 .qplimit = SZ_2K, 47 }, 48 [3] = { 49 .qplimit = SZ_4K, 50 }, 51 [4] = { 52 .qplimit = SZ_16K, 53 }, 54 [5] = { 55 .qplimit = SZ_64K, 56 }, 57 [6] = { 58 .qplimit = SZ_128K, 59 }, 60 [7] = { 61 .qplimit = SZ_256K, 62 }, 63 }; 64 65 /* types of hmc objects */ 66 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 67 IRDMA_HMC_IW_QP, 68 IRDMA_HMC_IW_CQ, 69 IRDMA_HMC_IW_HTE, 70 IRDMA_HMC_IW_ARP, 71 IRDMA_HMC_IW_APBVT_ENTRY, 72 IRDMA_HMC_IW_MR, 73 IRDMA_HMC_IW_XF, 74 IRDMA_HMC_IW_XFFL, 75 IRDMA_HMC_IW_Q1, 76 IRDMA_HMC_IW_Q1FL, 77 IRDMA_HMC_IW_PBLE, 78 IRDMA_HMC_IW_TIMER, 79 IRDMA_HMC_IW_FSIMC, 80 IRDMA_HMC_IW_FSIAV, 81 IRDMA_HMC_IW_RRF, 82 IRDMA_HMC_IW_RRFFL, 83 IRDMA_HMC_IW_HDR, 84 IRDMA_HMC_IW_MD, 85 IRDMA_HMC_IW_OOISC, 86 IRDMA_HMC_IW_OOISCFFL, 87 }; 88 89 /** 90 * irdma_iwarp_ce_handler - handle iwarp completions 91 * @iwcq: iwarp cq receiving event 92 */ 93 static void 94 irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 95 { 96 struct irdma_cq *cq = iwcq->back_cq; 97 98 if (!cq->user_mode) 99 atomic_set(&cq->armed, 0); 100 if (cq->ibcq.comp_handler) 101 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 102 } 103 104 /** 105 * irdma_puda_ce_handler - handle puda completion events 106 * @rf: RDMA PCI function 107 * @cq: puda completion q for event 108 */ 109 static void 110 irdma_puda_ce_handler(struct irdma_pci_f *rf, 111 struct irdma_sc_cq *cq) 112 { 113 struct irdma_sc_dev *dev = &rf->sc_dev; 114 u32 compl_error; 115 int status; 116 117 do { 118 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 119 if (status == -ENOENT) 120 break; 121 if (status) { 122 irdma_debug(dev, IRDMA_DEBUG_ERR, "puda status = %d\n", status); 123 break; 124 } 125 if (compl_error) { 126 irdma_debug(dev, IRDMA_DEBUG_ERR, 127 "puda compl_err =0x%x\n", 128 compl_error); 129 break; 130 } 131 } while (1); 132 133 irdma_sc_ccq_arm(cq); 134 } 135 136 /** 137 * irdma_process_ceq - handle ceq for completions 138 * @rf: RDMA PCI function 139 * @ceq: ceq having cq for completion 140 */ 141 static void 142 irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 143 { 144 struct irdma_sc_dev *dev = &rf->sc_dev; 145 struct irdma_sc_ceq *sc_ceq; 146 struct irdma_sc_cq *cq; 147 unsigned long flags; 148 149 sc_ceq = &ceq->sc_ceq; 150 do { 151 spin_lock_irqsave(&ceq->ce_lock, flags); 152 cq = irdma_sc_process_ceq(dev, sc_ceq); 153 if (!cq) { 154 spin_unlock_irqrestore(&ceq->ce_lock, flags); 155 break; 156 } 157 158 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 159 irdma_iwarp_ce_handler(cq); 160 161 spin_unlock_irqrestore(&ceq->ce_lock, flags); 162 163 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 164 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 165 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 166 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 167 irdma_puda_ce_handler(rf, cq); 168 } while (1); 169 } 170 171 static void 172 irdma_set_flush_fields(struct irdma_sc_qp *qp, 173 struct irdma_aeqe_info *info) 174 { 175 struct qp_err_code qp_err; 176 177 qp->sq_flush_code = info->sq; 178 qp->rq_flush_code = info->rq; 179 qp_err = irdma_ae_to_qp_err_code(info->ae_id); 180 181 qp->flush_code = qp_err.flush_code; 182 qp->event_type = qp_err.event_type; 183 } 184 185 /** 186 * irdma_complete_cqp_request - perform post-completion cleanup 187 * @cqp: device CQP 188 * @cqp_request: CQP request 189 * 190 * Mark CQP request as done, wake up waiting thread or invoke 191 * callback function and release/free CQP request. 192 */ 193 static void 194 irdma_complete_cqp_request(struct irdma_cqp *cqp, 195 struct irdma_cqp_request *cqp_request) 196 { 197 if (cqp_request->waiting) { 198 cqp_request->request_done = true; 199 wake_up(&cqp_request->waitq); 200 } else if (cqp_request->callback_fcn) { 201 cqp_request->callback_fcn(cqp_request); 202 } 203 irdma_put_cqp_request(cqp, cqp_request); 204 } 205 206 /** 207 * irdma_process_aeq - handle aeq events 208 * @rf: RDMA PCI function 209 */ 210 static void 211 irdma_process_aeq(struct irdma_pci_f *rf) 212 { 213 struct irdma_sc_dev *dev = &rf->sc_dev; 214 struct irdma_aeq *aeq = &rf->aeq; 215 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 216 struct irdma_aeqe_info aeinfo; 217 struct irdma_aeqe_info *info = &aeinfo; 218 int ret; 219 struct irdma_qp *iwqp = NULL; 220 struct irdma_cq *iwcq = NULL; 221 struct irdma_sc_qp *qp = NULL; 222 struct irdma_device *iwdev = rf->iwdev; 223 struct irdma_qp_host_ctx_info *ctx_info = NULL; 224 unsigned long flags; 225 226 u32 aeqcnt = 0; 227 228 if (!sc_aeq->size) 229 return; 230 231 do { 232 memset(info, 0, sizeof(*info)); 233 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 234 if (ret) 235 break; 236 237 aeqcnt++; 238 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ, 239 "ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 240 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 241 info->iwarp_state, info->ae_src); 242 243 if (info->qp) { 244 spin_lock_irqsave(&rf->qptable_lock, flags); 245 iwqp = rf->qp_table[info->qp_cq_id]; 246 if (!iwqp) { 247 spin_unlock_irqrestore(&rf->qptable_lock, 248 flags); 249 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 250 struct irdma_device *iwdev = rf->iwdev; 251 252 if (!iwdev->vsi.tc_change_pending) 253 continue; 254 255 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 256 wake_up(&iwdev->suspend_wq); 257 continue; 258 } 259 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ, 260 "qp_id %d is already freed\n", 261 info->qp_cq_id); 262 continue; 263 } 264 irdma_qp_add_ref(&iwqp->ibqp); 265 spin_unlock_irqrestore(&rf->qptable_lock, flags); 266 qp = &iwqp->sc_qp; 267 spin_lock_irqsave(&iwqp->lock, flags); 268 iwqp->hw_tcp_state = info->tcp_state; 269 iwqp->hw_iwarp_state = info->iwarp_state; 270 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 271 iwqp->last_aeq = info->ae_id; 272 spin_unlock_irqrestore(&iwqp->lock, flags); 273 ctx_info = &iwqp->ctx_info; 274 } else { 275 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 276 continue; 277 } 278 279 switch (info->ae_id) { 280 struct irdma_cm_node *cm_node; 281 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 282 cm_node = iwqp->cm_node; 283 if (cm_node->accept_pend) { 284 atomic_dec(&cm_node->listener->pend_accepts_cnt); 285 cm_node->accept_pend = 0; 286 } 287 iwqp->rts_ae_rcvd = 1; 288 wake_up_interruptible(&iwqp->waitq); 289 break; 290 case IRDMA_AE_LLP_FIN_RECEIVED: 291 if (qp->term_flags) 292 break; 293 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 294 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 295 if (iwqp->ibqp_state == IB_QPS_RTS) { 296 irdma_next_iw_state(iwqp, 297 IRDMA_QP_STATE_CLOSING, 298 0, 0, 0); 299 irdma_cm_disconn(iwqp); 300 } 301 irdma_schedule_cm_timer(iwqp->cm_node, 302 (struct irdma_puda_buf *)iwqp, 303 IRDMA_TIMER_TYPE_CLOSE, 304 1, 0); 305 } 306 break; 307 case IRDMA_AE_LLP_CLOSE_COMPLETE: 308 if (qp->term_flags) 309 irdma_terminate_done(qp, 0); 310 else 311 irdma_cm_disconn(iwqp); 312 break; 313 case IRDMA_AE_BAD_CLOSE: 314 case IRDMA_AE_RESET_SENT: 315 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 316 0); 317 irdma_cm_disconn(iwqp); 318 break; 319 case IRDMA_AE_LLP_CONNECTION_RESET: 320 if (atomic_read(&iwqp->close_timer_started)) 321 break; 322 irdma_cm_disconn(iwqp); 323 break; 324 case IRDMA_AE_QP_SUSPEND_COMPLETE: 325 if (iwqp->iwdev->vsi.tc_change_pending) { 326 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 327 wake_up(&iwqp->iwdev->suspend_wq); 328 } 329 break; 330 case IRDMA_AE_TERMINATE_SENT: 331 irdma_terminate_send_fin(qp); 332 break; 333 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 334 irdma_terminate_received(qp, info); 335 break; 336 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 337 case IRDMA_AE_CQ_OPERATION_ERROR: 338 irdma_dev_err(&iwdev->ibdev, 339 "Processing CQ[0x%x] op error, AE 0x%04X\n", 340 info->qp_cq_id, info->ae_id); 341 spin_lock_irqsave(&rf->cqtable_lock, flags); 342 iwcq = rf->cq_table[info->qp_cq_id]; 343 if (!iwcq) { 344 spin_unlock_irqrestore(&rf->cqtable_lock, 345 flags); 346 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ, 347 "cq_id %d is already freed\n", 348 info->qp_cq_id); 349 continue; 350 } 351 irdma_cq_add_ref(&iwcq->ibcq); 352 spin_unlock_irqrestore(&rf->cqtable_lock, flags); 353 if (iwcq->ibcq.event_handler) { 354 struct ib_event ibevent; 355 356 ibevent.device = iwcq->ibcq.device; 357 ibevent.event = IB_EVENT_CQ_ERR; 358 ibevent.element.cq = &iwcq->ibcq; 359 iwcq->ibcq.event_handler(&ibevent, 360 iwcq->ibcq.cq_context); 361 } 362 irdma_cq_rem_ref(&iwcq->ibcq); 363 break; 364 case IRDMA_AE_RESET_NOT_SENT: 365 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 366 break; 367 case IRDMA_AE_RESOURCE_EXHAUSTION: 368 irdma_dev_err(&iwdev->ibdev, 369 "Resource exhaustion reason: q1 = %d xmit or rreq = %d\n", 370 info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_Q1, 371 info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR); 372 break; 373 case IRDMA_AE_PRIV_OPERATION_DENIED: 374 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 375 case IRDMA_AE_STAG_ZERO_INVALID: 376 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 377 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 378 case IRDMA_AE_DDP_UBE_INVALID_MO: 379 case IRDMA_AE_DDP_UBE_INVALID_QN: 380 case IRDMA_AE_DDP_NO_L_BIT: 381 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 382 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 383 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 384 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 385 case IRDMA_AE_INVALID_ARP_ENTRY: 386 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 387 case IRDMA_AE_STALE_ARP_ENTRY: 388 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 389 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 390 case IRDMA_AE_LLP_SYN_RECEIVED: 391 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 392 case IRDMA_AE_LCE_QP_CATASTROPHIC: 393 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 394 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 395 default: 396 irdma_dev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d ae_source=%d\n", 397 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 398 if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) { 399 ctx_info->roce_info->err_rq_idx_valid = info->err_rq_idx_valid; 400 if (info->rq) { 401 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 402 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 403 ctx_info); 404 } 405 irdma_set_flush_fields(qp, info); 406 irdma_cm_disconn(iwqp); 407 break; 408 } 409 ctx_info->iwarp_info->err_rq_idx_valid = info->err_rq_idx_valid; 410 if (info->rq) { 411 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 412 ctx_info->tcp_info_valid = false; 413 ctx_info->iwarp_info_valid = true; 414 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 415 ctx_info); 416 } 417 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 418 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 419 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 420 irdma_cm_disconn(iwqp); 421 } else { 422 irdma_terminate_connection(qp, info); 423 } 424 break; 425 } 426 if (info->qp) 427 irdma_qp_rem_ref(&iwqp->ibqp); 428 } while (1); 429 430 if (aeqcnt) 431 irdma_sc_repost_aeq_entries(dev, aeqcnt); 432 } 433 434 /** 435 * irdma_ena_intr - set up device interrupts 436 * @dev: hardware control device structure 437 * @msix_id: id of the interrupt to be enabled 438 */ 439 static void 440 irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 441 { 442 dev->irq_ops->irdma_en_irq(dev, msix_id); 443 } 444 445 /** 446 * irdma_dpc - tasklet for aeq and ceq 0 447 * @t: tasklet_struct ptr 448 */ 449 static void 450 irdma_dpc(unsigned long t) 451 { 452 struct irdma_pci_f *rf = from_tasklet(rf, (struct tasklet_struct *)t, 453 dpc_tasklet); 454 455 if (rf->msix_shared) 456 irdma_process_ceq(rf, rf->ceqlist); 457 irdma_process_aeq(rf); 458 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 459 } 460 461 /** 462 * irdma_ceq_dpc - dpc handler for CEQ 463 * @t: tasklet_struct ptr 464 */ 465 static void 466 irdma_ceq_dpc(unsigned long t) 467 { 468 struct irdma_ceq *iwceq = from_tasklet(iwceq, (struct tasklet_struct *)t, 469 dpc_tasklet); 470 struct irdma_pci_f *rf = iwceq->rf; 471 472 irdma_process_ceq(rf, iwceq); 473 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 474 } 475 476 /** 477 * irdma_save_msix_info - copy msix vector information to iwarp device 478 * @rf: RDMA PCI function 479 * 480 * Allocate iwdev msix table and copy the msix info to the table 481 * Return 0 if successful, otherwise return error 482 */ 483 static int 484 irdma_save_msix_info(struct irdma_pci_f *rf) 485 { 486 struct irdma_qvlist_info *iw_qvlist; 487 struct irdma_qv_info *iw_qvinfo; 488 u32 ceq_idx; 489 u32 i; 490 u32 size; 491 492 if (!rf->msix_count) { 493 irdma_dev_err(to_ibdev(&rf->sc_dev), "No MSI-X vectors reserved for RDMA.\n"); 494 return -EINVAL; 495 } 496 497 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 498 size += sizeof(struct irdma_qvlist_info); 499 size += sizeof(struct irdma_qv_info) * rf->msix_count - 1; 500 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 501 if (!rf->iw_msixtbl) 502 return -ENOMEM; 503 504 rf->iw_qvlist = (struct irdma_qvlist_info *) 505 (&rf->iw_msixtbl[rf->msix_count]); 506 iw_qvlist = rf->iw_qvlist; 507 iw_qvinfo = iw_qvlist->qv_info; 508 iw_qvlist->num_vectors = rf->msix_count; 509 if (rf->msix_count <= num_online_cpus()) 510 rf->msix_shared = true; 511 else if (rf->msix_count > num_online_cpus() + 1) 512 rf->msix_count = num_online_cpus() + 1; 513 514 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 515 rf->iw_msixtbl[i].idx = rf->msix_info.entry + i; 516 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 517 if (!i) { 518 iw_qvinfo->aeq_idx = 0; 519 if (rf->msix_shared) 520 iw_qvinfo->ceq_idx = ceq_idx++; 521 else 522 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 523 } else { 524 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 525 iw_qvinfo->ceq_idx = ceq_idx++; 526 } 527 iw_qvinfo->itr_idx = IRDMA_IDX_NOITR; 528 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 529 } 530 531 return 0; 532 } 533 534 /** 535 * irdma_irq_handler - interrupt handler for aeq and ceq0 536 * @data: RDMA PCI function 537 */ 538 static void 539 irdma_irq_handler(void *data) 540 { 541 struct irdma_pci_f *rf = data; 542 543 tasklet_schedule(&rf->dpc_tasklet); 544 } 545 546 /** 547 * irdma_ceq_handler - interrupt handler for ceq 548 * @data: ceq pointer 549 */ 550 static void 551 irdma_ceq_handler(void *data) 552 { 553 struct irdma_ceq *iwceq = data; 554 555 tasklet_schedule(&iwceq->dpc_tasklet); 556 } 557 558 /** 559 * irdma_free_irq - free device interrupts in FreeBSD manner 560 * @rf: RDMA PCI function 561 * @msix_vec: msix vector to disable irq 562 * 563 * The function is called when destroying irq. It tearsdown 564 * the interrupt and release resources. 565 */ 566 static void 567 irdma_free_irq(struct irdma_pci_f *rf, struct irdma_msix_vector *msix_vec) 568 { 569 if (msix_vec->tag) { 570 bus_teardown_intr(rf->dev_ctx.dev, msix_vec->res, 571 msix_vec->tag); 572 msix_vec->tag = NULL; 573 } 574 if (msix_vec->res) { 575 bus_release_resource(rf->dev_ctx.dev, SYS_RES_IRQ, 576 msix_vec->idx + 1, 577 msix_vec->res); 578 msix_vec->res = NULL; 579 } 580 } 581 582 /** 583 * irdma_destroy_irq - destroy device interrupts 584 * @rf: RDMA PCI function 585 * @msix_vec: msix vector to disable irq 586 * @dev_id: parameter to pass to free_irq (used during irq setup) 587 * 588 * The function is called when destroying aeq/ceq 589 */ 590 static void 591 irdma_destroy_irq(struct irdma_pci_f *rf, 592 struct irdma_msix_vector *msix_vec, void *dev_id) 593 { 594 struct irdma_sc_dev *dev = &rf->sc_dev; 595 596 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 597 irdma_free_irq(rf, msix_vec); 598 } 599 600 /** 601 * irdma_destroy_cqp - destroy control qp 602 * @rf: RDMA PCI function 603 * @free_hwcqp: 1 if hw cqp should be freed 604 * 605 * Issue destroy cqp request and 606 * free the resources associated with the cqp 607 */ 608 static void 609 irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 610 { 611 struct irdma_sc_dev *dev = &rf->sc_dev; 612 struct irdma_cqp *cqp = &rf->cqp; 613 int status = 0; 614 615 if (rf->cqp_cmpl_wq) 616 destroy_workqueue(rf->cqp_cmpl_wq); 617 status = irdma_sc_cqp_destroy(dev->cqp, free_hwcqp); 618 if (status) 619 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy CQP failed %d\n", status); 620 621 irdma_cleanup_pending_cqp_op(rf); 622 irdma_free_dma_mem(dev->hw, &cqp->sq); 623 kfree(cqp->scratch_array); 624 cqp->scratch_array = NULL; 625 kfree(cqp->cqp_requests); 626 cqp->cqp_requests = NULL; 627 } 628 629 static void 630 irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 631 { 632 struct irdma_aeq *aeq = &rf->aeq; 633 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 634 dma_addr_t *pg_arr = (dma_addr_t *) aeq->palloc.level1.addr; 635 636 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 637 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 638 vfree(aeq->mem.va); 639 } 640 641 /** 642 * irdma_destroy_aeq - destroy aeq 643 * @rf: RDMA PCI function 644 * 645 * Issue a destroy aeq request and 646 * free the resources associated with the aeq 647 * The function is called during driver unload 648 */ 649 static void 650 irdma_destroy_aeq(struct irdma_pci_f *rf) 651 { 652 struct irdma_sc_dev *dev = &rf->sc_dev; 653 struct irdma_aeq *aeq = &rf->aeq; 654 int status = -EBUSY; 655 656 if (!rf->msix_shared) { 657 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 658 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 659 } 660 if (rf->reset) 661 goto exit; 662 663 aeq->sc_aeq.size = 0; 664 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 665 if (status) 666 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy AEQ failed %d\n", status); 667 668 exit: 669 if (aeq->virtual_map) 670 irdma_destroy_virt_aeq(rf); 671 else 672 irdma_free_dma_mem(dev->hw, &aeq->mem); 673 } 674 675 /** 676 * irdma_destroy_ceq - destroy ceq 677 * @rf: RDMA PCI function 678 * @iwceq: ceq to be destroyed 679 * 680 * Issue a destroy ceq request and 681 * free the resources associated with the ceq 682 */ 683 static void 684 irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 685 { 686 struct irdma_sc_dev *dev = &rf->sc_dev; 687 int status; 688 689 if (rf->reset) 690 goto exit; 691 692 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 693 if (status) { 694 irdma_debug(dev, IRDMA_DEBUG_ERR, "CEQ destroy command failed %d\n", status); 695 goto exit; 696 } 697 698 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 699 if (status) 700 irdma_debug(dev, IRDMA_DEBUG_ERR, 701 "CEQ destroy completion failed %d\n", 702 status); 703 exit: 704 spin_lock_destroy(&iwceq->ce_lock); 705 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock); 706 kfree(iwceq->sc_ceq.reg_cq); 707 irdma_free_dma_mem(dev->hw, &iwceq->mem); 708 } 709 710 /** 711 * irdma_del_ceq_0 - destroy ceq 0 712 * @rf: RDMA PCI function 713 * 714 * Disable the ceq 0 interrupt and destroy the ceq 0 715 */ 716 static void 717 irdma_del_ceq_0(struct irdma_pci_f *rf) 718 { 719 struct irdma_ceq *iwceq = rf->ceqlist; 720 struct irdma_msix_vector *msix_vec; 721 722 if (rf->msix_shared) { 723 msix_vec = &rf->iw_msixtbl[0]; 724 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 725 msix_vec->ceq_id, 726 msix_vec->idx, false); 727 irdma_destroy_irq(rf, msix_vec, rf); 728 } else { 729 msix_vec = &rf->iw_msixtbl[1]; 730 irdma_destroy_irq(rf, msix_vec, iwceq); 731 } 732 733 irdma_destroy_ceq(rf, iwceq); 734 rf->sc_dev.ceq_valid = false; 735 rf->ceqs_count = 0; 736 } 737 738 /** 739 * irdma_del_ceqs - destroy all ceq's except CEQ 0 740 * @rf: RDMA PCI function 741 * 742 * Go through all of the device ceq's, except 0, and for each 743 * ceq disable the ceq interrupt and destroy the ceq 744 */ 745 static void 746 irdma_del_ceqs(struct irdma_pci_f *rf) 747 { 748 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 749 struct irdma_msix_vector *msix_vec; 750 u32 i = 0; 751 752 if (rf->msix_shared) 753 msix_vec = &rf->iw_msixtbl[1]; 754 else 755 msix_vec = &rf->iw_msixtbl[2]; 756 757 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 758 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 759 msix_vec->idx, false); 760 irdma_destroy_irq(rf, msix_vec, iwceq); 761 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 762 IRDMA_OP_CEQ_DESTROY); 763 spin_lock_destroy(&iwceq->ce_lock); 764 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock); 765 kfree(iwceq->sc_ceq.reg_cq); 766 irdma_free_dma_mem(rf->sc_dev.hw, &iwceq->mem); 767 } 768 rf->ceqs_count = 1; 769 } 770 771 /** 772 * irdma_destroy_ccq - destroy control cq 773 * @rf: RDMA PCI function 774 * 775 * Issue destroy ccq request and 776 * free the resources associated with the ccq 777 */ 778 static void 779 irdma_destroy_ccq(struct irdma_pci_f *rf) 780 { 781 struct irdma_sc_dev *dev = &rf->sc_dev; 782 struct irdma_ccq *ccq = &rf->ccq; 783 int status = 0; 784 785 if (!rf->reset) 786 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 787 if (status) 788 irdma_debug(dev, IRDMA_DEBUG_ERR, "CCQ destroy failed %d\n", status); 789 irdma_free_dma_mem(dev->hw, &ccq->mem_cq); 790 } 791 792 /** 793 * irdma_close_hmc_objects_type - delete hmc objects of a given type 794 * @dev: iwarp device 795 * @obj_type: the hmc object type to be deleted 796 * @hmc_info: host memory info struct 797 * @privileged: permission to close HMC objects 798 * @reset: true if called before reset 799 */ 800 static void 801 irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 802 enum irdma_hmc_rsrc_type obj_type, 803 struct irdma_hmc_info *hmc_info, 804 bool privileged, bool reset) 805 { 806 struct irdma_hmc_del_obj_info info = {0}; 807 808 info.hmc_info = hmc_info; 809 info.rsrc_type = obj_type; 810 info.count = hmc_info->hmc_obj[obj_type].cnt; 811 info.privileged = privileged; 812 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 813 irdma_debug(dev, IRDMA_DEBUG_ERR, 814 "del HMC obj of type %d failed\n", 815 obj_type); 816 } 817 818 /** 819 * irdma_del_hmc_objects - remove all device hmc objects 820 * @dev: iwarp device 821 * @hmc_info: hmc_info to free 822 * @privileged: permission to delete HMC objects 823 * @reset: true if called before reset 824 * @vers: hardware version 825 */ 826 void 827 irdma_del_hmc_objects(struct irdma_sc_dev *dev, 828 struct irdma_hmc_info *hmc_info, bool privileged, 829 bool reset, enum irdma_vers vers) 830 { 831 unsigned int i; 832 833 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 834 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 835 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 836 hmc_info, privileged, reset); 837 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 838 break; 839 } 840 } 841 842 /** 843 * irdma_create_hmc_obj_type - create hmc object of a given type 844 * @dev: hardware control device structure 845 * @info: information for the hmc object to create 846 */ 847 static int 848 irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 849 struct irdma_hmc_create_obj_info *info) 850 { 851 return irdma_sc_create_hmc_obj(dev, info); 852 } 853 854 /** 855 * irdma_create_hmc_objs - create all hmc objects for the device 856 * @rf: RDMA PCI function 857 * @privileged: permission to create HMC objects 858 * @vers: HW version 859 * 860 * Create the device hmc objects and allocate hmc pages 861 * Return 0 if successful, otherwise clean up and return error 862 */ 863 static int 864 irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 865 enum irdma_vers vers) 866 { 867 struct irdma_sc_dev *dev = &rf->sc_dev; 868 struct irdma_hmc_create_obj_info info = {0}; 869 int i, status = 0; 870 871 info.hmc_info = dev->hmc_info; 872 info.privileged = privileged; 873 info.entry_type = rf->sd_type; 874 875 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 876 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE) 877 continue; 878 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 879 info.rsrc_type = iw_hmc_obj_types[i]; 880 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 881 info.add_sd_cnt = 0; 882 status = irdma_create_hmc_obj_type(dev, &info); 883 if (status) { 884 irdma_debug(dev, IRDMA_DEBUG_ERR, 885 "create obj type %d status = %d\n", 886 iw_hmc_obj_types[i], status); 887 break; 888 } 889 } 890 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 891 break; 892 } 893 894 if (!status) 895 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 896 true, true); 897 898 while (i) { 899 i--; 900 /* destroy the hmc objects of a given type */ 901 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 902 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 903 dev->hmc_info, privileged, 904 false); 905 } 906 907 return status; 908 } 909 910 /** 911 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 912 * @rf: RDMA PCI function 913 * @memptr: points to the memory addresses 914 * @size: size of memory needed 915 * @mask: mask for the aligned memory 916 * 917 * Get aligned memory of the requested size and 918 * update the memptr to point to the new aligned memory 919 * Return 0 if successful, otherwise return no memory error 920 */ 921 static int 922 irdma_obj_aligned_mem(struct irdma_pci_f *rf, 923 struct irdma_dma_mem *memptr, u32 size, 924 u32 mask) 925 { 926 unsigned long va, newva; 927 unsigned long extra; 928 929 va = (unsigned long)rf->obj_next.va; 930 newva = va; 931 if (mask) 932 newva = ALIGN(va, (unsigned long)mask + 1ULL); 933 extra = newva - va; 934 memptr->va = (u8 *)va + extra; 935 memptr->pa = rf->obj_next.pa + extra; 936 memptr->size = size; 937 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 938 return -ENOMEM; 939 940 rf->obj_next.va = (u8 *)memptr->va + size; 941 rf->obj_next.pa = memptr->pa + size; 942 943 return 0; 944 } 945 946 /** 947 * irdma_create_cqp - create control qp 948 * @rf: RDMA PCI function 949 * 950 * Return 0, if the cqp and all the resources associated with it 951 * are successfully created, otherwise return error 952 */ 953 static int 954 irdma_create_cqp(struct irdma_pci_f *rf) 955 { 956 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 957 struct irdma_dma_mem mem; 958 struct irdma_sc_dev *dev = &rf->sc_dev; 959 struct irdma_cqp_init_info cqp_init_info = {0}; 960 struct irdma_cqp *cqp = &rf->cqp; 961 u16 maj_err, min_err; 962 int i, status; 963 964 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 965 memset(cqp->cqp_requests, 0, sqsize * sizeof(*cqp->cqp_requests)); 966 if (!cqp->cqp_requests) 967 return -ENOMEM; 968 969 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 970 memset(cqp->scratch_array, 0, sqsize * sizeof(*cqp->scratch_array)); 971 if (!cqp->scratch_array) { 972 status = -ENOMEM; 973 goto err_scratch; 974 } 975 976 dev->cqp = &cqp->sc_cqp; 977 dev->cqp->dev = dev; 978 cqp->sq.size = sizeof(struct irdma_cqp_sq_wqe) * sqsize; 979 cqp->sq.va = irdma_allocate_dma_mem(dev->hw, &cqp->sq, cqp->sq.size, 980 IRDMA_CQP_ALIGNMENT); 981 if (!cqp->sq.va) { 982 status = -ENOMEM; 983 goto err_sq; 984 } 985 986 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 987 IRDMA_HOST_CTX_ALIGNMENT_M); 988 if (status) 989 goto err_ctx; 990 991 dev->cqp->host_ctx_pa = mem.pa; 992 dev->cqp->host_ctx = mem.va; 993 /* populate the cqp init info */ 994 cqp_init_info.dev = dev; 995 cqp_init_info.sq_size = sqsize; 996 cqp_init_info.sq = cqp->sq.va; 997 cqp_init_info.sq_pa = cqp->sq.pa; 998 cqp_init_info.host_ctx_pa = mem.pa; 999 cqp_init_info.host_ctx = mem.va; 1000 cqp_init_info.hmc_profile = rf->rsrc_profile; 1001 cqp_init_info.scratch_array = cqp->scratch_array; 1002 cqp_init_info.protocol_used = rf->protocol_used; 1003 cqp_init_info.en_rem_endpoint_trk = rf->en_rem_endpoint_trk; 1004 memcpy(&cqp_init_info.dcqcn_params, &rf->dcqcn_params, 1005 sizeof(cqp_init_info.dcqcn_params)); 1006 1007 switch (rf->rdma_ver) { 1008 case IRDMA_GEN_1: 1009 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 1010 break; 1011 case IRDMA_GEN_2: 1012 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 1013 break; 1014 } 1015 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 1016 if (status) { 1017 irdma_debug(dev, IRDMA_DEBUG_ERR, "cqp init status %d\n", status); 1018 goto err_ctx; 1019 } 1020 1021 spin_lock_init(&cqp->req_lock); 1022 spin_lock_init(&cqp->compl_lock); 1023 1024 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 1025 if (status) { 1026 irdma_debug(dev, IRDMA_DEBUG_ERR, 1027 "cqp create failed - status %d maj_err %d min_err %d\n", 1028 status, maj_err, min_err); 1029 goto err_create; 1030 } 1031 1032 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 1033 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 1034 1035 /* init the waitqueue of the cqp_requests and add them to the list */ 1036 for (i = 0; i < sqsize; i++) { 1037 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 1038 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 1039 } 1040 init_waitqueue_head(&cqp->remove_wq); 1041 return 0; 1042 1043 err_create: 1044 err_ctx: 1045 irdma_free_dma_mem(dev->hw, &cqp->sq); 1046 err_sq: 1047 kfree(cqp->scratch_array); 1048 cqp->scratch_array = NULL; 1049 err_scratch: 1050 kfree(cqp->cqp_requests); 1051 cqp->cqp_requests = NULL; 1052 1053 return status; 1054 } 1055 1056 /** 1057 * irdma_create_ccq - create control cq 1058 * @rf: RDMA PCI function 1059 * 1060 * Return 0, if the ccq and the resources associated with it 1061 * are successfully created, otherwise return error 1062 */ 1063 static int 1064 irdma_create_ccq(struct irdma_pci_f *rf) 1065 { 1066 struct irdma_sc_dev *dev = &rf->sc_dev; 1067 struct irdma_ccq_init_info info = {0}; 1068 struct irdma_ccq *ccq = &rf->ccq; 1069 int status; 1070 1071 dev->ccq = &ccq->sc_cq; 1072 dev->ccq->dev = dev; 1073 info.dev = dev; 1074 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1075 ccq->mem_cq.size = sizeof(struct irdma_cqe) * IW_CCQ_SIZE; 1076 ccq->mem_cq.va = irdma_allocate_dma_mem(dev->hw, &ccq->mem_cq, 1077 ccq->mem_cq.size, 1078 IRDMA_CQ0_ALIGNMENT); 1079 if (!ccq->mem_cq.va) 1080 return -ENOMEM; 1081 1082 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1083 ccq->shadow_area.size, 1084 IRDMA_SHADOWAREA_M); 1085 if (status) 1086 goto exit; 1087 1088 ccq->sc_cq.back_cq = ccq; 1089 /* populate the ccq init info */ 1090 info.cq_base = ccq->mem_cq.va; 1091 info.cq_pa = ccq->mem_cq.pa; 1092 info.num_elem = IW_CCQ_SIZE; 1093 info.shadow_area = ccq->shadow_area.va; 1094 info.shadow_area_pa = ccq->shadow_area.pa; 1095 info.ceqe_mask = false; 1096 info.ceq_id_valid = true; 1097 info.shadow_read_threshold = 16; 1098 info.vsi = &rf->default_vsi; 1099 status = irdma_sc_ccq_init(dev->ccq, &info); 1100 if (!status) 1101 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1102 exit: 1103 if (status) 1104 irdma_free_dma_mem(dev->hw, &ccq->mem_cq); 1105 1106 return status; 1107 } 1108 1109 /** 1110 * irdma_alloc_set_mac - set up a mac address table entry 1111 * @iwdev: irdma device 1112 * 1113 * Allocate a mac ip entry and add it to the hw table Return 0 1114 * if successful, otherwise return error 1115 */ 1116 static int 1117 irdma_alloc_set_mac(struct irdma_device *iwdev) 1118 { 1119 int status; 1120 1121 status = irdma_alloc_local_mac_entry(iwdev->rf, 1122 &iwdev->mac_ip_table_idx); 1123 if (!status) { 1124 status = irdma_add_local_mac_entry(iwdev->rf, 1125 (const u8 *)if_getlladdr(iwdev->netdev), 1126 (u8)iwdev->mac_ip_table_idx); 1127 if (status) 1128 irdma_del_local_mac_entry(iwdev->rf, 1129 (u8)iwdev->mac_ip_table_idx); 1130 } 1131 return status; 1132 } 1133 1134 /** 1135 * irdma_irq_request - set up the msix interrupt vector 1136 * @rf: RDMA PCI function 1137 * @msix_vec: interrupt vector information 1138 * @handler: function pointer to associate with interrupt 1139 * @argument: argument passed to the handler 1140 * 1141 * Allocate interrupt resources and setup interrupt 1142 * Return 0 if successful, otherwise return error 1143 * Note that after this function bus_describe_intr shall 1144 * be called. 1145 */ 1146 static int 1147 irdma_irq_request(struct irdma_pci_f *rf, 1148 struct irdma_msix_vector *msix_vec, 1149 driver_intr_t handler, void *argument) 1150 { 1151 device_t dev = rf->dev_ctx.dev; 1152 int rid = msix_vec->idx + 1; 1153 int err, status; 1154 1155 msix_vec->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 1156 if (!msix_vec->res) { 1157 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1158 "Unable to allocate bus resource int[%d]\n", 1159 rid); 1160 return -EINVAL; 1161 } 1162 err = bus_setup_intr(dev, msix_vec->res, INTR_TYPE_NET | INTR_MPSAFE, 1163 NULL, handler, argument, &msix_vec->tag); 1164 if (err) { 1165 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1166 "Unable to register handler with %x status\n", 1167 err); 1168 status = -EINVAL; 1169 goto fail_intr; 1170 } 1171 return 0; 1172 1173 fail_intr: 1174 bus_release_resource(dev, SYS_RES_IRQ, rid, msix_vec->res); 1175 msix_vec->res = NULL; 1176 1177 return status; 1178 } 1179 1180 /** 1181 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1182 * ceq 1183 * @rf: RDMA PCI function 1184 * @iwceq: ceq associated with the vector 1185 * @ceq_id: the id number of the iwceq 1186 * @msix_vec: interrupt vector information 1187 * 1188 * Allocate interrupt resources and enable irq handling 1189 * Return 0 if successful, otherwise return error 1190 */ 1191 static int 1192 irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1193 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1194 { 1195 int status; 1196 1197 if (rf->msix_shared && !ceq_id) { 1198 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1199 "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev)); 1200 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1201 status = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf); 1202 if (status) 1203 return status; 1204 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name); 1205 } else { 1206 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1207 "irdma-%s-CEQ-%d", 1208 dev_name(&rf->pcidev->dev), ceq_id); 1209 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1210 1211 status = irdma_irq_request(rf, msix_vec, irdma_ceq_handler, iwceq); 1212 if (status) 1213 return status; 1214 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name); 1215 } 1216 msix_vec->ceq_id = ceq_id; 1217 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1218 1219 return 0; 1220 } 1221 1222 /** 1223 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1224 * @rf: RDMA PCI function 1225 * 1226 * Allocate interrupt resources and enable irq handling 1227 * Return 0 if successful, otherwise return error 1228 */ 1229 static int 1230 irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1231 { 1232 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1233 u32 ret = 0; 1234 1235 if (!rf->msix_shared) { 1236 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1237 "irdma-%s-AEQ", dev_name(&rf->pcidev->dev)); 1238 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1239 ret = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf); 1240 if (ret) 1241 return ret; 1242 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name); 1243 } 1244 if (ret) { 1245 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, "aeq irq config fail\n"); 1246 return -EINVAL; 1247 } 1248 1249 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1250 1251 return 0; 1252 } 1253 1254 /** 1255 * irdma_create_ceq - create completion event queue 1256 * @rf: RDMA PCI function 1257 * @iwceq: pointer to the ceq resources to be created 1258 * @ceq_id: the id number of the iwceq 1259 * @vsi: SC vsi struct 1260 * 1261 * Return 0, if the ceq and the resources associated with it 1262 * are successfully created, otherwise return error 1263 */ 1264 static int 1265 irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1266 u32 ceq_id, struct irdma_sc_vsi *vsi) 1267 { 1268 int status; 1269 struct irdma_ceq_init_info info = {0}; 1270 struct irdma_sc_dev *dev = &rf->sc_dev; 1271 u64 scratch; 1272 u32 ceq_size; 1273 1274 info.ceq_id = ceq_id; 1275 iwceq->rf = rf; 1276 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1277 dev->hw_attrs.max_hw_ceq_size); 1278 iwceq->mem.size = sizeof(struct irdma_ceqe) * ceq_size; 1279 iwceq->mem.va = irdma_allocate_dma_mem(dev->hw, &iwceq->mem, 1280 iwceq->mem.size, 1281 IRDMA_CEQ_ALIGNMENT); 1282 if (!iwceq->mem.va) 1283 return -ENOMEM; 1284 1285 info.ceq_id = ceq_id; 1286 info.ceqe_base = iwceq->mem.va; 1287 info.ceqe_pa = iwceq->mem.pa; 1288 info.elem_cnt = ceq_size; 1289 info.reg_cq = kzalloc(sizeof(struct irdma_sc_cq *) * info.elem_cnt, GFP_KERNEL); 1290 1291 iwceq->sc_ceq.ceq_id = ceq_id; 1292 info.dev = dev; 1293 info.vsi = vsi; 1294 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1295 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1296 if (!status) { 1297 if (dev->ceq_valid) 1298 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1299 IRDMA_OP_CEQ_CREATE); 1300 else 1301 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1302 } 1303 1304 if (status) { 1305 kfree(info.reg_cq); 1306 irdma_free_dma_mem(dev->hw, &iwceq->mem); 1307 } 1308 1309 return status; 1310 } 1311 1312 /** 1313 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1314 * @rf: RDMA PCI function 1315 * 1316 * Allocate a list for all device completion event queues 1317 * Create the ceq 0 and configure it's msix interrupt vector 1318 * Return 0, if successfully set up, otherwise return error 1319 */ 1320 static int 1321 irdma_setup_ceq_0(struct irdma_pci_f *rf) 1322 { 1323 struct irdma_ceq *iwceq; 1324 struct irdma_msix_vector *msix_vec; 1325 u32 i; 1326 int status = 0; 1327 u32 num_ceqs; 1328 1329 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1330 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1331 memset(rf->ceqlist, 0, num_ceqs * sizeof(*rf->ceqlist)); 1332 if (!rf->ceqlist) { 1333 status = -ENOMEM; 1334 goto exit; 1335 } 1336 1337 iwceq = &rf->ceqlist[0]; 1338 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1339 if (status) { 1340 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1341 "create ceq status = %d\n", 1342 status); 1343 goto exit; 1344 } 1345 1346 spin_lock_init(&iwceq->ce_lock); 1347 i = rf->msix_shared ? 0 : 1; 1348 msix_vec = &rf->iw_msixtbl[i]; 1349 iwceq->irq = msix_vec->irq; 1350 iwceq->msix_idx = msix_vec->idx; 1351 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1352 if (status) { 1353 irdma_destroy_ceq(rf, iwceq); 1354 goto exit; 1355 } 1356 1357 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1358 rf->ceqs_count++; 1359 1360 exit: 1361 if (status && !rf->ceqs_count) { 1362 kfree(rf->ceqlist); 1363 rf->ceqlist = NULL; 1364 return status; 1365 } 1366 rf->sc_dev.ceq_valid = true; 1367 1368 return 0; 1369 } 1370 1371 /** 1372 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1373 * @rf: RDMA PCI function 1374 * @vsi: VSI structure for this CEQ 1375 * 1376 * Allocate a list for all device completion event queues 1377 * Create the ceq's and configure their msix interrupt vectors 1378 * Return 0, if ceqs are successfully set up, otherwise return error 1379 */ 1380 static int 1381 irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1382 { 1383 u32 i; 1384 u32 ceq_id; 1385 struct irdma_ceq *iwceq; 1386 struct irdma_msix_vector *msix_vec; 1387 int status; 1388 u32 num_ceqs; 1389 1390 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1391 i = (rf->msix_shared) ? 1 : 2; 1392 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1393 iwceq = &rf->ceqlist[ceq_id]; 1394 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1395 if (status) { 1396 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1397 "create ceq status = %d\n", 1398 status); 1399 goto del_ceqs; 1400 } 1401 spin_lock_init(&iwceq->ce_lock); 1402 msix_vec = &rf->iw_msixtbl[i]; 1403 iwceq->irq = msix_vec->irq; 1404 iwceq->msix_idx = msix_vec->idx; 1405 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1406 if (status) { 1407 irdma_destroy_ceq(rf, iwceq); 1408 goto del_ceqs; 1409 } 1410 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1411 rf->ceqs_count++; 1412 } 1413 1414 return 0; 1415 1416 del_ceqs: 1417 irdma_del_ceqs(rf); 1418 1419 return status; 1420 } 1421 1422 static int 1423 irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1424 { 1425 struct irdma_aeq *aeq = &rf->aeq; 1426 dma_addr_t *pg_arr; 1427 u32 pg_cnt; 1428 int status; 1429 1430 if (rf->rdma_ver < IRDMA_GEN_2) 1431 return -EOPNOTSUPP; 1432 1433 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1434 aeq->mem.va = vzalloc(aeq->mem.size); 1435 1436 if (!aeq->mem.va) 1437 return -ENOMEM; 1438 1439 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1440 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1441 if (status) { 1442 vfree(aeq->mem.va); 1443 return status; 1444 } 1445 1446 pg_arr = (dma_addr_t *) aeq->palloc.level1.addr; 1447 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1448 if (status) { 1449 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1450 vfree(aeq->mem.va); 1451 return status; 1452 } 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * irdma_create_aeq - create async event queue 1459 * @rf: RDMA PCI function 1460 * 1461 * Return 0, if the aeq and the resources associated with it 1462 * are successfully created, otherwise return error 1463 */ 1464 static int 1465 irdma_create_aeq(struct irdma_pci_f *rf) 1466 { 1467 struct irdma_aeq_init_info info = {0}; 1468 struct irdma_sc_dev *dev = &rf->sc_dev; 1469 struct irdma_aeq *aeq = &rf->aeq; 1470 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1471 u32 aeq_size; 1472 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1473 int status; 1474 1475 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1476 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1477 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1478 1479 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * aeq_size; 1480 aeq->mem.va = irdma_allocate_dma_mem(dev->hw, &aeq->mem, aeq->mem.size, 1481 IRDMA_AEQ_ALIGNMENT); 1482 if (aeq->mem.va) 1483 goto skip_virt_aeq; 1484 1485 /* physically mapped aeq failed. setup virtual aeq */ 1486 status = irdma_create_virt_aeq(rf, aeq_size); 1487 if (status) 1488 return status; 1489 1490 info.virtual_map = true; 1491 aeq->virtual_map = info.virtual_map; 1492 info.pbl_chunk_size = 1; 1493 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1494 1495 skip_virt_aeq: 1496 info.aeqe_base = aeq->mem.va; 1497 info.aeq_elem_pa = aeq->mem.pa; 1498 info.elem_cnt = aeq_size; 1499 info.dev = dev; 1500 info.msix_idx = rf->iw_msixtbl->idx; 1501 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1502 if (status) 1503 goto err; 1504 1505 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1506 if (status) 1507 goto err; 1508 1509 return 0; 1510 1511 err: 1512 if (aeq->virtual_map) 1513 irdma_destroy_virt_aeq(rf); 1514 else 1515 irdma_free_dma_mem(dev->hw, &aeq->mem); 1516 1517 return status; 1518 } 1519 1520 /** 1521 * irdma_setup_aeq - set up the device aeq 1522 * @rf: RDMA PCI function 1523 * 1524 * Create the aeq and configure its msix interrupt vector 1525 * Return 0 if successful, otherwise return error 1526 */ 1527 static int 1528 irdma_setup_aeq(struct irdma_pci_f *rf) 1529 { 1530 struct irdma_sc_dev *dev = &rf->sc_dev; 1531 int status; 1532 1533 status = irdma_create_aeq(rf); 1534 if (status) 1535 return status; 1536 1537 status = irdma_cfg_aeq_vector(rf); 1538 if (status) { 1539 irdma_destroy_aeq(rf); 1540 return status; 1541 } 1542 1543 if (!rf->msix_shared) 1544 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1545 1546 return 0; 1547 } 1548 1549 /** 1550 * irdma_initialize_ilq - create iwarp local queue for cm 1551 * @iwdev: irdma device 1552 * 1553 * Return 0 if successful, otherwise return error 1554 */ 1555 static int 1556 irdma_initialize_ilq(struct irdma_device *iwdev) 1557 { 1558 struct irdma_puda_rsrc_info info = {0}; 1559 int status; 1560 1561 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1562 info.cq_id = 1; 1563 info.qp_id = 1; 1564 info.count = 1; 1565 info.pd_id = 1; 1566 info.abi_ver = IRDMA_ABI_VER; 1567 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1568 info.rq_size = info.sq_size; 1569 info.buf_size = 1024; 1570 info.tx_buf_cnt = 2 * info.sq_size; 1571 info.receive = irdma_receive_ilq; 1572 info.xmit_complete = irdma_free_sqbuf; 1573 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1574 if (status) 1575 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, "ilq create fail\n"); 1576 1577 return status; 1578 } 1579 1580 /** 1581 * irdma_initialize_ieq - create iwarp exception queue 1582 * @iwdev: irdma device 1583 * 1584 * Return 0 if successful, otherwise return error 1585 */ 1586 static int 1587 irdma_initialize_ieq(struct irdma_device *iwdev) 1588 { 1589 struct irdma_puda_rsrc_info info = {0}; 1590 int status; 1591 1592 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1593 info.cq_id = 2; 1594 info.qp_id = iwdev->vsi.exception_lan_q; 1595 info.count = 1; 1596 info.pd_id = 2; 1597 info.abi_ver = IRDMA_ABI_VER; 1598 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1599 info.rq_size = info.sq_size; 1600 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1601 info.tx_buf_cnt = 4096; 1602 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1603 if (status) 1604 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, "ieq create fail\n"); 1605 1606 return status; 1607 } 1608 1609 /** 1610 * irdma_reinitialize_ieq - destroy and re-create ieq 1611 * @vsi: VSI structure 1612 */ 1613 void 1614 irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1615 { 1616 struct irdma_device *iwdev = vsi->back_vsi; 1617 struct irdma_pci_f *rf = iwdev->rf; 1618 1619 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1620 if (irdma_initialize_ieq(iwdev)) { 1621 iwdev->rf->reset = true; 1622 rf->gen_ops.request_reset(rf); 1623 } 1624 } 1625 1626 /** 1627 * irdma_hmc_setup - create hmc objects for the device 1628 * @rf: RDMA PCI function 1629 * 1630 * Set up the device private memory space for the number and size of 1631 * the hmc objects and create the objects 1632 * Return 0 if successful, otherwise return error 1633 */ 1634 static int 1635 irdma_hmc_setup(struct irdma_pci_f *rf) 1636 { 1637 int status; 1638 struct irdma_sc_dev *dev = &rf->sc_dev; 1639 u32 qpcnt; 1640 1641 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1642 1643 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1644 status = irdma_cfg_fpm_val(dev, qpcnt); 1645 if (status) 1646 return status; 1647 1648 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1649 1650 return status; 1651 } 1652 1653 /** 1654 * irdma_del_init_mem - deallocate memory resources 1655 * @rf: RDMA PCI function 1656 */ 1657 static void 1658 irdma_del_init_mem(struct irdma_pci_f *rf) 1659 { 1660 struct irdma_sc_dev *dev = &rf->sc_dev; 1661 1662 kfree(dev->hmc_info->sd_table.sd_entry); 1663 dev->hmc_info->sd_table.sd_entry = NULL; 1664 vfree(rf->mem_rsrc); 1665 rf->mem_rsrc = NULL; 1666 irdma_free_dma_mem(&rf->hw, &rf->obj_mem); 1667 if (rf->rdma_ver != IRDMA_GEN_1) { 1668 kfree(rf->allocated_ws_nodes); 1669 rf->allocated_ws_nodes = NULL; 1670 } 1671 mutex_destroy(&dev->ws_mutex); 1672 kfree(rf->ceqlist); 1673 rf->ceqlist = NULL; 1674 kfree(rf->iw_msixtbl); 1675 rf->iw_msixtbl = NULL; 1676 kfree(rf->hmc_info_mem); 1677 rf->hmc_info_mem = NULL; 1678 } 1679 /** 1680 * irdma_initialize_dev - initialize device 1681 * @rf: RDMA PCI function 1682 * 1683 * Allocate memory for the hmc objects and initialize iwdev 1684 * Return 0 if successful, otherwise clean up the resources 1685 * and return error 1686 */ 1687 static int 1688 irdma_initialize_dev(struct irdma_pci_f *rf) 1689 { 1690 int status; 1691 struct irdma_sc_dev *dev = &rf->sc_dev; 1692 struct irdma_device_init_info info = {0}; 1693 struct irdma_dma_mem mem; 1694 u32 size; 1695 1696 size = sizeof(struct irdma_hmc_pble_rsrc) + 1697 sizeof(struct irdma_hmc_info) + 1698 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1699 1700 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1701 if (!rf->hmc_info_mem) 1702 return -ENOMEM; 1703 1704 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1705 dev->hmc_info = &rf->hw.hmc; 1706 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1707 (rf->pble_rsrc + 1); 1708 1709 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1710 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1711 if (status) 1712 goto error; 1713 1714 info.fpm_query_buf_pa = mem.pa; 1715 info.fpm_query_buf = mem.va; 1716 1717 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1718 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1719 if (status) 1720 goto error; 1721 1722 info.fpm_commit_buf_pa = mem.pa; 1723 info.fpm_commit_buf = mem.va; 1724 1725 info.bar0 = rf->hw.hw_addr; 1726 info.hmc_fn_id = rf->peer_info->pf_id; 1727 /* 1728 * the debug_mask is already assigned at this point through sysctl and so the value shouldn't be overwritten 1729 */ 1730 info.debug_mask = rf->sc_dev.debug_mask; 1731 info.hw = &rf->hw; 1732 status = irdma_sc_dev_init(&rf->sc_dev, &info); 1733 if (status) 1734 goto error; 1735 1736 return status; 1737 error: 1738 kfree(rf->hmc_info_mem); 1739 rf->hmc_info_mem = NULL; 1740 1741 return status; 1742 } 1743 1744 /** 1745 * irdma_rt_deinit_hw - clean up the irdma device resources 1746 * @iwdev: irdma device 1747 * 1748 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1749 * device queues and free the pble and the hmc objects 1750 */ 1751 void 1752 irdma_rt_deinit_hw(struct irdma_device *iwdev) 1753 { 1754 struct irdma_sc_qp qp = {{0}}; 1755 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_INIT, "state = %d\n", iwdev->init_state); 1756 1757 switch (iwdev->init_state) { 1758 case IP_ADDR_REGISTERED: 1759 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1760 irdma_del_local_mac_entry(iwdev->rf, 1761 (u8)iwdev->mac_ip_table_idx); 1762 /* fallthrough */ 1763 case AEQ_CREATED: 1764 case PBLE_CHUNK_MEM: 1765 case CEQS_CREATED: 1766 case REM_ENDPOINT_TRK_CREATED: 1767 if (iwdev->rf->en_rem_endpoint_trk) { 1768 qp.dev = &iwdev->rf->sc_dev; 1769 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; 1770 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; 1771 irdma_cqp_qp_destroy_cmd(qp.dev, &qp); 1772 } 1773 /* fallthrough */ 1774 case IEQ_CREATED: 1775 if (!iwdev->roce_mode) 1776 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1777 iwdev->rf->reset); 1778 /* fallthrough */ 1779 case ILQ_CREATED: 1780 if (!iwdev->roce_mode) 1781 irdma_puda_dele_rsrc(&iwdev->vsi, 1782 IRDMA_PUDA_RSRC_TYPE_ILQ, 1783 iwdev->rf->reset); 1784 break; 1785 default: 1786 irdma_dev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1787 break; 1788 } 1789 1790 irdma_cleanup_cm_core(&iwdev->cm_core); 1791 if (iwdev->vsi.pestat) { 1792 irdma_vsi_stats_free(&iwdev->vsi); 1793 kfree(iwdev->vsi.pestat); 1794 } 1795 if (iwdev->cleanup_wq) 1796 destroy_workqueue(iwdev->cleanup_wq); 1797 } 1798 1799 static int 1800 irdma_setup_init_state(struct irdma_pci_f *rf) 1801 { 1802 int status; 1803 1804 status = irdma_save_msix_info(rf); 1805 if (status) 1806 return status; 1807 1808 rf->obj_mem.size = 8192; 1809 rf->obj_mem.va = irdma_allocate_dma_mem(&rf->hw, &rf->obj_mem, 1810 rf->obj_mem.size, 1811 IRDMA_HW_PAGE_SIZE); 1812 if (!rf->obj_mem.va) { 1813 status = -ENOMEM; 1814 goto clean_msixtbl; 1815 } 1816 1817 rf->obj_next = rf->obj_mem; 1818 status = irdma_initialize_dev(rf); 1819 if (status) 1820 goto clean_obj_mem; 1821 1822 return 0; 1823 1824 clean_obj_mem: 1825 irdma_free_dma_mem(&rf->hw, &rf->obj_mem); 1826 clean_msixtbl: 1827 kfree(rf->iw_msixtbl); 1828 rf->iw_msixtbl = NULL; 1829 return status; 1830 } 1831 1832 /** 1833 * irdma_get_used_rsrc - determine resources used internally 1834 * @iwdev: irdma device 1835 * 1836 * Called at the end of open to get all internal allocations 1837 */ 1838 static void 1839 irdma_get_used_rsrc(struct irdma_device *iwdev) 1840 { 1841 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, 1842 iwdev->rf->max_pd); 1843 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, 1844 iwdev->rf->max_qp); 1845 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, 1846 iwdev->rf->max_cq); 1847 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, 1848 iwdev->rf->max_mr); 1849 } 1850 1851 void 1852 irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1853 { 1854 enum init_completion_state state = rf->init_state; 1855 1856 rf->init_state = INVALID_STATE; 1857 if (rf->rsrc_created) { 1858 irdma_destroy_aeq(rf); 1859 irdma_destroy_pble_prm(rf->pble_rsrc); 1860 irdma_del_ceqs(rf); 1861 rf->rsrc_created = false; 1862 } 1863 1864 switch (state) { 1865 case CEQ0_CREATED: 1866 irdma_del_ceq_0(rf); 1867 /* fallthrough */ 1868 case CCQ_CREATED: 1869 irdma_destroy_ccq(rf); 1870 /* fallthrough */ 1871 case HW_RSRC_INITIALIZED: 1872 case HMC_OBJS_CREATED: 1873 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1874 rf->reset, rf->rdma_ver); 1875 /* fallthrough */ 1876 case CQP_CREATED: 1877 irdma_destroy_cqp(rf, !rf->reset); 1878 /* fallthrough */ 1879 case INITIAL_STATE: 1880 irdma_del_init_mem(rf); 1881 break; 1882 case INVALID_STATE: 1883 default: 1884 irdma_dev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1885 break; 1886 } 1887 } 1888 1889 /** 1890 * irdma_rt_init_hw - Initializes runtime portion of HW 1891 * @iwdev: irdma device 1892 * @l2params: qos, tc, mtu info from netdev driver 1893 * 1894 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1895 * device resource objects. 1896 */ 1897 int 1898 irdma_rt_init_hw(struct irdma_device *iwdev, 1899 struct irdma_l2params *l2params) 1900 { 1901 struct irdma_pci_f *rf = iwdev->rf; 1902 struct irdma_sc_dev *dev = &rf->sc_dev; 1903 struct irdma_sc_qp qp = {{0}}; 1904 struct irdma_vsi_init_info vsi_info = {0}; 1905 struct irdma_vsi_stats_info stats_info = {0}; 1906 int status; 1907 1908 vsi_info.dev = dev; 1909 vsi_info.back_vsi = iwdev; 1910 vsi_info.params = l2params; 1911 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1912 vsi_info.register_qset = rf->gen_ops.register_qset; 1913 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1914 vsi_info.exception_lan_q = 2; 1915 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1916 1917 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1918 if (status) 1919 return status; 1920 1921 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1922 if (!stats_info.pestat) { 1923 irdma_cleanup_cm_core(&iwdev->cm_core); 1924 return -ENOMEM; 1925 } 1926 stats_info.fcn_id = dev->hmc_fn_id; 1927 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1928 if (status) { 1929 irdma_cleanup_cm_core(&iwdev->cm_core); 1930 kfree(stats_info.pestat); 1931 return status; 1932 } 1933 1934 do { 1935 if (!iwdev->roce_mode) { 1936 status = irdma_initialize_ilq(iwdev); 1937 if (status) 1938 break; 1939 iwdev->init_state = ILQ_CREATED; 1940 status = irdma_initialize_ieq(iwdev); 1941 if (status) 1942 break; 1943 iwdev->init_state = IEQ_CREATED; 1944 } 1945 if (iwdev->rf->en_rem_endpoint_trk) { 1946 qp.dev = dev; 1947 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; 1948 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; 1949 status = irdma_cqp_qp_create_cmd(dev, &qp); 1950 if (status) 1951 break; 1952 iwdev->init_state = REM_ENDPOINT_TRK_CREATED; 1953 } 1954 if (!rf->rsrc_created) { 1955 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1956 if (status) 1957 break; 1958 1959 iwdev->init_state = CEQS_CREATED; 1960 1961 status = irdma_hmc_init_pble(&rf->sc_dev, 1962 rf->pble_rsrc); 1963 if (status) { 1964 irdma_del_ceqs(rf); 1965 break; 1966 } 1967 1968 iwdev->init_state = PBLE_CHUNK_MEM; 1969 1970 status = irdma_setup_aeq(rf); 1971 if (status) { 1972 irdma_destroy_pble_prm(rf->pble_rsrc); 1973 irdma_del_ceqs(rf); 1974 break; 1975 } 1976 iwdev->init_state = AEQ_CREATED; 1977 rf->rsrc_created = true; 1978 } 1979 1980 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1981 irdma_alloc_set_mac(iwdev); 1982 irdma_add_ip(iwdev); 1983 iwdev->init_state = IP_ADDR_REGISTERED; 1984 1985 /* 1986 * handles asynch cleanup tasks - disconnect CM , free qp, free cq bufs 1987 */ 1988 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1989 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1990 if (!iwdev->cleanup_wq) 1991 return -ENOMEM; 1992 irdma_get_used_rsrc(iwdev); 1993 init_waitqueue_head(&iwdev->suspend_wq); 1994 1995 return 0; 1996 } while (0); 1997 1998 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1999 status, iwdev->init_state); 2000 irdma_rt_deinit_hw(iwdev); 2001 2002 return status; 2003 } 2004 2005 /** 2006 * irdma_ctrl_init_hw - Initializes control portion of HW 2007 * @rf: RDMA PCI function 2008 * 2009 * Create admin queues, HMC obejcts and RF resource objects 2010 */ 2011 int 2012 irdma_ctrl_init_hw(struct irdma_pci_f *rf) 2013 { 2014 struct irdma_sc_dev *dev = &rf->sc_dev; 2015 int status; 2016 do { 2017 status = irdma_setup_init_state(rf); 2018 if (status) 2019 break; 2020 rf->init_state = INITIAL_STATE; 2021 2022 status = irdma_create_cqp(rf); 2023 if (status) 2024 break; 2025 rf->init_state = CQP_CREATED; 2026 2027 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 2028 if (rf->rdma_ver != IRDMA_GEN_1) { 2029 status = irdma_get_rdma_features(dev); 2030 if (status) 2031 break; 2032 } 2033 2034 status = irdma_hmc_setup(rf); 2035 if (status) 2036 break; 2037 rf->init_state = HMC_OBJS_CREATED; 2038 2039 status = irdma_initialize_hw_rsrc(rf); 2040 if (status) 2041 break; 2042 rf->init_state = HW_RSRC_INITIALIZED; 2043 2044 status = irdma_create_ccq(rf); 2045 if (status) 2046 break; 2047 rf->init_state = CCQ_CREATED; 2048 2049 status = irdma_setup_ceq_0(rf); 2050 if (status) 2051 break; 2052 rf->init_state = CEQ0_CREATED; 2053 /* Handles processing of CQP completions */ 2054 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", 2055 WQ_HIGHPRI | WQ_UNBOUND); 2056 if (!rf->cqp_cmpl_wq) { 2057 status = -ENOMEM; 2058 break; 2059 } 2060 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 2061 irdma_sc_ccq_arm(dev->ccq); 2062 return 0; 2063 } while (0); 2064 2065 pr_err("IRDMA hardware initialization FAILED init_state=%d status=%d\n", 2066 rf->init_state, status); 2067 irdma_ctrl_deinit_hw(rf); 2068 return status; 2069 } 2070 2071 /** 2072 * irdma_set_hw_rsrc - set hw memory resources. 2073 * @rf: RDMA PCI function 2074 */ 2075 static void 2076 irdma_set_hw_rsrc(struct irdma_pci_f *rf) 2077 { 2078 rf->allocated_qps = (void *)(rf->mem_rsrc + 2079 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 2080 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 2081 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 2082 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 2083 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 2084 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 2085 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 2086 2087 rf->qp_table = (struct irdma_qp **) 2088 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 2089 rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]); 2090 2091 spin_lock_init(&rf->rsrc_lock); 2092 spin_lock_init(&rf->arp_lock); 2093 spin_lock_init(&rf->qptable_lock); 2094 spin_lock_init(&rf->cqtable_lock); 2095 spin_lock_init(&rf->qh_list_lock); 2096 } 2097 2098 /** 2099 * irdma_calc_mem_rsrc_size - calculate memory resources size. 2100 * @rf: RDMA PCI function 2101 */ 2102 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf){ 2103 u32 rsrc_size; 2104 2105 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 2106 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 2107 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 2108 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 2109 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 2110 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 2111 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 2112 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 2113 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 2114 rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq; 2115 2116 return rsrc_size; 2117 } 2118 2119 /** 2120 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 2121 * @rf: RDMA PCI function 2122 */ 2123 u32 2124 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 2125 { 2126 u32 rsrc_size; 2127 u32 mrdrvbits; 2128 u32 ret; 2129 2130 if (rf->rdma_ver != IRDMA_GEN_1) { 2131 rf->allocated_ws_nodes = 2132 kcalloc(BITS_TO_LONGS(IRDMA_MAX_WS_NODES), 2133 sizeof(unsigned long), GFP_KERNEL); 2134 if (!rf->allocated_ws_nodes) 2135 return -ENOMEM; 2136 2137 set_bit(0, rf->allocated_ws_nodes); 2138 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 2139 } 2140 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 2141 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 2142 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 2143 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 2144 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 2145 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 2146 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 2147 rf->max_mcg = rf->max_qp; 2148 2149 rsrc_size = irdma_calc_mem_rsrc_size(rf); 2150 rf->mem_rsrc = vzalloc(rsrc_size); 2151 if (!rf->mem_rsrc) { 2152 ret = -ENOMEM; 2153 goto mem_rsrc_vmalloc_fail; 2154 } 2155 2156 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2157 2158 irdma_set_hw_rsrc(rf); 2159 2160 set_bit(0, rf->allocated_mrs); 2161 set_bit(0, rf->allocated_qps); 2162 set_bit(0, rf->allocated_cqs); 2163 set_bit(0, rf->allocated_pds); 2164 set_bit(0, rf->allocated_arps); 2165 set_bit(0, rf->allocated_ahs); 2166 set_bit(0, rf->allocated_mcgs); 2167 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2168 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2169 set_bit(IRDMA_REM_ENDPOINT_TRK_QPID, rf->allocated_qps); /* qp 3 Remote Endpt trk */ 2170 set_bit(1, rf->allocated_cqs); 2171 set_bit(1, rf->allocated_pds); 2172 set_bit(2, rf->allocated_cqs); 2173 set_bit(2, rf->allocated_pds); 2174 2175 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2176 /* stag index mask has a minimum of 14 bits */ 2177 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2178 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2179 2180 return 0; 2181 2182 mem_rsrc_vmalloc_fail: 2183 kfree(rf->allocated_ws_nodes); 2184 rf->allocated_ws_nodes = NULL; 2185 2186 return ret; 2187 } 2188 2189 /** 2190 * irdma_cqp_ce_handler - handle cqp completions 2191 * @rf: RDMA PCI function 2192 * @cq: cq for cqp completions 2193 */ 2194 void 2195 irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2196 { 2197 struct irdma_cqp_request *cqp_request; 2198 struct irdma_sc_dev *dev = &rf->sc_dev; 2199 u32 cqe_count = 0; 2200 struct irdma_ccq_cqe_info info; 2201 unsigned long flags; 2202 int ret; 2203 2204 do { 2205 memset(&info, 0, sizeof(info)); 2206 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2207 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2208 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2209 if (ret) 2210 break; 2211 2212 cqp_request = (struct irdma_cqp_request *) 2213 (uintptr_t)info.scratch; 2214 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2215 info.maj_err_code, 2216 info.min_err_code)) 2217 irdma_dev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2218 info.op_code, info.maj_err_code, info.min_err_code); 2219 if (cqp_request) { 2220 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2221 cqp_request->compl_info.min_err_code = info.min_err_code; 2222 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2223 cqp_request->compl_info.error = info.error; 2224 irdma_complete_cqp_request(&rf->cqp, cqp_request); 2225 } 2226 2227 cqe_count++; 2228 } while (1); 2229 2230 if (cqe_count) { 2231 irdma_process_bh(dev); 2232 irdma_sc_ccq_arm(dev->ccq); 2233 } 2234 } 2235 2236 /** 2237 * cqp_compl_worker - Handle cqp completions 2238 * @work: Pointer to work structure 2239 */ 2240 void 2241 cqp_compl_worker(struct work_struct *work) 2242 { 2243 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2244 cqp_cmpl_work); 2245 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2246 2247 irdma_cqp_ce_handler(rf, cq); 2248 } 2249 2250 /** 2251 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2252 * @cm_core: cm's core 2253 * @port: port to identify apbvt entry 2254 */ 2255 static struct irdma_apbvt_entry * 2256 irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2257 u16 port) 2258 { 2259 struct irdma_apbvt_entry *entry; 2260 2261 HASH_FOR_EACH_POSSIBLE(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2262 if (entry->port == port) { 2263 entry->use_cnt++; 2264 return entry; 2265 } 2266 } 2267 2268 return NULL; 2269 } 2270 2271 /** 2272 * irdma_next_iw_state - modify qp state 2273 * @iwqp: iwarp qp to modify 2274 * @state: next state for qp 2275 * @del_hash: del hash 2276 * @term: term message 2277 * @termlen: length of term message 2278 */ 2279 void 2280 irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2281 u8 termlen) 2282 { 2283 struct irdma_modify_qp_info info = {0}; 2284 2285 info.next_iwarp_state = state; 2286 info.remove_hash_idx = del_hash; 2287 info.cq_num_valid = true; 2288 info.arp_cache_idx_valid = true; 2289 info.dont_send_term = true; 2290 info.dont_send_fin = true; 2291 info.termlen = termlen; 2292 2293 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2294 info.dont_send_term = false; 2295 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2296 info.dont_send_fin = false; 2297 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2298 info.reset_tcp_conn = true; 2299 iwqp->hw_iwarp_state = state; 2300 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2301 iwqp->iwarp_state = info.next_iwarp_state; 2302 } 2303 2304 /** 2305 * irdma_del_local_mac_entry - remove a mac entry from the hw 2306 * table 2307 * @rf: RDMA PCI function 2308 * @idx: the index of the mac ip address to delete 2309 */ 2310 void 2311 irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2312 { 2313 struct irdma_cqp *iwcqp = &rf->cqp; 2314 struct irdma_cqp_request *cqp_request; 2315 struct cqp_cmds_info *cqp_info; 2316 2317 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2318 if (!cqp_request) 2319 return; 2320 2321 cqp_info = &cqp_request->info; 2322 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2323 cqp_info->post_sq = 1; 2324 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2325 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2326 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2327 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2328 2329 irdma_handle_cqp_op(rf, cqp_request); 2330 irdma_put_cqp_request(iwcqp, cqp_request); 2331 } 2332 2333 /** 2334 * irdma_add_local_mac_entry - add a mac ip address entry to the 2335 * hw table 2336 * @rf: RDMA PCI function 2337 * @mac_addr: pointer to mac address 2338 * @idx: the index of the mac ip address to add 2339 */ 2340 int 2341 irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) 2342 { 2343 struct irdma_local_mac_entry_info *info; 2344 struct irdma_cqp *iwcqp = &rf->cqp; 2345 struct irdma_cqp_request *cqp_request; 2346 struct cqp_cmds_info *cqp_info; 2347 int status; 2348 2349 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2350 if (!cqp_request) 2351 return -ENOMEM; 2352 2353 cqp_info = &cqp_request->info; 2354 cqp_info->post_sq = 1; 2355 info = &cqp_info->in.u.add_local_mac_entry.info; 2356 ether_addr_copy(info->mac_addr, mac_addr); 2357 info->entry_idx = idx; 2358 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2359 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2360 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2361 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2362 2363 status = irdma_handle_cqp_op(rf, cqp_request); 2364 irdma_put_cqp_request(iwcqp, cqp_request); 2365 2366 return status; 2367 } 2368 2369 /** 2370 * irdma_alloc_local_mac_entry - allocate a mac entry 2371 * @rf: RDMA PCI function 2372 * @mac_tbl_idx: the index of the new mac address 2373 * 2374 * Allocate a mac address entry and update the mac_tbl_idx 2375 * to hold the index of the newly created mac address 2376 * Return 0 if successful, otherwise return error 2377 */ 2378 int 2379 irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2380 { 2381 struct irdma_cqp *iwcqp = &rf->cqp; 2382 struct irdma_cqp_request *cqp_request; 2383 struct cqp_cmds_info *cqp_info; 2384 int status = 0; 2385 2386 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2387 if (!cqp_request) 2388 return -ENOMEM; 2389 2390 cqp_info = &cqp_request->info; 2391 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2392 cqp_info->post_sq = 1; 2393 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2394 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2395 status = irdma_handle_cqp_op(rf, cqp_request); 2396 if (!status) 2397 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2398 2399 irdma_put_cqp_request(iwcqp, cqp_request); 2400 2401 return status; 2402 } 2403 2404 /** 2405 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2406 * @iwdev: irdma device 2407 * @accel_local_port: port for apbvt 2408 * @add_port: add ordelete port 2409 */ 2410 static int 2411 irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2412 u16 accel_local_port, bool add_port) 2413 { 2414 struct irdma_apbvt_info *info; 2415 struct irdma_cqp_request *cqp_request; 2416 struct cqp_cmds_info *cqp_info; 2417 int status; 2418 2419 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2420 if (!cqp_request) 2421 return -ENOMEM; 2422 2423 cqp_info = &cqp_request->info; 2424 info = &cqp_info->in.u.manage_apbvt_entry.info; 2425 memset(info, 0, sizeof(*info)); 2426 info->add = add_port; 2427 info->port = accel_local_port; 2428 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2429 cqp_info->post_sq = 1; 2430 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2431 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2432 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_DEV, "%s: port=0x%04x\n", 2433 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2434 2435 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2436 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2437 2438 return status; 2439 } 2440 2441 /** 2442 * irdma_add_apbvt - add tcp port to HW apbvt table 2443 * @iwdev: irdma device 2444 * @port: port for apbvt 2445 */ 2446 struct irdma_apbvt_entry * 2447 irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2448 { 2449 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2450 struct irdma_apbvt_entry *entry; 2451 unsigned long flags; 2452 2453 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2454 entry = irdma_lookup_apbvt_entry(cm_core, port); 2455 if (entry) { 2456 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2457 return entry; 2458 } 2459 2460 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2461 if (!entry) { 2462 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2463 return NULL; 2464 } 2465 2466 entry->port = port; 2467 entry->use_cnt = 1; 2468 HASH_ADD(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2469 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2470 2471 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2472 kfree(entry); 2473 return NULL; 2474 } 2475 2476 return entry; 2477 } 2478 2479 /** 2480 * irdma_del_apbvt - delete tcp port from HW apbvt table 2481 * @iwdev: irdma device 2482 * @entry: apbvt entry object 2483 */ 2484 void 2485 irdma_del_apbvt(struct irdma_device *iwdev, 2486 struct irdma_apbvt_entry *entry) 2487 { 2488 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2489 unsigned long flags; 2490 2491 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2492 if (--entry->use_cnt) { 2493 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2494 return; 2495 } 2496 2497 HASH_DEL(cm_core->apbvt_hash_tbl, &entry->hlist); 2498 /* 2499 * apbvt_lock is held across CQP delete APBVT OP (non-waiting) to protect against race where add APBVT CQP can 2500 * race ahead of the delete APBVT for same port. 2501 */ 2502 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2503 kfree(entry); 2504 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2505 } 2506 2507 /** 2508 * irdma_manage_arp_cache - manage hw arp cache 2509 * @rf: RDMA PCI function 2510 * @mac_addr: mac address ptr 2511 * @ip_addr: ip addr for arp cache 2512 * @action: add, delete or modify 2513 */ 2514 void 2515 irdma_manage_arp_cache(struct irdma_pci_f *rf, const unsigned char *mac_addr, 2516 u32 *ip_addr, u32 action) 2517 { 2518 struct irdma_add_arp_cache_entry_info *info; 2519 struct irdma_cqp_request *cqp_request; 2520 struct cqp_cmds_info *cqp_info; 2521 int arp_index; 2522 2523 arp_index = irdma_arp_table(rf, ip_addr, mac_addr, action); 2524 if (arp_index == -1) 2525 return; 2526 2527 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2528 if (!cqp_request) 2529 return; 2530 2531 cqp_info = &cqp_request->info; 2532 if (action == IRDMA_ARP_ADD) { 2533 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2534 info = &cqp_info->in.u.add_arp_cache_entry.info; 2535 memset(info, 0, sizeof(*info)); 2536 info->arp_index = (u16)arp_index; 2537 info->permanent = true; 2538 ether_addr_copy(info->mac_addr, mac_addr); 2539 cqp_info->in.u.add_arp_cache_entry.scratch = 2540 (uintptr_t)cqp_request; 2541 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2542 } else { 2543 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2544 cqp_info->in.u.del_arp_cache_entry.scratch = 2545 (uintptr_t)cqp_request; 2546 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2547 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2548 } 2549 2550 cqp_info->post_sq = 1; 2551 irdma_handle_cqp_op(rf, cqp_request); 2552 irdma_put_cqp_request(&rf->cqp, cqp_request); 2553 } 2554 2555 /** 2556 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2557 * @cqp_request: qhash cqp completion 2558 */ 2559 static void 2560 irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2561 { 2562 struct irdma_cm_node *cm_node = cqp_request->param; 2563 2564 irdma_send_syn(cm_node, 1); 2565 irdma_rem_ref_cm_node(cm_node); 2566 } 2567 2568 /** 2569 * irdma_manage_qhash - add or modify qhash 2570 * @iwdev: irdma device 2571 * @cminfo: cm info for qhash 2572 * @etype: type (syn or quad) 2573 * @mtype: type of qhash 2574 * @cmnode: cmnode associated with connection 2575 * @wait: wait for completion 2576 */ 2577 int 2578 irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2579 enum irdma_quad_entry_type etype, 2580 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2581 bool wait) 2582 { 2583 struct irdma_qhash_table_info *info; 2584 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2585 struct irdma_cqp_request *cqp_request; 2586 struct cqp_cmds_info *cqp_info; 2587 struct irdma_cm_node *cm_node = cmnode; 2588 int status; 2589 2590 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2591 if (!cqp_request) 2592 return -ENOMEM; 2593 2594 cqp_info = &cqp_request->info; 2595 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2596 memset(info, 0, sizeof(*info)); 2597 info->vsi = &iwdev->vsi; 2598 info->manage = mtype; 2599 info->entry_type = etype; 2600 if (cminfo->vlan_id < VLAN_N_VID) { 2601 info->vlan_valid = true; 2602 info->vlan_id = cminfo->vlan_id; 2603 } else { 2604 info->vlan_valid = false; 2605 } 2606 info->ipv4_valid = cminfo->ipv4; 2607 info->user_pri = cminfo->user_pri; 2608 ether_addr_copy(info->mac_addr, if_getlladdr(iwdev->netdev)); 2609 info->qp_num = cminfo->qh_qpid; 2610 info->dest_port = cminfo->loc_port; 2611 info->dest_ip[0] = cminfo->loc_addr[0]; 2612 info->dest_ip[1] = cminfo->loc_addr[1]; 2613 info->dest_ip[2] = cminfo->loc_addr[2]; 2614 info->dest_ip[3] = cminfo->loc_addr[3]; 2615 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2616 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2617 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2618 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2619 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2620 info->src_port = cminfo->rem_port; 2621 info->src_ip[0] = cminfo->rem_addr[0]; 2622 info->src_ip[1] = cminfo->rem_addr[1]; 2623 info->src_ip[2] = cminfo->rem_addr[2]; 2624 info->src_ip[3] = cminfo->rem_addr[3]; 2625 } 2626 if (cmnode) { 2627 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2628 cqp_request->param = cmnode; 2629 if (!wait) 2630 atomic_inc(&cm_node->refcnt); 2631 } 2632 if (info->ipv4_valid) 2633 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_CM, 2634 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2635 (!mtype) ? "DELETE" : "ADD", 2636 __builtin_return_address(0), info->dest_port, 2637 info->src_port, info->dest_ip, info->src_ip, 2638 info->mac_addr, cminfo->vlan_id, 2639 cmnode ? cmnode : NULL); 2640 else 2641 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_CM, 2642 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2643 (!mtype) ? "DELETE" : "ADD", 2644 __builtin_return_address(0), info->dest_port, 2645 info->src_port, info->dest_ip, info->src_ip, 2646 info->mac_addr, cminfo->vlan_id, 2647 cmnode ? cmnode : NULL); 2648 2649 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2650 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2651 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2652 cqp_info->post_sq = 1; 2653 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2654 if (status && cm_node && !wait) 2655 irdma_rem_ref_cm_node(cm_node); 2656 2657 irdma_put_cqp_request(iwcqp, cqp_request); 2658 2659 return status; 2660 } 2661 2662 /** 2663 * irdma_hw_flush_wqes - flush qp's wqe 2664 * @rf: RDMA PCI function 2665 * @qp: hardware control qp 2666 * @info: info for flush 2667 * @wait: flag wait for completion 2668 */ 2669 int 2670 irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2671 struct irdma_qp_flush_info *info, bool wait) 2672 { 2673 int status; 2674 struct irdma_qp_flush_info *hw_info; 2675 struct irdma_cqp_request *cqp_request; 2676 struct cqp_cmds_info *cqp_info; 2677 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2678 2679 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2680 if (!cqp_request) 2681 return -ENOMEM; 2682 2683 cqp_info = &cqp_request->info; 2684 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2685 memcpy(hw_info, info, sizeof(*hw_info)); 2686 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2687 cqp_info->post_sq = 1; 2688 cqp_info->in.u.qp_flush_wqes.qp = qp; 2689 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2690 status = irdma_handle_cqp_op(rf, cqp_request); 2691 if (status) { 2692 qp->qp_uk.sq_flush_complete = true; 2693 qp->qp_uk.rq_flush_complete = true; 2694 irdma_put_cqp_request(&rf->cqp, cqp_request); 2695 return status; 2696 } 2697 2698 if (!wait || cqp_request->compl_info.maj_err_code) 2699 goto put_cqp; 2700 2701 if (info->rq) { 2702 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2703 cqp_request->compl_info.min_err_code == 0) { 2704 /* RQ WQE flush was requested but did not happen */ 2705 qp->qp_uk.rq_flush_complete = true; 2706 } 2707 } 2708 if (info->sq) { 2709 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2710 cqp_request->compl_info.min_err_code == 0) { 2711 /* SQ WQE flush was requested but did not happen */ 2712 qp->qp_uk.sq_flush_complete = true; 2713 } 2714 } 2715 2716 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_VERBS, 2717 "qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2718 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2719 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2720 cqp_request->compl_info.maj_err_code, cqp_request->compl_info.min_err_code); 2721 put_cqp: 2722 irdma_put_cqp_request(&rf->cqp, cqp_request); 2723 2724 return status; 2725 } 2726 2727 /** 2728 * irdma_gen_ae - generate AE 2729 * @rf: RDMA PCI function 2730 * @qp: qp associated with AE 2731 * @info: info for ae 2732 * @wait: wait for completion 2733 */ 2734 void 2735 irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2736 struct irdma_gen_ae_info *info, bool wait) 2737 { 2738 struct irdma_gen_ae_info *ae_info; 2739 struct irdma_cqp_request *cqp_request; 2740 struct cqp_cmds_info *cqp_info; 2741 2742 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2743 if (!cqp_request) 2744 return; 2745 2746 cqp_info = &cqp_request->info; 2747 ae_info = &cqp_request->info.in.u.gen_ae.info; 2748 memcpy(ae_info, info, sizeof(*ae_info)); 2749 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2750 cqp_info->post_sq = 1; 2751 cqp_info->in.u.gen_ae.qp = qp; 2752 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2753 2754 irdma_handle_cqp_op(rf, cqp_request); 2755 irdma_put_cqp_request(&rf->cqp, cqp_request); 2756 } 2757 2758 void 2759 irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2760 { 2761 struct irdma_qp_flush_info info = {0}; 2762 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2763 u8 flush_code = iwqp->sc_qp.flush_code; 2764 2765 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2766 return; 2767 2768 /* Set flush info fields */ 2769 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2770 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2771 2772 /* Generate userflush errors in CQE */ 2773 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2774 info.sq_minor_code = FLUSH_GENERAL_ERR; 2775 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2776 info.rq_minor_code = FLUSH_GENERAL_ERR; 2777 info.userflushcode = true; 2778 2779 if (flush_mask & IRDMA_REFLUSH) { 2780 if (info.sq) 2781 iwqp->sc_qp.flush_sq = false; 2782 if (info.rq) 2783 iwqp->sc_qp.flush_rq = false; 2784 } else { 2785 if (flush_code) { 2786 if (info.sq && iwqp->sc_qp.sq_flush_code) 2787 info.sq_minor_code = flush_code; 2788 if (info.rq && iwqp->sc_qp.rq_flush_code) 2789 info.rq_minor_code = flush_code; 2790 } 2791 if (irdma_upload_context && irdma_upload_qp_context(iwqp, 0, 1)) 2792 irdma_dev_warn(&iwqp->iwdev->ibdev, "failed to upload QP context\n"); 2793 if (!iwqp->user_mode) 2794 irdma_sched_qp_flush_work(iwqp); 2795 } 2796 2797 /* Issue flush */ 2798 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2799 flush_mask & IRDMA_FLUSH_WAIT); 2800 iwqp->flush_issued = true; 2801 } 2802