1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef __MLX5_CORE_H__ 27 #define __MLX5_CORE_H__ 28 29 #include <linux/types.h> 30 #include <linux/kernel.h> 31 #include <linux/sched.h> 32 33 #include <dev/mlxfw/mlxfw.h> 34 35 #define DRIVER_NAME "mlx5_core" 36 #ifndef DRIVER_VERSION 37 #define DRIVER_VERSION "3.7.1" 38 #endif 39 #define DRIVER_RELDATE "November 2021" 40 41 extern int mlx5_core_debug_mask; 42 43 #define mlx5_core_dbg(dev, format, ...) \ 44 pr_debug("%s:%s:%d:(pid %d): " format, \ 45 (dev)->priv.name, __func__, __LINE__, curthread->td_proc->p_pid, \ 46 ##__VA_ARGS__) 47 48 #define mlx5_core_dbg_mask(dev, mask, format, ...) \ 49 do { \ 50 if ((mask) & mlx5_core_debug_mask) \ 51 mlx5_core_dbg(dev, format, ##__VA_ARGS__); \ 52 } while (0) 53 54 #define mlx5_core_err(_dev, format, ...) \ 55 device_printf((_dev)->pdev->dev.bsddev, "ERR: ""%s:%d:(pid %d): " format, \ 56 __func__, __LINE__, curthread->td_proc->p_pid, \ 57 ##__VA_ARGS__) 58 59 #define mlx5_core_warn(_dev, format, ...) \ 60 device_printf((_dev)->pdev->dev.bsddev, "WARN: ""%s:%d:(pid %d): " format, \ 61 __func__, __LINE__, curthread->td_proc->p_pid, \ 62 ##__VA_ARGS__) 63 64 #define mlx5_core_info(_dev, format, ...) \ 65 device_printf((_dev)->pdev->dev.bsddev, "INFO: ""%s:%d:(pid %d): " format, \ 66 __func__, __LINE__, curthread->td_proc->p_pid, \ 67 ##__VA_ARGS__) 68 69 enum { 70 MLX5_CMD_DATA, /* print command payload only */ 71 MLX5_CMD_TIME, /* print command execution time */ 72 }; 73 74 enum mlx5_semaphore_space_address { 75 MLX5_SEMAPHORE_SW_RESET = 0x20, 76 }; 77 78 struct mlx5_core_dev; 79 80 enum mlx5_pddr_page_select { 81 MLX5_PDDR_OPERATIONAL_INFO_PAGE = 0x0, 82 MLX5_PDDR_TROUBLESHOOTING_INFO_PAGE = 0x1, 83 MLX5_PDDR_MODULE_INFO_PAGE = 0x3, 84 }; 85 86 enum mlx5_pddr_monitor_opcodes { 87 MLX5_LINK_NO_ISSUE_OBSERVED = 0x0, 88 MLX5_LINK_PORT_CLOSED = 0x1, 89 MLX5_LINK_AN_FAILURE = 0x2, 90 MLX5_LINK_TRAINING_FAILURE = 0x5, 91 MLX5_LINK_LOGICAL_MISMATCH = 0x9, 92 MLX5_LINK_REMOTE_FAULT_INDICATION = 0xe, 93 MLX5_LINK_BAD_SIGNAL_INTEGRITY = 0xf, 94 MLX5_LINK_CABLE_COMPLIANCE_CODE_MISMATCH = 0x10, 95 MLX5_LINK_INTERNAL_ERR = 0x17, 96 MLX5_LINK_INFO_NOT_AVAIL = 0x3ff, 97 MLX5_LINK_CABLE_UNPLUGGED = 0x400, 98 MLX5_LINK_LONG_RANGE_FOR_NON_MLX_CABLE = 0x401, 99 MLX5_LINK_BUS_STUCK = 0x402, 100 MLX5_LINK_UNSUPP_EEPROM = 0x403, 101 MLX5_LINK_PART_NUM_LIST = 0x404, 102 MLX5_LINK_UNSUPP_CABLE = 0x405, 103 MLX5_LINK_MODULE_TEMP_SHUTDOWN = 0x406, 104 MLX5_LINK_SHORTED_CABLE = 0x407, 105 MLX5_LINK_POWER_BUDGET_EXCEEDED = 0x408, 106 MLX5_LINK_MNG_FORCED_DOWN = 0x409, 107 }; 108 109 int mlx5_query_hca_caps(struct mlx5_core_dev *dev); 110 int mlx5_query_board_id(struct mlx5_core_dev *dev); 111 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 112 u8 feature_group, u8 access_reg_group); 113 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, 114 u8 feature_group, u8 access_reg_group); 115 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, 116 u8 feature_group, u8 access_reg_group); 117 int mlx5_query_mfrl_reg(struct mlx5_core_dev *mdev, u8 *reset_level); 118 int mlx5_set_mfrl_reg(struct mlx5_core_dev *mdev, u8 reset_level); 119 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev); 120 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); 121 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); 122 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev); 123 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 124 unsigned long param); 125 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force); 126 void mlx5_disable_device(struct mlx5_core_dev *dev); 127 void mlx5_recover_device(struct mlx5_core_dev *dev); 128 int mlx5_query_pddr_troubleshooting_info(struct mlx5_core_dev *mdev, 129 u16 *monitor_opcode, 130 u8 *status_message, size_t sm_len); 131 132 int mlx5_register_device(struct mlx5_core_dev *dev); 133 void mlx5_unregister_device(struct mlx5_core_dev *dev); 134 135 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw); 136 137 void mlx5e_init(void); 138 void mlx5e_cleanup(void); 139 140 int mlx5_ctl_init(void); 141 void mlx5_ctl_fini(void); 142 void mlx5_fwdump_prep(struct mlx5_core_dev *mdev); 143 int mlx5_fwdump(struct mlx5_core_dev *mdev); 144 void mlx5_fwdump_clean(struct mlx5_core_dev *mdev); 145 146 struct mlx5_crspace_regmap { 147 uint32_t addr; 148 unsigned cnt; 149 }; 150 151 extern struct pci_driver mlx5_core_driver; 152 153 SYSCTL_DECL(_hw_mlx5); 154 155 enum { 156 MLX5_NIC_IFC_FULL = 0, 157 MLX5_NIC_IFC_DISABLED = 1, 158 MLX5_NIC_IFC_NO_DRAM_NIC = 2, 159 MLX5_NIC_IFC_INVALID = 3, 160 MLX5_NIC_IFC_SW_RESET = 7, 161 }; 162 163 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev); 164 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state); 165 166 #endif /* __MLX5_CORE_H__ */ 167