1 /*-
2 * Copyright (C) 2018 Cavium Inc.
3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
4 * Copyright (c) 2014 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * This software was developed by Semihalf under
8 * the sponsorship of the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /* Generic ECAM PCIe driver */
33
34 #include <sys/cdefs.h>
35 #include "opt_platform.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/rman.h>
42 #include <sys/module.h>
43 #include <sys/bus.h>
44 #include <sys/endian.h>
45 #include <sys/cpuset.h>
46 #include <sys/rwlock.h>
47
48 #include <contrib/dev/acpica/include/acpi.h>
49 #include <contrib/dev/acpica/include/accommon.h>
50
51 #include <dev/acpica/acpivar.h>
52 #include <dev/acpica/acpi_pcibvar.h>
53
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcib_private.h>
57 #include <dev/pci/pci_host_generic.h>
58 #include <dev/pci/pci_host_generic_acpi.h>
59
60 #include <machine/cpu.h>
61 #include <machine/bus.h>
62 #include <machine/intr.h>
63
64 #include "pcib_if.h"
65 #include "acpi_bus_if.h"
66
67 /* Assembling ECAM Configuration Address */
68 #define PCIE_BUS_SHIFT 20
69 #define PCIE_SLOT_SHIFT 15
70 #define PCIE_FUNC_SHIFT 12
71 #define PCIE_BUS_MASK 0xFF
72 #define PCIE_SLOT_MASK 0x1F
73 #define PCIE_FUNC_MASK 0x07
74 #define PCIE_REG_MASK 0xFFF
75
76 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
77 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
78 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
79 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
80 ((reg) & PCIE_REG_MASK))
81
82 #define PCI_IO_WINDOW_OFFSET 0x1000
83
84 #define SPACE_CODE_SHIFT 24
85 #define SPACE_CODE_MASK 0x3
86 #define SPACE_CODE_IO_SPACE 0x1
87 #define PROPS_CELL_SIZE 1
88 #define PCI_ADDR_CELL_SIZE 2
89
90 static struct {
91 char oem_id[ACPI_OEM_ID_SIZE + 1];
92 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
93 uint32_t quirks;
94 } pci_acpi_quirks[] = {
95 { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
96 { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK },
97 { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK },
98 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK },
99 { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
100 { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK },
101 { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK },
102 { 0 },
103 };
104
105 /* Forward prototypes */
106
107 static int generic_pcie_acpi_probe(device_t dev);
108 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
109 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
110
111 /*
112 * generic_pcie_acpi_probe - look for root bridge flag
113 */
114 static int
generic_pcie_acpi_probe(device_t dev)115 generic_pcie_acpi_probe(device_t dev)
116 {
117 ACPI_DEVICE_INFO *devinfo;
118 ACPI_HANDLE h;
119 int root;
120
121 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
122 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
123 return (ENXIO);
124 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
125 AcpiOsFree(devinfo);
126 if (!root)
127 return (ENXIO);
128
129 device_set_desc(dev, "Generic PCI host controller");
130 return (BUS_PROBE_GENERIC);
131 }
132
133 /*
134 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
135 * 'produced' by this bridge
136 */
137 static ACPI_STATUS
pci_host_generic_acpi_parse_resource(ACPI_RESOURCE * res,void * arg)138 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
139 {
140 device_t dev = (device_t)arg;
141 struct generic_pcie_acpi_softc *sc;
142 rman_res_t min, max, off;
143 int r, restype;
144
145 sc = device_get_softc(dev);
146 r = sc->base.nranges;
147 switch (res->Type) {
148 case ACPI_RESOURCE_TYPE_ADDRESS16:
149 restype = res->Data.Address16.ResourceType;
150 min = res->Data.Address16.Address.Minimum;
151 max = res->Data.Address16.Address.Maximum;
152 break;
153 case ACPI_RESOURCE_TYPE_ADDRESS32:
154 restype = res->Data.Address32.ResourceType;
155 min = res->Data.Address32.Address.Minimum;
156 max = res->Data.Address32.Address.Maximum;
157 off = res->Data.Address32.Address.TranslationOffset;
158 break;
159 case ACPI_RESOURCE_TYPE_ADDRESS64:
160 restype = res->Data.Address64.ResourceType;
161 min = res->Data.Address64.Address.Minimum;
162 max = res->Data.Address64.Address.Maximum;
163 off = res->Data.Address64.Address.TranslationOffset;
164 break;
165 case ACPI_RESOURCE_TYPE_FIXED_MEMORY32:
166 /*
167 * The Microsoft Dev Kit 2023 uses a fixed memory region
168 * for some PCI controllers. For this memory the
169 * ResourceType is ACPI_IO_RANGE meaning we create an IO
170 * resource. As drivers expect it to be a memory resource
171 * force the type here.
172 */
173 restype = ACPI_MEMORY_RANGE;
174 min = res->Data.FixedMemory32.Address;
175 max = res->Data.FixedMemory32.Address +
176 res->Data.FixedMemory32.AddressLength - 1;
177 off = 0;
178 break;
179 default:
180 return (AE_OK);
181 }
182
183 /* Save detected ranges */
184 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
185 res->Data.Address.ResourceType == ACPI_IO_RANGE) {
186 sc->base.ranges[r].pci_base = min;
187 sc->base.ranges[r].phys_base = min + off;
188 sc->base.ranges[r].size = max - min + 1;
189 if (restype == ACPI_MEMORY_RANGE)
190 sc->base.ranges[r].flags |= FLAG_TYPE_MEM;
191 else if (restype == ACPI_IO_RANGE)
192 sc->base.ranges[r].flags |= FLAG_TYPE_IO;
193 sc->base.nranges++;
194 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
195 sc->base.bus_start = min;
196 sc->base.bus_end = max;
197 }
198 return (AE_OK);
199 }
200
201 static void
pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc * sc,ACPI_TABLE_HEADER * hdr)202 pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc,
203 ACPI_TABLE_HEADER *hdr)
204 {
205 int i;
206
207 for (i = 0; pci_acpi_quirks[i].quirks; i++) {
208 if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id,
209 ACPI_OEM_ID_SIZE) != 0)
210 continue;
211 if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id,
212 ACPI_OEM_TABLE_ID_SIZE) != 0)
213 continue;
214 sc->base.quirks |= pci_acpi_quirks[i].quirks;
215 }
216 }
217
218 static int
pci_host_acpi_get_ecam_resource(device_t dev)219 pci_host_acpi_get_ecam_resource(device_t dev)
220 {
221 struct generic_pcie_acpi_softc *sc;
222 struct acpi_device *ad;
223 struct resource_list *rl;
224 ACPI_TABLE_HEADER *hdr;
225 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
226 ACPI_HANDLE handle;
227 ACPI_STATUS status;
228 rman_res_t base, start, end;
229 int found, val;
230
231 sc = device_get_softc(dev);
232 handle = acpi_get_handle(dev);
233
234 /* Try MCFG first */
235 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
236 if (ACPI_SUCCESS(status)) {
237 found = FALSE;
238 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
239 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
240 while (mcfg_entry < mcfg_end && !found) {
241 if (mcfg_entry->PciSegment == sc->base.ecam &&
242 mcfg_entry->StartBusNumber <= sc->base.bus_start &&
243 mcfg_entry->EndBusNumber >= sc->base.bus_start)
244 found = TRUE;
245 else
246 mcfg_entry++;
247 }
248 if (found) {
249 if (mcfg_entry->EndBusNumber < sc->base.bus_end)
250 sc->base.bus_end = mcfg_entry->EndBusNumber;
251 base = mcfg_entry->Address;
252 } else {
253 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
254 sc->base.bus_start, sc->base.bus_end);
255 return (ENXIO);
256 }
257 pci_host_acpi_get_oem_quirks(sc, hdr);
258 if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK)
259 device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
260 } else {
261 status = acpi_GetInteger(handle, "_CBA", &val);
262 if (ACPI_SUCCESS(status))
263 base = val;
264 else
265 return (ENXIO);
266 }
267
268 /* add as MEM rid 0 */
269 ad = device_get_ivars(dev);
270 rl = &ad->ad_rl;
271 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
272 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
273 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
274 if (bootverbose)
275 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
276 sc->base.bus_start, sc->base.bus_end, start, end);
277 return (0);
278 }
279
280 int
pci_host_generic_acpi_init(device_t dev)281 pci_host_generic_acpi_init(device_t dev)
282 {
283 struct generic_pcie_acpi_softc *sc;
284 ACPI_HANDLE handle;
285 ACPI_STATUS status;
286 int error;
287
288 sc = device_get_softc(dev);
289 handle = acpi_get_handle(dev);
290
291 /* Get Start bus number for the PCI host bus is from _BBN method */
292 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
293 if (ACPI_FAILURE(status)) {
294 device_printf(dev, "No _BBN, using start bus 0\n");
295 sc->base.bus_start = 0;
296 }
297 sc->base.bus_end = 255;
298
299 /* Get PCI Segment (domain) needed for MCFG lookup */
300 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
301 if (ACPI_FAILURE(status)) {
302 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
303 sc->base.ecam = 0;
304 }
305
306 /* Bus decode ranges */
307 status = AcpiWalkResources(handle, "_CRS",
308 pci_host_generic_acpi_parse_resource, (void *)dev);
309 if (ACPI_FAILURE(status))
310 return (ENXIO);
311
312 /* Coherency attribute */
313 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
314 sc->base.coherent = 0;
315 if (bootverbose)
316 device_printf(dev, "Bus is%s cache-coherent\n",
317 sc->base.coherent ? "" : " not");
318
319 /* add config space resource */
320 pci_host_acpi_get_ecam_resource(dev);
321 acpi_pcib_fetch_prt(dev, &sc->ap_prt);
322
323 error = pci_host_generic_core_attach(dev);
324 if (error != 0)
325 return (error);
326
327 return (0);
328 }
329
330 static int
pci_host_generic_acpi_attach(device_t dev)331 pci_host_generic_acpi_attach(device_t dev)
332 {
333 int error;
334
335 error = pci_host_generic_acpi_init(dev);
336 if (error != 0)
337 return (error);
338
339 device_add_child(dev, "pci", -1);
340 return (bus_generic_attach(dev));
341 }
342
343 static int
generic_pcie_acpi_read_ivar(device_t dev,device_t child,int index,uintptr_t * result)344 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
345 uintptr_t *result)
346 {
347 struct generic_pcie_acpi_softc *sc;
348
349 sc = device_get_softc(dev);
350
351 if (index == PCIB_IVAR_BUS) {
352 *result = sc->base.bus_start;
353 return (0);
354 }
355
356 if (index == PCIB_IVAR_DOMAIN) {
357 *result = sc->base.ecam;
358 return (0);
359 }
360
361 if (bootverbose)
362 device_printf(dev, "ERROR: Unknown index %d.\n", index);
363 return (ENOENT);
364 }
365
366 static int
generic_pcie_acpi_route_interrupt(device_t bus,device_t dev,int pin)367 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
368 {
369 struct generic_pcie_acpi_softc *sc;
370
371 sc = device_get_softc(bus);
372 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
373 }
374
375 static u_int
generic_pcie_get_xref(device_t pci,device_t child)376 generic_pcie_get_xref(device_t pci, device_t child)
377 {
378 struct generic_pcie_acpi_softc *sc;
379 uintptr_t rid;
380 u_int xref, devid;
381 int err;
382
383 sc = device_get_softc(pci);
384 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
385 if (err != 0)
386 return (ACPI_MSI_XREF);
387 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
388 if (err != 0)
389 return (ACPI_MSI_XREF);
390 return (xref);
391 }
392
393 static u_int
generic_pcie_map_id(device_t pci,device_t child,uintptr_t * id)394 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
395 {
396 struct generic_pcie_acpi_softc *sc;
397 uintptr_t rid;
398 u_int xref, devid;
399 int err;
400
401 sc = device_get_softc(pci);
402 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
403 if (err != 0)
404 return (err);
405 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
406 if (err == 0)
407 *id = devid;
408 else
409 *id = rid; /* RID not in IORT, likely FW bug, ignore */
410 return (0);
411 }
412
413 static int
generic_pcie_get_iommu(device_t pci,device_t child,uintptr_t * id)414 generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id)
415 {
416 struct generic_pcie_acpi_softc *sc;
417 struct pci_id_ofw_iommu *iommu;
418 u_int iommu_sid, iommu_xref;
419 uintptr_t rid;
420 int err;
421
422 iommu = (struct pci_id_ofw_iommu *)id;
423
424 sc = device_get_softc(pci);
425 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
426 if (err != 0)
427 return (err);
428 err = acpi_iort_map_pci_smmuv3(sc->base.ecam, rid, &iommu_xref,
429 &iommu_sid);
430 if (err == 0) {
431 iommu->id = iommu_sid;
432 iommu->xref = iommu_xref;
433 }
434
435 return (err);
436 }
437
438 static int
generic_pcie_acpi_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)439 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
440 int maxcount, int *irqs)
441 {
442
443 #if defined(INTRNG)
444 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
445 count, maxcount, irqs));
446 #else
447 return (ENXIO);
448 #endif
449 }
450
451 static int
generic_pcie_acpi_release_msi(device_t pci,device_t child,int count,int * irqs)452 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
453 int *irqs)
454 {
455
456 #if defined(INTRNG)
457 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
458 count, irqs));
459 #else
460 return (ENXIO);
461 #endif
462 }
463
464 static int
generic_pcie_acpi_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)465 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
466 uint32_t *data)
467 {
468
469 #if defined(INTRNG)
470 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
471 addr, data));
472 #else
473 return (ENXIO);
474 #endif
475 }
476
477 static int
generic_pcie_acpi_alloc_msix(device_t pci,device_t child,int * irq)478 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
479 {
480
481 #if defined(INTRNG)
482 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
483 irq));
484 #else
485 return (ENXIO);
486 #endif
487 }
488
489 static int
generic_pcie_acpi_release_msix(device_t pci,device_t child,int irq)490 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
491 {
492
493 #if defined(INTRNG)
494 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
495 irq));
496 #else
497 return (ENXIO);
498 #endif
499 }
500
501 static int
generic_pcie_acpi_get_id(device_t pci,device_t child,enum pci_id_type type,uintptr_t * id)502 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
503 uintptr_t *id)
504 {
505 if (type == PCI_ID_OFW_IOMMU)
506 return (generic_pcie_get_iommu(pci, child, id));
507
508 if (type == PCI_ID_MSI)
509 return (generic_pcie_map_id(pci, child, id));
510
511 return (pcib_get_id(pci, child, type, id));
512 }
513
514 static device_method_t generic_pcie_acpi_methods[] = {
515 DEVMETHOD(device_probe, generic_pcie_acpi_probe),
516 DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
517 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
518
519 /* pcib interface */
520 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
521 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
522 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
523 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
524 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
525 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
526 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
527
528 DEVMETHOD_END
529 };
530
531 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
532 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
533
534 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, 0, 0);
535