1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Thomas Skibo 5 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* Generic driver to attach sdhci controllers on simplebus. 30 * Derived mainly from sdhci_pci.c 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/ofw/ofw_subr.h> 56 #include <dev/extres/clk/clk.h> 57 #include <dev/extres/clk/clk_fixed.h> 58 #include <dev/extres/syscon/syscon.h> 59 #include <dev/extres/phy/phy.h> 60 61 #include <dev/mmc/bridge.h> 62 63 #include <dev/sdhci/sdhci.h> 64 65 #include "mmcbr_if.h" 66 #include "sdhci_if.h" 67 68 #include "opt_mmccam.h" 69 70 #include "clkdev_if.h" 71 #include "syscon_if.h" 72 73 #define MAX_SLOTS 6 74 #define SDHCI_FDT_ARMADA38X 1 75 #define SDHCI_FDT_GENERIC 2 76 #define SDHCI_FDT_XLNX_ZY7 3 77 #define SDHCI_FDT_QUALCOMM 4 78 #define SDHCI_FDT_RK3399 5 79 80 #define RK3399_GRF_EMMCCORE_CON0 0xf000 81 #define RK3399_CORECFG_BASECLKFREQ 0xff00 82 #define RK3399_CORECFG_TIMEOUTCLKUNIT (1 << 7) 83 #define RK3399_CORECFG_TUNINGCOUNT 0x3f 84 #define RK3399_GRF_EMMCCORE_CON11 0xf02c 85 #define RK3399_CORECFG_CLOCKMULTIPLIER 0xff 86 87 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) 88 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) 89 90 #define EMMCCARDCLK_ID 1000 91 92 static struct ofw_compat_data compat_data[] = { 93 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, 94 { "sdhci_generic", SDHCI_FDT_GENERIC }, 95 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM }, 96 { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 }, 97 { "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 }, 98 { NULL, 0 } 99 }; 100 101 struct sdhci_fdt_softc { 102 device_t dev; /* Controller device */ 103 u_int quirks; /* Chip specific quirks */ 104 u_int caps; /* If we override SDHCI_CAPABILITIES */ 105 uint32_t max_clk; /* Max possible freq */ 106 uint8_t sdma_boundary; /* If we override the SDMA boundary */ 107 struct resource *irq_res; /* IRQ resource */ 108 void *intrhand; /* Interrupt handle */ 109 110 int num_slots; /* Number of slots on this controller*/ 111 struct sdhci_slot slots[MAX_SLOTS]; 112 struct resource *mem_res[MAX_SLOTS]; /* Memory resource */ 113 114 bool wp_inverted; /* WP pin is inverted */ 115 bool no_18v; /* No 1.8V support */ 116 117 clk_t clk_xin; /* xin24m fixed clock */ 118 clk_t clk_ahb; /* ahb clock */ 119 phy_t phy; /* phy to be used */ 120 }; 121 122 struct rk3399_emmccardclk_sc { 123 device_t clkdev; 124 bus_addr_t reg; 125 }; 126 127 static int 128 rk3399_emmccardclk_init(struct clknode *clk, device_t dev) 129 { 130 131 clknode_init_parent_idx(clk, 0); 132 return (0); 133 } 134 135 static clknode_method_t rk3399_emmccardclk_clknode_methods[] = { 136 /* Device interface */ 137 CLKNODEMETHOD(clknode_init, rk3399_emmccardclk_init), 138 CLKNODEMETHOD_END 139 }; 140 DEFINE_CLASS_1(rk3399_emmccardclk_clknode, rk3399_emmccardclk_clknode_class, 141 rk3399_emmccardclk_clknode_methods, sizeof(struct rk3399_emmccardclk_sc), 142 clknode_class); 143 144 static int 145 rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells, 146 phandle_t *cells, struct clknode **clk) 147 { 148 149 if (ncells == 0) 150 *clk = clknode_find_by_id(clkdom, EMMCCARDCLK_ID); 151 else 152 return (ERANGE); 153 154 if (*clk == NULL) 155 return (ENXIO); 156 return (0); 157 } 158 159 static void 160 sdhci_init_rk3399_emmccardclk(device_t dev) 161 { 162 struct clknode_init_def def; 163 struct rk3399_emmccardclk_sc *sc; 164 struct clkdom *clkdom; 165 struct clknode *clk; 166 clk_t clk_parent; 167 bus_addr_t paddr; 168 bus_size_t psize; 169 const char **clknames; 170 phandle_t node; 171 int i, nclocks, ncells, error; 172 173 node = ofw_bus_get_node(dev); 174 175 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 176 device_printf(dev, "cannot parse 'reg' property\n"); 177 return; 178 } 179 180 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 181 "#clock-cells", &ncells); 182 if (error != 0 || ncells != 2) { 183 device_printf(dev, "couldn't find parent clocks\n"); 184 return; 185 } 186 187 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", 188 &clknames); 189 /* No clocks to export */ 190 if (nclocks <= 0) 191 return; 192 193 if (nclocks != 1) { 194 device_printf(dev, "Having %d clock instead of 1, aborting\n", 195 nclocks); 196 return; 197 } 198 199 clkdom = clkdom_create(dev); 200 clkdom_set_ofw_mapper(clkdom, rk3399_ofw_map); 201 202 memset(&def, 0, sizeof(def)); 203 def.id = EMMCCARDCLK_ID; 204 def.name = clknames[0]; 205 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); 206 for (i = 0; i < ncells; i++) { 207 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); 208 if (error != 0) { 209 device_printf(dev, "cannot get clock %d\n", error); 210 return; 211 } 212 def.parent_names[i] = clk_get_name(clk_parent); 213 if (bootverbose) 214 device_printf(dev, "clk parent: %s\n", 215 def.parent_names[i]); 216 clk_release(clk_parent); 217 } 218 def.parent_cnt = ncells; 219 220 clk = clknode_create(clkdom, &rk3399_emmccardclk_clknode_class, &def); 221 if (clk == NULL) { 222 device_printf(dev, "cannot create clknode\n"); 223 return; 224 } 225 226 sc = clknode_get_softc(clk); 227 sc->reg = paddr; 228 sc->clkdev = device_get_parent(dev); 229 230 clknode_register(clkdom, clk); 231 232 if (clkdom_finit(clkdom) != 0) { 233 device_printf(dev, "cannot finalize clkdom initialization\n"); 234 return; 235 } 236 237 if (bootverbose) 238 clkdom_dump(clkdom); 239 } 240 241 static int 242 sdhci_init_rk3399(device_t dev) 243 { 244 struct sdhci_fdt_softc *sc = device_get_softc(dev); 245 struct syscon *grf = NULL; 246 phandle_t node; 247 uint64_t freq; 248 uint32_t mask, val; 249 int error; 250 251 /* Get and activate clocks */ 252 error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin); 253 if (error != 0) { 254 device_printf(dev, "cannot get xin clock\n"); 255 return (ENXIO); 256 } 257 error = clk_enable(sc->clk_xin); 258 if (error != 0) { 259 device_printf(dev, "cannot enable xin clock\n"); 260 return (ENXIO); 261 } 262 error = clk_get_freq(sc->clk_xin, &freq); 263 if (error != 0) { 264 device_printf(dev, "cannot get xin clock frequency\n"); 265 return (ENXIO); 266 } 267 error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb); 268 if (error != 0) { 269 device_printf(dev, "cannot get ahb clock\n"); 270 return (ENXIO); 271 } 272 error = clk_enable(sc->clk_ahb); 273 if (error != 0) { 274 device_printf(dev, "cannot enable ahb clock\n"); 275 return (ENXIO); 276 } 277 278 /* Register clock */ 279 sdhci_init_rk3399_emmccardclk(dev); 280 281 /* Enable PHY */ 282 error = phy_get_by_ofw_name(dev, 0, "phy_arasan", &sc->phy); 283 if (error != 0) { 284 device_printf(dev, "Could not get phy\n"); 285 return (ENXIO); 286 } 287 error = phy_enable(sc->phy); 288 if (error != 0) { 289 device_printf(dev, "Could not enable phy\n"); 290 return (ENXIO); 291 } 292 /* Get syscon */ 293 node = ofw_bus_get_node(dev); 294 if (OF_hasprop(node, "arasan,soc-ctl-syscon") && 295 syscon_get_by_ofw_property(dev, node, 296 "arasan,soc-ctl-syscon", &grf) != 0) { 297 device_printf(dev, "cannot get grf driver handle\n"); 298 return (ENXIO); 299 } 300 301 /* Disable clock multiplier */ 302 mask = RK3399_CORECFG_CLOCKMULTIPLIER; 303 val = 0; 304 SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val); 305 306 /* Set base clock frequency */ 307 mask = RK3399_CORECFG_BASECLKFREQ; 308 val = SHIFTIN((freq + (1000000 / 2)) / 1000000, 309 RK3399_CORECFG_BASECLKFREQ); 310 SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val); 311 312 return (0); 313 } 314 315 static uint8_t 316 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 317 { 318 struct sdhci_fdt_softc *sc = device_get_softc(dev); 319 320 return (bus_read_1(sc->mem_res[slot->num], off)); 321 } 322 323 static void 324 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 325 uint8_t val) 326 { 327 struct sdhci_fdt_softc *sc = device_get_softc(dev); 328 329 bus_write_1(sc->mem_res[slot->num], off, val); 330 } 331 332 static uint16_t 333 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 334 { 335 struct sdhci_fdt_softc *sc = device_get_softc(dev); 336 337 return (bus_read_2(sc->mem_res[slot->num], off)); 338 } 339 340 static void 341 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 342 uint16_t val) 343 { 344 struct sdhci_fdt_softc *sc = device_get_softc(dev); 345 346 bus_write_2(sc->mem_res[slot->num], off, val); 347 } 348 349 static uint32_t 350 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 351 { 352 struct sdhci_fdt_softc *sc = device_get_softc(dev); 353 uint32_t val32; 354 355 val32 = bus_read_4(sc->mem_res[slot->num], off); 356 if (off == SDHCI_CAPABILITIES && sc->no_18v) 357 val32 &= ~SDHCI_CAN_VDD_180; 358 359 return (val32); 360 } 361 362 static void 363 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 364 uint32_t val) 365 { 366 struct sdhci_fdt_softc *sc = device_get_softc(dev); 367 368 bus_write_4(sc->mem_res[slot->num], off, val); 369 } 370 371 static void 372 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 373 bus_size_t off, uint32_t *data, bus_size_t count) 374 { 375 struct sdhci_fdt_softc *sc = device_get_softc(dev); 376 377 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 378 } 379 380 static void 381 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 382 bus_size_t off, uint32_t *data, bus_size_t count) 383 { 384 struct sdhci_fdt_softc *sc = device_get_softc(dev); 385 386 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 387 } 388 389 static void 390 sdhci_fdt_intr(void *arg) 391 { 392 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 393 int i; 394 395 for (i = 0; i < sc->num_slots; i++) 396 sdhci_generic_intr(&sc->slots[i]); 397 } 398 399 static int 400 sdhci_fdt_get_ro(device_t bus, device_t dev) 401 { 402 struct sdhci_fdt_softc *sc = device_get_softc(bus); 403 404 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 405 } 406 407 static int 408 sdhci_fdt_probe(device_t dev) 409 { 410 struct sdhci_fdt_softc *sc = device_get_softc(dev); 411 phandle_t node; 412 pcell_t cid; 413 414 sc->quirks = 0; 415 sc->num_slots = 1; 416 sc->max_clk = 0; 417 418 if (!ofw_bus_status_okay(dev)) 419 return (ENXIO); 420 421 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 422 case SDHCI_FDT_ARMADA38X: 423 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; 424 device_set_desc(dev, "ARMADA38X SDHCI controller"); 425 break; 426 case SDHCI_FDT_GENERIC: 427 device_set_desc(dev, "generic fdt SDHCI controller"); 428 break; 429 case SDHCI_FDT_QUALCOMM: 430 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 431 SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY; 432 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 433 device_set_desc(dev, "Qualcomm FDT SDHCI controller"); 434 break; 435 case SDHCI_FDT_RK3399: 436 device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller"); 437 break; 438 case SDHCI_FDT_XLNX_ZY7: 439 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 440 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 441 break; 442 default: 443 return (ENXIO); 444 } 445 446 node = ofw_bus_get_node(dev); 447 448 /* Allow dts to patch quirks, slots, and max-frequency. */ 449 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 450 sc->quirks = cid; 451 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) 452 sc->num_slots = cid; 453 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 454 sc->max_clk = cid; 455 if (OF_hasprop(node, "no-1-8-v")) 456 sc->no_18v = true; 457 if (OF_hasprop(node, "wp-inverted")) 458 sc->wp_inverted = true; 459 460 return (0); 461 } 462 463 static int 464 sdhci_fdt_attach(device_t dev) 465 { 466 struct sdhci_fdt_softc *sc = device_get_softc(dev); 467 struct sdhci_slot *slot; 468 int err, slots, rid, i; 469 470 sc->dev = dev; 471 472 /* Allocate IRQ. */ 473 rid = 0; 474 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 475 RF_ACTIVE); 476 if (sc->irq_res == NULL) { 477 device_printf(dev, "Can't allocate IRQ\n"); 478 return (ENOMEM); 479 } 480 481 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 482 SDHCI_FDT_RK3399) { 483 /* Initialize SDHCI */ 484 err = sdhci_init_rk3399(dev); 485 if (err != 0) { 486 device_printf(dev, "Cannot init RK3399 SDHCI\n"); 487 return (err); 488 } 489 } 490 491 /* Scan all slots. */ 492 slots = sc->num_slots; /* number of slots determined in probe(). */ 493 sc->num_slots = 0; 494 for (i = 0; i < slots; i++) { 495 slot = &sc->slots[sc->num_slots]; 496 497 /* Allocate memory. */ 498 rid = 0; 499 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 500 &rid, RF_ACTIVE); 501 if (sc->mem_res[i] == NULL) { 502 device_printf(dev, 503 "Can't allocate memory for slot %d\n", i); 504 continue; 505 } 506 507 slot->quirks = sc->quirks; 508 slot->caps = sc->caps; 509 slot->max_clk = sc->max_clk; 510 slot->sdma_boundary = sc->sdma_boundary; 511 512 if (sdhci_init_slot(dev, slot, i) != 0) 513 continue; 514 515 sc->num_slots++; 516 } 517 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 518 519 /* Activate the interrupt */ 520 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 521 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 522 if (err) { 523 device_printf(dev, "Cannot setup IRQ\n"); 524 return (err); 525 } 526 527 /* Process cards detection. */ 528 for (i = 0; i < sc->num_slots; i++) 529 sdhci_start_slot(&sc->slots[i]); 530 531 return (0); 532 } 533 534 static int 535 sdhci_fdt_detach(device_t dev) 536 { 537 struct sdhci_fdt_softc *sc = device_get_softc(dev); 538 int i; 539 540 bus_generic_detach(dev); 541 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 542 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 543 sc->irq_res); 544 545 for (i = 0; i < sc->num_slots; i++) { 546 sdhci_cleanup_slot(&sc->slots[i]); 547 bus_release_resource(dev, SYS_RES_MEMORY, 548 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 549 } 550 551 return (0); 552 } 553 554 static device_method_t sdhci_fdt_methods[] = { 555 /* device_if */ 556 DEVMETHOD(device_probe, sdhci_fdt_probe), 557 DEVMETHOD(device_attach, sdhci_fdt_attach), 558 DEVMETHOD(device_detach, sdhci_fdt_detach), 559 560 /* Bus interface */ 561 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 562 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 563 564 /* mmcbr_if */ 565 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 566 DEVMETHOD(mmcbr_request, sdhci_generic_request), 567 DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), 568 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 569 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 570 571 /* SDHCI registers accessors */ 572 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 573 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 574 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 575 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 576 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 577 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 578 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 579 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 580 581 DEVMETHOD_END 582 }; 583 584 static driver_t sdhci_fdt_driver = { 585 "sdhci_fdt", 586 sdhci_fdt_methods, 587 sizeof(struct sdhci_fdt_softc), 588 }; 589 static devclass_t sdhci_fdt_devclass; 590 591 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass, 592 NULL, NULL); 593 SDHCI_DEPEND(sdhci_fdt); 594 #ifndef MMCCAM 595 MMC_DECLARE_BRIDGE(sdhci_fdt); 596 #endif 597