1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <machine/bus.h>
34
35 #include <dev/uart/uart.h>
36 #include <dev/uart/uart_cpu.h>
37 #include <dev/uart/uart_bus.h>
38
39 #include <dev/ic/z8530.h>
40
41 #include "uart_if.h"
42
43 #define DEFAULT_RCLK 307200
44
45 /* Hack! */
46 #ifdef __powerpc__
47 #define UART_PCLK 0
48 #else
49 #define UART_PCLK MCB2_PCLK
50 #endif
51
52 /* Multiplexed I/O. */
53 static __inline void
uart_setmreg(struct uart_bas * bas,int reg,int val)54 uart_setmreg(struct uart_bas *bas, int reg, int val)
55 {
56
57 uart_setreg(bas, REG_CTRL, reg);
58 uart_barrier(bas);
59 uart_setreg(bas, REG_CTRL, val);
60 }
61
62 static __inline uint8_t
uart_getmreg(struct uart_bas * bas,int reg)63 uart_getmreg(struct uart_bas *bas, int reg)
64 {
65
66 uart_setreg(bas, REG_CTRL, reg);
67 uart_barrier(bas);
68 return (uart_getreg(bas, REG_CTRL));
69 }
70
71 static int
z8530_divisor(int rclk,int baudrate)72 z8530_divisor(int rclk, int baudrate)
73 {
74 int act_baud, divisor, error;
75
76 if (baudrate == 0)
77 return (-1);
78
79 divisor = (rclk + baudrate) / (baudrate << 1) - 2;
80 if (divisor < 0 || divisor >= 65536)
81 return (-1);
82 act_baud = rclk / 2 / (divisor + 2);
83
84 /* 10 times error in percent: */
85 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
86
87 /* 3.0% maximum error tolerance: */
88 if (error < -30 || error > 30)
89 return (-1);
90
91 return (divisor);
92 }
93
94 static int
z8530_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity,uint8_t * tpcp)95 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
96 int parity, uint8_t *tpcp)
97 {
98 int divisor;
99 uint8_t mpm, rpc, tpc;
100
101 rpc = RPC_RXE;
102 mpm = MPM_CM16;
103 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
104
105 if (databits >= 8) {
106 rpc |= RPC_RB8;
107 tpc |= TPC_TB8;
108 } else if (databits == 7) {
109 rpc |= RPC_RB7;
110 tpc |= TPC_TB7;
111 } else if (databits == 6) {
112 rpc |= RPC_RB6;
113 tpc |= TPC_TB6;
114 } else {
115 rpc |= RPC_RB5;
116 tpc |= TPC_TB5;
117 }
118 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
119 switch (parity) {
120 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
121 case UART_PARITY_NONE: break;
122 case UART_PARITY_ODD: mpm |= MPM_PE; break;
123 default: return (EINVAL);
124 }
125
126 if (baudrate > 0) {
127 divisor = z8530_divisor(bas->rclk, baudrate);
128 if (divisor == -1)
129 return (EINVAL);
130 } else
131 divisor = -1;
132
133 uart_setmreg(bas, WR_MCB2, UART_PCLK);
134 uart_barrier(bas);
135
136 if (divisor >= 0) {
137 uart_setmreg(bas, WR_TCL, divisor & 0xff);
138 uart_barrier(bas);
139 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
140 uart_barrier(bas);
141 }
142
143 uart_setmreg(bas, WR_RPC, rpc);
144 uart_barrier(bas);
145 uart_setmreg(bas, WR_MPM, mpm);
146 uart_barrier(bas);
147 uart_setmreg(bas, WR_TPC, tpc);
148 uart_barrier(bas);
149 uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
150 uart_barrier(bas);
151 *tpcp = tpc;
152 return (0);
153 }
154
155 static int
z8530_setup(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)156 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
157 int parity)
158 {
159 uint8_t tpc;
160
161 if (bas->rclk == 0)
162 bas->rclk = DEFAULT_RCLK;
163
164 /* Assume we don't need to perform a full hardware reset. */
165 switch (bas->chan) {
166 case 1:
167 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
168 break;
169 case 2:
170 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
171 break;
172 }
173 uart_barrier(bas);
174 /* Set clock sources. */
175 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
176 uart_setmreg(bas, WR_MCB2, UART_PCLK);
177 uart_barrier(bas);
178 /* Set data encoding. */
179 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
180 uart_barrier(bas);
181
182 tpc = TPC_DTR | TPC_RTS;
183 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
184 return (int)tpc;
185 }
186
187 /*
188 * Low-level UART interface.
189 */
190 static int z8530_probe(struct uart_bas *bas);
191 static void z8530_init(struct uart_bas *bas, int, int, int, int);
192 static void z8530_term(struct uart_bas *bas);
193 static void z8530_putc(struct uart_bas *bas, int);
194 static int z8530_rxready(struct uart_bas *bas);
195 static int z8530_getc(struct uart_bas *bas, struct mtx *);
196
197 static struct uart_ops uart_z8530_ops = {
198 .probe = z8530_probe,
199 .init = z8530_init,
200 .term = z8530_term,
201 .putc = z8530_putc,
202 .rxready = z8530_rxready,
203 .getc = z8530_getc,
204 };
205
206 static int
z8530_probe(struct uart_bas * bas)207 z8530_probe(struct uart_bas *bas)
208 {
209
210 return (0);
211 }
212
213 static void
z8530_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)214 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
215 int parity)
216 {
217
218 z8530_setup(bas, baudrate, databits, stopbits, parity);
219 }
220
221 static void
z8530_term(struct uart_bas * bas)222 z8530_term(struct uart_bas *bas)
223 {
224 }
225
226 static void
z8530_putc(struct uart_bas * bas,int c)227 z8530_putc(struct uart_bas *bas, int c)
228 {
229
230 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
231 ;
232 uart_setreg(bas, REG_DATA, c);
233 uart_barrier(bas);
234 }
235
236 static int
z8530_rxready(struct uart_bas * bas)237 z8530_rxready(struct uart_bas *bas)
238 {
239
240 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);
241 }
242
243 static int
z8530_getc(struct uart_bas * bas,struct mtx * hwmtx)244 z8530_getc(struct uart_bas *bas, struct mtx *hwmtx)
245 {
246 int c;
247
248 uart_lock(hwmtx);
249
250 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {
251 uart_unlock(hwmtx);
252 DELAY(10);
253 uart_lock(hwmtx);
254 }
255
256 c = uart_getreg(bas, REG_DATA);
257
258 uart_unlock(hwmtx);
259
260 return (c);
261 }
262
263 /*
264 * High-level UART interface.
265 */
266 struct z8530_softc {
267 struct uart_softc base;
268 uint8_t tpc;
269 uint8_t txidle;
270 };
271
272 static int z8530_bus_attach(struct uart_softc *);
273 static int z8530_bus_detach(struct uart_softc *);
274 static int z8530_bus_flush(struct uart_softc *, int);
275 static int z8530_bus_getsig(struct uart_softc *);
276 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
277 static int z8530_bus_ipend(struct uart_softc *);
278 static int z8530_bus_param(struct uart_softc *, int, int, int, int);
279 static int z8530_bus_probe(struct uart_softc *);
280 static int z8530_bus_receive(struct uart_softc *);
281 static int z8530_bus_setsig(struct uart_softc *, int);
282 static int z8530_bus_transmit(struct uart_softc *);
283 static void z8530_bus_grab(struct uart_softc *);
284 static void z8530_bus_ungrab(struct uart_softc *);
285
286 static kobj_method_t z8530_methods[] = {
287 KOBJMETHOD(uart_attach, z8530_bus_attach),
288 KOBJMETHOD(uart_detach, z8530_bus_detach),
289 KOBJMETHOD(uart_flush, z8530_bus_flush),
290 KOBJMETHOD(uart_getsig, z8530_bus_getsig),
291 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
292 KOBJMETHOD(uart_ipend, z8530_bus_ipend),
293 KOBJMETHOD(uart_param, z8530_bus_param),
294 KOBJMETHOD(uart_probe, z8530_bus_probe),
295 KOBJMETHOD(uart_receive, z8530_bus_receive),
296 KOBJMETHOD(uart_setsig, z8530_bus_setsig),
297 KOBJMETHOD(uart_transmit, z8530_bus_transmit),
298 KOBJMETHOD(uart_grab, z8530_bus_grab),
299 KOBJMETHOD(uart_ungrab, z8530_bus_ungrab),
300 { 0, 0 }
301 };
302
303 struct uart_class uart_z8530_class = {
304 "z8530",
305 z8530_methods,
306 sizeof(struct z8530_softc),
307 .uc_ops = &uart_z8530_ops,
308 .uc_range = 2,
309 .uc_rclk = DEFAULT_RCLK,
310 .uc_rshift = 0
311 };
312 UART_CLASS(uart_z8530_class);
313
314 #define SIGCHG(c, i, s, d) \
315 if (c) { \
316 i |= (i & s) ? s : s | d; \
317 } else { \
318 i = (i & s) ? (i & ~s) | d : i; \
319 }
320
321 static int
z8530_bus_attach(struct uart_softc * sc)322 z8530_bus_attach(struct uart_softc *sc)
323 {
324 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
325 struct uart_bas *bas;
326 struct uart_devinfo *di;
327
328 bas = &sc->sc_bas;
329 if (sc->sc_sysdev != NULL) {
330 di = sc->sc_sysdev;
331 z8530->tpc = TPC_DTR|TPC_RTS;
332 z8530_param(bas, di->baudrate, di->databits, di->stopbits,
333 di->parity, &z8530->tpc);
334 } else {
335 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
336 z8530->tpc &= ~(TPC_DTR|TPC_RTS);
337 }
338 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */
339
340 (void)z8530_bus_getsig(sc);
341
342 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
343 uart_barrier(bas);
344 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
345 uart_barrier(bas);
346 uart_setmreg(bas, WR_IV, 0);
347 uart_barrier(bas);
348 uart_setmreg(bas, WR_TPC, z8530->tpc);
349 uart_barrier(bas);
350 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
351 uart_barrier(bas);
352 return (0);
353 }
354
355 static int
z8530_bus_detach(struct uart_softc * sc)356 z8530_bus_detach(struct uart_softc *sc)
357 {
358
359 return (0);
360 }
361
362 static int
z8530_bus_flush(struct uart_softc * sc,int what)363 z8530_bus_flush(struct uart_softc *sc, int what)
364 {
365
366 return (0);
367 }
368
369 static int
z8530_bus_getsig(struct uart_softc * sc)370 z8530_bus_getsig(struct uart_softc *sc)
371 {
372 uint32_t new, old, sig;
373 uint8_t bes;
374
375 do {
376 old = sc->sc_hwsig;
377 sig = old;
378 uart_lock(sc->sc_hwmtx);
379 bes = uart_getmreg(&sc->sc_bas, RR_BES);
380 uart_unlock(sc->sc_hwmtx);
381 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
382 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
383 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
384 new = sig & ~SER_MASK_DELTA;
385 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
386 return (sig);
387 }
388
389 static int
z8530_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)390 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
391 {
392 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
393 struct uart_bas *bas;
394 int baudrate, divisor, error;
395
396 bas = &sc->sc_bas;
397 error = 0;
398 uart_lock(sc->sc_hwmtx);
399 switch (request) {
400 case UART_IOCTL_BREAK:
401 if (data)
402 z8530->tpc |= TPC_BRK;
403 else
404 z8530->tpc &= ~TPC_BRK;
405 uart_setmreg(bas, WR_TPC, z8530->tpc);
406 uart_barrier(bas);
407 break;
408 case UART_IOCTL_BAUD:
409 divisor = uart_getmreg(bas, RR_TCH);
410 divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL);
411 baudrate = bas->rclk / 2 / (divisor + 2);
412 *(int*)data = baudrate;
413 break;
414 default:
415 error = EINVAL;
416 break;
417 }
418 uart_unlock(sc->sc_hwmtx);
419 return (error);
420 }
421
422 static int
z8530_bus_ipend(struct uart_softc * sc)423 z8530_bus_ipend(struct uart_softc *sc)
424 {
425 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
426 struct uart_bas *bas;
427 int ipend;
428 uint32_t sig;
429 uint8_t bes, ip, iv, src;
430
431 bas = &sc->sc_bas;
432 ipend = 0;
433
434 uart_lock(sc->sc_hwmtx);
435 switch (bas->chan) {
436 case 1:
437 ip = uart_getmreg(bas, RR_IP);
438 break;
439 case 2: /* XXX hack!!! */
440 iv = uart_getmreg(bas, RR_IV) & 0x0E;
441 switch (iv) {
442 case IV_TEB: ip = IP_TIA; break;
443 case IV_XSB: ip = IP_SIA; break;
444 case IV_RAB: ip = IP_RIA; break;
445 default: ip = 0; break;
446 }
447 break;
448 default:
449 ip = 0;
450 break;
451 }
452
453 if (ip & IP_RIA)
454 ipend |= SER_INT_RXREADY;
455
456 if (ip & IP_TIA) {
457 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
458 uart_barrier(bas);
459 if (z8530->txidle) {
460 ipend |= SER_INT_TXIDLE;
461 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */
462 }
463 }
464
465 if (ip & IP_SIA) {
466 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
467 uart_barrier(bas);
468 bes = uart_getmreg(bas, RR_BES);
469 if (bes & BES_BRK)
470 ipend |= SER_INT_BREAK;
471 sig = sc->sc_hwsig;
472 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
473 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
474 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
475 if (sig & SER_MASK_DELTA)
476 ipend |= SER_INT_SIGCHG;
477 src = uart_getmreg(bas, RR_SRC);
478 if (src & SRC_OVR) {
479 uart_setreg(bas, REG_CTRL, CR_RSTERR);
480 uart_barrier(bas);
481 ipend |= SER_INT_OVERRUN;
482 }
483 }
484
485 if (ipend) {
486 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
487 uart_barrier(bas);
488 }
489
490 uart_unlock(sc->sc_hwmtx);
491
492 return (ipend);
493 }
494
495 static int
z8530_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)496 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
497 int stopbits, int parity)
498 {
499 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
500 int error;
501
502 uart_lock(sc->sc_hwmtx);
503 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
504 &z8530->tpc);
505 uart_unlock(sc->sc_hwmtx);
506 return (error);
507 }
508
509 static int
z8530_bus_probe(struct uart_softc * sc)510 z8530_bus_probe(struct uart_softc *sc)
511 {
512 int error;
513 char ch;
514
515 error = z8530_probe(&sc->sc_bas);
516 if (error)
517 return (error);
518
519 sc->sc_rxfifosz = 3;
520 sc->sc_txfifosz = 1;
521
522 ch = sc->sc_bas.chan - 1 + 'A';
523
524 device_set_descf(sc->sc_dev, "z8530, channel %c", ch);
525 return (0);
526 }
527
528 static int
z8530_bus_receive(struct uart_softc * sc)529 z8530_bus_receive(struct uart_softc *sc)
530 {
531 struct uart_bas *bas;
532 int xc;
533 uint8_t bes, src;
534
535 bas = &sc->sc_bas;
536 uart_lock(sc->sc_hwmtx);
537 bes = uart_getmreg(bas, RR_BES);
538 while (bes & BES_RXA) {
539 if (uart_rx_full(sc)) {
540 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
541 break;
542 }
543 xc = uart_getreg(bas, REG_DATA);
544 uart_barrier(bas);
545 src = uart_getmreg(bas, RR_SRC);
546 if (src & SRC_FE)
547 xc |= UART_STAT_FRAMERR;
548 if (src & SRC_PE)
549 xc |= UART_STAT_PARERR;
550 if (src & SRC_OVR)
551 xc |= UART_STAT_OVERRUN;
552 uart_rx_put(sc, xc);
553 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
554 uart_setreg(bas, REG_CTRL, CR_RSTERR);
555 uart_barrier(bas);
556 }
557 bes = uart_getmreg(bas, RR_BES);
558 }
559 /* Discard everything left in the Rx FIFO. */
560 while (bes & BES_RXA) {
561 (void)uart_getreg(bas, REG_DATA);
562 uart_barrier(bas);
563 src = uart_getmreg(bas, RR_SRC);
564 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
565 uart_setreg(bas, REG_CTRL, CR_RSTERR);
566 uart_barrier(bas);
567 }
568 bes = uart_getmreg(bas, RR_BES);
569 }
570 uart_unlock(sc->sc_hwmtx);
571 return (0);
572 }
573
574 static int
z8530_bus_setsig(struct uart_softc * sc,int sig)575 z8530_bus_setsig(struct uart_softc *sc, int sig)
576 {
577 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
578 struct uart_bas *bas;
579 uint32_t new, old;
580
581 bas = &sc->sc_bas;
582 do {
583 old = sc->sc_hwsig;
584 new = old;
585 if (sig & SER_DDTR) {
586 SIGCHG(sig & SER_DTR, new, SER_DTR,
587 SER_DDTR);
588 }
589 if (sig & SER_DRTS) {
590 SIGCHG(sig & SER_RTS, new, SER_RTS,
591 SER_DRTS);
592 }
593 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
594
595 uart_lock(sc->sc_hwmtx);
596 if (new & SER_DTR)
597 z8530->tpc |= TPC_DTR;
598 else
599 z8530->tpc &= ~TPC_DTR;
600 if (new & SER_RTS)
601 z8530->tpc |= TPC_RTS;
602 else
603 z8530->tpc &= ~TPC_RTS;
604 uart_setmreg(bas, WR_TPC, z8530->tpc);
605 uart_barrier(bas);
606 uart_unlock(sc->sc_hwmtx);
607 return (0);
608 }
609
610 static int
z8530_bus_transmit(struct uart_softc * sc)611 z8530_bus_transmit(struct uart_softc *sc)
612 {
613 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
614 struct uart_bas *bas;
615
616 bas = &sc->sc_bas;
617 uart_lock(sc->sc_hwmtx);
618 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
619 ;
620 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
621 uart_barrier(bas);
622 sc->sc_txbusy = 1;
623 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */
624 uart_unlock(sc->sc_hwmtx);
625 return (0);
626 }
627
628 static void
z8530_bus_grab(struct uart_softc * sc)629 z8530_bus_grab(struct uart_softc *sc)
630 {
631 struct uart_bas *bas;
632
633 bas = &sc->sc_bas;
634 uart_lock(sc->sc_hwmtx);
635 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE);
636 uart_barrier(bas);
637 uart_unlock(sc->sc_hwmtx);
638 }
639
640 static void
z8530_bus_ungrab(struct uart_softc * sc)641 z8530_bus_ungrab(struct uart_softc *sc)
642 {
643 struct uart_bas *bas;
644
645 bas = &sc->sc_bas;
646 uart_lock(sc->sc_hwmtx);
647 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
648 uart_barrier(bas);
649 uart_unlock(sc->sc_hwmtx);
650 }
651