1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved.
5 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved.
6 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * This file contains the driver for the DesignWare series USB 2.0 OTG
32 * Controller.
33 */
34
35 /*
36 * LIMITATION: Drivers must be bound to all OUT endpoints in the
37 * active configuration for this driver to work properly. Blocking any
38 * OUT endpoint will block all OUT endpoints including the control
39 * endpoint. Usually this is not a problem.
40 */
41
42 /*
43 * NOTE: Writing to non-existing registers appears to cause an
44 * internal reset.
45 */
46
47 #ifdef USB_GLOBAL_INCLUDE_FILE
48 #include USB_GLOBAL_INCLUDE_FILE
49 #else
50 #include <sys/stdint.h>
51 #include <sys/stddef.h>
52 #include <sys/param.h>
53 #include <sys/queue.h>
54 #include <sys/types.h>
55 #include <sys/systm.h>
56 #include <sys/kernel.h>
57 #include <sys/bus.h>
58 #include <sys/module.h>
59 #include <sys/lock.h>
60 #include <sys/mutex.h>
61 #include <sys/condvar.h>
62 #include <sys/sysctl.h>
63 #include <sys/sx.h>
64 #include <sys/unistd.h>
65 #include <sys/callout.h>
66 #include <sys/malloc.h>
67 #include <sys/priv.h>
68 #include <sys/rman.h>
69
70 #include <dev/usb/usb.h>
71 #include <dev/usb/usbdi.h>
72
73 #define USB_DEBUG_VAR dwc_otg_debug
74
75 #include <dev/usb/usb_core.h>
76 #include <dev/usb/usb_debug.h>
77 #include <dev/usb/usb_busdma.h>
78 #include <dev/usb/usb_process.h>
79 #include <dev/usb/usb_transfer.h>
80 #include <dev/usb/usb_device.h>
81 #include <dev/usb/usb_hub.h>
82 #include <dev/usb/usb_util.h>
83
84 #include <dev/usb/usb_controller.h>
85 #include <dev/usb/usb_bus.h>
86 #endif /* USB_GLOBAL_INCLUDE_FILE */
87
88 #include <dev/usb/controller/dwc_otg.h>
89 #include <dev/usb/controller/dwc_otgreg.h>
90
91 #define DWC_OTG_BUS2SC(bus) \
92 __containerof(bus, struct dwc_otg_softc, sc_bus)
93
94 #define DWC_OTG_PC2UDEV(pc) \
95 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
96
97 #define DWC_OTG_MSK_GINT_THREAD_IRQ \
98 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \
99 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \
100 GINTSTS_SESSREQINT)
101
102 #ifndef DWC_OTG_PHY_DEFAULT
103 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI
104 #endif
105
106 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT;
107
108 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
109 "USB DWC OTG");
110 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN,
111 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+");
112
113 #ifdef USB_DEBUG
114 static int dwc_otg_debug = 0;
115
116 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
117 &dwc_otg_debug, 0, "DWC OTG debug level");
118 #endif
119
120 #define DWC_OTG_INTR_ENDPT 1
121
122 /* prototypes */
123
124 static const struct usb_bus_methods dwc_otg_bus_methods;
125 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods;
126 static const struct usb_pipe_methods dwc_otg_device_isoc_methods;
127
128 static dwc_otg_cmd_t dwc_otg_setup_rx;
129 static dwc_otg_cmd_t dwc_otg_data_rx;
130 static dwc_otg_cmd_t dwc_otg_data_tx;
131 static dwc_otg_cmd_t dwc_otg_data_tx_sync;
132
133 static dwc_otg_cmd_t dwc_otg_host_setup_tx;
134 static dwc_otg_cmd_t dwc_otg_host_data_tx;
135 static dwc_otg_cmd_t dwc_otg_host_data_rx;
136
137 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t);
138 static void dwc_otg_do_poll(struct usb_bus *);
139 static void dwc_otg_standard_done(struct usb_xfer *);
140 static void dwc_otg_root_intr(struct dwc_otg_softc *);
141 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *);
142
143 /*
144 * Here is a configuration that the chip supports.
145 */
146 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = {
147 [0] = {
148 .max_in_frame_size = 64,/* fixed */
149 .max_out_frame_size = 64, /* fixed */
150 .is_simplex = 1,
151 .support_control = 1,
152 }
153 };
154
155 static void
dwc_otg_get_hw_ep_profile(struct usb_device * udev,const struct usb_hw_ep_profile ** ppf,uint8_t ep_addr)156 dwc_otg_get_hw_ep_profile(struct usb_device *udev,
157 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
158 {
159 struct dwc_otg_softc *sc;
160
161 sc = DWC_OTG_BUS2SC(udev->bus);
162
163 if (ep_addr < sc->sc_dev_ep_max)
164 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb;
165 else
166 *ppf = NULL;
167 }
168
169 static void
dwc_otg_write_fifo(struct dwc_otg_softc * sc,struct usb_page_cache * pc,uint32_t offset,uint32_t fifo,uint32_t count)170 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
171 uint32_t offset, uint32_t fifo, uint32_t count)
172 {
173 uint32_t temp;
174
175 /* round down length to nearest 4-bytes */
176 temp = count & ~3;
177
178 /* check if we can write the data directly */
179 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
180 struct usb_page_search buf_res;
181
182 /* pre-subtract length */
183 count -= temp;
184
185 /* iterate buffer list */
186 do {
187 /* get current buffer pointer */
188 usbd_get_page(pc, offset, &buf_res);
189
190 if (buf_res.length > temp)
191 buf_res.length = temp;
192
193 /* transfer data into FIFO */
194 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
195 fifo, buf_res.buffer, buf_res.length / 4);
196
197 offset += buf_res.length;
198 fifo += buf_res.length;
199 temp -= buf_res.length;
200 } while (temp != 0);
201 }
202
203 /* check for remainder */
204 if (count != 0) {
205 /* clear topmost word before copy */
206 sc->sc_bounce_buffer[(count - 1) / 4] = 0;
207
208 /* copy out data */
209 usbd_copy_out(pc, offset,
210 sc->sc_bounce_buffer, count);
211
212 /* transfer data into FIFO */
213 bus_space_write_region_4(sc->sc_io_tag,
214 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer,
215 (count + 3) / 4);
216 }
217 }
218
219 static void
dwc_otg_read_fifo(struct dwc_otg_softc * sc,struct usb_page_cache * pc,uint32_t offset,uint32_t count)220 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
221 uint32_t offset, uint32_t count)
222 {
223 uint32_t temp;
224
225 /* round down length to nearest 4-bytes */
226 temp = count & ~3;
227
228 /* check if we can read the data directly */
229 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
230 struct usb_page_search buf_res;
231
232 /* pre-subtract length */
233 count -= temp;
234
235 /* iterate buffer list */
236 do {
237 /* get current buffer pointer */
238 usbd_get_page(pc, offset, &buf_res);
239
240 if (buf_res.length > temp)
241 buf_res.length = temp;
242
243 /* transfer data from FIFO */
244 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
245 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4);
246
247 offset += buf_res.length;
248 sc->sc_current_rx_fifo += buf_res.length;
249 sc->sc_current_rx_bytes -= buf_res.length;
250 temp -= buf_res.length;
251 } while (temp != 0);
252 }
253
254 /* check for remainder */
255 if (count != 0) {
256 /* read data into bounce buffer */
257 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
258 sc->sc_current_rx_fifo,
259 sc->sc_bounce_buffer, (count + 3) / 4);
260
261 /* store data into proper buffer */
262 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count);
263
264 /* round length up to nearest 4 bytes */
265 count = (count + 3) & ~3;
266
267 /* update counters */
268 sc->sc_current_rx_bytes -= count;
269 sc->sc_current_rx_fifo += count;
270 }
271 }
272
273 static void
dwc_otg_tx_fifo_reset(struct dwc_otg_softc * sc,uint32_t value)274 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value)
275 {
276 uint32_t temp;
277
278 /* reset FIFO */
279 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value);
280
281 /* wait for reset to complete */
282 for (temp = 0; temp != 16; temp++) {
283 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL);
284 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)))
285 break;
286 }
287 }
288
289 static int
dwc_otg_init_fifo(struct dwc_otg_softc * sc,uint8_t mode)290 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
291 {
292 struct dwc_otg_profile *pf;
293 uint32_t fifo_size;
294 uint32_t fifo_regs;
295 uint32_t tx_start;
296 uint8_t x;
297
298 fifo_size = sc->sc_fifo_size;
299
300 /*
301 * NOTE: Reserved fixed size area at end of RAM, which must
302 * not be allocated to the FIFOs:
303 */
304 fifo_regs = 4 * 16;
305
306 if (fifo_size < fifo_regs) {
307 DPRINTF("Too little FIFO\n");
308 return (EINVAL);
309 }
310
311 /* subtract FIFO regs from total once */
312 fifo_size -= fifo_regs;
313
314 /* split equally for IN and OUT */
315 fifo_size /= 2;
316
317 /* Align to 4 bytes boundary (refer to PGM) */
318 fifo_size &= ~3;
319
320 /* set global receive FIFO size */
321 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4);
322
323 tx_start = fifo_size;
324
325 if (fifo_size < 64) {
326 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n");
327 return (EINVAL);
328 }
329
330 if (mode == DWC_MODE_HOST) {
331 /* reset active endpoints */
332 sc->sc_active_rx_ep = 0;
333
334 /* split equally for periodic and non-periodic */
335 fifo_size /= 2;
336
337 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size);
338
339 /* align to 4 bytes boundary */
340 fifo_size &= ~3;
341
342 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
343 ((fifo_size / 4) << 16) |
344 (tx_start / 4));
345
346 tx_start += fifo_size;
347
348 for (x = 0; x != sc->sc_host_ch_max; x++) {
349 /* enable all host interrupts */
350 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x),
351 HCINT_DEFAULT_MASK);
352 }
353
354 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ,
355 ((fifo_size / 4) << 16) |
356 (tx_start / 4));
357
358 /* reset host channel state */
359 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
360
361 /* enable all host channel interrupts */
362 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK,
363 (1U << sc->sc_host_ch_max) - 1U);
364
365 /* enable proper host channel interrupts */
366 sc->sc_irq_mask |= GINTMSK_HCHINTMSK;
367 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK;
368 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
369 }
370
371 if (mode == DWC_MODE_DEVICE) {
372 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
373 (0x10 << 16) | (tx_start / 4));
374 fifo_size -= 0x40;
375 tx_start += 0x40;
376
377 /* setup control endpoint profile */
378 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0];
379
380 /* reset active endpoints */
381 sc->sc_active_rx_ep = 1;
382
383 for (x = 1; x != sc->sc_dev_ep_max; x++) {
384 pf = sc->sc_hw_ep_profile + x;
385
386 pf->usb.max_out_frame_size = 1024 * 3;
387 pf->usb.is_simplex = 0; /* assume duplex */
388 pf->usb.support_bulk = 1;
389 pf->usb.support_interrupt = 1;
390 pf->usb.support_isochronous = 1;
391 pf->usb.support_out = 1;
392
393 if (x < sc->sc_dev_in_ep_max) {
394 uint32_t limit;
395
396 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE,
397 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2,
398 DWC_OTG_TX_MAX_FIFO_SIZE);
399
400 /* see if there is enough FIFO space */
401 if (limit <= fifo_size) {
402 pf->max_buffer = limit;
403 pf->usb.support_in = 1;
404 } else {
405 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40);
406 if (limit <= fifo_size) {
407 pf->usb.support_in = 1;
408 } else {
409 pf->usb.is_simplex = 1;
410 limit = 0;
411 }
412 }
413 /* set FIFO size */
414 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
415 ((limit / 4) << 16) | (tx_start / 4));
416 tx_start += limit;
417 fifo_size -= limit;
418 pf->usb.max_in_frame_size = limit;
419 } else {
420 pf->usb.is_simplex = 1;
421 }
422
423 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x,
424 pf->usb.max_in_frame_size,
425 pf->usb.max_out_frame_size);
426 }
427
428 /* enable proper device channel interrupts */
429 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK;
430 sc->sc_irq_mask |= GINTMSK_IEPINTMSK;
431 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
432 }
433
434 /* reset RX FIFO */
435 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH);
436
437 if (mode != DWC_MODE_OTG) {
438 /* reset all TX FIFOs */
439 dwc_otg_tx_fifo_reset(sc,
440 GRSTCTL_TXFIFO(0x10) |
441 GRSTCTL_TXFFLSH);
442 } else {
443 /* reset active endpoints */
444 sc->sc_active_rx_ep = 0;
445
446 /* reset host channel state */
447 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
448 }
449 return (0);
450 }
451
452 static uint8_t
dwc_otg_uses_split(struct usb_device * udev)453 dwc_otg_uses_split(struct usb_device *udev)
454 {
455 /*
456 * When a LOW or FULL speed device is connected directly to
457 * the USB port we don't use split transactions:
458 */
459 return (udev->speed != USB_SPEED_HIGH &&
460 udev->parent_hs_hub != NULL &&
461 udev->parent_hs_hub->parent_hub != NULL);
462 }
463
464 static void
dwc_otg_update_host_frame_interval(struct dwc_otg_softc * sc)465 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc)
466 {
467
468 /*
469 * Disabled until further. Assuming that the register is already
470 * programmed correctly by the boot loader.
471 */
472 #if 0
473 uint32_t temp;
474
475 /* setup HOST frame interval register, based on existing value */
476 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
477 if (temp >= 10000)
478 temp /= 1000;
479 else
480 temp /= 125;
481
482 /* figure out nearest X-tal value */
483 if (temp >= 54)
484 temp = 60; /* MHz */
485 else if (temp >= 39)
486 temp = 48; /* MHz */
487 else
488 temp = 30; /* MHz */
489
490 if (sc->sc_flags.status_high_speed)
491 temp *= 125;
492 else
493 temp *= 1000;
494
495 DPRINTF("HFIR=0x%08x\n", temp);
496
497 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
498 #endif
499 }
500
501 static void
dwc_otg_clocks_on(struct dwc_otg_softc * sc)502 dwc_otg_clocks_on(struct dwc_otg_softc *sc)
503 {
504 if (sc->sc_flags.clocks_off &&
505 sc->sc_flags.port_powered) {
506 DPRINTFN(5, "\n");
507
508 /* TODO - platform specific */
509
510 sc->sc_flags.clocks_off = 0;
511 }
512 }
513
514 static void
dwc_otg_clocks_off(struct dwc_otg_softc * sc)515 dwc_otg_clocks_off(struct dwc_otg_softc *sc)
516 {
517 if (!sc->sc_flags.clocks_off) {
518 DPRINTFN(5, "\n");
519
520 /* TODO - platform specific */
521
522 sc->sc_flags.clocks_off = 1;
523 }
524 }
525
526 static void
dwc_otg_pull_up(struct dwc_otg_softc * sc)527 dwc_otg_pull_up(struct dwc_otg_softc *sc)
528 {
529 uint32_t temp;
530
531 /* pullup D+, if possible */
532
533 if (!sc->sc_flags.d_pulled_up &&
534 sc->sc_flags.port_powered) {
535 sc->sc_flags.d_pulled_up = 1;
536
537 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
538 temp &= ~DCTL_SFTDISCON;
539 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
540 }
541 }
542
543 static void
dwc_otg_pull_down(struct dwc_otg_softc * sc)544 dwc_otg_pull_down(struct dwc_otg_softc *sc)
545 {
546 uint32_t temp;
547
548 /* pulldown D+, if possible */
549
550 if (sc->sc_flags.d_pulled_up) {
551 sc->sc_flags.d_pulled_up = 0;
552
553 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
554 temp |= DCTL_SFTDISCON;
555 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
556 }
557 }
558
559 static void
dwc_otg_enable_sof_irq(struct dwc_otg_softc * sc)560 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc)
561 {
562 /* In device mode we don't use the SOF interrupt */
563 if (sc->sc_flags.status_device_mode != 0)
564 return;
565 /* Ensure the SOF interrupt is not disabled */
566 sc->sc_needsof = 1;
567 /* Check if the SOF interrupt is already enabled */
568 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0)
569 return;
570 sc->sc_irq_mask |= GINTMSK_SOFMSK;
571 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
572 }
573
574 static void
dwc_otg_resume_irq(struct dwc_otg_softc * sc)575 dwc_otg_resume_irq(struct dwc_otg_softc *sc)
576 {
577 if (sc->sc_flags.status_suspend) {
578 /* update status bits */
579 sc->sc_flags.status_suspend = 0;
580 sc->sc_flags.change_suspend = 1;
581
582 if (sc->sc_flags.status_device_mode) {
583 /*
584 * Disable resume interrupt and enable suspend
585 * interrupt:
586 */
587 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK;
588 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
589 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
590 }
591
592 /* complete root HUB interrupt endpoint */
593 dwc_otg_root_intr(sc);
594 }
595 }
596
597 static void
dwc_otg_suspend_irq(struct dwc_otg_softc * sc)598 dwc_otg_suspend_irq(struct dwc_otg_softc *sc)
599 {
600 if (!sc->sc_flags.status_suspend) {
601 /* update status bits */
602 sc->sc_flags.status_suspend = 1;
603 sc->sc_flags.change_suspend = 1;
604
605 if (sc->sc_flags.status_device_mode) {
606 /*
607 * Disable suspend interrupt and enable resume
608 * interrupt:
609 */
610 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK;
611 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK;
612 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
613 }
614
615 /* complete root HUB interrupt endpoint */
616 dwc_otg_root_intr(sc);
617 }
618 }
619
620 static void
dwc_otg_wakeup_peer(struct dwc_otg_softc * sc)621 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc)
622 {
623 if (!sc->sc_flags.status_suspend)
624 return;
625
626 DPRINTFN(5, "Remote wakeup\n");
627
628 if (sc->sc_flags.status_device_mode) {
629 uint32_t temp;
630
631 /* enable remote wakeup signalling */
632 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
633 temp |= DCTL_RMTWKUPSIG;
634 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
635
636 /* Wait 8ms for remote wakeup to complete. */
637 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
638
639 temp &= ~DCTL_RMTWKUPSIG;
640 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
641 } else {
642 /* enable USB port */
643 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
644
645 /* wait 10ms */
646 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
647
648 /* resume port */
649 sc->sc_hprt_val |= HPRT_PRTRES;
650 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
651
652 /* Wait 100ms for resume signalling to complete. */
653 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
654
655 /* clear suspend and resume */
656 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES);
657 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
658
659 /* Wait 4ms */
660 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
661 }
662
663 /* need to fake resume IRQ */
664 dwc_otg_resume_irq(sc);
665 }
666
667 static void
dwc_otg_set_address(struct dwc_otg_softc * sc,uint8_t addr)668 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr)
669 {
670 uint32_t temp;
671
672 DPRINTFN(5, "addr=%d\n", addr);
673
674 temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
675 temp &= ~DCFG_DEVADDR_SET(0x7F);
676 temp |= DCFG_DEVADDR_SET(addr);
677 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
678 }
679
680 static void
dwc_otg_common_rx_ack(struct dwc_otg_softc * sc)681 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc)
682 {
683 DPRINTFN(5, "RX status clear\n");
684
685 /* enable RX FIFO level interrupt */
686 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK;
687 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
688
689 if (sc->sc_current_rx_bytes != 0) {
690 /* need to dump remaining data */
691 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
692 sc->sc_current_rx_fifo, sc->sc_bounce_buffer,
693 sc->sc_current_rx_bytes / 4);
694 /* clear number of active bytes to receive */
695 sc->sc_current_rx_bytes = 0;
696 }
697 /* clear cached status */
698 sc->sc_last_rx_status = 0;
699 }
700
701 static void
dwc_otg_clear_hcint(struct dwc_otg_softc * sc,uint8_t x)702 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x)
703 {
704 uint32_t hcint;
705
706 /* clear all pending interrupts */
707 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
708 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint);
709
710 /* clear buffered interrupts */
711 sc->sc_chan_state[x].hcint = 0;
712 }
713
714 static uint8_t
dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc * sc,struct dwc_otg_td * td)715 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
716 {
717 uint32_t temp;
718
719 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
720
721 if (td->ep_type == UE_ISOCHRONOUS) {
722 /*
723 * NOTE: USB INTERRUPT transactions are executed like
724 * USB CONTROL transactions! See the setup standard
725 * chain function for more information.
726 */
727 if (!(temp & GINTSTS_PTXFEMP)) {
728 DPRINTF("Periodic TX FIFO is not empty\n");
729 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) {
730 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK;
731 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
732 }
733 return (1); /* busy */
734 }
735 } else {
736 if (!(temp & GINTSTS_NPTXFEMP)) {
737 DPRINTF("Non-periodic TX FIFO is not empty\n");
738 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) {
739 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK;
740 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
741 }
742 return (1); /* busy */
743 }
744 }
745 return (0); /* ready for transmit */
746 }
747
748 static uint8_t
dwc_otg_host_channel_alloc(struct dwc_otg_softc * sc,struct dwc_otg_td * td,uint8_t is_out)749 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc,
750 struct dwc_otg_td *td, uint8_t is_out)
751 {
752 uint8_t x;
753 uint8_t y;
754 uint8_t z;
755
756 if (td->channel[0] < DWC_OTG_MAX_CHANNELS)
757 return (0); /* already allocated */
758
759 /* check if device is suspended */
760 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
761 return (1); /* busy - cannot transfer data */
762
763 /* compute needed TX FIFO size */
764 if (is_out != 0) {
765 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0)
766 return (1); /* busy - cannot transfer data */
767 }
768 z = td->max_packet_count;
769 for (x = y = 0; x != sc->sc_host_ch_max; x++) {
770 /* check if channel is allocated */
771 if (sc->sc_chan_state[x].allocated != 0)
772 continue;
773 /* check if channel is still enabled */
774 if (sc->sc_chan_state[x].wait_halted != 0)
775 continue;
776 /* store channel number */
777 td->channel[y++] = x;
778 /* check if we got all channels */
779 if (y == z)
780 break;
781 }
782 if (y != z) {
783 /* reset channel variable */
784 td->channel[0] = DWC_OTG_MAX_CHANNELS;
785 td->channel[1] = DWC_OTG_MAX_CHANNELS;
786 td->channel[2] = DWC_OTG_MAX_CHANNELS;
787 /* wait a bit */
788 dwc_otg_enable_sof_irq(sc);
789 return (1); /* busy - not enough channels */
790 }
791
792 for (y = 0; y != z; y++) {
793 x = td->channel[y];
794
795 /* set allocated */
796 sc->sc_chan_state[x].allocated = 1;
797
798 /* set wait halted */
799 sc->sc_chan_state[x].wait_halted = 1;
800
801 /* clear interrupts */
802 dwc_otg_clear_hcint(sc, x);
803
804 DPRINTF("CH=%d HCCHAR=0x%08x "
805 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt);
806
807 /* set active channel */
808 sc->sc_active_rx_ep |= (1 << x);
809 }
810 return (0); /* allocated */
811 }
812
813 static void
dwc_otg_host_channel_free_sub(struct dwc_otg_softc * sc,struct dwc_otg_td * td,uint8_t index)814 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index)
815 {
816 uint32_t hcchar;
817 uint8_t x;
818
819 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS)
820 return; /* already freed */
821
822 /* free channel */
823 x = td->channel[index];
824 td->channel[index] = DWC_OTG_MAX_CHANNELS;
825
826 DPRINTF("CH=%d\n", x);
827
828 /*
829 * We need to let programmed host channels run till complete
830 * else the host channel will stop functioning.
831 */
832 sc->sc_chan_state[x].allocated = 0;
833
834 /* ack any pending messages */
835 if (sc->sc_last_rx_status != 0 &&
836 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) {
837 dwc_otg_common_rx_ack(sc);
838 }
839
840 /* clear active channel */
841 sc->sc_active_rx_ep &= ~(1 << x);
842
843 /* check if already halted */
844 if (sc->sc_chan_state[x].wait_halted == 0)
845 return;
846
847 /* disable host channel */
848 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
849 if (hcchar & HCCHAR_CHENA) {
850 DPRINTF("Halting channel %d\n", x);
851 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
852 hcchar | HCCHAR_CHDIS);
853 /* don't write HCCHAR until the channel is halted */
854 } else {
855 sc->sc_chan_state[x].wait_halted = 0;
856 }
857 }
858
859 static void
dwc_otg_host_channel_free(struct dwc_otg_softc * sc,struct dwc_otg_td * td)860 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
861 {
862 uint8_t x;
863 for (x = 0; x != td->max_packet_count; x++)
864 dwc_otg_host_channel_free_sub(sc, td, x);
865 }
866
867 static void
dwc_otg_host_dump_rx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)868 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
869 {
870 uint8_t x;
871 /* dump any pending messages */
872 if (sc->sc_last_rx_status == 0)
873 return;
874 for (x = 0; x != td->max_packet_count; x++) {
875 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS ||
876 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status))
877 continue;
878 dwc_otg_common_rx_ack(sc);
879 break;
880 }
881 }
882
883 static uint8_t
dwc_otg_host_setup_tx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)884 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
885 {
886 struct usb_device_request req __aligned(4);
887 uint32_t hcint;
888 uint32_t hcchar;
889 uint8_t delta;
890
891 dwc_otg_host_dump_rx(sc, td);
892
893 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) {
894 hcint = sc->sc_chan_state[td->channel[0]].hcint;
895
896 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
897 td->channel[0], td->state, hcint,
898 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])),
899 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0])));
900 } else {
901 hcint = 0;
902 goto check_state;
903 }
904
905 if (hcint & (HCINT_RETRY |
906 HCINT_ACK | HCINT_NYET)) {
907 /* give success bits priority over failure bits */
908 } else if (hcint & HCINT_STALL) {
909 DPRINTF("CH=%d STALL\n", td->channel[0]);
910 td->error_stall = 1;
911 td->error_any = 1;
912 goto complete;
913 } else if (hcint & HCINT_ERRORS) {
914 DPRINTF("CH=%d ERROR\n", td->channel[0]);
915 td->errcnt++;
916 if (td->hcsplt != 0 || td->errcnt >= 3) {
917 td->error_any = 1;
918 goto complete;
919 }
920 }
921
922 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
923 HCINT_ACK | HCINT_NYET)) {
924 if (!(hcint & HCINT_ERRORS))
925 td->errcnt = 0;
926 }
927
928 check_state:
929 switch (td->state) {
930 case DWC_CHAN_ST_START:
931 goto send_pkt;
932
933 case DWC_CHAN_ST_WAIT_ANE:
934 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
935 td->did_nak = 1;
936 td->tt_scheduled = 0;
937 goto send_pkt;
938 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
939 td->offset += td->tx_bytes;
940 td->remainder -= td->tx_bytes;
941 td->toggle = 1;
942 td->tt_scheduled = 0;
943 goto complete;
944 }
945 break;
946
947 case DWC_CHAN_ST_WAIT_S_ANE:
948 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
949 td->did_nak = 1;
950 td->tt_scheduled = 0;
951 goto send_pkt;
952 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
953 goto send_cpkt;
954 }
955 break;
956
957 case DWC_CHAN_ST_WAIT_C_ANE:
958 if (hcint & HCINT_NYET) {
959 goto send_cpkt;
960 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
961 td->did_nak = 1;
962 td->tt_scheduled = 0;
963 goto send_pkt;
964 } else if (hcint & HCINT_ACK) {
965 td->offset += td->tx_bytes;
966 td->remainder -= td->tx_bytes;
967 td->toggle = 1;
968 goto complete;
969 }
970 break;
971
972 case DWC_CHAN_ST_WAIT_C_PKT:
973 goto send_cpkt;
974
975 default:
976 break;
977 }
978 goto busy;
979
980 send_pkt:
981 /* free existing channel, if any */
982 dwc_otg_host_channel_free(sc, td);
983
984 if (sizeof(req) != td->remainder) {
985 td->error_any = 1;
986 goto complete;
987 }
988
989 if (td->hcsplt != 0) {
990 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
991 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
992 td->state = DWC_CHAN_ST_START;
993 goto busy;
994 }
995 delta = sc->sc_last_frame_num - td->tt_start_slot;
996 if (delta > 5) {
997 /* missed it */
998 td->tt_scheduled = 0;
999 td->state = DWC_CHAN_ST_START;
1000 goto busy;
1001 }
1002 }
1003
1004 /* allocate a new channel */
1005 if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1006 td->state = DWC_CHAN_ST_START;
1007 goto busy;
1008 }
1009
1010 if (td->hcsplt != 0) {
1011 td->hcsplt &= ~HCSPLT_COMPSPLT;
1012 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1013 } else {
1014 td->state = DWC_CHAN_ST_WAIT_ANE;
1015 }
1016
1017 /* copy out control request */
1018 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1019
1020 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1021 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) |
1022 (1 << HCTSIZ_PKTCNT_SHIFT) |
1023 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1024
1025 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1026
1027 hcchar = td->hcchar;
1028 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1029 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1030
1031 /* must enable channel before writing data to FIFO */
1032 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1033
1034 /* transfer data into FIFO */
1035 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
1036 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4);
1037
1038 /* wait until next slot before trying complete split */
1039 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1040
1041 /* store number of bytes transmitted */
1042 td->tx_bytes = sizeof(req);
1043 goto busy;
1044
1045 send_cpkt:
1046 /* free existing channel, if any */
1047 dwc_otg_host_channel_free(sc, td);
1048
1049 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1050 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1051 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1052 goto busy;
1053 }
1054 delta = sc->sc_last_frame_num - td->tt_start_slot;
1055 if (delta > DWC_OTG_TT_SLOT_MAX) {
1056 /* we missed the service interval */
1057 if (td->ep_type != UE_ISOCHRONOUS)
1058 td->error_any = 1;
1059 goto complete;
1060 }
1061 /* allocate a new channel */
1062 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1063 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1064 goto busy;
1065 }
1066
1067 /* wait until next slot before trying complete split */
1068 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1069
1070 td->hcsplt |= HCSPLT_COMPSPLT;
1071 td->state = DWC_CHAN_ST_WAIT_C_ANE;
1072
1073 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1074 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1075
1076 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1077
1078 hcchar = td->hcchar;
1079 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1080 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1081
1082 /* must enable channel before writing data to FIFO */
1083 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1084
1085 busy:
1086 return (1); /* busy */
1087
1088 complete:
1089 dwc_otg_host_channel_free(sc, td);
1090 return (0); /* complete */
1091 }
1092
1093 static uint8_t
dwc_otg_setup_rx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)1094 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1095 {
1096 struct usb_device_request req __aligned(4);
1097 uint32_t temp;
1098 uint16_t count;
1099
1100 /* check endpoint status */
1101
1102 if (sc->sc_last_rx_status == 0)
1103 goto not_complete;
1104
1105 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
1106 goto not_complete;
1107
1108 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1109 GRXSTSRD_STP_DATA) {
1110 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1111 GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
1112 /* release FIFO */
1113 dwc_otg_common_rx_ack(sc);
1114 goto not_complete;
1115 }
1116 /* release FIFO */
1117 dwc_otg_common_rx_ack(sc);
1118 return (0); /* complete */
1119 }
1120
1121 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1122 GRXSTSRD_DPID_DATA0) {
1123 /* release FIFO */
1124 dwc_otg_common_rx_ack(sc);
1125 goto not_complete;
1126 }
1127
1128 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status);
1129
1130 /* clear did stall */
1131 td->did_stall = 0;
1132
1133 /* get the packet byte count */
1134 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1135
1136 if (count != sizeof(req)) {
1137 DPRINTFN(0, "Unsupported SETUP packet "
1138 "length, %d bytes\n", count);
1139 /* release FIFO */
1140 dwc_otg_common_rx_ack(sc);
1141 goto not_complete;
1142 }
1143
1144 /* read FIFO */
1145 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req));
1146
1147 /* copy out control request */
1148 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1149
1150 td->offset = sizeof(req);
1151 td->remainder = 0;
1152
1153 /* sneak peek the set address */
1154 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1155 (req.bRequest == UR_SET_ADDRESS)) {
1156 /* must write address before ZLP */
1157 dwc_otg_set_address(sc, req.wValue[0] & 0x7F);
1158 }
1159
1160 /* don't send any data by default */
1161 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS);
1162 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS);
1163
1164 /* reset IN endpoint buffer */
1165 dwc_otg_tx_fifo_reset(sc,
1166 GRSTCTL_TXFIFO(0) |
1167 GRSTCTL_TXFFLSH);
1168
1169 /* acknowledge RX status */
1170 dwc_otg_common_rx_ack(sc);
1171 td->did_stall = 1;
1172
1173 not_complete:
1174 /* abort any ongoing transfer, before enabling again */
1175 if (!td->did_stall) {
1176 td->did_stall = 1;
1177
1178 DPRINTFN(5, "stalling IN and OUT direction\n");
1179
1180 temp = sc->sc_out_ctl[0];
1181
1182 /* set stall after enabling endpoint */
1183 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
1184 temp | DOEPCTL_STALL);
1185
1186 temp = sc->sc_in_ctl[0];
1187
1188 /* set stall assuming endpoint is enabled */
1189 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
1190 temp | DIEPCTL_STALL);
1191 }
1192 return (1); /* not complete */
1193 }
1194
1195 static uint8_t
dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc * sc,struct dwc_otg_td * td)1196 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1197 {
1198 uint8_t delta;
1199
1200 delta = sc->sc_tmr_val - td->tmr_val;
1201 if (delta >= 128)
1202 return (1); /* busy */
1203
1204 td->tmr_val = sc->sc_tmr_val + td->tmr_res;
1205
1206 /* set toggle, if any */
1207 if (td->set_toggle) {
1208 td->set_toggle = 0;
1209 td->toggle = 1;
1210 }
1211 return (0);
1212 }
1213
1214 static uint8_t
dwc_otg_host_rate_check(struct dwc_otg_softc * sc,struct dwc_otg_td * td)1215 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1216 {
1217 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num;
1218
1219 if (td->ep_type == UE_ISOCHRONOUS) {
1220 /* non TT isochronous traffic */
1221 if (frame_num & (td->tmr_res - 1))
1222 goto busy;
1223 if ((frame_num ^ td->tmr_val) & td->tmr_res)
1224 goto busy;
1225 td->tmr_val = td->tmr_res + sc->sc_last_frame_num;
1226 td->toggle = 0;
1227 return (0);
1228 } else if (td->ep_type == UE_INTERRUPT) {
1229 if (!td->tt_scheduled)
1230 goto busy;
1231 td->tt_scheduled = 0;
1232 return (0);
1233 } else if (td->did_nak != 0) {
1234 /* check if we should pause sending queries for 125us */
1235 if (td->tmr_res == frame_num) {
1236 /* wait a bit */
1237 dwc_otg_enable_sof_irq(sc);
1238 goto busy;
1239 }
1240 } else if (td->set_toggle) {
1241 td->set_toggle = 0;
1242 td->toggle = 1;
1243 }
1244 /* query for data one more time */
1245 td->tmr_res = frame_num;
1246 td->did_nak = 0;
1247 return (0);
1248 busy:
1249 return (1);
1250 }
1251
1252 static uint8_t
dwc_otg_host_data_rx_sub(struct dwc_otg_softc * sc,struct dwc_otg_td * td,uint8_t channel)1253 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td,
1254 uint8_t channel)
1255 {
1256 uint32_t count;
1257
1258 /* check endpoint status */
1259 if (sc->sc_last_rx_status == 0)
1260 goto busy;
1261
1262 if (channel >= DWC_OTG_MAX_CHANNELS)
1263 goto busy;
1264
1265 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1266 goto busy;
1267
1268 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) {
1269 case GRXSTSRH_IN_DATA:
1270
1271 DPRINTF("DATA ST=%d STATUS=0x%08x\n",
1272 (int)td->state, (int)sc->sc_last_rx_status);
1273
1274 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1275 /*
1276 * When using SPLIT transactions on interrupt
1277 * endpoints, sometimes data occurs twice.
1278 */
1279 DPRINTF("Data already received\n");
1280 break;
1281 }
1282
1283 /* get the packet byte count */
1284 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1285
1286 /* check for ISOCHRONOUS endpoint */
1287 if (td->ep_type == UE_ISOCHRONOUS) {
1288 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1289 GRXSTSRD_DPID_DATA0) {
1290 /* more data to be received */
1291 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE;
1292 } else {
1293 /* all data received */
1294 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
1295 /* verify the packet byte count */
1296 if (count != td->remainder) {
1297 /* we have a short packet */
1298 td->short_pkt = 1;
1299 td->got_short = 1;
1300 }
1301 }
1302 } else {
1303 /* verify the packet byte count */
1304 if (count != td->max_packet_size) {
1305 if (count < td->max_packet_size) {
1306 /* we have a short packet */
1307 td->short_pkt = 1;
1308 td->got_short = 1;
1309 } else {
1310 /* invalid USB packet */
1311 td->error_any = 1;
1312
1313 /* release FIFO */
1314 dwc_otg_common_rx_ack(sc);
1315 goto complete;
1316 }
1317 }
1318 td->toggle ^= 1;
1319 td->tt_scheduled = 0;
1320 }
1321
1322 /* verify the packet byte count */
1323 if (count > td->remainder) {
1324 /* invalid USB packet */
1325 td->error_any = 1;
1326
1327 /* release FIFO */
1328 dwc_otg_common_rx_ack(sc);
1329 goto complete;
1330 }
1331
1332 /* read data from FIFO */
1333 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1334
1335 td->remainder -= count;
1336 td->offset += count;
1337 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1338 break;
1339 default:
1340 break;
1341 }
1342 /* release FIFO */
1343 dwc_otg_common_rx_ack(sc);
1344 busy:
1345 return (0);
1346 complete:
1347 return (1);
1348 }
1349
1350 static uint8_t
dwc_otg_host_data_rx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)1351 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1352 {
1353 uint32_t hcint = 0;
1354 uint32_t hcchar;
1355 uint8_t delta;
1356 uint8_t channel;
1357 uint8_t x;
1358
1359 for (x = 0; x != td->max_packet_count; x++) {
1360 channel = td->channel[x];
1361 if (channel >= DWC_OTG_MAX_CHANNELS)
1362 continue;
1363 hcint |= sc->sc_chan_state[channel].hcint;
1364
1365 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1366 channel, td->state, hcint,
1367 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1368 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1369
1370 /* check interrupt bits */
1371 if (hcint & (HCINT_RETRY |
1372 HCINT_ACK | HCINT_NYET)) {
1373 /* give success bits priority over failure bits */
1374 } else if (hcint & HCINT_STALL) {
1375 DPRINTF("CH=%d STALL\n", channel);
1376 td->error_stall = 1;
1377 td->error_any = 1;
1378 goto complete;
1379 } else if (hcint & HCINT_ERRORS) {
1380 DPRINTF("CH=%d ERROR\n", channel);
1381 td->errcnt++;
1382 if (td->hcsplt != 0 || td->errcnt >= 3) {
1383 if (td->ep_type != UE_ISOCHRONOUS) {
1384 td->error_any = 1;
1385 goto complete;
1386 }
1387 }
1388 }
1389
1390 /* check channels for data, if any */
1391 if (dwc_otg_host_data_rx_sub(sc, td, channel))
1392 goto complete;
1393
1394 /* refresh interrupt status */
1395 hcint |= sc->sc_chan_state[channel].hcint;
1396
1397 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1398 HCINT_ACK | HCINT_NYET)) {
1399 if (!(hcint & HCINT_ERRORS))
1400 td->errcnt = 0;
1401 }
1402 }
1403
1404 switch (td->state) {
1405 case DWC_CHAN_ST_START:
1406 if (td->hcsplt != 0)
1407 goto receive_spkt;
1408 else
1409 goto receive_pkt;
1410
1411 case DWC_CHAN_ST_WAIT_ANE:
1412 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1413 if (td->ep_type == UE_INTERRUPT) {
1414 /*
1415 * The USB specification does not
1416 * mandate a particular data toggle
1417 * value for USB INTERRUPT
1418 * transfers. Switch the data toggle
1419 * value to receive the packet
1420 * correctly:
1421 */
1422 if (hcint & HCINT_DATATGLERR) {
1423 DPRINTF("Retrying packet due to "
1424 "data toggle error\n");
1425 td->toggle ^= 1;
1426 goto receive_pkt;
1427 }
1428 } else if (td->ep_type == UE_ISOCHRONOUS) {
1429 if (td->hcsplt != 0) {
1430 /*
1431 * Sometimes the complete
1432 * split packet may be queued
1433 * too early and the
1434 * transaction translator will
1435 * return a NAK. Ignore
1436 * this message and retry the
1437 * complete split instead.
1438 */
1439 DPRINTF("Retrying complete split\n");
1440 goto receive_pkt;
1441 }
1442 goto complete;
1443 }
1444 td->did_nak = 1;
1445 td->tt_scheduled = 0;
1446 if (td->hcsplt != 0)
1447 goto receive_spkt;
1448 else
1449 goto receive_pkt;
1450 } else if (hcint & HCINT_NYET) {
1451 if (td->hcsplt != 0) {
1452 /* try again */
1453 goto receive_pkt;
1454 } else {
1455 /* not a valid token for IN endpoints */
1456 td->error_any = 1;
1457 goto complete;
1458 }
1459 } else if (hcint & HCINT_ACK) {
1460 /* wait for data - ACK arrived first */
1461 if (!(hcint & HCINT_SOFTWARE_ONLY))
1462 goto busy;
1463
1464 if (td->ep_type == UE_ISOCHRONOUS) {
1465 /* check if we are complete */
1466 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) {
1467 goto complete;
1468 } else if (td->hcsplt != 0) {
1469 goto receive_pkt;
1470 } else {
1471 /* get more packets */
1472 goto busy;
1473 }
1474 } else {
1475 /* check if we are complete */
1476 if ((td->remainder == 0) || (td->got_short != 0)) {
1477 if (td->short_pkt)
1478 goto complete;
1479
1480 /*
1481 * Else need to receive a zero length
1482 * packet.
1483 */
1484 }
1485 td->tt_scheduled = 0;
1486 td->did_nak = 0;
1487 if (td->hcsplt != 0)
1488 goto receive_spkt;
1489 else
1490 goto receive_pkt;
1491 }
1492 }
1493 break;
1494
1495 case DWC_CHAN_ST_WAIT_S_ANE:
1496 /*
1497 * NOTE: The DWC OTG hardware provides a fake ACK in
1498 * case of interrupt and isochronous transfers:
1499 */
1500 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1501 td->did_nak = 1;
1502 td->tt_scheduled = 0;
1503 goto receive_spkt;
1504 } else if (hcint & HCINT_NYET) {
1505 td->tt_scheduled = 0;
1506 goto receive_spkt;
1507 } else if (hcint & HCINT_ACK) {
1508 td->did_nak = 0;
1509 goto receive_pkt;
1510 }
1511 break;
1512
1513 case DWC_CHAN_ST_WAIT_C_PKT:
1514 goto receive_pkt;
1515
1516 default:
1517 break;
1518 }
1519 goto busy;
1520
1521 receive_pkt:
1522 /* free existing channel, if any */
1523 dwc_otg_host_channel_free(sc, td);
1524
1525 if (td->hcsplt != 0) {
1526 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1527 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1528 if (td->ep_type != UE_ISOCHRONOUS) {
1529 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1530 goto busy;
1531 }
1532 }
1533 delta = sc->sc_last_frame_num - td->tt_start_slot;
1534 if (delta > DWC_OTG_TT_SLOT_MAX) {
1535 if (td->ep_type != UE_ISOCHRONOUS) {
1536 /* we missed the service interval */
1537 td->error_any = 1;
1538 }
1539 goto complete;
1540 }
1541 /* complete split */
1542 td->hcsplt |= HCSPLT_COMPSPLT;
1543 } else if (dwc_otg_host_rate_check(sc, td)) {
1544 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1545 goto busy;
1546 }
1547
1548 /* allocate a new channel */
1549 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1550 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1551 goto busy;
1552 }
1553
1554 /* set toggle, if any */
1555 if (td->set_toggle) {
1556 td->set_toggle = 0;
1557 td->toggle = 1;
1558 }
1559
1560 td->state = DWC_CHAN_ST_WAIT_ANE;
1561
1562 for (x = 0; x != td->max_packet_count; x++) {
1563 channel = td->channel[x];
1564
1565 /* receive one packet */
1566 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1567 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) |
1568 (1 << HCTSIZ_PKTCNT_SHIFT) |
1569 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1570 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1571
1572 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1573
1574 hcchar = td->hcchar;
1575 hcchar |= HCCHAR_EPDIR_IN;
1576
1577 if (td->ep_type == UE_ISOCHRONOUS) {
1578 if (td->hcsplt != 0) {
1579 /* continously buffer */
1580 if (sc->sc_last_frame_num & 1)
1581 hcchar &= ~HCCHAR_ODDFRM;
1582 else
1583 hcchar |= HCCHAR_ODDFRM;
1584 } else {
1585 /* multi buffer, if any */
1586 if (sc->sc_last_frame_num & 1)
1587 hcchar |= HCCHAR_ODDFRM;
1588 else
1589 hcchar &= ~HCCHAR_ODDFRM;
1590 }
1591 } else {
1592 hcchar &= ~HCCHAR_ODDFRM;
1593 }
1594
1595 /* must enable channel before data can be received */
1596 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1597 }
1598 /* wait until next slot before trying complete split */
1599 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1600
1601 goto busy;
1602
1603 receive_spkt:
1604 /* free existing channel(s), if any */
1605 dwc_otg_host_channel_free(sc, td);
1606
1607 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1608 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1609 td->state = DWC_CHAN_ST_START;
1610 goto busy;
1611 }
1612 delta = sc->sc_last_frame_num - td->tt_start_slot;
1613 if (delta > 5) {
1614 /* missed it */
1615 td->tt_scheduled = 0;
1616 td->state = DWC_CHAN_ST_START;
1617 goto busy;
1618 }
1619
1620 /* allocate a new channel */
1621 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1622 td->state = DWC_CHAN_ST_START;
1623 goto busy;
1624 }
1625
1626 channel = td->channel[0];
1627
1628 td->hcsplt &= ~HCSPLT_COMPSPLT;
1629 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1630
1631 /* receive one packet */
1632 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1633 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1634
1635 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1636
1637 /* send after next SOF event */
1638 if ((sc->sc_last_frame_num & 1) == 0 &&
1639 td->ep_type == UE_ISOCHRONOUS)
1640 td->hcchar |= HCCHAR_ODDFRM;
1641 else
1642 td->hcchar &= ~HCCHAR_ODDFRM;
1643
1644 hcchar = td->hcchar;
1645 hcchar |= HCCHAR_EPDIR_IN;
1646
1647 /* wait until next slot before trying complete split */
1648 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1649
1650 /* must enable channel before data can be received */
1651 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1652 busy:
1653 return (1); /* busy */
1654
1655 complete:
1656 dwc_otg_host_channel_free(sc, td);
1657 return (0); /* complete */
1658 }
1659
1660 static uint8_t
dwc_otg_data_rx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)1661 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1662 {
1663 uint32_t temp;
1664 uint16_t count;
1665 uint8_t got_short;
1666
1667 got_short = 0;
1668
1669 /* check endpoint status */
1670 if (sc->sc_last_rx_status == 0)
1671 goto not_complete;
1672
1673 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
1674 goto not_complete;
1675
1676 /* check for SETUP packet */
1677 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1678 GRXSTSRD_STP_DATA ||
1679 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1680 GRXSTSRD_STP_COMPLETE) {
1681 if (td->remainder == 0) {
1682 /*
1683 * We are actually complete and have
1684 * received the next SETUP
1685 */
1686 DPRINTFN(5, "faking complete\n");
1687 return (0); /* complete */
1688 }
1689 /*
1690 * USB Host Aborted the transfer.
1691 */
1692 td->error_any = 1;
1693 return (0); /* complete */
1694 }
1695
1696 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1697 GRXSTSRD_OUT_DATA) {
1698 /* release FIFO */
1699 dwc_otg_common_rx_ack(sc);
1700 goto not_complete;
1701 }
1702
1703 /* get the packet byte count */
1704 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1705
1706 /* verify the packet byte count */
1707 if (count != td->max_packet_size) {
1708 if (count < td->max_packet_size) {
1709 /* we have a short packet */
1710 td->short_pkt = 1;
1711 got_short = 1;
1712 } else {
1713 /* invalid USB packet */
1714 td->error_any = 1;
1715
1716 /* release FIFO */
1717 dwc_otg_common_rx_ack(sc);
1718 return (0); /* we are complete */
1719 }
1720 }
1721 /* verify the packet byte count */
1722 if (count > td->remainder) {
1723 /* invalid USB packet */
1724 td->error_any = 1;
1725
1726 /* release FIFO */
1727 dwc_otg_common_rx_ack(sc);
1728 return (0); /* we are complete */
1729 }
1730
1731 /* read data from FIFO */
1732 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1733
1734 td->remainder -= count;
1735 td->offset += count;
1736
1737 /* release FIFO */
1738 dwc_otg_common_rx_ack(sc);
1739
1740 temp = sc->sc_out_ctl[td->ep_no];
1741
1742 /* check for isochronous mode */
1743 if ((temp & DIEPCTL_EPTYPE_MASK) ==
1744 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
1745 /* toggle odd or even frame bit */
1746 if (temp & DIEPCTL_SETD1PID) {
1747 temp &= ~DIEPCTL_SETD1PID;
1748 temp |= DIEPCTL_SETD0PID;
1749 } else {
1750 temp &= ~DIEPCTL_SETD0PID;
1751 temp |= DIEPCTL_SETD1PID;
1752 }
1753 sc->sc_out_ctl[td->ep_no] = temp;
1754 }
1755
1756 /* check if we are complete */
1757 if ((td->remainder == 0) || got_short) {
1758 if (td->short_pkt) {
1759 /* we are complete */
1760 return (0);
1761 }
1762 /* else need to receive a zero length packet */
1763 }
1764
1765 not_complete:
1766
1767 /* enable SETUP and transfer complete interrupt */
1768 if (td->ep_no == 0) {
1769 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
1770 DXEPTSIZ_SET_MULTI(3) |
1771 DXEPTSIZ_SET_NPKT(1) |
1772 DXEPTSIZ_SET_NBYTES(td->max_packet_size));
1773 } else {
1774 /* allow reception of multiple packets */
1775 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
1776 DXEPTSIZ_SET_MULTI(1) |
1777 DXEPTSIZ_SET_NPKT(4) |
1778 DXEPTSIZ_SET_NBYTES(4 *
1779 ((td->max_packet_size + 3) & ~3)));
1780 }
1781 temp = sc->sc_out_ctl[td->ep_no];
1782 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
1783 DOEPCTL_EPENA | DOEPCTL_CNAK);
1784
1785 return (1); /* not complete */
1786 }
1787
1788 static uint8_t
dwc_otg_host_data_tx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)1789 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1790 {
1791 uint32_t count;
1792 uint32_t hcint;
1793 uint32_t hcchar;
1794 uint8_t delta;
1795 uint8_t channel;
1796 uint8_t x;
1797
1798 dwc_otg_host_dump_rx(sc, td);
1799
1800 /* check that last channel is complete */
1801 channel = td->channel[td->npkt];
1802
1803 if (channel < DWC_OTG_MAX_CHANNELS) {
1804 hcint = sc->sc_chan_state[channel].hcint;
1805
1806 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1807 channel, td->state, hcint,
1808 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1809 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1810
1811 if (hcint & (HCINT_RETRY |
1812 HCINT_ACK | HCINT_NYET)) {
1813 /* give success bits priority over failure bits */
1814 } else if (hcint & HCINT_STALL) {
1815 DPRINTF("CH=%d STALL\n", channel);
1816 td->error_stall = 1;
1817 td->error_any = 1;
1818 goto complete;
1819 } else if (hcint & HCINT_ERRORS) {
1820 DPRINTF("CH=%d ERROR\n", channel);
1821 td->errcnt++;
1822 if (td->hcsplt != 0 || td->errcnt >= 3) {
1823 td->error_any = 1;
1824 goto complete;
1825 }
1826 }
1827
1828 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1829 HCINT_ACK | HCINT_NYET)) {
1830 if (!(hcint & HCINT_ERRORS))
1831 td->errcnt = 0;
1832 }
1833 } else {
1834 hcint = 0;
1835 }
1836
1837 switch (td->state) {
1838 case DWC_CHAN_ST_START:
1839 goto send_pkt;
1840
1841 case DWC_CHAN_ST_WAIT_ANE:
1842 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1843 td->did_nak = 1;
1844 td->tt_scheduled = 0;
1845 goto send_pkt;
1846 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1847 td->offset += td->tx_bytes;
1848 td->remainder -= td->tx_bytes;
1849 td->toggle ^= 1;
1850 /* check if next response will be a NAK */
1851 if (hcint & HCINT_NYET)
1852 td->did_nak = 1;
1853 else
1854 td->did_nak = 0;
1855 td->tt_scheduled = 0;
1856
1857 /* check remainder */
1858 if (td->remainder == 0) {
1859 if (td->short_pkt)
1860 goto complete;
1861
1862 /*
1863 * Else we need to transmit a short
1864 * packet:
1865 */
1866 }
1867 goto send_pkt;
1868 }
1869 break;
1870
1871 case DWC_CHAN_ST_WAIT_S_ANE:
1872 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1873 td->did_nak = 1;
1874 td->tt_scheduled = 0;
1875 goto send_pkt;
1876 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1877 td->did_nak = 0;
1878 goto send_cpkt;
1879 }
1880 break;
1881
1882 case DWC_CHAN_ST_WAIT_C_ANE:
1883 if (hcint & HCINT_NYET) {
1884 goto send_cpkt;
1885 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1886 td->did_nak = 1;
1887 td->tt_scheduled = 0;
1888 goto send_pkt;
1889 } else if (hcint & HCINT_ACK) {
1890 td->offset += td->tx_bytes;
1891 td->remainder -= td->tx_bytes;
1892 td->toggle ^= 1;
1893 td->did_nak = 0;
1894 td->tt_scheduled = 0;
1895
1896 /* check remainder */
1897 if (td->remainder == 0) {
1898 if (td->short_pkt)
1899 goto complete;
1900
1901 /* else we need to transmit a short packet */
1902 }
1903 goto send_pkt;
1904 }
1905 break;
1906
1907 case DWC_CHAN_ST_WAIT_C_PKT:
1908 goto send_cpkt;
1909
1910 case DWC_CHAN_ST_TX_WAIT_ISOC:
1911 /* Check if ISOCHRONOUS OUT traffic is complete */
1912 if ((hcint & HCINT_HCH_DONE_MASK) == 0)
1913 break;
1914
1915 td->offset += td->tx_bytes;
1916 td->remainder -= td->tx_bytes;
1917 goto complete;
1918 default:
1919 break;
1920 }
1921 goto busy;
1922
1923 send_pkt:
1924 /* free existing channel(s), if any */
1925 dwc_otg_host_channel_free(sc, td);
1926
1927 if (td->hcsplt != 0) {
1928 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1929 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1930 td->state = DWC_CHAN_ST_START;
1931 goto busy;
1932 }
1933 delta = sc->sc_last_frame_num - td->tt_start_slot;
1934 if (delta > 5) {
1935 /* missed it */
1936 td->tt_scheduled = 0;
1937 td->state = DWC_CHAN_ST_START;
1938 goto busy;
1939 }
1940 } else if (dwc_otg_host_rate_check(sc, td)) {
1941 td->state = DWC_CHAN_ST_START;
1942 goto busy;
1943 }
1944
1945 /* allocate a new channel */
1946 if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1947 td->state = DWC_CHAN_ST_START;
1948 goto busy;
1949 }
1950
1951 /* set toggle, if any */
1952 if (td->set_toggle) {
1953 td->set_toggle = 0;
1954 td->toggle = 1;
1955 }
1956
1957 if (td->ep_type == UE_ISOCHRONOUS) {
1958 /* ISOCHRONOUS OUT transfers don't have any ACKs */
1959 td->state = DWC_CHAN_ST_TX_WAIT_ISOC;
1960 td->hcsplt &= ~HCSPLT_COMPSPLT;
1961 if (td->hcsplt != 0) {
1962 /* get maximum transfer length */
1963 count = td->remainder;
1964 if (count > HCSPLT_XACTLEN_BURST) {
1965 DPRINTF("TT overflow\n");
1966 td->error_any = 1;
1967 goto complete;
1968 }
1969 /* Update transaction position */
1970 td->hcsplt &= ~HCSPLT_XACTPOS_MASK;
1971 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT);
1972 }
1973 } else if (td->hcsplt != 0) {
1974 td->hcsplt &= ~HCSPLT_COMPSPLT;
1975 /* Wait for ACK/NAK/ERR from TT */
1976 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1977 } else {
1978 /* Wait for ACK/NAK/STALL from device */
1979 td->state = DWC_CHAN_ST_WAIT_ANE;
1980 }
1981
1982 td->tx_bytes = 0;
1983
1984 for (x = 0; x != td->max_packet_count; x++) {
1985 uint32_t rem_bytes;
1986
1987 channel = td->channel[x];
1988
1989 /* send one packet at a time */
1990 count = td->max_packet_size;
1991 rem_bytes = td->remainder - td->tx_bytes;
1992 if (rem_bytes < count) {
1993 /* we have a short packet */
1994 td->short_pkt = 1;
1995 count = rem_bytes;
1996 }
1997 if (count == rem_bytes) {
1998 /* last packet */
1999 switch (x) {
2000 case 0:
2001 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2002 (count << HCTSIZ_XFERSIZE_SHIFT) |
2003 (1 << HCTSIZ_PKTCNT_SHIFT) |
2004 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2005 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2006 break;
2007 case 1:
2008 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2009 (count << HCTSIZ_XFERSIZE_SHIFT) |
2010 (1 << HCTSIZ_PKTCNT_SHIFT) |
2011 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT));
2012 break;
2013 default:
2014 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2015 (count << HCTSIZ_XFERSIZE_SHIFT) |
2016 (1 << HCTSIZ_PKTCNT_SHIFT) |
2017 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT));
2018 break;
2019 }
2020 } else if (td->ep_type == UE_ISOCHRONOUS &&
2021 td->max_packet_count > 1) {
2022 /* ISOCHRONOUS multi packet */
2023 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2024 (count << HCTSIZ_XFERSIZE_SHIFT) |
2025 (1 << HCTSIZ_PKTCNT_SHIFT) |
2026 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT));
2027 } else {
2028 /* TODO: HCTSIZ_DOPNG */
2029 /* standard BULK/INTERRUPT/CONTROL packet */
2030 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2031 (count << HCTSIZ_XFERSIZE_SHIFT) |
2032 (1 << HCTSIZ_PKTCNT_SHIFT) |
2033 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2034 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2035 }
2036
2037 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2038
2039 hcchar = td->hcchar;
2040 hcchar &= ~HCCHAR_EPDIR_IN;
2041
2042 /* send after next SOF event */
2043 if ((sc->sc_last_frame_num & 1) == 0 &&
2044 td->ep_type == UE_ISOCHRONOUS)
2045 hcchar |= HCCHAR_ODDFRM;
2046 else
2047 hcchar &= ~HCCHAR_ODDFRM;
2048
2049 /* must enable before writing data to FIFO */
2050 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2051
2052 if (count != 0) {
2053 /* write data into FIFO */
2054 dwc_otg_write_fifo(sc, td->pc, td->offset +
2055 td->tx_bytes, DOTG_DFIFO(channel), count);
2056 }
2057
2058 /* store number of bytes transmitted */
2059 td->tx_bytes += count;
2060
2061 /* store last packet index */
2062 td->npkt = x;
2063
2064 /* check for last packet */
2065 if (count == rem_bytes)
2066 break;
2067 }
2068 goto busy;
2069
2070 send_cpkt:
2071 /* free existing channel, if any */
2072 dwc_otg_host_channel_free(sc, td);
2073
2074 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
2075 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
2076 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2077 goto busy;
2078 }
2079 delta = sc->sc_last_frame_num - td->tt_start_slot;
2080 if (delta > DWC_OTG_TT_SLOT_MAX) {
2081 /* we missed the service interval */
2082 if (td->ep_type != UE_ISOCHRONOUS)
2083 td->error_any = 1;
2084 goto complete;
2085 }
2086
2087 /* allocate a new channel */
2088 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
2089 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2090 goto busy;
2091 }
2092
2093 channel = td->channel[0];
2094
2095 td->hcsplt |= HCSPLT_COMPSPLT;
2096 td->state = DWC_CHAN_ST_WAIT_C_ANE;
2097
2098 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2099 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
2100
2101 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2102
2103 hcchar = td->hcchar;
2104 hcchar &= ~HCCHAR_EPDIR_IN;
2105
2106 /* receive complete split ASAP */
2107 if ((sc->sc_last_frame_num & 1) != 0 &&
2108 td->ep_type == UE_ISOCHRONOUS)
2109 hcchar |= HCCHAR_ODDFRM;
2110 else
2111 hcchar &= ~HCCHAR_ODDFRM;
2112
2113 /* must enable channel before data can be received */
2114 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2115
2116 /* wait until next slot before trying complete split */
2117 td->tt_complete_slot = sc->sc_last_frame_num + 1;
2118 busy:
2119 return (1); /* busy */
2120
2121 complete:
2122 dwc_otg_host_channel_free(sc, td);
2123 return (0); /* complete */
2124 }
2125
2126 static uint8_t
dwc_otg_data_tx(struct dwc_otg_softc * sc,struct dwc_otg_td * td)2127 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2128 {
2129 uint32_t max_buffer;
2130 uint32_t count;
2131 uint32_t fifo_left;
2132 uint32_t mpkt;
2133 uint32_t temp;
2134 uint8_t to;
2135
2136 to = 3; /* don't loop forever! */
2137
2138 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer;
2139
2140 repeat:
2141 /* check for endpoint 0 data */
2142
2143 temp = sc->sc_last_rx_status;
2144
2145 if ((td->ep_no == 0) && (temp != 0) &&
2146 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2147 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2148 GRXSTSRD_STP_DATA &&
2149 (temp & GRXSTSRD_PKTSTS_MASK) !=
2150 GRXSTSRD_STP_COMPLETE) {
2151 /* dump data - wrong direction */
2152 dwc_otg_common_rx_ack(sc);
2153 } else {
2154 /*
2155 * The current transfer was cancelled
2156 * by the USB Host:
2157 */
2158 td->error_any = 1;
2159 return (0); /* complete */
2160 }
2161 }
2162
2163 /* fill in more TX data, if possible */
2164 if (td->tx_bytes != 0) {
2165 uint16_t cpkt;
2166
2167 /* check if packets have been transferred */
2168 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2169
2170 /* get current packet number */
2171 cpkt = DXEPTSIZ_GET_NPKT(temp);
2172
2173 if (cpkt >= td->npkt) {
2174 fifo_left = 0;
2175 } else {
2176 if (max_buffer != 0) {
2177 fifo_left = (td->npkt - cpkt) *
2178 td->max_packet_size;
2179
2180 if (fifo_left > max_buffer)
2181 fifo_left = max_buffer;
2182 } else {
2183 fifo_left = td->max_packet_size;
2184 }
2185 }
2186
2187 count = td->tx_bytes;
2188 if (count > fifo_left)
2189 count = fifo_left;
2190
2191 if (count != 0) {
2192 /* write data into FIFO */
2193 dwc_otg_write_fifo(sc, td->pc, td->offset,
2194 DOTG_DFIFO(td->ep_no), count);
2195
2196 td->tx_bytes -= count;
2197 td->remainder -= count;
2198 td->offset += count;
2199 td->npkt = cpkt;
2200 }
2201 if (td->tx_bytes != 0)
2202 goto not_complete;
2203
2204 /* check remainder */
2205 if (td->remainder == 0) {
2206 if (td->short_pkt)
2207 return (0); /* complete */
2208
2209 /* else we need to transmit a short packet */
2210 }
2211 }
2212
2213 if (!to--)
2214 goto not_complete;
2215
2216 /* check if not all packets have been transferred */
2217 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2218
2219 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2220 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x "
2221 "DIEPCTL=0x%08x\n", td->ep_no,
2222 DXEPTSIZ_GET_NPKT(temp),
2223 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2224
2225 goto not_complete;
2226 }
2227
2228 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no);
2229
2230 /* try to optimise by sending more data */
2231 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) {
2232 /* send multiple packets at the same time */
2233 mpkt = max_buffer / td->max_packet_size;
2234
2235 if (mpkt > 0x3FE)
2236 mpkt = 0x3FE;
2237
2238 count = td->remainder;
2239 if (count > 0x7FFFFF)
2240 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size);
2241
2242 td->npkt = count / td->max_packet_size;
2243
2244 /*
2245 * NOTE: We could use 0x3FE instead of "mpkt" in the
2246 * check below to get more throughput, but then we
2247 * have a dependency towards non-generic chip features
2248 * to disable the TX-FIFO-EMPTY interrupts on a per
2249 * endpoint basis. Increase the maximum buffer size of
2250 * the IN endpoint to increase the performance.
2251 */
2252 if (td->npkt > mpkt) {
2253 td->npkt = mpkt;
2254 count = td->max_packet_size * mpkt;
2255 } else if ((count == 0) || (count % td->max_packet_size)) {
2256 /* we are transmitting a short packet */
2257 td->npkt++;
2258 td->short_pkt = 1;
2259 }
2260 } else {
2261 /* send one packet at a time */
2262 mpkt = 1;
2263 count = td->max_packet_size;
2264 if (td->remainder < count) {
2265 /* we have a short packet */
2266 td->short_pkt = 1;
2267 count = td->remainder;
2268 }
2269 td->npkt = 1;
2270 }
2271 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
2272 DXEPTSIZ_SET_MULTI(1) |
2273 DXEPTSIZ_SET_NPKT(td->npkt) |
2274 DXEPTSIZ_SET_NBYTES(count));
2275
2276 /* make room for buffering */
2277 td->npkt += mpkt;
2278
2279 temp = sc->sc_in_ctl[td->ep_no];
2280
2281 /* check for isochronous mode */
2282 if ((temp & DIEPCTL_EPTYPE_MASK) ==
2283 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
2284 /* toggle odd or even frame bit */
2285 if (temp & DIEPCTL_SETD1PID) {
2286 temp &= ~DIEPCTL_SETD1PID;
2287 temp |= DIEPCTL_SETD0PID;
2288 } else {
2289 temp &= ~DIEPCTL_SETD0PID;
2290 temp |= DIEPCTL_SETD1PID;
2291 }
2292 sc->sc_in_ctl[td->ep_no] = temp;
2293 }
2294
2295 /* must enable before writing data to FIFO */
2296 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2297 DIEPCTL_EPENA | DIEPCTL_CNAK);
2298
2299 td->tx_bytes = count;
2300
2301 /* check remainder */
2302 if (td->tx_bytes == 0 &&
2303 td->remainder == 0) {
2304 if (td->short_pkt)
2305 return (0); /* complete */
2306
2307 /* else we need to transmit a short packet */
2308 }
2309 goto repeat;
2310
2311 not_complete:
2312 return (1); /* not complete */
2313 }
2314
2315 static uint8_t
dwc_otg_data_tx_sync(struct dwc_otg_softc * sc,struct dwc_otg_td * td)2316 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2317 {
2318 uint32_t temp;
2319
2320 /*
2321 * If all packets are transferred we are complete:
2322 */
2323 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2324
2325 /* check that all packets have been transferred */
2326 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2327 DPRINTFN(5, "busy ep=%d\n", td->ep_no);
2328 goto not_complete;
2329 }
2330 return (0);
2331
2332 not_complete:
2333
2334 /* we only want to know if there is a SETUP packet or free IN packet */
2335
2336 temp = sc->sc_last_rx_status;
2337
2338 if ((td->ep_no == 0) && (temp != 0) &&
2339 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2340 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2341 GRXSTSRD_STP_DATA ||
2342 (temp & GRXSTSRD_PKTSTS_MASK) ==
2343 GRXSTSRD_STP_COMPLETE) {
2344 DPRINTFN(5, "faking complete\n");
2345 /*
2346 * Race condition: We are complete!
2347 */
2348 return (0);
2349 } else {
2350 /* dump data - wrong direction */
2351 dwc_otg_common_rx_ack(sc);
2352 }
2353 }
2354 return (1); /* not complete */
2355 }
2356
2357 static void
dwc_otg_xfer_do_fifo(struct dwc_otg_softc * sc,struct usb_xfer * xfer)2358 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2359 {
2360 struct dwc_otg_td *td;
2361 uint8_t toggle;
2362 uint8_t tmr_val;
2363 uint8_t tmr_res;
2364
2365 DPRINTFN(9, "\n");
2366
2367 td = xfer->td_transfer_cache;
2368 if (td == NULL)
2369 return;
2370
2371 while (1) {
2372 if ((td->func) (sc, td)) {
2373 /* operation in progress */
2374 break;
2375 }
2376 if (((void *)td) == xfer->td_transfer_last) {
2377 goto done;
2378 }
2379 if (td->error_any) {
2380 goto done;
2381 } else if (td->remainder > 0) {
2382 /*
2383 * We had a short transfer. If there is no alternate
2384 * next, stop processing !
2385 */
2386 if (!td->alt_next)
2387 goto done;
2388 }
2389
2390 /*
2391 * Fetch the next transfer descriptor and transfer
2392 * some flags to the next transfer descriptor
2393 */
2394 tmr_res = td->tmr_res;
2395 tmr_val = td->tmr_val;
2396 toggle = td->toggle;
2397 td = td->obj_next;
2398 xfer->td_transfer_cache = td;
2399 td->toggle = toggle; /* transfer toggle */
2400 td->tmr_res = tmr_res;
2401 td->tmr_val = tmr_val;
2402 }
2403 return;
2404
2405 done:
2406 xfer->td_transfer_cache = NULL;
2407 sc->sc_xfer_complete = 1;
2408 }
2409
2410 static uint8_t
dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc * sc,struct usb_xfer * xfer)2411 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2412 {
2413 struct dwc_otg_td *td;
2414
2415 DPRINTFN(9, "\n");
2416
2417 td = xfer->td_transfer_cache;
2418 if (td == NULL) {
2419 /* compute all actual lengths */
2420 dwc_otg_standard_done(xfer);
2421 return (1);
2422 }
2423 return (0);
2424 }
2425
2426 static void
dwc_otg_timer(void * _sc)2427 dwc_otg_timer(void *_sc)
2428 {
2429 struct dwc_otg_softc *sc = _sc;
2430
2431 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2432
2433 DPRINTF("\n");
2434
2435 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2436
2437 /* increment timer value */
2438 sc->sc_tmr_val++;
2439
2440 /* enable SOF interrupt, which will poll jobs */
2441 dwc_otg_enable_sof_irq(sc);
2442
2443 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2444
2445 if (sc->sc_timer_active) {
2446 /* restart timer */
2447 usb_callout_reset(&sc->sc_timer,
2448 hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2449 &dwc_otg_timer, sc);
2450 }
2451 }
2452
2453 static void
dwc_otg_timer_start(struct dwc_otg_softc * sc)2454 dwc_otg_timer_start(struct dwc_otg_softc *sc)
2455 {
2456 if (sc->sc_timer_active != 0)
2457 return;
2458
2459 sc->sc_timer_active = 1;
2460
2461 /* restart timer */
2462 usb_callout_reset(&sc->sc_timer,
2463 hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2464 &dwc_otg_timer, sc);
2465 }
2466
2467 static void
dwc_otg_timer_stop(struct dwc_otg_softc * sc)2468 dwc_otg_timer_stop(struct dwc_otg_softc *sc)
2469 {
2470 if (sc->sc_timer_active == 0)
2471 return;
2472
2473 sc->sc_timer_active = 0;
2474
2475 /* stop timer */
2476 usb_callout_stop(&sc->sc_timer);
2477 }
2478
2479 static uint16_t
dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info * pinfo)2480 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo)
2481 {
2482 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX)
2483 pinfo->slot_index++;
2484 return (pinfo->slot_index);
2485 }
2486
2487 static uint8_t
dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc * sc)2488 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc)
2489 {
2490 TAILQ_HEAD(, usb_xfer) head;
2491 struct usb_xfer *xfer;
2492 struct usb_xfer *xfer_next;
2493 struct dwc_otg_td *td;
2494 uint16_t temp;
2495 uint16_t slot;
2496
2497 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2498
2499 if (sc->sc_last_frame_num == temp)
2500 return (0);
2501
2502 sc->sc_last_frame_num = temp;
2503
2504 TAILQ_INIT(&head);
2505
2506 if ((temp & 7) == 0) {
2507 /* reset the schedule */
2508 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info));
2509
2510 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2511 td = xfer->td_transfer_cache;
2512 if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2513 continue;
2514
2515 /* check for IN direction */
2516 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0)
2517 continue;
2518
2519 sc->sc_needsof = 1;
2520
2521 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2522 continue;
2523
2524 /* compute slot */
2525 slot = dwc_otg_compute_isoc_rx_tt_slot(
2526 sc->sc_tt_info + td->tt_index);
2527 if (slot > 3) {
2528 /*
2529 * Not enough time to get complete
2530 * split executed.
2531 */
2532 continue;
2533 }
2534 /* Delayed start */
2535 td->tt_start_slot = temp + slot;
2536 td->tt_scheduled = 1;
2537 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2538 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2539 }
2540
2541 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2542 td = xfer->td_transfer_cache;
2543 if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2544 continue;
2545
2546 /* check for OUT direction */
2547 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0)
2548 continue;
2549
2550 sc->sc_needsof = 1;
2551
2552 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2553 continue;
2554
2555 /* Start ASAP */
2556 td->tt_start_slot = temp;
2557 td->tt_scheduled = 1;
2558 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2559 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2560 }
2561
2562 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2563 td = xfer->td_transfer_cache;
2564 if (td == NULL || td->ep_type != UE_INTERRUPT)
2565 continue;
2566
2567 if (td->tt_scheduled != 0) {
2568 sc->sc_needsof = 1;
2569 continue;
2570 }
2571
2572 if (dwc_otg_host_rate_check_interrupt(sc, td))
2573 continue;
2574
2575 if (td->hcsplt == 0) {
2576 sc->sc_needsof = 1;
2577 td->tt_scheduled = 1;
2578 continue;
2579 }
2580
2581 /* start ASAP */
2582 td->tt_start_slot = temp;
2583 sc->sc_needsof = 1;
2584 td->tt_scheduled = 1;
2585 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2586 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2587 }
2588
2589 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2590 td = xfer->td_transfer_cache;
2591 if (td == NULL ||
2592 td->ep_type != UE_CONTROL) {
2593 continue;
2594 }
2595
2596 sc->sc_needsof = 1;
2597
2598 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2599 continue;
2600
2601 /* start ASAP */
2602 td->tt_start_slot = temp;
2603 td->tt_scheduled = 1;
2604 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2605 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2606 }
2607 }
2608 if ((temp & 7) < 6) {
2609 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2610 td = xfer->td_transfer_cache;
2611 if (td == NULL ||
2612 td->ep_type != UE_BULK) {
2613 continue;
2614 }
2615
2616 sc->sc_needsof = 1;
2617
2618 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2619 continue;
2620
2621 /* start ASAP */
2622 td->tt_start_slot = temp;
2623 td->tt_scheduled = 1;
2624 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2625 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2626 }
2627 }
2628
2629 /* Put TT transfers in execution order at the end */
2630 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2631
2632 /* move all TT transfers in front, keeping the current order */
2633 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2634 td = xfer->td_transfer_cache;
2635 if (td == NULL || td->hcsplt == 0)
2636 continue;
2637 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2638 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2639 }
2640 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry);
2641 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2642
2643 /* put non-TT non-ISOCHRONOUS transfers last */
2644 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2645 td = xfer->td_transfer_cache;
2646 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS)
2647 continue;
2648 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2649 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2650 }
2651 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2652
2653 if ((temp & 7) == 0) {
2654 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n",
2655 (int)temp, (int)sc->sc_needsof);
2656
2657 /* update SOF IRQ mask */
2658 if (sc->sc_irq_mask & GINTMSK_SOFMSK) {
2659 if (sc->sc_needsof == 0) {
2660 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2661 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2662 }
2663 } else {
2664 if (sc->sc_needsof != 0) {
2665 sc->sc_irq_mask |= GINTMSK_SOFMSK;
2666 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2667 }
2668 }
2669
2670 /* clear need SOF flag */
2671 sc->sc_needsof = 0;
2672 }
2673 return (1);
2674 }
2675
2676 static void
dwc_otg_interrupt_poll_locked(struct dwc_otg_softc * sc)2677 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc)
2678 {
2679 struct usb_xfer *xfer;
2680 uint32_t count;
2681 uint32_t temp;
2682 uint32_t haint;
2683 uint8_t got_rx_status;
2684 uint8_t x;
2685
2686 if (sc->sc_flags.status_device_mode == 0) {
2687 /*
2688 * Update host transfer schedule, so that new
2689 * transfers can be issued:
2690 */
2691 dwc_otg_update_host_transfer_schedule_locked(sc);
2692 }
2693 count = 0;
2694 repeat:
2695 if (++count == 16) {
2696 /* give other interrupts a chance */
2697 DPRINTF("Yield\n");
2698 return;
2699 }
2700
2701 /* get all host channel interrupts */
2702 haint = DWC_OTG_READ_4(sc, DOTG_HAINT);
2703 while (1) {
2704 x = ffs(haint) - 1;
2705 if (x >= sc->sc_host_ch_max)
2706 break;
2707 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2708 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2709 temp &= ~HCINT_SOFTWARE_ONLY;
2710 sc->sc_chan_state[x].hcint |= temp;
2711 haint &= ~(1U << x);
2712 }
2713
2714 if (sc->sc_last_rx_status == 0) {
2715 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2716 if (temp & GINTSTS_RXFLVL) {
2717 /* pop current status */
2718 sc->sc_last_rx_status =
2719 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD);
2720 }
2721
2722 if (sc->sc_last_rx_status != 0) {
2723 uint8_t ep_no;
2724
2725 temp = sc->sc_last_rx_status &
2726 GRXSTSRD_PKTSTS_MASK;
2727
2728 /* non-data messages we simply skip */
2729 if (temp != GRXSTSRD_STP_DATA &&
2730 temp != GRXSTSRD_STP_COMPLETE &&
2731 temp != GRXSTSRD_OUT_DATA) {
2732 /* check for halted channel */
2733 if (temp == GRXSTSRH_HALTED) {
2734 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status);
2735 sc->sc_chan_state[ep_no].wait_halted = 0;
2736 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no);
2737 }
2738 /* store bytes and FIFO offset */
2739 sc->sc_current_rx_bytes = 0;
2740 sc->sc_current_rx_fifo = 0;
2741
2742 /* acknowledge status */
2743 dwc_otg_common_rx_ack(sc);
2744 goto repeat;
2745 }
2746
2747 temp = GRXSTSRD_BCNT_GET(
2748 sc->sc_last_rx_status);
2749 ep_no = GRXSTSRD_CHNUM_GET(
2750 sc->sc_last_rx_status);
2751
2752 /* store bytes and FIFO offset */
2753 sc->sc_current_rx_bytes = (temp + 3) & ~3;
2754 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no);
2755
2756 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2757
2758 /* check if we should dump the data */
2759 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2760 dwc_otg_common_rx_ack(sc);
2761 goto repeat;
2762 }
2763
2764 got_rx_status = 1;
2765
2766 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n",
2767 sc->sc_last_rx_status, ep_no,
2768 (sc->sc_last_rx_status >> 15) & 3,
2769 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
2770 (sc->sc_last_rx_status >> 17) & 15);
2771 } else {
2772 got_rx_status = 0;
2773 }
2774 } else {
2775 uint8_t ep_no;
2776
2777 ep_no = GRXSTSRD_CHNUM_GET(
2778 sc->sc_last_rx_status);
2779
2780 /* check if we should dump the data */
2781 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2782 dwc_otg_common_rx_ack(sc);
2783 goto repeat;
2784 }
2785
2786 got_rx_status = 1;
2787 }
2788
2789 /* execute FIFOs */
2790 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
2791 dwc_otg_xfer_do_fifo(sc, xfer);
2792
2793 if (got_rx_status) {
2794 /* check if data was consumed */
2795 if (sc->sc_last_rx_status == 0)
2796 goto repeat;
2797
2798 /* disable RX FIFO level interrupt */
2799 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK;
2800 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2801 }
2802 }
2803
2804 static void
dwc_otg_interrupt_complete_locked(struct dwc_otg_softc * sc)2805 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc)
2806 {
2807 struct usb_xfer *xfer;
2808 repeat:
2809 /* scan for completion events */
2810 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2811 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
2812 goto repeat;
2813 }
2814 }
2815
2816 static void
dwc_otg_vbus_interrupt(struct dwc_otg_softc * sc,uint8_t is_on)2817 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on)
2818 {
2819 DPRINTFN(5, "vbus = %u\n", is_on);
2820
2821 /*
2822 * If the USB host mode is forced, then assume VBUS is always
2823 * present else rely on the input to this function:
2824 */
2825 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) {
2826 if (!sc->sc_flags.status_vbus) {
2827 sc->sc_flags.status_vbus = 1;
2828
2829 /* complete root HUB interrupt endpoint */
2830
2831 dwc_otg_root_intr(sc);
2832 }
2833 } else {
2834 if (sc->sc_flags.status_vbus) {
2835 sc->sc_flags.status_vbus = 0;
2836 sc->sc_flags.status_bus_reset = 0;
2837 sc->sc_flags.status_suspend = 0;
2838 sc->sc_flags.change_suspend = 0;
2839 sc->sc_flags.change_connect = 1;
2840
2841 /* complete root HUB interrupt endpoint */
2842
2843 dwc_otg_root_intr(sc);
2844 }
2845 }
2846 }
2847
2848 int
dwc_otg_filter_interrupt(void * arg)2849 dwc_otg_filter_interrupt(void *arg)
2850 {
2851 struct dwc_otg_softc *sc = arg;
2852 int retval = FILTER_HANDLED;
2853 uint32_t status;
2854
2855 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2856
2857 /* read and clear interrupt status */
2858 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2859
2860 /* clear interrupts we are handling here */
2861 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ);
2862
2863 /* check for USB state change interrupts */
2864 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0)
2865 retval = FILTER_SCHEDULE_THREAD;
2866
2867 /* clear FIFO empty interrupts */
2868 if (status & sc->sc_irq_mask &
2869 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) {
2870 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
2871 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2872 }
2873 /* clear all IN endpoint interrupts */
2874 if (status & GINTSTS_IEPINT) {
2875 uint32_t temp;
2876 uint8_t x;
2877
2878 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
2879 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2880 /*
2881 * NOTE: Need to clear all interrupt bits,
2882 * because some appears to be unmaskable and
2883 * can cause an interrupt loop:
2884 */
2885 if (temp != 0)
2886 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp);
2887 }
2888 }
2889
2890 /* poll FIFOs, if any */
2891 dwc_otg_interrupt_poll_locked(sc);
2892
2893 if (sc->sc_xfer_complete != 0)
2894 retval = FILTER_SCHEDULE_THREAD;
2895
2896 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2897
2898 return (retval);
2899 }
2900
2901 void
dwc_otg_interrupt(void * arg)2902 dwc_otg_interrupt(void *arg)
2903 {
2904 struct dwc_otg_softc *sc = arg;
2905 uint32_t status;
2906
2907 USB_BUS_LOCK(&sc->sc_bus);
2908 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2909
2910 /* read and clear interrupt status */
2911 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2912
2913 /* clear interrupts we are handling here */
2914 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ);
2915
2916 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n",
2917 status, DWC_OTG_READ_4(sc, DOTG_HAINT),
2918 DWC_OTG_READ_4(sc, DOTG_HFNUM));
2919
2920 if (status & GINTSTS_USBRST) {
2921 /* set correct state */
2922 sc->sc_flags.status_device_mode = 1;
2923 sc->sc_flags.status_bus_reset = 0;
2924 sc->sc_flags.status_suspend = 0;
2925 sc->sc_flags.change_suspend = 0;
2926 sc->sc_flags.change_connect = 1;
2927
2928 /* Disable SOF interrupt */
2929 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2930 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2931
2932 /* complete root HUB interrupt endpoint */
2933 dwc_otg_root_intr(sc);
2934 }
2935
2936 /* check for any bus state change interrupts */
2937 if (status & GINTSTS_ENUMDONE) {
2938 uint32_t temp;
2939
2940 DPRINTFN(5, "end of reset\n");
2941
2942 /* set correct state */
2943 sc->sc_flags.status_device_mode = 1;
2944 sc->sc_flags.status_bus_reset = 1;
2945 sc->sc_flags.status_suspend = 0;
2946 sc->sc_flags.change_suspend = 0;
2947 sc->sc_flags.change_connect = 1;
2948 sc->sc_flags.status_low_speed = 0;
2949 sc->sc_flags.port_enabled = 1;
2950
2951 /* reset FIFOs */
2952 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE);
2953
2954 /* reset function address */
2955 dwc_otg_set_address(sc, 0);
2956
2957 /* figure out enumeration speed */
2958 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2959 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
2960 sc->sc_flags.status_high_speed = 1;
2961 else
2962 sc->sc_flags.status_high_speed = 0;
2963
2964 /*
2965 * Disable resume and SOF interrupt, and enable
2966 * suspend and RX frame interrupt:
2967 */
2968 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK);
2969 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
2970 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2971
2972 /* complete root HUB interrupt endpoint */
2973 dwc_otg_root_intr(sc);
2974 }
2975
2976 if (status & GINTSTS_PRTINT) {
2977 uint32_t hprt;
2978
2979 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT);
2980
2981 /* clear change bits */
2982 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & (
2983 HPRT_PRTPWR | HPRT_PRTENCHNG |
2984 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) |
2985 sc->sc_hprt_val);
2986
2987 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt);
2988
2989 sc->sc_flags.status_device_mode = 0;
2990
2991 if (hprt & HPRT_PRTCONNSTS)
2992 sc->sc_flags.status_bus_reset = 1;
2993 else
2994 sc->sc_flags.status_bus_reset = 0;
2995
2996 if ((hprt & HPRT_PRTENCHNG) &&
2997 (hprt & HPRT_PRTENA) == 0)
2998 sc->sc_flags.change_enabled = 1;
2999
3000 if (hprt & HPRT_PRTENA)
3001 sc->sc_flags.port_enabled = 1;
3002 else
3003 sc->sc_flags.port_enabled = 0;
3004
3005 if (hprt & HPRT_PRTOVRCURRCHNG)
3006 sc->sc_flags.change_over_current = 1;
3007
3008 if (hprt & HPRT_PRTOVRCURRACT)
3009 sc->sc_flags.port_over_current = 1;
3010 else
3011 sc->sc_flags.port_over_current = 0;
3012
3013 if (hprt & HPRT_PRTPWR)
3014 sc->sc_flags.port_powered = 1;
3015 else
3016 sc->sc_flags.port_powered = 0;
3017
3018 if (((hprt & HPRT_PRTSPD_MASK)
3019 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW)
3020 sc->sc_flags.status_low_speed = 1;
3021 else
3022 sc->sc_flags.status_low_speed = 0;
3023
3024 if (((hprt & HPRT_PRTSPD_MASK)
3025 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH)
3026 sc->sc_flags.status_high_speed = 1;
3027 else
3028 sc->sc_flags.status_high_speed = 0;
3029
3030 if (hprt & HPRT_PRTCONNDET)
3031 sc->sc_flags.change_connect = 1;
3032
3033 if (hprt & HPRT_PRTSUSP)
3034 dwc_otg_suspend_irq(sc);
3035 else
3036 dwc_otg_resume_irq(sc);
3037
3038 /* complete root HUB interrupt endpoint */
3039 dwc_otg_root_intr(sc);
3040
3041 /* update host frame interval */
3042 dwc_otg_update_host_frame_interval(sc);
3043 }
3044
3045 /*
3046 * If resume and suspend is set at the same time we interpret
3047 * that like RESUME. Resume is set when there is at least 3
3048 * milliseconds of inactivity on the USB BUS.
3049 */
3050 if (status & GINTSTS_WKUPINT) {
3051 DPRINTFN(5, "resume interrupt\n");
3052
3053 dwc_otg_resume_irq(sc);
3054
3055 } else if (status & GINTSTS_USBSUSP) {
3056 DPRINTFN(5, "suspend interrupt\n");
3057
3058 dwc_otg_suspend_irq(sc);
3059 }
3060 /* check VBUS */
3061 if (status & (GINTSTS_USBSUSP |
3062 GINTSTS_USBRST |
3063 GINTMSK_OTGINTMSK |
3064 GINTSTS_SESSREQINT)) {
3065 uint32_t temp;
3066
3067 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3068
3069 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
3070
3071 dwc_otg_vbus_interrupt(sc,
3072 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3073 }
3074
3075 if (sc->sc_xfer_complete != 0) {
3076 sc->sc_xfer_complete = 0;
3077
3078 /* complete FIFOs, if any */
3079 dwc_otg_interrupt_complete_locked(sc);
3080 }
3081 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3082 USB_BUS_UNLOCK(&sc->sc_bus);
3083 }
3084
3085 static void
dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp * temp)3086 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
3087 {
3088 struct dwc_otg_td *td;
3089
3090 /* get current Transfer Descriptor */
3091 td = temp->td_next;
3092 temp->td = td;
3093
3094 /* prepare for next TD */
3095 temp->td_next = td->obj_next;
3096
3097 /* fill out the Transfer Descriptor */
3098 td->func = temp->func;
3099 td->pc = temp->pc;
3100 td->offset = temp->offset;
3101 td->remainder = temp->len;
3102 td->tx_bytes = 0;
3103 td->error_any = 0;
3104 td->error_stall = 0;
3105 td->npkt = 0;
3106 td->did_stall = temp->did_stall;
3107 td->short_pkt = temp->short_pkt;
3108 td->alt_next = temp->setup_alt_next;
3109 td->set_toggle = 0;
3110 td->got_short = 0;
3111 td->did_nak = 0;
3112 td->channel[0] = DWC_OTG_MAX_CHANNELS;
3113 td->channel[1] = DWC_OTG_MAX_CHANNELS;
3114 td->channel[2] = DWC_OTG_MAX_CHANNELS;
3115 td->state = 0;
3116 td->errcnt = 0;
3117 td->tt_scheduled = 0;
3118 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
3119 }
3120
3121 static void
dwc_otg_setup_standard_chain(struct usb_xfer * xfer)3122 dwc_otg_setup_standard_chain(struct usb_xfer *xfer)
3123 {
3124 struct dwc_otg_std_temp temp;
3125 struct dwc_otg_td *td;
3126 uint32_t x;
3127 uint8_t need_sync;
3128 uint8_t is_host;
3129
3130 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
3131 xfer->address, UE_GET_ADDR(xfer->endpointno),
3132 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
3133
3134 temp.max_frame_size = xfer->max_frame_size;
3135
3136 td = xfer->td_start[0];
3137 xfer->td_transfer_first = td;
3138 xfer->td_transfer_cache = td;
3139
3140 /* setup temp */
3141
3142 temp.pc = NULL;
3143 temp.td = NULL;
3144 temp.td_next = xfer->td_start[0];
3145 temp.offset = 0;
3146 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3147 xfer->flags_int.isochronous_xfr;
3148 temp.did_stall = !xfer->flags_int.control_stall;
3149
3150 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
3151
3152 /* check if we should prepend a setup message */
3153
3154 if (xfer->flags_int.control_xfr) {
3155 if (xfer->flags_int.control_hdr) {
3156 if (is_host)
3157 temp.func = &dwc_otg_host_setup_tx;
3158 else
3159 temp.func = &dwc_otg_setup_rx;
3160
3161 temp.len = xfer->frlengths[0];
3162 temp.pc = xfer->frbuffers + 0;
3163 temp.short_pkt = temp.len ? 1 : 0;
3164
3165 /* check for last frame */
3166 if (xfer->nframes == 1) {
3167 /* no STATUS stage yet, SETUP is last */
3168 if (xfer->flags_int.control_act)
3169 temp.setup_alt_next = 0;
3170 }
3171
3172 dwc_otg_setup_standard_chain_sub(&temp);
3173 }
3174 x = 1;
3175 } else {
3176 x = 0;
3177 }
3178
3179 if (x != xfer->nframes) {
3180 if (xfer->endpointno & UE_DIR_IN) {
3181 if (is_host) {
3182 temp.func = &dwc_otg_host_data_rx;
3183 need_sync = 0;
3184 } else {
3185 temp.func = &dwc_otg_data_tx;
3186 need_sync = 1;
3187 }
3188 } else {
3189 if (is_host) {
3190 temp.func = &dwc_otg_host_data_tx;
3191 need_sync = 0;
3192 } else {
3193 temp.func = &dwc_otg_data_rx;
3194 need_sync = 0;
3195 }
3196 }
3197
3198 /* setup "pc" pointer */
3199 temp.pc = xfer->frbuffers + x;
3200 } else {
3201 need_sync = 0;
3202 }
3203 while (x != xfer->nframes) {
3204 /* DATA0 / DATA1 message */
3205
3206 temp.len = xfer->frlengths[x];
3207
3208 x++;
3209
3210 if (x == xfer->nframes) {
3211 if (xfer->flags_int.control_xfr) {
3212 if (xfer->flags_int.control_act) {
3213 temp.setup_alt_next = 0;
3214 }
3215 } else {
3216 temp.setup_alt_next = 0;
3217 }
3218 }
3219 if (temp.len == 0) {
3220 /* make sure that we send an USB packet */
3221
3222 temp.short_pkt = 0;
3223
3224 } else {
3225 /* regular data transfer */
3226
3227 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3228 }
3229
3230 dwc_otg_setup_standard_chain_sub(&temp);
3231
3232 if (xfer->flags_int.isochronous_xfr) {
3233 temp.offset += temp.len;
3234 } else {
3235 /* get next Page Cache pointer */
3236 temp.pc = xfer->frbuffers + x;
3237 }
3238 }
3239
3240 if (xfer->flags_int.control_xfr) {
3241 /* always setup a valid "pc" pointer for status and sync */
3242 temp.pc = xfer->frbuffers + 0;
3243 temp.len = 0;
3244 temp.short_pkt = 0;
3245 temp.setup_alt_next = 0;
3246
3247 /* check if we need to sync */
3248 if (need_sync) {
3249 /* we need a SYNC point after TX */
3250 temp.func = &dwc_otg_data_tx_sync;
3251 dwc_otg_setup_standard_chain_sub(&temp);
3252 }
3253
3254 /* check if we should append a status stage */
3255 if (!xfer->flags_int.control_act) {
3256 /*
3257 * Send a DATA1 message and invert the current
3258 * endpoint direction.
3259 */
3260 if (xfer->endpointno & UE_DIR_IN) {
3261 if (is_host) {
3262 temp.func = &dwc_otg_host_data_tx;
3263 need_sync = 0;
3264 } else {
3265 temp.func = &dwc_otg_data_rx;
3266 need_sync = 0;
3267 }
3268 } else {
3269 if (is_host) {
3270 temp.func = &dwc_otg_host_data_rx;
3271 need_sync = 0;
3272 } else {
3273 temp.func = &dwc_otg_data_tx;
3274 need_sync = 1;
3275 }
3276 }
3277
3278 dwc_otg_setup_standard_chain_sub(&temp);
3279
3280 /* data toggle should be DATA1 */
3281 td = temp.td;
3282 td->set_toggle = 1;
3283
3284 if (need_sync) {
3285 /* we need a SYNC point after TX */
3286 temp.func = &dwc_otg_data_tx_sync;
3287 dwc_otg_setup_standard_chain_sub(&temp);
3288 }
3289 }
3290 } else {
3291 /* check if we need to sync */
3292 if (need_sync) {
3293 temp.pc = xfer->frbuffers + 0;
3294 temp.len = 0;
3295 temp.short_pkt = 0;
3296 temp.setup_alt_next = 0;
3297
3298 /* we need a SYNC point after TX */
3299 temp.func = &dwc_otg_data_tx_sync;
3300 dwc_otg_setup_standard_chain_sub(&temp);
3301 }
3302 }
3303
3304 /* must have at least one frame! */
3305 td = temp.td;
3306 xfer->td_transfer_last = td;
3307
3308 if (is_host) {
3309 struct dwc_otg_softc *sc;
3310 uint32_t hcchar;
3311 uint32_t hcsplt;
3312
3313 sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3314
3315 /* get first again */
3316 td = xfer->td_transfer_first;
3317 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
3318
3319 hcchar =
3320 (xfer->address << HCCHAR_DEVADDR_SHIFT) |
3321 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) |
3322 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) |
3323 HCCHAR_CHENA;
3324
3325 /*
3326 * We are not always able to meet the timing
3327 * requirements of the USB interrupt endpoint's
3328 * complete split token, when doing transfers going
3329 * via a transaction translator. Use the CONTROL
3330 * transfer type instead of the INTERRUPT transfer
3331 * type in general, as a means to workaround
3332 * that. This trick should work for both FULL and LOW
3333 * speed USB traffic going through a TT. For non-TT
3334 * traffic it works as well. The reason for using
3335 * CONTROL type instead of BULK is that some TTs might
3336 * reject LOW speed BULK traffic.
3337 */
3338 if (td->ep_type == UE_INTERRUPT)
3339 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT);
3340 else
3341 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT);
3342
3343 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
3344 hcchar |= HCCHAR_EPDIR_IN;
3345
3346 switch (xfer->xroot->udev->speed) {
3347 case USB_SPEED_LOW:
3348 hcchar |= HCCHAR_LSPDDEV;
3349 /* FALLTHROUGH */
3350 case USB_SPEED_FULL:
3351 /* check if root HUB port is running High Speed */
3352 if (dwc_otg_uses_split(xfer->xroot->udev)) {
3353 hcsplt = HCSPLT_SPLTENA |
3354 (xfer->xroot->udev->hs_port_no <<
3355 HCSPLT_PRTADDR_SHIFT) |
3356 (xfer->xroot->udev->hs_hub_addr <<
3357 HCSPLT_HUBADDR_SHIFT);
3358 } else {
3359 hcsplt = 0;
3360 }
3361 if (td->ep_type == UE_INTERRUPT) {
3362 uint32_t ival;
3363 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3364 if (ival == 0)
3365 ival = 1;
3366 else if (ival > 127)
3367 ival = 127;
3368 td->tmr_val = sc->sc_tmr_val + ival;
3369 td->tmr_res = ival;
3370 } else if (td->ep_type == UE_ISOCHRONOUS) {
3371 td->tmr_res = 1;
3372 td->tmr_val = sc->sc_last_frame_num;
3373 if (td->hcchar & HCCHAR_EPDIR_IN)
3374 td->tmr_val++;
3375 } else {
3376 td->tmr_val = 0;
3377 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3378 }
3379 break;
3380 case USB_SPEED_HIGH:
3381 hcsplt = 0;
3382 if (td->ep_type == UE_INTERRUPT) {
3383 uint32_t ival;
3384 hcchar |= ((xfer->max_packet_count & 3)
3385 << HCCHAR_MC_SHIFT);
3386 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3387 if (ival == 0)
3388 ival = 1;
3389 else if (ival > 127)
3390 ival = 127;
3391 td->tmr_val = sc->sc_tmr_val + ival;
3392 td->tmr_res = ival;
3393 } else if (td->ep_type == UE_ISOCHRONOUS) {
3394 hcchar |= ((xfer->max_packet_count & 3)
3395 << HCCHAR_MC_SHIFT);
3396 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer);
3397 td->tmr_val = sc->sc_last_frame_num;
3398 if (td->hcchar & HCCHAR_EPDIR_IN)
3399 td->tmr_val += td->tmr_res;
3400
3401 } else {
3402 td->tmr_val = 0;
3403 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3404 }
3405 break;
3406 default:
3407 hcsplt = 0;
3408 td->tmr_val = 0;
3409 td->tmr_res = 0;
3410 break;
3411 }
3412
3413 /* store configuration in all TD's */
3414 while (1) {
3415 td->hcchar = hcchar;
3416 td->hcsplt = hcsplt;
3417
3418 if (((void *)td) == xfer->td_transfer_last)
3419 break;
3420
3421 td = td->obj_next;
3422 }
3423 }
3424 }
3425
3426 static void
dwc_otg_timeout(void * arg)3427 dwc_otg_timeout(void *arg)
3428 {
3429 struct usb_xfer *xfer = arg;
3430
3431 DPRINTF("xfer=%p\n", xfer);
3432
3433 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
3434
3435 /* transfer is transferred */
3436 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT);
3437 }
3438
3439 static void
dwc_otg_start_standard_chain(struct usb_xfer * xfer)3440 dwc_otg_start_standard_chain(struct usb_xfer *xfer)
3441 {
3442 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3443
3444 DPRINTFN(9, "\n");
3445
3446 /*
3447 * Poll one time in device mode, which will turn on the
3448 * endpoint interrupts. Else wait for SOF interrupt in host
3449 * mode.
3450 */
3451 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3452
3453 if (sc->sc_flags.status_device_mode != 0) {
3454 dwc_otg_xfer_do_fifo(sc, xfer);
3455 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3456 goto done;
3457 } else {
3458 struct dwc_otg_td *td = xfer->td_transfer_cache;
3459 if (td->ep_type == UE_ISOCHRONOUS &&
3460 (td->hcchar & HCCHAR_EPDIR_IN) == 0) {
3461 /*
3462 * Need to start ISOCHRONOUS OUT transfer ASAP
3463 * because execution is delayed by one 125us
3464 * microframe:
3465 */
3466 dwc_otg_xfer_do_fifo(sc, xfer);
3467 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3468 goto done;
3469 }
3470 }
3471
3472 /* put transfer on interrupt queue */
3473 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3474
3475 /* start timeout, if any */
3476 if (xfer->timeout != 0) {
3477 usbd_transfer_timeout_ms(xfer,
3478 &dwc_otg_timeout, xfer->timeout);
3479 }
3480
3481 if (sc->sc_flags.status_device_mode != 0)
3482 goto done;
3483
3484 /* enable SOF interrupt, if any */
3485 dwc_otg_enable_sof_irq(sc);
3486 done:
3487 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3488 }
3489
3490 static void
dwc_otg_root_intr(struct dwc_otg_softc * sc)3491 dwc_otg_root_intr(struct dwc_otg_softc *sc)
3492 {
3493 DPRINTFN(9, "\n");
3494
3495 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3496
3497 /* set port bit */
3498 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
3499
3500 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3501 sizeof(sc->sc_hub_idata));
3502 }
3503
3504 static usb_error_t
dwc_otg_standard_done_sub(struct usb_xfer * xfer)3505 dwc_otg_standard_done_sub(struct usb_xfer *xfer)
3506 {
3507 struct dwc_otg_td *td;
3508 uint32_t len;
3509 usb_error_t error;
3510
3511 DPRINTFN(9, "\n");
3512
3513 td = xfer->td_transfer_cache;
3514
3515 do {
3516 len = td->remainder;
3517
3518 /* store last data toggle */
3519 xfer->endpoint->toggle_next = td->toggle;
3520
3521 if (xfer->aframes != xfer->nframes) {
3522 /*
3523 * Verify the length and subtract
3524 * the remainder from "frlengths[]":
3525 */
3526 if (len > xfer->frlengths[xfer->aframes]) {
3527 td->error_any = 1;
3528 } else {
3529 xfer->frlengths[xfer->aframes] -= len;
3530 }
3531 }
3532 /* Check for transfer error */
3533 if (td->error_any) {
3534 /* the transfer is finished */
3535 error = (td->error_stall ?
3536 USB_ERR_STALLED : USB_ERR_IOERROR);
3537 td = NULL;
3538 break;
3539 }
3540 /* Check for short transfer */
3541 if (len > 0) {
3542 if (xfer->flags_int.short_frames_ok ||
3543 xfer->flags_int.isochronous_xfr) {
3544 /* follow alt next */
3545 if (td->alt_next) {
3546 td = td->obj_next;
3547 } else {
3548 td = NULL;
3549 }
3550 } else {
3551 /* the transfer is finished */
3552 td = NULL;
3553 }
3554 error = 0;
3555 break;
3556 }
3557 td = td->obj_next;
3558
3559 /* this USB frame is complete */
3560 error = 0;
3561 break;
3562
3563 } while (0);
3564
3565 /* update transfer cache */
3566
3567 xfer->td_transfer_cache = td;
3568
3569 return (error);
3570 }
3571
3572 static void
dwc_otg_standard_done(struct usb_xfer * xfer)3573 dwc_otg_standard_done(struct usb_xfer *xfer)
3574 {
3575 usb_error_t err = 0;
3576
3577 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
3578 xfer, xfer->endpoint);
3579
3580 /* reset scanner */
3581
3582 xfer->td_transfer_cache = xfer->td_transfer_first;
3583
3584 if (xfer->flags_int.control_xfr) {
3585 if (xfer->flags_int.control_hdr) {
3586 err = dwc_otg_standard_done_sub(xfer);
3587 }
3588 xfer->aframes = 1;
3589
3590 if (xfer->td_transfer_cache == NULL) {
3591 goto done;
3592 }
3593 }
3594 while (xfer->aframes != xfer->nframes) {
3595 err = dwc_otg_standard_done_sub(xfer);
3596 xfer->aframes++;
3597
3598 if (xfer->td_transfer_cache == NULL) {
3599 goto done;
3600 }
3601 }
3602
3603 if (xfer->flags_int.control_xfr &&
3604 !xfer->flags_int.control_act) {
3605 err = dwc_otg_standard_done_sub(xfer);
3606 }
3607 done:
3608 dwc_otg_device_done(xfer, err);
3609 }
3610
3611 /*------------------------------------------------------------------------*
3612 * dwc_otg_device_done
3613 *
3614 * NOTE: this function can be called more than one time on the
3615 * same USB transfer!
3616 *------------------------------------------------------------------------*/
3617 static void
dwc_otg_device_done(struct usb_xfer * xfer,usb_error_t error)3618 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
3619 {
3620 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3621
3622 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
3623 xfer, xfer->endpoint, error);
3624
3625 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3626
3627 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
3628 /* Interrupts are cleared by the interrupt handler */
3629 } else {
3630 struct dwc_otg_td *td;
3631
3632 td = xfer->td_transfer_cache;
3633 if (td != NULL)
3634 dwc_otg_host_channel_free(sc, td);
3635 }
3636 /* dequeue transfer and start next transfer */
3637 usbd_transfer_done(xfer, error);
3638
3639 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3640 }
3641
3642 static void
dwc_otg_xfer_stall(struct usb_xfer * xfer)3643 dwc_otg_xfer_stall(struct usb_xfer *xfer)
3644 {
3645 dwc_otg_device_done(xfer, USB_ERR_STALLED);
3646 }
3647
3648 static void
dwc_otg_set_stall(struct usb_device * udev,struct usb_endpoint * ep,uint8_t * did_stall)3649 dwc_otg_set_stall(struct usb_device *udev,
3650 struct usb_endpoint *ep, uint8_t *did_stall)
3651 {
3652 struct dwc_otg_softc *sc;
3653 uint32_t temp;
3654 uint32_t reg;
3655 uint8_t ep_no;
3656
3657 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3658
3659 /* check mode */
3660 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3661 /* not supported */
3662 return;
3663 }
3664
3665 sc = DWC_OTG_BUS2SC(udev->bus);
3666
3667 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3668
3669 /* get endpoint address */
3670 ep_no = ep->edesc->bEndpointAddress;
3671
3672 DPRINTFN(5, "endpoint=0x%x\n", ep_no);
3673
3674 if (ep_no & UE_DIR_IN) {
3675 reg = DOTG_DIEPCTL(ep_no & UE_ADDR);
3676 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3677 } else {
3678 reg = DOTG_DOEPCTL(ep_no & UE_ADDR);
3679 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3680 }
3681
3682 /* disable and stall endpoint */
3683 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3684 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3685
3686 /* clear active OUT ep */
3687 if (!(ep_no & UE_DIR_IN)) {
3688 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR));
3689
3690 if (sc->sc_last_rx_status != 0 &&
3691 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET(
3692 sc->sc_last_rx_status)) {
3693 /* dump data */
3694 dwc_otg_common_rx_ack(sc);
3695 /* poll interrupt */
3696 dwc_otg_interrupt_poll_locked(sc);
3697 dwc_otg_interrupt_complete_locked(sc);
3698 }
3699 }
3700 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3701 }
3702
3703 static void
dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc * sc,uint32_t mps,uint8_t ep_no,uint8_t ep_type,uint8_t ep_dir)3704 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps,
3705 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
3706 {
3707 uint32_t reg;
3708 uint32_t temp;
3709
3710 if (ep_type == UE_CONTROL) {
3711 /* clearing stall is not needed */
3712 return;
3713 }
3714
3715 if (ep_dir) {
3716 reg = DOTG_DIEPCTL(ep_no);
3717 } else {
3718 reg = DOTG_DOEPCTL(ep_no);
3719 sc->sc_active_rx_ep |= (1U << ep_no);
3720 }
3721
3722 /* round up and mask away the multiplier count */
3723 mps = (mps + 3) & 0x7FC;
3724
3725 if (ep_type == UE_BULK) {
3726 temp = DIEPCTL_EPTYPE_SET(
3727 DIEPCTL_EPTYPE_BULK) |
3728 DIEPCTL_USBACTEP;
3729 } else if (ep_type == UE_INTERRUPT) {
3730 temp = DIEPCTL_EPTYPE_SET(
3731 DIEPCTL_EPTYPE_INTERRUPT) |
3732 DIEPCTL_USBACTEP;
3733 } else {
3734 temp = DIEPCTL_EPTYPE_SET(
3735 DIEPCTL_EPTYPE_ISOC) |
3736 DIEPCTL_USBACTEP;
3737 }
3738
3739 temp |= DIEPCTL_MPS_SET(mps);
3740 temp |= DIEPCTL_TXFNUM_SET(ep_no);
3741
3742 if (ep_dir)
3743 sc->sc_in_ctl[ep_no] = temp;
3744 else
3745 sc->sc_out_ctl[ep_no] = temp;
3746
3747 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3748 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3749 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3750
3751 /* we only reset the transmit FIFO */
3752 if (ep_dir) {
3753 dwc_otg_tx_fifo_reset(sc,
3754 GRSTCTL_TXFIFO(ep_no) |
3755 GRSTCTL_TXFFLSH);
3756
3757 DWC_OTG_WRITE_4(sc,
3758 DOTG_DIEPTSIZ(ep_no), 0);
3759 }
3760
3761 /* poll interrupt */
3762 dwc_otg_interrupt_poll_locked(sc);
3763 dwc_otg_interrupt_complete_locked(sc);
3764 }
3765
3766 static void
dwc_otg_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)3767 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3768 {
3769 struct dwc_otg_softc *sc;
3770 struct usb_endpoint_descriptor *ed;
3771
3772 DPRINTFN(5, "endpoint=%p\n", ep);
3773
3774 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3775
3776 /* check mode */
3777 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3778 /* not supported */
3779 return;
3780 }
3781 /* get softc */
3782 sc = DWC_OTG_BUS2SC(udev->bus);
3783
3784 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3785
3786 /* get endpoint descriptor */
3787 ed = ep->edesc;
3788
3789 /* reset endpoint */
3790 dwc_otg_clear_stall_sub_locked(sc,
3791 UGETW(ed->wMaxPacketSize),
3792 (ed->bEndpointAddress & UE_ADDR),
3793 (ed->bmAttributes & UE_XFERTYPE),
3794 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3795
3796 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3797 }
3798
3799 static void
dwc_otg_device_state_change(struct usb_device * udev)3800 dwc_otg_device_state_change(struct usb_device *udev)
3801 {
3802 struct dwc_otg_softc *sc;
3803 uint8_t x;
3804
3805 /* check mode */
3806 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3807 /* not supported */
3808 return;
3809 }
3810
3811 /* get softc */
3812 sc = DWC_OTG_BUS2SC(udev->bus);
3813
3814 /* deactivate all other endpoint but the control endpoint */
3815 if (udev->state == USB_STATE_CONFIGURED ||
3816 udev->state == USB_STATE_ADDRESSED) {
3817 USB_BUS_LOCK(&sc->sc_bus);
3818
3819 for (x = 1; x != sc->sc_dev_ep_max; x++) {
3820 if (x < sc->sc_dev_in_ep_max) {
3821 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x),
3822 DIEPCTL_EPDIS);
3823 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0);
3824 }
3825
3826 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x),
3827 DOEPCTL_EPDIS);
3828 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0);
3829 }
3830 USB_BUS_UNLOCK(&sc->sc_bus);
3831 }
3832 }
3833
3834 int
dwc_otg_init(struct dwc_otg_softc * sc)3835 dwc_otg_init(struct dwc_otg_softc *sc)
3836 {
3837 uint32_t temp;
3838 int err;
3839
3840 DPRINTF("start\n");
3841
3842 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
3843 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
3844 sc->sc_io_size = rman_get_size(sc->sc_io_res);
3845
3846 /* set up the bus structure */
3847 sc->sc_bus.devices = sc->sc_devices;
3848 sc->sc_bus.devices_max = DWC_OTG_MAX_DEVICES;
3849 sc->sc_bus.dma_bits = 32;
3850 sc->sc_bus.usbrev = USB_REV_2_0;
3851 sc->sc_bus.methods = &dwc_otg_bus_methods;
3852
3853 /* get all DMA memory */
3854 if (usb_bus_mem_alloc_all(&sc->sc_bus,
3855 USB_GET_DMA_TAG(sc->sc_bus.parent), NULL)) {
3856 return (ENOMEM);
3857 }
3858
3859 sc->sc_bus.bdev = device_add_child(sc->sc_bus.parent, "usbus", -1);
3860 if (sc->sc_bus.bdev == NULL)
3861 return (ENXIO);
3862
3863 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
3864
3865 err = bus_setup_intr(sc->sc_bus.parent, sc->sc_irq_res,
3866 INTR_TYPE_TTY | INTR_MPSAFE, &dwc_otg_filter_interrupt,
3867 &dwc_otg_interrupt, sc, &sc->sc_intr_hdl);
3868 if (err) {
3869 sc->sc_intr_hdl = NULL;
3870 return (ENXIO);
3871 }
3872
3873 usb_callout_init_mtx(&sc->sc_timer,
3874 &sc->sc_bus.bus_mtx, 0);
3875
3876 USB_BUS_LOCK(&sc->sc_bus);
3877
3878 /* turn on clocks */
3879 dwc_otg_clocks_on(sc);
3880
3881 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3882 DPRINTF("Version = 0x%08x\n", temp);
3883
3884 /* disconnect */
3885 DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3886 DCTL_SFTDISCON);
3887
3888 /* wait for host to detect disconnect */
3889 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
3890
3891 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
3892 GRSTCTL_CSFTRST);
3893
3894 /* wait a little bit for block to reset */
3895 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
3896
3897 switch (sc->sc_mode) {
3898 case DWC_MODE_DEVICE:
3899 temp = GUSBCFG_FORCEDEVMODE;
3900 break;
3901 case DWC_MODE_HOST:
3902 temp = GUSBCFG_FORCEHOSTMODE;
3903 break;
3904 default:
3905 temp = 0;
3906 break;
3907 }
3908
3909 if (sc->sc_phy_type == 0)
3910 sc->sc_phy_type = dwc_otg_phy_type + 1;
3911 if (sc->sc_phy_bits == 0)
3912 sc->sc_phy_bits = 16;
3913
3914 /* select HSIC, ULPI, UTMI+ or internal PHY mode */
3915 switch (sc->sc_phy_type) {
3916 case DWC_OTG_PHY_HSIC:
3917 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3918 GUSBCFG_PHYIF |
3919 GUSBCFG_TRD_TIM_SET(5) | temp);
3920 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL,
3921 0x000000EC);
3922
3923 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3924 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3925 temp & ~GLPMCFG_HSIC_CONN);
3926 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3927 temp | GLPMCFG_HSIC_CONN);
3928 break;
3929 case DWC_OTG_PHY_ULPI:
3930 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3931 GUSBCFG_ULPI_UTMI_SEL |
3932 GUSBCFG_TRD_TIM_SET(5) | temp);
3933 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3934
3935 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3936 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3937 temp & ~GLPMCFG_HSIC_CONN);
3938 break;
3939 case DWC_OTG_PHY_UTMI:
3940 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3941 (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) |
3942 GUSBCFG_TRD_TIM_SET(5) | temp);
3943 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3944
3945 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3946 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3947 temp & ~GLPMCFG_HSIC_CONN);
3948 break;
3949 case DWC_OTG_PHY_INTERNAL:
3950 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3951 GUSBCFG_PHYSEL |
3952 GUSBCFG_TRD_TIM_SET(5) | temp);
3953 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3954
3955 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3956 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3957 temp & ~GLPMCFG_HSIC_CONN);
3958
3959 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3960 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3961 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3962 DOTG_GGPIO_PWRDWN);
3963 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3964 break;
3965 default:
3966 break;
3967 }
3968
3969 /* clear global nak */
3970 DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3971 DCTL_CGOUTNAK |
3972 DCTL_CGNPINNAK);
3973
3974 /* disable USB port */
3975 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF);
3976
3977 /* wait 10ms */
3978 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3979
3980 /* enable USB port */
3981 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
3982
3983 /* wait 10ms */
3984 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3985
3986 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3987
3988 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3989
3990 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3991
3992 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3993
3994 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS)
3995 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS;
3996
3997 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3998
3999 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS)
4000 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS;
4001
4002 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
4003
4004 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
4005
4006 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n",
4007 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max,
4008 sc->sc_host_ch_max);
4009
4010 /* setup FIFO */
4011 if (dwc_otg_init_fifo(sc, sc->sc_mode)) {
4012 USB_BUS_UNLOCK(&sc->sc_bus);
4013 return (EINVAL);
4014 }
4015
4016 /* enable interrupts */
4017 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ;
4018 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
4019
4020 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) {
4021 /* enable all endpoint interrupts */
4022 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4023 if (temp & GHWCFG2_MPI) {
4024 uint8_t x;
4025
4026 DPRINTF("Disable Multi Process Interrupts\n");
4027
4028 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
4029 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0);
4030 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0);
4031 }
4032 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0);
4033 }
4034 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK,
4035 DIEPMSK_XFERCOMPLMSK);
4036 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0);
4037 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF);
4038 }
4039
4040 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) {
4041 /* setup clocks */
4042 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
4043 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
4044 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
4045 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
4046 }
4047
4048 /* only enable global IRQ */
4049 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG,
4050 GAHBCFG_GLBLINTRMSK);
4051
4052 /* turn off clocks */
4053 dwc_otg_clocks_off(sc);
4054
4055 /* read initial VBUS state */
4056
4057 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
4058
4059 DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
4060
4061 dwc_otg_vbus_interrupt(sc,
4062 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4063
4064 USB_BUS_UNLOCK(&sc->sc_bus);
4065
4066 /* catch any lost interrupts */
4067
4068 dwc_otg_do_poll(&sc->sc_bus);
4069
4070 return (0); /* success */
4071 }
4072
4073 void
dwc_otg_uninit(struct dwc_otg_softc * sc)4074 dwc_otg_uninit(struct dwc_otg_softc *sc)
4075 {
4076 USB_BUS_LOCK(&sc->sc_bus);
4077
4078 /* stop host timer */
4079 dwc_otg_timer_stop(sc);
4080
4081 /* set disconnect */
4082 DWC_OTG_WRITE_4(sc, DOTG_DCTL,
4083 DCTL_SFTDISCON);
4084
4085 /* turn off global IRQ */
4086 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0);
4087
4088 sc->sc_flags.port_enabled = 0;
4089 sc->sc_flags.port_powered = 0;
4090 sc->sc_flags.status_vbus = 0;
4091 sc->sc_flags.status_bus_reset = 0;
4092 sc->sc_flags.status_suspend = 0;
4093 sc->sc_flags.change_suspend = 0;
4094 sc->sc_flags.change_connect = 1;
4095
4096 dwc_otg_pull_down(sc);
4097 dwc_otg_clocks_off(sc);
4098
4099 USB_BUS_UNLOCK(&sc->sc_bus);
4100
4101 usb_callout_drain(&sc->sc_timer);
4102 }
4103
4104 static void
dwc_otg_suspend(struct dwc_otg_softc * sc)4105 dwc_otg_suspend(struct dwc_otg_softc *sc)
4106 {
4107 return;
4108 }
4109
4110 static void
dwc_otg_resume(struct dwc_otg_softc * sc)4111 dwc_otg_resume(struct dwc_otg_softc *sc)
4112 {
4113 return;
4114 }
4115
4116 static void
dwc_otg_do_poll(struct usb_bus * bus)4117 dwc_otg_do_poll(struct usb_bus *bus)
4118 {
4119 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4120
4121 USB_BUS_LOCK(&sc->sc_bus);
4122 USB_BUS_SPIN_LOCK(&sc->sc_bus);
4123 dwc_otg_interrupt_poll_locked(sc);
4124 dwc_otg_interrupt_complete_locked(sc);
4125 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
4126 USB_BUS_UNLOCK(&sc->sc_bus);
4127 }
4128
4129 /*------------------------------------------------------------------------*
4130 * DWC OTG bulk support
4131 * DWC OTG control support
4132 * DWC OTG interrupt support
4133 *------------------------------------------------------------------------*/
4134 static void
dwc_otg_device_non_isoc_open(struct usb_xfer * xfer)4135 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer)
4136 {
4137 }
4138
4139 static void
dwc_otg_device_non_isoc_close(struct usb_xfer * xfer)4140 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer)
4141 {
4142 dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4143 }
4144
4145 static void
dwc_otg_device_non_isoc_enter(struct usb_xfer * xfer)4146 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer)
4147 {
4148 }
4149
4150 static void
dwc_otg_device_non_isoc_start(struct usb_xfer * xfer)4151 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer)
4152 {
4153 /* setup TDs */
4154 dwc_otg_setup_standard_chain(xfer);
4155 dwc_otg_start_standard_chain(xfer);
4156 }
4157
4158 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods =
4159 {
4160 .open = dwc_otg_device_non_isoc_open,
4161 .close = dwc_otg_device_non_isoc_close,
4162 .enter = dwc_otg_device_non_isoc_enter,
4163 .start = dwc_otg_device_non_isoc_start,
4164 };
4165
4166 /*------------------------------------------------------------------------*
4167 * DWC OTG full speed isochronous support
4168 *------------------------------------------------------------------------*/
4169 static void
dwc_otg_device_isoc_open(struct usb_xfer * xfer)4170 dwc_otg_device_isoc_open(struct usb_xfer *xfer)
4171 {
4172 }
4173
4174 static void
dwc_otg_device_isoc_close(struct usb_xfer * xfer)4175 dwc_otg_device_isoc_close(struct usb_xfer *xfer)
4176 {
4177 dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4178 }
4179
4180 static void
dwc_otg_device_isoc_enter(struct usb_xfer * xfer)4181 dwc_otg_device_isoc_enter(struct usb_xfer *xfer)
4182 {
4183 }
4184
4185 static void
dwc_otg_device_isoc_start(struct usb_xfer * xfer)4186 dwc_otg_device_isoc_start(struct usb_xfer *xfer)
4187 {
4188 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
4189 uint32_t temp;
4190 uint32_t framenum;
4191
4192 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
4193 xfer, xfer->endpoint->isoc_next, xfer->nframes);
4194
4195 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) {
4196 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4197
4198 /* get the current frame index */
4199 framenum = (temp & HFNUM_FRNUM_MASK);
4200 } else {
4201 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4202
4203 /* get the current frame index */
4204 framenum = DSTS_SOFFN_GET(temp);
4205 }
4206
4207 /*
4208 * Check if port is doing 8000 or 1000 frames per second:
4209 */
4210 if (sc->sc_flags.status_high_speed)
4211 framenum /= 8;
4212
4213 if (usbd_xfer_get_isochronous_start_frame(
4214 xfer, framenum, 0, 1, DWC_OTG_FRAME_MASK, NULL))
4215 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
4216
4217 /* setup TDs */
4218 dwc_otg_setup_standard_chain(xfer);
4219
4220 /* start TD chain */
4221 dwc_otg_start_standard_chain(xfer);
4222 }
4223
4224 static const struct usb_pipe_methods dwc_otg_device_isoc_methods =
4225 {
4226 .open = dwc_otg_device_isoc_open,
4227 .close = dwc_otg_device_isoc_close,
4228 .enter = dwc_otg_device_isoc_enter,
4229 .start = dwc_otg_device_isoc_start,
4230 };
4231
4232 /*------------------------------------------------------------------------*
4233 * DWC OTG root control support
4234 *------------------------------------------------------------------------*
4235 * Simulate a hardware HUB by handling all the necessary requests.
4236 *------------------------------------------------------------------------*/
4237
4238 static const struct usb_device_descriptor dwc_otg_devd = {
4239 .bLength = sizeof(struct usb_device_descriptor),
4240 .bDescriptorType = UDESC_DEVICE,
4241 .bcdUSB = {0x00, 0x02},
4242 .bDeviceClass = UDCLASS_HUB,
4243 .bDeviceSubClass = UDSUBCLASS_HUB,
4244 .bDeviceProtocol = UDPROTO_HSHUBSTT,
4245 .bMaxPacketSize = 64,
4246 .bcdDevice = {0x00, 0x01},
4247 .iManufacturer = 1,
4248 .iProduct = 2,
4249 .bNumConfigurations = 1,
4250 };
4251
4252 static const struct dwc_otg_config_desc dwc_otg_confd = {
4253 .confd = {
4254 .bLength = sizeof(struct usb_config_descriptor),
4255 .bDescriptorType = UDESC_CONFIG,
4256 .wTotalLength[0] = sizeof(dwc_otg_confd),
4257 .bNumInterface = 1,
4258 .bConfigurationValue = 1,
4259 .iConfiguration = 0,
4260 .bmAttributes = UC_SELF_POWERED,
4261 .bMaxPower = 0,
4262 },
4263 .ifcd = {
4264 .bLength = sizeof(struct usb_interface_descriptor),
4265 .bDescriptorType = UDESC_INTERFACE,
4266 .bNumEndpoints = 1,
4267 .bInterfaceClass = UICLASS_HUB,
4268 .bInterfaceSubClass = UISUBCLASS_HUB,
4269 .bInterfaceProtocol = 0,
4270 },
4271 .endpd = {
4272 .bLength = sizeof(struct usb_endpoint_descriptor),
4273 .bDescriptorType = UDESC_ENDPOINT,
4274 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT),
4275 .bmAttributes = UE_INTERRUPT,
4276 .wMaxPacketSize[0] = 8,
4277 .bInterval = 255,
4278 },
4279 };
4280 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
4281
4282 static const struct usb_hub_descriptor_min dwc_otg_hubd = {
4283 .bDescLength = sizeof(dwc_otg_hubd),
4284 .bDescriptorType = UDESC_HUB,
4285 .bNbrPorts = 1,
4286 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
4287 .bPwrOn2PwrGood = 50,
4288 .bHubContrCurrent = 0,
4289 .DeviceRemovable = {0}, /* port is removable */
4290 };
4291
4292 #define STRING_VENDOR \
4293 "D\0W\0C\0O\0T\0G"
4294
4295 #define STRING_PRODUCT \
4296 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
4297
4298 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor);
4299 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product);
4300
4301 static usb_error_t
dwc_otg_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)4302 dwc_otg_roothub_exec(struct usb_device *udev,
4303 struct usb_device_request *req, const void **pptr, uint16_t *plength)
4304 {
4305 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4306 const void *ptr;
4307 uint16_t len;
4308 uint16_t value;
4309 uint16_t index;
4310 usb_error_t err;
4311
4312 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
4313
4314 /* buffer reset */
4315 ptr = (const void *)&sc->sc_hub_temp;
4316 len = 0;
4317 err = 0;
4318
4319 value = UGETW(req->wValue);
4320 index = UGETW(req->wIndex);
4321
4322 /* demultiplex the control request */
4323
4324 switch (req->bmRequestType) {
4325 case UT_READ_DEVICE:
4326 switch (req->bRequest) {
4327 case UR_GET_DESCRIPTOR:
4328 goto tr_handle_get_descriptor;
4329 case UR_GET_CONFIG:
4330 goto tr_handle_get_config;
4331 case UR_GET_STATUS:
4332 goto tr_handle_get_status;
4333 default:
4334 goto tr_stalled;
4335 }
4336 break;
4337
4338 case UT_WRITE_DEVICE:
4339 switch (req->bRequest) {
4340 case UR_SET_ADDRESS:
4341 goto tr_handle_set_address;
4342 case UR_SET_CONFIG:
4343 goto tr_handle_set_config;
4344 case UR_CLEAR_FEATURE:
4345 goto tr_valid; /* nop */
4346 case UR_SET_DESCRIPTOR:
4347 goto tr_valid; /* nop */
4348 case UR_SET_FEATURE:
4349 default:
4350 goto tr_stalled;
4351 }
4352 break;
4353
4354 case UT_WRITE_ENDPOINT:
4355 switch (req->bRequest) {
4356 case UR_CLEAR_FEATURE:
4357 switch (UGETW(req->wValue)) {
4358 case UF_ENDPOINT_HALT:
4359 goto tr_handle_clear_halt;
4360 case UF_DEVICE_REMOTE_WAKEUP:
4361 goto tr_handle_clear_wakeup;
4362 default:
4363 goto tr_stalled;
4364 }
4365 break;
4366 case UR_SET_FEATURE:
4367 switch (UGETW(req->wValue)) {
4368 case UF_ENDPOINT_HALT:
4369 goto tr_handle_set_halt;
4370 case UF_DEVICE_REMOTE_WAKEUP:
4371 goto tr_handle_set_wakeup;
4372 default:
4373 goto tr_stalled;
4374 }
4375 break;
4376 case UR_SYNCH_FRAME:
4377 goto tr_valid; /* nop */
4378 default:
4379 goto tr_stalled;
4380 }
4381 break;
4382
4383 case UT_READ_ENDPOINT:
4384 switch (req->bRequest) {
4385 case UR_GET_STATUS:
4386 goto tr_handle_get_ep_status;
4387 default:
4388 goto tr_stalled;
4389 }
4390 break;
4391
4392 case UT_WRITE_INTERFACE:
4393 switch (req->bRequest) {
4394 case UR_SET_INTERFACE:
4395 goto tr_handle_set_interface;
4396 case UR_CLEAR_FEATURE:
4397 goto tr_valid; /* nop */
4398 case UR_SET_FEATURE:
4399 default:
4400 goto tr_stalled;
4401 }
4402 break;
4403
4404 case UT_READ_INTERFACE:
4405 switch (req->bRequest) {
4406 case UR_GET_INTERFACE:
4407 goto tr_handle_get_interface;
4408 case UR_GET_STATUS:
4409 goto tr_handle_get_iface_status;
4410 default:
4411 goto tr_stalled;
4412 }
4413 break;
4414
4415 case UT_WRITE_CLASS_INTERFACE:
4416 case UT_WRITE_VENDOR_INTERFACE:
4417 /* XXX forward */
4418 break;
4419
4420 case UT_READ_CLASS_INTERFACE:
4421 case UT_READ_VENDOR_INTERFACE:
4422 /* XXX forward */
4423 break;
4424
4425 case UT_WRITE_CLASS_DEVICE:
4426 switch (req->bRequest) {
4427 case UR_CLEAR_FEATURE:
4428 goto tr_valid;
4429 case UR_SET_DESCRIPTOR:
4430 case UR_SET_FEATURE:
4431 break;
4432 default:
4433 goto tr_stalled;
4434 }
4435 break;
4436
4437 case UT_WRITE_CLASS_OTHER:
4438 switch (req->bRequest) {
4439 case UR_CLEAR_FEATURE:
4440 goto tr_handle_clear_port_feature;
4441 case UR_SET_FEATURE:
4442 goto tr_handle_set_port_feature;
4443 case UR_CLEAR_TT_BUFFER:
4444 case UR_RESET_TT:
4445 case UR_STOP_TT:
4446 goto tr_valid;
4447
4448 default:
4449 goto tr_stalled;
4450 }
4451 break;
4452
4453 case UT_READ_CLASS_OTHER:
4454 switch (req->bRequest) {
4455 case UR_GET_TT_STATE:
4456 goto tr_handle_get_tt_state;
4457 case UR_GET_STATUS:
4458 goto tr_handle_get_port_status;
4459 default:
4460 goto tr_stalled;
4461 }
4462 break;
4463
4464 case UT_READ_CLASS_DEVICE:
4465 switch (req->bRequest) {
4466 case UR_GET_DESCRIPTOR:
4467 goto tr_handle_get_class_descriptor;
4468 case UR_GET_STATUS:
4469 goto tr_handle_get_class_status;
4470
4471 default:
4472 goto tr_stalled;
4473 }
4474 break;
4475 default:
4476 goto tr_stalled;
4477 }
4478 goto tr_valid;
4479
4480 tr_handle_get_descriptor:
4481 switch (value >> 8) {
4482 case UDESC_DEVICE:
4483 if (value & 0xff) {
4484 goto tr_stalled;
4485 }
4486 len = sizeof(dwc_otg_devd);
4487 ptr = (const void *)&dwc_otg_devd;
4488 goto tr_valid;
4489 case UDESC_CONFIG:
4490 if (value & 0xff) {
4491 goto tr_stalled;
4492 }
4493 len = sizeof(dwc_otg_confd);
4494 ptr = (const void *)&dwc_otg_confd;
4495 goto tr_valid;
4496 case UDESC_STRING:
4497 switch (value & 0xff) {
4498 case 0: /* Language table */
4499 len = sizeof(usb_string_lang_en);
4500 ptr = (const void *)&usb_string_lang_en;
4501 goto tr_valid;
4502
4503 case 1: /* Vendor */
4504 len = sizeof(dwc_otg_vendor);
4505 ptr = (const void *)&dwc_otg_vendor;
4506 goto tr_valid;
4507
4508 case 2: /* Product */
4509 len = sizeof(dwc_otg_product);
4510 ptr = (const void *)&dwc_otg_product;
4511 goto tr_valid;
4512 default:
4513 break;
4514 }
4515 break;
4516 default:
4517 goto tr_stalled;
4518 }
4519 goto tr_stalled;
4520
4521 tr_handle_get_config:
4522 len = 1;
4523 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
4524 goto tr_valid;
4525
4526 tr_handle_get_status:
4527 len = 2;
4528 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
4529 goto tr_valid;
4530
4531 tr_handle_set_address:
4532 if (value & 0xFF00) {
4533 goto tr_stalled;
4534 }
4535 sc->sc_rt_addr = value;
4536 goto tr_valid;
4537
4538 tr_handle_set_config:
4539 if (value >= 2) {
4540 goto tr_stalled;
4541 }
4542 sc->sc_conf = value;
4543 goto tr_valid;
4544
4545 tr_handle_get_interface:
4546 len = 1;
4547 sc->sc_hub_temp.wValue[0] = 0;
4548 goto tr_valid;
4549
4550 tr_handle_get_tt_state:
4551 tr_handle_get_class_status:
4552 tr_handle_get_iface_status:
4553 tr_handle_get_ep_status:
4554 len = 2;
4555 USETW(sc->sc_hub_temp.wValue, 0);
4556 goto tr_valid;
4557
4558 tr_handle_set_halt:
4559 tr_handle_set_interface:
4560 tr_handle_set_wakeup:
4561 tr_handle_clear_wakeup:
4562 tr_handle_clear_halt:
4563 goto tr_valid;
4564
4565 tr_handle_clear_port_feature:
4566 if (index != 1)
4567 goto tr_stalled;
4568
4569 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
4570
4571 switch (value) {
4572 case UHF_PORT_SUSPEND:
4573 dwc_otg_wakeup_peer(sc);
4574 break;
4575
4576 case UHF_PORT_ENABLE:
4577 if (sc->sc_flags.status_device_mode == 0) {
4578 DWC_OTG_WRITE_4(sc, DOTG_HPRT,
4579 sc->sc_hprt_val | HPRT_PRTENA);
4580 }
4581 sc->sc_flags.port_enabled = 0;
4582 break;
4583
4584 case UHF_C_PORT_RESET:
4585 sc->sc_flags.change_reset = 0;
4586 break;
4587
4588 case UHF_C_PORT_ENABLE:
4589 sc->sc_flags.change_enabled = 0;
4590 break;
4591
4592 case UHF_C_PORT_OVER_CURRENT:
4593 sc->sc_flags.change_over_current = 0;
4594 break;
4595
4596 case UHF_PORT_TEST:
4597 case UHF_PORT_INDICATOR:
4598 /* nops */
4599 break;
4600
4601 case UHF_PORT_POWER:
4602 sc->sc_flags.port_powered = 0;
4603 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4604 sc->sc_hprt_val = 0;
4605 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA);
4606 }
4607 dwc_otg_pull_down(sc);
4608 dwc_otg_clocks_off(sc);
4609 break;
4610
4611 case UHF_C_PORT_CONNECTION:
4612 /* clear connect change flag */
4613 sc->sc_flags.change_connect = 0;
4614 break;
4615
4616 case UHF_C_PORT_SUSPEND:
4617 sc->sc_flags.change_suspend = 0;
4618 break;
4619
4620 default:
4621 err = USB_ERR_IOERROR;
4622 goto done;
4623 }
4624 goto tr_valid;
4625
4626 tr_handle_set_port_feature:
4627 if (index != 1) {
4628 goto tr_stalled;
4629 }
4630 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
4631
4632 switch (value) {
4633 case UHF_PORT_ENABLE:
4634 break;
4635
4636 case UHF_PORT_SUSPEND:
4637 if (sc->sc_flags.status_device_mode == 0) {
4638 /* set suspend BIT */
4639 sc->sc_hprt_val |= HPRT_PRTSUSP;
4640 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4641
4642 /* generate HUB suspend event */
4643 dwc_otg_suspend_irq(sc);
4644 }
4645 break;
4646
4647 case UHF_PORT_RESET:
4648 if (sc->sc_flags.status_device_mode == 0) {
4649 DPRINTF("PORT RESET\n");
4650
4651 /* enable PORT reset */
4652 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST);
4653
4654 /* Wait 62.5ms for reset to complete */
4655 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4656
4657 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4658
4659 /* Wait 62.5ms for reset to complete */
4660 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4661
4662 /* reset FIFOs */
4663 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST);
4664
4665 sc->sc_flags.change_reset = 1;
4666 } else {
4667 err = USB_ERR_IOERROR;
4668 }
4669 break;
4670
4671 case UHF_PORT_TEST:
4672 case UHF_PORT_INDICATOR:
4673 /* nops */
4674 break;
4675 case UHF_PORT_POWER:
4676 sc->sc_flags.port_powered = 1;
4677 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4678 sc->sc_hprt_val |= HPRT_PRTPWR;
4679 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4680 }
4681 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) {
4682 /* pull up D+, if any */
4683 dwc_otg_pull_up(sc);
4684 }
4685 break;
4686 default:
4687 err = USB_ERR_IOERROR;
4688 goto done;
4689 }
4690 goto tr_valid;
4691
4692 tr_handle_get_port_status:
4693
4694 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
4695
4696 if (index != 1)
4697 goto tr_stalled;
4698
4699 if (sc->sc_flags.status_vbus)
4700 dwc_otg_clocks_on(sc);
4701 else
4702 dwc_otg_clocks_off(sc);
4703
4704 /* Select Device Side Mode */
4705
4706 if (sc->sc_flags.status_device_mode) {
4707 value = UPS_PORT_MODE_DEVICE;
4708 dwc_otg_timer_stop(sc);
4709 } else {
4710 value = 0;
4711 dwc_otg_timer_start(sc);
4712 }
4713
4714 if (sc->sc_flags.status_high_speed)
4715 value |= UPS_HIGH_SPEED;
4716 else if (sc->sc_flags.status_low_speed)
4717 value |= UPS_LOW_SPEED;
4718
4719 if (sc->sc_flags.port_powered)
4720 value |= UPS_PORT_POWER;
4721
4722 if (sc->sc_flags.port_enabled)
4723 value |= UPS_PORT_ENABLED;
4724
4725 if (sc->sc_flags.port_over_current)
4726 value |= UPS_OVERCURRENT_INDICATOR;
4727
4728 if (sc->sc_flags.status_vbus &&
4729 sc->sc_flags.status_bus_reset)
4730 value |= UPS_CURRENT_CONNECT_STATUS;
4731
4732 if (sc->sc_flags.status_suspend)
4733 value |= UPS_SUSPEND;
4734
4735 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4736
4737 value = 0;
4738
4739 if (sc->sc_flags.change_enabled)
4740 value |= UPS_C_PORT_ENABLED;
4741 if (sc->sc_flags.change_connect)
4742 value |= UPS_C_CONNECT_STATUS;
4743 if (sc->sc_flags.change_suspend)
4744 value |= UPS_C_SUSPEND;
4745 if (sc->sc_flags.change_reset)
4746 value |= UPS_C_PORT_RESET;
4747 if (sc->sc_flags.change_over_current)
4748 value |= UPS_C_OVERCURRENT_INDICATOR;
4749
4750 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4751 len = sizeof(sc->sc_hub_temp.ps);
4752 goto tr_valid;
4753
4754 tr_handle_get_class_descriptor:
4755 if (value & 0xFF) {
4756 goto tr_stalled;
4757 }
4758 ptr = (const void *)&dwc_otg_hubd;
4759 len = sizeof(dwc_otg_hubd);
4760 goto tr_valid;
4761
4762 tr_stalled:
4763 err = USB_ERR_STALLED;
4764 tr_valid:
4765 done:
4766 *plength = len;
4767 *pptr = ptr;
4768 return (err);
4769 }
4770
4771 static void
dwc_otg_xfer_setup(struct usb_setup_params * parm)4772 dwc_otg_xfer_setup(struct usb_setup_params *parm)
4773 {
4774 struct usb_xfer *xfer;
4775 void *last_obj;
4776 uint32_t ntd;
4777 uint32_t n;
4778 uint8_t ep_no;
4779 uint8_t ep_type;
4780
4781 xfer = parm->curr_xfer;
4782
4783 /*
4784 * NOTE: This driver does not use any of the parameters that
4785 * are computed from the following values. Just set some
4786 * reasonable dummies:
4787 */
4788 parm->hc_max_packet_size = 0x500;
4789 parm->hc_max_packet_count = 3;
4790 parm->hc_max_frame_size = 3 * 0x500;
4791
4792 usbd_transfer_setup_sub(parm);
4793
4794 /*
4795 * compute maximum number of TDs
4796 */
4797 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
4798
4799 if (ep_type == UE_CONTROL) {
4800 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
4801 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */;
4802 } else {
4803 ntd = xfer->nframes + 1 /* SYNC */ ;
4804 }
4805
4806 /*
4807 * check if "usbd_transfer_setup_sub" set an error
4808 */
4809 if (parm->err)
4810 return;
4811
4812 /*
4813 * allocate transfer descriptors
4814 */
4815 last_obj = NULL;
4816
4817 ep_no = xfer->endpointno & UE_ADDR;
4818
4819 /*
4820 * Check for a valid endpoint profile in USB device mode:
4821 */
4822 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4823 const struct usb_hw_ep_profile *pf;
4824
4825 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4826
4827 if (pf == NULL) {
4828 /* should not happen */
4829 parm->err = USB_ERR_INVAL;
4830 return;
4831 }
4832 }
4833
4834 /* align data */
4835 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4836
4837 for (n = 0; n != ntd; n++) {
4838 struct dwc_otg_td *td;
4839
4840 if (parm->buf) {
4841 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4842
4843 /* compute shared bandwidth resource index for TT */
4844 if (dwc_otg_uses_split(parm->udev)) {
4845 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)
4846 td->tt_index = parm->udev->device_index;
4847 else
4848 td->tt_index = parm->udev->parent_hs_hub->device_index;
4849 } else {
4850 td->tt_index = parm->udev->device_index;
4851 }
4852
4853 /* init TD */
4854 td->max_packet_size = xfer->max_packet_size;
4855 td->max_packet_count = xfer->max_packet_count;
4856 /* range check */
4857 if (td->max_packet_count == 0 || td->max_packet_count > 3)
4858 td->max_packet_count = 1;
4859 td->ep_no = ep_no;
4860 td->ep_type = ep_type;
4861 td->obj_next = last_obj;
4862
4863 last_obj = td;
4864 }
4865 parm->size[0] += sizeof(*td);
4866 }
4867
4868 xfer->td_start[0] = last_obj;
4869 }
4870
4871 static void
dwc_otg_xfer_unsetup(struct usb_xfer * xfer)4872 dwc_otg_xfer_unsetup(struct usb_xfer *xfer)
4873 {
4874 return;
4875 }
4876
4877 static void
dwc_otg_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)4878 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4879 struct usb_endpoint *ep)
4880 {
4881 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4882
4883 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
4884 ep, udev->address,
4885 edesc->bEndpointAddress, udev->flags.usb_mode,
4886 sc->sc_rt_addr, udev->device_index);
4887
4888 if (udev->device_index != sc->sc_rt_addr) {
4889 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
4890 if (udev->speed != USB_SPEED_FULL &&
4891 udev->speed != USB_SPEED_HIGH) {
4892 /* not supported */
4893 return;
4894 }
4895 } else {
4896 if (udev->speed == USB_SPEED_HIGH &&
4897 (edesc->wMaxPacketSize[1] & 0x18) != 0 &&
4898 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
4899 /* not supported */
4900 DPRINTFN(-1, "Non-isochronous high bandwidth "
4901 "endpoint not supported\n");
4902 return;
4903 }
4904 }
4905 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
4906 ep->methods = &dwc_otg_device_isoc_methods;
4907 else
4908 ep->methods = &dwc_otg_device_non_isoc_methods;
4909 }
4910 }
4911
4912 static void
dwc_otg_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)4913 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4914 {
4915 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4916
4917 switch (state) {
4918 case USB_HW_POWER_SUSPEND:
4919 dwc_otg_suspend(sc);
4920 break;
4921 case USB_HW_POWER_SHUTDOWN:
4922 dwc_otg_uninit(sc);
4923 break;
4924 case USB_HW_POWER_RESUME:
4925 dwc_otg_resume(sc);
4926 break;
4927 default:
4928 break;
4929 }
4930 }
4931
4932 static void
dwc_otg_get_dma_delay(struct usb_device * udev,uint32_t * pus)4933 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4934 {
4935 /* DMA delay - wait until any use of memory is finished */
4936 *pus = (2125); /* microseconds */
4937 }
4938
4939 static void
dwc_otg_device_resume(struct usb_device * udev)4940 dwc_otg_device_resume(struct usb_device *udev)
4941 {
4942 DPRINTF("\n");
4943
4944 /* poll all transfers again to restart resumed ones */
4945 dwc_otg_do_poll(udev->bus);
4946 }
4947
4948 static void
dwc_otg_device_suspend(struct usb_device * udev)4949 dwc_otg_device_suspend(struct usb_device *udev)
4950 {
4951 DPRINTF("\n");
4952 }
4953
4954 static const struct usb_bus_methods dwc_otg_bus_methods =
4955 {
4956 .endpoint_init = &dwc_otg_ep_init,
4957 .xfer_setup = &dwc_otg_xfer_setup,
4958 .xfer_unsetup = &dwc_otg_xfer_unsetup,
4959 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile,
4960 .xfer_stall = &dwc_otg_xfer_stall,
4961 .set_stall = &dwc_otg_set_stall,
4962 .clear_stall = &dwc_otg_clear_stall,
4963 .roothub_exec = &dwc_otg_roothub_exec,
4964 .xfer_poll = &dwc_otg_do_poll,
4965 .device_state_change = &dwc_otg_device_state_change,
4966 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep,
4967 .get_dma_delay = &dwc_otg_get_dma_delay,
4968 .device_resume = &dwc_otg_device_resume,
4969 .device_suspend = &dwc_otg_device_suspend,
4970 };
4971