1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2UDEV(pc) \ 93 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTMSK_ENUMDONEMSK | \ 97 GINTMSK_USBRSTMSK | \ 98 GINTMSK_USBSUSPMSK | \ 99 GINTMSK_IEPINTMSK | \ 100 GINTMSK_SESSREQINTMSK | \ 101 GINTMSK_RXFLVLMSK | \ 102 GINTMSK_HCHINTMSK | \ 103 GINTMSK_OTGINTMSK | \ 104 GINTMSK_PRTINTMSK) 105 106 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 107 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 108 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 109 GINTSTS_SESSREQINT) 110 111 #define DWC_OTG_PHY_ULPI 0 112 #define DWC_OTG_PHY_HSIC 1 113 #define DWC_OTG_PHY_INTERNAL 2 114 115 #ifndef DWC_OTG_PHY_DEFAULT 116 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 117 #endif 118 119 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 120 121 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 122 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 123 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 124 125 #ifdef USB_DEBUG 126 static int dwc_otg_debug; 127 128 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 129 &dwc_otg_debug, 0, "DWC OTG debug level"); 130 #endif 131 132 #define DWC_OTG_INTR_ENDPT 1 133 134 /* prototypes */ 135 136 static const struct usb_bus_methods dwc_otg_bus_methods; 137 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 138 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 139 140 static dwc_otg_cmd_t dwc_otg_setup_rx; 141 static dwc_otg_cmd_t dwc_otg_data_rx; 142 static dwc_otg_cmd_t dwc_otg_data_tx; 143 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 144 145 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 146 static dwc_otg_cmd_t dwc_otg_host_data_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_rx; 148 149 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 150 static void dwc_otg_do_poll(struct usb_bus *); 151 static void dwc_otg_standard_done(struct usb_xfer *); 152 static void dwc_otg_root_intr(struct dwc_otg_softc *); 153 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 154 static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static int 184 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 185 { 186 struct dwc_otg_profile *pf; 187 uint32_t fifo_size; 188 uint32_t fifo_regs; 189 uint32_t tx_start; 190 uint8_t x; 191 192 fifo_size = sc->sc_fifo_size; 193 194 /* 195 * NOTE: Reserved fixed size area at end of RAM, which must 196 * not be allocated to the FIFOs: 197 */ 198 fifo_regs = 4 * 16; 199 200 if (fifo_size < fifo_regs) { 201 DPRINTF("Too little FIFO\n"); 202 return (EINVAL); 203 } 204 205 /* subtract FIFO regs from total once */ 206 fifo_size -= fifo_regs; 207 208 /* split equally for IN and OUT */ 209 fifo_size /= 2; 210 211 /* align to 4 bytes boundary */ 212 fifo_size &= ~3; 213 214 /* set global receive FIFO size */ 215 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 216 217 tx_start = fifo_size; 218 219 if (fifo_size < 64) { 220 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 221 return (EINVAL); 222 } 223 224 /* disable any leftover host channels */ 225 for (x = 0; x != sc->sc_host_ch_max; x++) { 226 if (sc->sc_chan_state[x].wait_sof == 0) 227 continue; 228 dwc_otg_host_channel_disable(sc, x); 229 } 230 231 if (mode == DWC_MODE_HOST) { 232 233 /* reset active endpoints */ 234 sc->sc_active_rx_ep = 0; 235 236 /* split equally for periodic and non-periodic */ 237 fifo_size /= 2; 238 239 /* align to 4 bytes boundary */ 240 fifo_size &= ~3; 241 242 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 243 ((fifo_size / 4) << 16) | 244 (tx_start / 4)); 245 246 tx_start += fifo_size; 247 248 for (x = 0; x != sc->sc_host_ch_max; x++) { 249 /* disable all host interrupts */ 250 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 251 HCINT_DEFAULT_MASK); 252 } 253 254 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 255 ((fifo_size / 4) << 16) | 256 (tx_start / 4)); 257 258 /* reset host channel state */ 259 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 260 261 /* reset FIFO TX levels */ 262 sc->sc_tx_cur_p_level = 0; 263 sc->sc_tx_cur_np_level = 0; 264 265 /* store maximum periodic and non-periodic FIFO TX size */ 266 sc->sc_tx_max_size = fifo_size; 267 268 /* enable all host channel interrupts */ 269 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 270 (1U << sc->sc_host_ch_max) - 1U); 271 } 272 273 if (mode == DWC_MODE_DEVICE) { 274 275 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 276 (0x10 << 16) | (tx_start / 4)); 277 fifo_size -= 0x40; 278 tx_start += 0x40; 279 280 /* setup control endpoint profile */ 281 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 282 283 /* reset active endpoints */ 284 sc->sc_active_rx_ep = 1; 285 286 for (x = 1; x != sc->sc_dev_ep_max; x++) { 287 288 pf = sc->sc_hw_ep_profile + x; 289 290 pf->usb.max_out_frame_size = 1024 * 3; 291 pf->usb.is_simplex = 0; /* assume duplex */ 292 pf->usb.support_bulk = 1; 293 pf->usb.support_interrupt = 1; 294 pf->usb.support_isochronous = 1; 295 pf->usb.support_out = 1; 296 297 if (x < sc->sc_dev_in_ep_max) { 298 uint32_t limit; 299 300 limit = (x == 1) ? DWC_OTG_MAX_TXN : 301 (DWC_OTG_MAX_TXN / 2); 302 303 if (fifo_size >= limit) { 304 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 305 ((limit / 4) << 16) | 306 (tx_start / 4)); 307 tx_start += limit; 308 fifo_size -= limit; 309 pf->usb.max_in_frame_size = 0x200; 310 pf->usb.support_in = 1; 311 pf->max_buffer = limit; 312 313 } else if (fifo_size >= 0x80) { 314 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 315 ((0x80 / 4) << 16) | (tx_start / 4)); 316 tx_start += 0x80; 317 fifo_size -= 0x80; 318 pf->usb.max_in_frame_size = 0x40; 319 pf->usb.support_in = 1; 320 321 } else { 322 pf->usb.is_simplex = 1; 323 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 324 (0x0 << 16) | (tx_start / 4)); 325 } 326 } else { 327 pf->usb.is_simplex = 1; 328 } 329 330 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 331 pf->usb.max_in_frame_size, 332 pf->usb.max_out_frame_size); 333 } 334 } 335 336 /* reset RX FIFO */ 337 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 338 GRSTCTL_RXFFLSH); 339 340 if (mode != DWC_MODE_OTG) { 341 /* reset all TX FIFOs */ 342 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 343 GRSTCTL_TXFIFO(0x10) | 344 GRSTCTL_TXFFLSH); 345 } else { 346 /* reset active endpoints */ 347 sc->sc_active_rx_ep = 0; 348 349 /* reset periodic and non-periodic FIFO TX size */ 350 sc->sc_tx_max_size = fifo_size; 351 352 /* reset host channel state */ 353 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 354 355 /* reset FIFO TX levels */ 356 sc->sc_tx_cur_p_level = 0; 357 sc->sc_tx_cur_np_level = 0; 358 } 359 return (0); 360 } 361 362 static void 363 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 364 { 365 366 /* 367 * Disabled until further. Assuming that the register is already 368 * programmed correctly by the boot loader. 369 */ 370 #if 0 371 uint32_t temp; 372 373 /* setup HOST frame interval register, based on existing value */ 374 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 375 if (temp >= 10000) 376 temp /= 1000; 377 else 378 temp /= 125; 379 380 /* figure out nearest X-tal value */ 381 if (temp >= 54) 382 temp = 60; /* MHz */ 383 else if (temp >= 39) 384 temp = 48; /* MHz */ 385 else 386 temp = 30; /* MHz */ 387 388 if (sc->sc_flags.status_high_speed) 389 temp *= 125; 390 else 391 temp *= 1000; 392 393 DPRINTF("HFIR=0x%08x\n", temp); 394 395 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 396 #endif 397 } 398 399 static void 400 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 401 { 402 if (sc->sc_flags.clocks_off && 403 sc->sc_flags.port_powered) { 404 405 DPRINTFN(5, "\n"); 406 407 /* TODO - platform specific */ 408 409 sc->sc_flags.clocks_off = 0; 410 } 411 } 412 413 static void 414 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 415 { 416 if (!sc->sc_flags.clocks_off) { 417 418 DPRINTFN(5, "\n"); 419 420 /* TODO - platform specific */ 421 422 sc->sc_flags.clocks_off = 1; 423 } 424 } 425 426 static void 427 dwc_otg_pull_up(struct dwc_otg_softc *sc) 428 { 429 uint32_t temp; 430 431 /* pullup D+, if possible */ 432 433 if (!sc->sc_flags.d_pulled_up && 434 sc->sc_flags.port_powered) { 435 sc->sc_flags.d_pulled_up = 1; 436 437 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 438 temp &= ~DCTL_SFTDISCON; 439 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 440 } 441 } 442 443 static void 444 dwc_otg_pull_down(struct dwc_otg_softc *sc) 445 { 446 uint32_t temp; 447 448 /* pulldown D+, if possible */ 449 450 if (sc->sc_flags.d_pulled_up) { 451 sc->sc_flags.d_pulled_up = 0; 452 453 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 454 temp |= DCTL_SFTDISCON; 455 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 456 } 457 } 458 459 static void 460 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 461 { 462 /* In device mode we don't use the SOF interrupt */ 463 if (sc->sc_flags.status_device_mode != 0 || 464 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 465 return; 466 sc->sc_irq_mask |= GINTMSK_SOFMSK; 467 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 468 } 469 470 static void 471 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 472 { 473 if (sc->sc_flags.status_suspend) { 474 /* update status bits */ 475 sc->sc_flags.status_suspend = 0; 476 sc->sc_flags.change_suspend = 1; 477 478 if (sc->sc_flags.status_device_mode) { 479 /* 480 * Disable resume interrupt and enable suspend 481 * interrupt: 482 */ 483 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 484 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 485 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 486 } 487 488 /* complete root HUB interrupt endpoint */ 489 dwc_otg_root_intr(sc); 490 } 491 } 492 493 static void 494 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 495 { 496 if (!sc->sc_flags.status_suspend) { 497 /* update status bits */ 498 sc->sc_flags.status_suspend = 1; 499 sc->sc_flags.change_suspend = 1; 500 501 if (sc->sc_flags.status_device_mode) { 502 /* 503 * Disable suspend interrupt and enable resume 504 * interrupt: 505 */ 506 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 507 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 508 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 509 } 510 511 /* complete root HUB interrupt endpoint */ 512 dwc_otg_root_intr(sc); 513 } 514 } 515 516 static void 517 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 518 { 519 if (!sc->sc_flags.status_suspend) 520 return; 521 522 DPRINTFN(5, "Remote wakeup\n"); 523 524 if (sc->sc_flags.status_device_mode) { 525 uint32_t temp; 526 527 /* enable remote wakeup signalling */ 528 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 529 temp |= DCTL_RMTWKUPSIG; 530 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 531 532 /* Wait 8ms for remote wakeup to complete. */ 533 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 534 535 temp &= ~DCTL_RMTWKUPSIG; 536 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 537 } else { 538 /* enable USB port */ 539 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 540 541 /* wait 10ms */ 542 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 543 544 /* resume port */ 545 sc->sc_hprt_val |= HPRT_PRTRES; 546 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 547 548 /* Wait 100ms for resume signalling to complete. */ 549 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 550 551 /* clear suspend and resume */ 552 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 553 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 554 555 /* Wait 4ms */ 556 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 557 } 558 559 /* need to fake resume IRQ */ 560 dwc_otg_resume_irq(sc); 561 } 562 563 static void 564 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 565 { 566 uint32_t temp; 567 568 DPRINTFN(5, "addr=%d\n", addr); 569 570 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 571 temp &= ~DCFG_DEVADDR_SET(0x7F); 572 temp |= DCFG_DEVADDR_SET(addr); 573 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 574 } 575 576 static void 577 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 578 { 579 DPRINTFN(5, "RX status clear\n"); 580 581 /* enable RX FIFO level interrupt */ 582 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 583 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 584 585 /* clear cached status */ 586 sc->sc_last_rx_status = 0; 587 } 588 589 static void 590 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 591 { 592 uint32_t hcint; 593 594 /* clear all pending interrupts */ 595 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 596 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 597 598 /* clear buffered interrupts */ 599 sc->sc_chan_state[x].hcint = 0; 600 } 601 602 static uint8_t 603 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) 604 { 605 uint32_t tx_p_size; 606 uint32_t tx_np_size; 607 uint8_t x; 608 609 if (td->channel < DWC_OTG_MAX_CHANNELS) 610 return (0); /* already allocated */ 611 612 /* check if device is suspended */ 613 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 614 return (1); /* busy - cannot transfer data */ 615 616 /* compute needed TX FIFO size */ 617 if (is_out != 0) { 618 if (td->ep_type == UE_ISOCHRONOUS) { 619 tx_p_size = td->max_packet_size; 620 tx_np_size = 0; 621 if (td->hcsplt != 0 && tx_p_size > HCSPLT_XACTLEN_BURST) 622 tx_p_size = HCSPLT_XACTLEN_BURST; 623 if ((sc->sc_tx_cur_p_level + tx_p_size) > sc->sc_tx_max_size) { 624 DPRINTF("Too little FIFO space\n"); 625 return (1); /* too little FIFO */ 626 } 627 } else { 628 tx_p_size = 0; 629 tx_np_size = td->max_packet_size; 630 if (td->hcsplt != 0 && tx_np_size > HCSPLT_XACTLEN_BURST) 631 tx_np_size = HCSPLT_XACTLEN_BURST; 632 if ((sc->sc_tx_cur_np_level + tx_np_size) > sc->sc_tx_max_size) { 633 DPRINTF("Too little FIFO space\n"); 634 return (1); /* too little FIFO */ 635 } 636 } 637 } else { 638 /* not a TX transaction */ 639 tx_p_size = 0; 640 tx_np_size = 0; 641 } 642 643 for (x = 0; x != sc->sc_host_ch_max; x++) { 644 if (sc->sc_chan_state[x].allocated != 0) 645 continue; 646 /* check if channel is still enabled */ 647 if (sc->sc_chan_state[x].wait_sof != 0) 648 continue; 649 650 sc->sc_chan_state[x].allocated = 1; 651 sc->sc_chan_state[x].tx_p_size = tx_p_size; 652 sc->sc_chan_state[x].tx_np_size = tx_np_size; 653 654 /* keep track of used TX FIFO, if any */ 655 sc->sc_tx_cur_p_level += tx_p_size; 656 sc->sc_tx_cur_np_level += tx_np_size; 657 658 /* clear interrupts */ 659 dwc_otg_clear_hcint(sc, x); 660 661 DPRINTF("CH=%d HCCHAR=0x%08x " 662 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 663 664 /* set active channel */ 665 sc->sc_active_rx_ep |= (1 << x); 666 667 /* set channel */ 668 td->channel = x; 669 670 return (0); /* allocated */ 671 } 672 /* wait a bit */ 673 dwc_otg_enable_sof_irq(sc); 674 return (1); /* busy */ 675 } 676 677 static void 678 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 679 { 680 uint8_t x; 681 682 if (td->channel >= DWC_OTG_MAX_CHANNELS) 683 return; /* already freed */ 684 685 /* free channel */ 686 x = td->channel; 687 td->channel = DWC_OTG_MAX_CHANNELS; 688 689 DPRINTF("CH=%d\n", x); 690 691 /* 692 * We need to let programmed host channels run till complete 693 * else the host channel will stop functioning. Assume that 694 * after a fixed given amount of time the host channel is no 695 * longer doing any USB traffic: 696 */ 697 if (td->ep_type == UE_ISOCHRONOUS) { 698 /* double buffered */ 699 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX; 700 } else { 701 /* single buffered */ 702 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN; 703 } 704 705 sc->sc_chan_state[x].allocated = 0; 706 707 /* ack any pending messages */ 708 if (sc->sc_last_rx_status != 0 && 709 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 710 dwc_otg_common_rx_ack(sc); 711 } 712 713 /* clear active channel */ 714 sc->sc_active_rx_ep &= ~(1 << x); 715 } 716 717 static void 718 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 719 { 720 /* dump any pending messages */ 721 if (sc->sc_last_rx_status != 0) { 722 if (td->channel < DWC_OTG_MAX_CHANNELS && 723 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 724 dwc_otg_common_rx_ack(sc); 725 } 726 } 727 } 728 729 static uint8_t 730 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 731 { 732 struct usb_device_request req __aligned(4); 733 uint32_t hcint; 734 uint32_t hcchar; 735 uint8_t delta; 736 737 dwc_otg_host_dump_rx(sc, td); 738 739 if (td->channel < DWC_OTG_MAX_CHANNELS) { 740 hcint = sc->sc_chan_state[td->channel].hcint; 741 742 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 743 td->channel, td->state, hcint, 744 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 745 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 746 } else { 747 hcint = 0; 748 goto check_state; 749 } 750 751 if (hcint & (HCINT_RETRY | 752 HCINT_ACK | HCINT_NYET)) { 753 /* give success bits priority over failure bits */ 754 } else if (hcint & HCINT_STALL) { 755 DPRINTF("CH=%d STALL\n", td->channel); 756 td->error_stall = 1; 757 td->error_any = 1; 758 goto complete; 759 } else if (hcint & HCINT_ERRORS) { 760 DPRINTF("CH=%d ERROR\n", td->channel); 761 td->errcnt++; 762 if (td->hcsplt != 0 || td->errcnt >= 3) { 763 td->error_any = 1; 764 goto complete; 765 } 766 } 767 768 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 769 HCINT_ACK | HCINT_NYET)) { 770 if (!(hcint & HCINT_ERRORS)) 771 td->errcnt = 0; 772 } 773 774 check_state: 775 switch (td->state) { 776 case DWC_CHAN_ST_START: 777 goto send_pkt; 778 779 case DWC_CHAN_ST_WAIT_ANE: 780 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 781 td->did_nak++; 782 td->tt_scheduled = 0; 783 goto send_pkt; 784 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 785 td->offset += td->tx_bytes; 786 td->remainder -= td->tx_bytes; 787 td->toggle = 1; 788 td->tt_scheduled = 0; 789 goto complete; 790 } 791 break; 792 793 case DWC_CHAN_ST_WAIT_S_ANE: 794 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 795 td->did_nak++; 796 td->tt_scheduled = 0; 797 goto send_pkt; 798 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 799 goto send_cpkt; 800 } 801 break; 802 803 case DWC_CHAN_ST_WAIT_C_ANE: 804 if (hcint & HCINT_NYET) { 805 goto send_cpkt; 806 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 807 td->did_nak++; 808 td->tt_scheduled = 0; 809 goto send_pkt; 810 } else if (hcint & HCINT_ACK) { 811 td->offset += td->tx_bytes; 812 td->remainder -= td->tx_bytes; 813 td->toggle = 1; 814 goto complete; 815 } 816 break; 817 818 case DWC_CHAN_ST_WAIT_C_PKT: 819 goto send_cpkt; 820 821 default: 822 break; 823 } 824 goto busy; 825 826 send_pkt: 827 /* free existing channel, if any */ 828 dwc_otg_host_channel_free(sc, td); 829 830 if (sizeof(req) != td->remainder) { 831 td->error_any = 1; 832 goto complete; 833 } 834 835 if (td->hcsplt != 0) { 836 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 837 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 838 td->state = DWC_CHAN_ST_START; 839 goto busy; 840 } 841 delta = sc->sc_last_frame_num - td->tt_start_slot; 842 if (delta > 5) { 843 /* missed it */ 844 td->tt_scheduled = 0; 845 td->state = DWC_CHAN_ST_START; 846 goto busy; 847 } 848 } 849 850 /* allocate a new channel */ 851 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 852 td->state = DWC_CHAN_ST_START; 853 goto busy; 854 } 855 856 if (td->hcsplt != 0) { 857 td->hcsplt &= ~HCSPLT_COMPSPLT; 858 td->state = DWC_CHAN_ST_WAIT_S_ANE; 859 } else { 860 td->state = DWC_CHAN_ST_WAIT_ANE; 861 } 862 863 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 864 865 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 866 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 867 (1 << HCTSIZ_PKTCNT_SHIFT) | 868 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 869 870 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 871 872 hcchar = td->hcchar; 873 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 874 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 875 876 /* must enable channel before writing data to FIFO */ 877 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 878 879 /* transfer data into FIFO */ 880 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 881 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 882 883 /* wait until next slot before trying complete split */ 884 td->tt_complete_slot = sc->sc_last_frame_num + 1; 885 886 /* store number of bytes transmitted */ 887 td->tx_bytes = sizeof(req); 888 goto busy; 889 890 send_cpkt: 891 /* free existing channel, if any */ 892 dwc_otg_host_channel_free(sc, td); 893 894 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 895 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 896 td->state = DWC_CHAN_ST_WAIT_C_PKT; 897 goto busy; 898 } 899 delta = sc->sc_last_frame_num - td->tt_start_slot; 900 if (delta > DWC_OTG_TT_SLOT_MAX) { 901 /* we missed the service interval */ 902 if (td->ep_type != UE_ISOCHRONOUS) 903 td->error_any = 1; 904 goto complete; 905 } 906 /* allocate a new channel */ 907 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 908 td->state = DWC_CHAN_ST_WAIT_C_PKT; 909 goto busy; 910 } 911 912 /* wait until next slot before trying complete split */ 913 td->tt_complete_slot = sc->sc_last_frame_num + 1; 914 915 td->hcsplt |= HCSPLT_COMPSPLT; 916 td->state = DWC_CHAN_ST_WAIT_C_ANE; 917 918 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 919 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 920 921 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 922 923 hcchar = td->hcchar; 924 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 925 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 926 927 /* must enable channel before writing data to FIFO */ 928 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 929 930 busy: 931 return (1); /* busy */ 932 933 complete: 934 dwc_otg_host_channel_free(sc, td); 935 return (0); /* complete */ 936 } 937 938 static uint8_t 939 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 940 { 941 struct usb_device_request req __aligned(4); 942 uint32_t temp; 943 uint16_t count; 944 945 /* check endpoint status */ 946 947 if (sc->sc_last_rx_status == 0) 948 goto not_complete; 949 950 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 951 goto not_complete; 952 953 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 954 GRXSTSRD_DPID_DATA0) { 955 /* release FIFO */ 956 dwc_otg_common_rx_ack(sc); 957 goto not_complete; 958 } 959 960 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 961 GRXSTSRD_STP_DATA) { 962 /* release FIFO */ 963 dwc_otg_common_rx_ack(sc); 964 goto not_complete; 965 } 966 967 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 968 969 /* clear did stall */ 970 td->did_stall = 0; 971 972 /* get the packet byte count */ 973 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 974 975 /* verify data length */ 976 if (count != td->remainder) { 977 DPRINTFN(0, "Invalid SETUP packet " 978 "length, %d bytes\n", count); 979 /* release FIFO */ 980 dwc_otg_common_rx_ack(sc); 981 goto not_complete; 982 } 983 if (count != sizeof(req)) { 984 DPRINTFN(0, "Unsupported SETUP packet " 985 "length, %d bytes\n", count); 986 /* release FIFO */ 987 dwc_otg_common_rx_ack(sc); 988 goto not_complete; 989 } 990 991 /* copy in control request */ 992 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 993 994 /* copy data into real buffer */ 995 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 996 997 td->offset = sizeof(req); 998 td->remainder = 0; 999 1000 /* sneak peek the set address */ 1001 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1002 (req.bRequest == UR_SET_ADDRESS)) { 1003 /* must write address before ZLP */ 1004 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1005 } 1006 1007 /* don't send any data by default */ 1008 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 1009 DXEPTSIZ_SET_NPKT(0) | 1010 DXEPTSIZ_SET_NBYTES(0)); 1011 1012 temp = sc->sc_in_ctl[0]; 1013 1014 /* enable IN endpoint */ 1015 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1016 temp | DIEPCTL_EPENA); 1017 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1018 temp | DIEPCTL_SNAK); 1019 1020 /* reset IN endpoint buffer */ 1021 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1022 GRSTCTL_TXFIFO(0) | 1023 GRSTCTL_TXFFLSH); 1024 1025 /* acknowledge RX status */ 1026 dwc_otg_common_rx_ack(sc); 1027 return (0); /* complete */ 1028 1029 not_complete: 1030 /* abort any ongoing transfer, before enabling again */ 1031 1032 temp = sc->sc_out_ctl[0]; 1033 1034 temp |= DOEPCTL_EPENA | 1035 DOEPCTL_SNAK; 1036 1037 /* enable OUT endpoint */ 1038 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 1039 1040 if (!td->did_stall) { 1041 td->did_stall = 1; 1042 1043 DPRINTFN(5, "stalling IN and OUT direction\n"); 1044 1045 /* set stall after enabling endpoint */ 1046 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1047 temp | DOEPCTL_STALL); 1048 1049 temp = sc->sc_in_ctl[0]; 1050 1051 /* set stall assuming endpoint is enabled */ 1052 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1053 temp | DIEPCTL_STALL); 1054 } 1055 1056 /* setup number of buffers to receive */ 1057 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1058 DXEPTSIZ_SET_MULTI(3) | 1059 DXEPTSIZ_SET_NPKT(1) | 1060 DXEPTSIZ_SET_NBYTES(sizeof(req))); 1061 1062 return (1); /* not complete */ 1063 } 1064 1065 static uint8_t 1066 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1067 { 1068 uint8_t delta; 1069 1070 delta = sc->sc_tmr_val - td->tmr_val; 1071 if (delta >= 128) 1072 return (1); /* busy */ 1073 1074 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1075 1076 /* set toggle, if any */ 1077 if (td->set_toggle) { 1078 td->set_toggle = 0; 1079 td->toggle = 1; 1080 } 1081 return (0); 1082 } 1083 1084 static uint8_t 1085 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1086 { 1087 if (td->ep_type == UE_ISOCHRONOUS) { 1088 /* non TT isochronous traffic */ 1089 if ((td->tmr_val != 0) || 1090 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1091 goto busy; 1092 } 1093 td->tmr_val = 1; /* executed */ 1094 td->toggle = 0; 1095 1096 } else if (td->ep_type == UE_INTERRUPT) { 1097 if (!td->tt_scheduled) 1098 goto busy; 1099 td->tt_scheduled = 0; 1100 } else if (td->did_nak >= DWC_OTG_NAK_MAX) { 1101 goto busy; 1102 } else if (td->set_toggle) { 1103 td->set_toggle = 0; 1104 td->toggle = 1; 1105 } 1106 return (0); 1107 busy: 1108 return (1); 1109 } 1110 1111 static uint8_t 1112 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1113 { 1114 uint32_t count; 1115 uint8_t channel; 1116 1117 /* check endpoint status */ 1118 if (sc->sc_last_rx_status == 0) 1119 goto busy; 1120 1121 channel = td->channel; 1122 if (channel >= DWC_OTG_MAX_CHANNELS) 1123 goto busy; 1124 1125 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1126 goto busy; 1127 1128 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1129 case GRXSTSRH_IN_DATA: 1130 1131 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1132 (int)td->state, (int)sc->sc_last_rx_status); 1133 1134 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1135 /* 1136 * When using SPLIT transactions on interrupt 1137 * endpoints, sometimes data occurs twice. 1138 */ 1139 DPRINTF("Data already received\n"); 1140 break; 1141 } 1142 1143 /* get the packet byte count */ 1144 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1145 1146 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1147 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1148 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1149 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1150 } else { 1151 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1152 1153 /* verify the packet byte count */ 1154 if (count < td->max_packet_size) { 1155 /* we have a short packet */ 1156 td->short_pkt = 1; 1157 td->got_short = 1; 1158 } 1159 } 1160 td->toggle = 0; 1161 } else { 1162 /* verify the packet byte count */ 1163 if (count != td->max_packet_size) { 1164 if (count < td->max_packet_size) { 1165 /* we have a short packet */ 1166 td->short_pkt = 1; 1167 td->got_short = 1; 1168 } else { 1169 /* invalid USB packet */ 1170 td->error_any = 1; 1171 1172 /* release FIFO */ 1173 dwc_otg_common_rx_ack(sc); 1174 goto complete; 1175 } 1176 } 1177 td->toggle ^= 1; 1178 td->tt_scheduled = 0; 1179 } 1180 1181 /* verify the packet byte count */ 1182 if (count > td->remainder) { 1183 /* invalid USB packet */ 1184 td->error_any = 1; 1185 1186 /* release FIFO */ 1187 dwc_otg_common_rx_ack(sc); 1188 goto complete; 1189 } 1190 1191 usbd_copy_in(td->pc, td->offset, 1192 sc->sc_rx_bounce_buffer, count); 1193 1194 td->remainder -= count; 1195 td->offset += count; 1196 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1197 break; 1198 default: 1199 break; 1200 } 1201 /* release FIFO */ 1202 dwc_otg_common_rx_ack(sc); 1203 busy: 1204 return (0); 1205 complete: 1206 return (1); 1207 } 1208 1209 static uint8_t 1210 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1211 { 1212 uint32_t hcint; 1213 uint32_t hcchar; 1214 uint8_t delta; 1215 uint8_t channel; 1216 1217 channel = td->channel; 1218 1219 if (channel < DWC_OTG_MAX_CHANNELS) { 1220 hcint = sc->sc_chan_state[channel].hcint; 1221 1222 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1223 channel, td->state, hcint, 1224 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1225 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1226 1227 /* check interrupt bits */ 1228 if (hcint & (HCINT_RETRY | 1229 HCINT_ACK | HCINT_NYET)) { 1230 /* give success bits priority over failure bits */ 1231 } else if (hcint & HCINT_STALL) { 1232 DPRINTF("CH=%d STALL\n", channel); 1233 td->error_stall = 1; 1234 td->error_any = 1; 1235 goto complete; 1236 } else if (hcint & HCINT_ERRORS) { 1237 DPRINTF("CH=%d ERROR\n", channel); 1238 td->errcnt++; 1239 if (td->hcsplt != 0 || td->errcnt >= 3) { 1240 if (td->ep_type != UE_ISOCHRONOUS) { 1241 td->error_any = 1; 1242 goto complete; 1243 } 1244 } 1245 } 1246 1247 /* check channels for data, if any */ 1248 if (dwc_otg_host_data_rx_sub(sc, td)) 1249 goto complete; 1250 1251 /* refresh interrupt status */ 1252 hcint = sc->sc_chan_state[channel].hcint; 1253 1254 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1255 HCINT_ACK | HCINT_NYET)) { 1256 if (!(hcint & HCINT_ERRORS)) 1257 td->errcnt = 0; 1258 } 1259 } else { 1260 hcint = 0; 1261 } 1262 1263 switch (td->state) { 1264 case DWC_CHAN_ST_START: 1265 if (td->hcsplt != 0) 1266 goto receive_spkt; 1267 else 1268 goto receive_pkt; 1269 1270 case DWC_CHAN_ST_WAIT_ANE: 1271 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1272 if (td->ep_type == UE_INTERRUPT) { 1273 /* 1274 * The USB specification does not 1275 * mandate a particular data toggle 1276 * value for USB INTERRUPT 1277 * transfers. Switch the data toggle 1278 * value to receive the packet 1279 * correctly: 1280 */ 1281 if (hcint & HCINT_DATATGLERR) { 1282 DPRINTF("Retrying packet due to " 1283 "data toggle error\n"); 1284 td->toggle ^= 1; 1285 goto receive_pkt; 1286 } 1287 } 1288 td->did_nak++; 1289 td->tt_scheduled = 0; 1290 if (td->hcsplt != 0) 1291 goto receive_spkt; 1292 else 1293 goto receive_pkt; 1294 } else if (hcint & HCINT_NYET) { 1295 if (td->hcsplt != 0) { 1296 /* try again */ 1297 goto receive_pkt; 1298 } else { 1299 /* not a valid token for IN endpoints */ 1300 td->error_any = 1; 1301 goto complete; 1302 } 1303 } else if (hcint & HCINT_ACK) { 1304 /* wait for data - ACK arrived first */ 1305 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1306 goto busy; 1307 1308 if (td->ep_type == UE_ISOCHRONOUS) { 1309 /* check if we are complete */ 1310 if ((td->remainder == 0) || 1311 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1312 goto complete; 1313 } 1314 /* get another packet */ 1315 goto receive_pkt; 1316 } else { 1317 /* check if we are complete */ 1318 if ((td->remainder == 0) || (td->got_short != 0)) { 1319 if (td->short_pkt) 1320 goto complete; 1321 1322 /* 1323 * Else need to receive a zero length 1324 * packet. 1325 */ 1326 } 1327 td->tt_scheduled = 0; 1328 td->did_nak = 0; 1329 if (td->hcsplt != 0) 1330 goto receive_spkt; 1331 else 1332 goto receive_pkt; 1333 } 1334 } 1335 break; 1336 1337 case DWC_CHAN_ST_WAIT_S_ANE: 1338 /* 1339 * NOTE: The DWC OTG hardware provides a fake ACK in 1340 * case of interrupt and isochronous transfers: 1341 */ 1342 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1343 td->did_nak++; 1344 td->tt_scheduled = 0; 1345 goto receive_spkt; 1346 } else if (hcint & HCINT_NYET) { 1347 td->tt_scheduled = 0; 1348 goto receive_spkt; 1349 } else if (hcint & HCINT_ACK) { 1350 td->did_nak = 0; 1351 goto receive_pkt; 1352 } 1353 break; 1354 1355 case DWC_CHAN_ST_WAIT_C_PKT: 1356 goto receive_pkt; 1357 1358 default: 1359 break; 1360 } 1361 goto busy; 1362 1363 receive_pkt: 1364 /* free existing channel, if any */ 1365 dwc_otg_host_channel_free(sc, td); 1366 1367 if (td->hcsplt != 0) { 1368 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1369 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1370 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1371 goto busy; 1372 } 1373 delta = sc->sc_last_frame_num - td->tt_start_slot; 1374 if (delta > DWC_OTG_TT_SLOT_MAX) { 1375 if (td->ep_type != UE_ISOCHRONOUS) { 1376 /* we missed the service interval */ 1377 td->error_any = 1; 1378 } 1379 goto complete; 1380 } 1381 /* complete split */ 1382 td->hcsplt |= HCSPLT_COMPSPLT; 1383 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1384 dwc_otg_host_rate_check(sc, td)) { 1385 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1386 goto busy; 1387 } 1388 1389 /* allocate a new channel */ 1390 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1391 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1392 goto busy; 1393 } 1394 1395 channel = td->channel; 1396 1397 /* set toggle, if any */ 1398 if (td->set_toggle) { 1399 td->set_toggle = 0; 1400 td->toggle = 1; 1401 } 1402 1403 td->state = DWC_CHAN_ST_WAIT_ANE; 1404 1405 /* receive one packet */ 1406 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1407 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1408 (1 << HCTSIZ_PKTCNT_SHIFT) | 1409 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1410 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1411 1412 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1413 1414 hcchar = td->hcchar; 1415 hcchar |= HCCHAR_EPDIR_IN; 1416 1417 /* receive complete split ASAP */ 1418 if ((sc->sc_last_frame_num & 1) != 0) 1419 hcchar |= HCCHAR_ODDFRM; 1420 else 1421 hcchar &= ~HCCHAR_ODDFRM; 1422 1423 /* must enable channel before data can be received */ 1424 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1425 1426 /* wait until next slot before trying complete split */ 1427 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1428 1429 goto busy; 1430 1431 receive_spkt: 1432 /* free existing channel(s), if any */ 1433 dwc_otg_host_channel_free(sc, td); 1434 1435 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1436 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1437 td->state = DWC_CHAN_ST_START; 1438 goto busy; 1439 } 1440 delta = sc->sc_last_frame_num - td->tt_start_slot; 1441 if (delta > 5) { 1442 /* missed it */ 1443 td->tt_scheduled = 0; 1444 td->state = DWC_CHAN_ST_START; 1445 goto busy; 1446 } 1447 1448 /* allocate a new channel */ 1449 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1450 td->state = DWC_CHAN_ST_START; 1451 goto busy; 1452 } 1453 1454 channel = td->channel; 1455 1456 td->hcsplt &= ~HCSPLT_COMPSPLT; 1457 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1458 1459 /* receive one packet */ 1460 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1461 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1462 1463 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1464 1465 /* send after next SOF event */ 1466 if ((sc->sc_last_frame_num & 1) == 0) 1467 td->hcchar |= HCCHAR_ODDFRM; 1468 else 1469 td->hcchar &= ~HCCHAR_ODDFRM; 1470 1471 hcchar = td->hcchar; 1472 hcchar |= HCCHAR_EPDIR_IN; 1473 1474 /* wait until next slot before trying complete split */ 1475 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1476 1477 /* must enable channel before data can be received */ 1478 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1479 busy: 1480 return (1); /* busy */ 1481 1482 complete: 1483 dwc_otg_host_channel_free(sc, td); 1484 return (0); /* complete */ 1485 } 1486 1487 static uint8_t 1488 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1489 { 1490 uint32_t temp; 1491 uint16_t count; 1492 uint8_t got_short; 1493 1494 got_short = 0; 1495 1496 /* check endpoint status */ 1497 if (sc->sc_last_rx_status == 0) 1498 goto not_complete; 1499 1500 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1501 goto not_complete; 1502 1503 /* check for SETUP packet */ 1504 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1505 GRXSTSRD_STP_DATA) { 1506 if (td->remainder == 0) { 1507 /* 1508 * We are actually complete and have 1509 * received the next SETUP 1510 */ 1511 DPRINTFN(5, "faking complete\n"); 1512 return (0); /* complete */ 1513 } 1514 /* 1515 * USB Host Aborted the transfer. 1516 */ 1517 td->error_any = 1; 1518 return (0); /* complete */ 1519 } 1520 1521 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1522 GRXSTSRD_OUT_DATA) { 1523 /* release FIFO */ 1524 dwc_otg_common_rx_ack(sc); 1525 goto not_complete; 1526 } 1527 1528 /* get the packet byte count */ 1529 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1530 1531 /* verify the packet byte count */ 1532 if (count != td->max_packet_size) { 1533 if (count < td->max_packet_size) { 1534 /* we have a short packet */ 1535 td->short_pkt = 1; 1536 got_short = 1; 1537 } else { 1538 /* invalid USB packet */ 1539 td->error_any = 1; 1540 1541 /* release FIFO */ 1542 dwc_otg_common_rx_ack(sc); 1543 return (0); /* we are complete */ 1544 } 1545 } 1546 /* verify the packet byte count */ 1547 if (count > td->remainder) { 1548 /* invalid USB packet */ 1549 td->error_any = 1; 1550 1551 /* release FIFO */ 1552 dwc_otg_common_rx_ack(sc); 1553 return (0); /* we are complete */ 1554 } 1555 1556 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1557 td->remainder -= count; 1558 td->offset += count; 1559 1560 /* release FIFO */ 1561 dwc_otg_common_rx_ack(sc); 1562 1563 /* check if we are complete */ 1564 if ((td->remainder == 0) || got_short) { 1565 if (td->short_pkt) { 1566 /* we are complete */ 1567 return (0); 1568 } 1569 /* else need to receive a zero length packet */ 1570 } 1571 1572 not_complete: 1573 1574 temp = sc->sc_out_ctl[td->ep_no]; 1575 1576 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1577 1578 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1579 1580 /* enable SETUP and transfer complete interrupt */ 1581 if (td->ep_no == 0) { 1582 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1583 DXEPTSIZ_SET_NPKT(1) | 1584 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1585 } else { 1586 /* allow reception of multiple packets */ 1587 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1588 DXEPTSIZ_SET_MULTI(1) | 1589 DXEPTSIZ_SET_NPKT(4) | 1590 DXEPTSIZ_SET_NBYTES(4 * 1591 ((td->max_packet_size + 3) & ~3))); 1592 } 1593 return (1); /* not complete */ 1594 } 1595 1596 static uint8_t 1597 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1598 { 1599 uint32_t count; 1600 uint32_t hcint; 1601 uint32_t hcchar; 1602 uint8_t delta; 1603 uint8_t channel; 1604 1605 dwc_otg_host_dump_rx(sc, td); 1606 1607 channel = td->channel; 1608 1609 if (channel < DWC_OTG_MAX_CHANNELS) { 1610 hcint = sc->sc_chan_state[channel].hcint; 1611 1612 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1613 channel, td->state, hcint, 1614 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1615 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1616 1617 if (hcint & (HCINT_RETRY | 1618 HCINT_ACK | HCINT_NYET)) { 1619 /* give success bits priority over failure bits */ 1620 } else if (hcint & HCINT_STALL) { 1621 DPRINTF("CH=%d STALL\n", channel); 1622 td->error_stall = 1; 1623 td->error_any = 1; 1624 goto complete; 1625 } else if (hcint & HCINT_ERRORS) { 1626 DPRINTF("CH=%d ERROR\n", channel); 1627 td->errcnt++; 1628 if (td->hcsplt != 0 || td->errcnt >= 3) { 1629 td->error_any = 1; 1630 goto complete; 1631 } 1632 } 1633 1634 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1635 HCINT_ACK | HCINT_NYET)) { 1636 1637 if (!(hcint & HCINT_ERRORS)) 1638 td->errcnt = 0; 1639 } 1640 } else { 1641 hcint = 0; 1642 } 1643 1644 switch (td->state) { 1645 case DWC_CHAN_ST_START: 1646 goto send_pkt; 1647 1648 case DWC_CHAN_ST_WAIT_ANE: 1649 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1650 td->did_nak++; 1651 td->tt_scheduled = 0; 1652 goto send_pkt; 1653 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1654 td->offset += td->tx_bytes; 1655 td->remainder -= td->tx_bytes; 1656 td->toggle ^= 1; 1657 td->did_nak = 0; 1658 td->tt_scheduled = 0; 1659 1660 /* check remainder */ 1661 if (td->remainder == 0) { 1662 if (td->short_pkt) 1663 goto complete; 1664 1665 /* 1666 * Else we need to transmit a short 1667 * packet: 1668 */ 1669 } 1670 goto send_pkt; 1671 } 1672 break; 1673 1674 case DWC_CHAN_ST_WAIT_S_ANE: 1675 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1676 td->did_nak++; 1677 td->tt_scheduled = 0; 1678 goto send_pkt; 1679 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1680 td->did_nak = 0; 1681 goto send_cpkt; 1682 } 1683 break; 1684 1685 case DWC_CHAN_ST_WAIT_C_ANE: 1686 if (hcint & HCINT_NYET) { 1687 goto send_cpkt; 1688 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1689 td->did_nak++; 1690 td->tt_scheduled = 0; 1691 goto send_pkt; 1692 } else if (hcint & HCINT_ACK) { 1693 td->offset += td->tx_bytes; 1694 td->remainder -= td->tx_bytes; 1695 td->toggle ^= 1; 1696 td->did_nak = 0; 1697 td->tt_scheduled = 0; 1698 1699 /* check remainder */ 1700 if (td->remainder == 0) { 1701 if (td->short_pkt) 1702 goto complete; 1703 1704 /* else we need to transmit a short packet */ 1705 } 1706 goto send_pkt; 1707 } 1708 break; 1709 1710 case DWC_CHAN_ST_WAIT_C_PKT: 1711 goto send_cpkt; 1712 1713 case DWC_CHAN_ST_TX_WAIT_ISOC: 1714 1715 /* Check if isochronous OUT traffic is complete */ 1716 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1717 break; 1718 1719 td->offset += td->tx_bytes; 1720 td->remainder -= td->tx_bytes; 1721 1722 if (td->hcsplt != 0 || td->remainder == 0) 1723 goto complete; 1724 1725 /* check for next packet */ 1726 if (td->max_packet_count > 1) 1727 td->tt_xactpos++; 1728 1729 /* free existing channel, if any */ 1730 dwc_otg_host_channel_free(sc, td); 1731 1732 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1733 1734 /* FALLTHROUGH */ 1735 1736 case DWC_CHAN_ST_TX_PKT_ISOC: 1737 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1738 break; 1739 channel = td->channel; 1740 goto send_isoc_pkt; 1741 default: 1742 break; 1743 } 1744 goto busy; 1745 1746 send_pkt: 1747 /* free existing channel(s), if any */ 1748 dwc_otg_host_channel_free(sc, td); 1749 1750 if (td->hcsplt != 0) { 1751 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1752 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1753 td->state = DWC_CHAN_ST_START; 1754 goto busy; 1755 } 1756 delta = sc->sc_last_frame_num - td->tt_start_slot; 1757 if (delta > 5) { 1758 /* missed it */ 1759 td->tt_scheduled = 0; 1760 td->state = DWC_CHAN_ST_START; 1761 goto busy; 1762 } 1763 } else if (dwc_otg_host_rate_check(sc, td)) { 1764 td->state = DWC_CHAN_ST_START; 1765 goto busy; 1766 } 1767 1768 /* allocate a new channel */ 1769 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1770 td->state = DWC_CHAN_ST_START; 1771 goto busy; 1772 } 1773 1774 channel = td->channel; 1775 1776 /* set toggle, if any */ 1777 if (td->set_toggle) { 1778 td->set_toggle = 0; 1779 td->toggle = 1; 1780 } 1781 1782 if (td->ep_type == UE_ISOCHRONOUS) { 1783 send_isoc_pkt: 1784 /* Isochronous OUT transfers don't have any ACKs */ 1785 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1786 td->hcsplt &= ~HCSPLT_COMPSPLT; 1787 if (td->hcsplt != 0) { 1788 /* get maximum transfer length */ 1789 count = td->remainder; 1790 if (count > HCSPLT_XACTLEN_BURST) { 1791 DPRINTF("TT overflow\n"); 1792 td->error_any = 1; 1793 goto complete; 1794 } 1795 /* Update transaction position */ 1796 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1797 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1798 } else { 1799 /* send one packet at a time */ 1800 count = td->max_packet_size; 1801 if (td->remainder < count) { 1802 /* we have a short packet */ 1803 td->short_pkt = 1; 1804 count = td->remainder; 1805 } 1806 } 1807 } else if (td->hcsplt != 0) { 1808 1809 td->hcsplt &= ~HCSPLT_COMPSPLT; 1810 1811 /* Wait for ACK/NAK/ERR from TT */ 1812 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1813 1814 /* send one packet at a time */ 1815 count = td->max_packet_size; 1816 if (td->remainder < count) { 1817 /* we have a short packet */ 1818 td->short_pkt = 1; 1819 count = td->remainder; 1820 } 1821 } else { 1822 /* Wait for ACK/NAK/STALL from device */ 1823 td->state = DWC_CHAN_ST_WAIT_ANE; 1824 1825 /* send one packet at a time */ 1826 count = td->max_packet_size; 1827 if (td->remainder < count) { 1828 /* we have a short packet */ 1829 td->short_pkt = 1; 1830 count = td->remainder; 1831 } 1832 } 1833 1834 /* check for High-Speed multi-packets */ 1835 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1836 if (td->npkt == 0) { 1837 if (td->remainder >= (3 * td->max_packet_size)) 1838 td->npkt = 3; 1839 else if (td->remainder >= (2 * td->max_packet_size)) 1840 td->npkt = 2; 1841 else 1842 td->npkt = 1; 1843 1844 if (td->npkt > td->max_packet_count) 1845 td->npkt = td->max_packet_count; 1846 1847 td->tt_xactpos = 1; /* overload */ 1848 } 1849 if (td->tt_xactpos == td->npkt) { 1850 if (td->npkt == 1) { 1851 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1852 (count << HCTSIZ_XFERSIZE_SHIFT) | 1853 (1 << HCTSIZ_PKTCNT_SHIFT) | 1854 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1855 } else if (td->npkt == 2) { 1856 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1857 (count << HCTSIZ_XFERSIZE_SHIFT) | 1858 (1 << HCTSIZ_PKTCNT_SHIFT) | 1859 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1860 } else { 1861 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1862 (count << HCTSIZ_XFERSIZE_SHIFT) | 1863 (1 << HCTSIZ_PKTCNT_SHIFT) | 1864 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1865 } 1866 td->npkt = 0; 1867 } else { 1868 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1869 (count << HCTSIZ_XFERSIZE_SHIFT) | 1870 (1 << HCTSIZ_PKTCNT_SHIFT) | 1871 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1872 } 1873 } else { 1874 /* TODO: HCTSIZ_DOPNG */ 1875 1876 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1877 (count << HCTSIZ_XFERSIZE_SHIFT) | 1878 (1 << HCTSIZ_PKTCNT_SHIFT) | 1879 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1880 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1881 } 1882 1883 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1884 1885 hcchar = td->hcchar; 1886 hcchar &= ~HCCHAR_EPDIR_IN; 1887 1888 /* send after next SOF event */ 1889 if ((sc->sc_last_frame_num & 1) == 0) 1890 hcchar |= HCCHAR_ODDFRM; 1891 else 1892 hcchar &= ~HCCHAR_ODDFRM; 1893 1894 /* must enable before writing data to FIFO */ 1895 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1896 1897 if (count != 0) { 1898 1899 /* clear topmost word before copy */ 1900 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1901 1902 /* copy out data */ 1903 usbd_copy_out(td->pc, td->offset, 1904 sc->sc_tx_bounce_buffer, count); 1905 1906 /* transfer data into FIFO */ 1907 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1908 DOTG_DFIFO(channel), 1909 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1910 } 1911 1912 /* store number of bytes transmitted */ 1913 td->tx_bytes = count; 1914 goto busy; 1915 1916 send_cpkt: 1917 /* free existing channel, if any */ 1918 dwc_otg_host_channel_free(sc, td); 1919 1920 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1921 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1922 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1923 goto busy; 1924 } 1925 delta = sc->sc_last_frame_num - td->tt_start_slot; 1926 if (delta > DWC_OTG_TT_SLOT_MAX) { 1927 /* we missed the service interval */ 1928 if (td->ep_type != UE_ISOCHRONOUS) 1929 td->error_any = 1; 1930 goto complete; 1931 } 1932 1933 /* allocate a new channel */ 1934 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1935 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1936 goto busy; 1937 } 1938 1939 channel = td->channel; 1940 1941 td->hcsplt |= HCSPLT_COMPSPLT; 1942 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1943 1944 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1945 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1946 1947 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1948 1949 hcchar = td->hcchar; 1950 hcchar &= ~HCCHAR_EPDIR_IN; 1951 1952 /* receive complete split ASAP */ 1953 if ((sc->sc_last_frame_num & 1) != 0) 1954 hcchar |= HCCHAR_ODDFRM; 1955 else 1956 hcchar &= ~HCCHAR_ODDFRM; 1957 1958 /* must enable channel before data can be received */ 1959 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1960 1961 /* wait until next slot before trying complete split */ 1962 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1963 busy: 1964 return (1); /* busy */ 1965 1966 complete: 1967 dwc_otg_host_channel_free(sc, td); 1968 return (0); /* complete */ 1969 } 1970 1971 static uint8_t 1972 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1973 { 1974 uint32_t max_buffer; 1975 uint32_t count; 1976 uint32_t fifo_left; 1977 uint32_t mpkt; 1978 uint32_t temp; 1979 uint8_t to; 1980 1981 to = 3; /* don't loop forever! */ 1982 1983 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1984 1985 repeat: 1986 /* check for for endpoint 0 data */ 1987 1988 temp = sc->sc_last_rx_status; 1989 1990 if ((td->ep_no == 0) && (temp != 0) && 1991 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1992 1993 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1994 GRXSTSRD_STP_DATA) { 1995 1996 /* dump data - wrong direction */ 1997 dwc_otg_common_rx_ack(sc); 1998 } else { 1999 /* 2000 * The current transfer was cancelled 2001 * by the USB Host: 2002 */ 2003 td->error_any = 1; 2004 return (0); /* complete */ 2005 } 2006 } 2007 2008 /* fill in more TX data, if possible */ 2009 if (td->tx_bytes != 0) { 2010 2011 uint16_t cpkt; 2012 2013 /* check if packets have been transferred */ 2014 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2015 2016 /* get current packet number */ 2017 cpkt = DXEPTSIZ_GET_NPKT(temp); 2018 2019 if (cpkt >= td->npkt) { 2020 fifo_left = 0; 2021 } else { 2022 if (max_buffer != 0) { 2023 fifo_left = (td->npkt - cpkt) * 2024 td->max_packet_size; 2025 2026 if (fifo_left > max_buffer) 2027 fifo_left = max_buffer; 2028 } else { 2029 fifo_left = td->max_packet_size; 2030 } 2031 } 2032 2033 count = td->tx_bytes; 2034 if (count > fifo_left) 2035 count = fifo_left; 2036 2037 if (count != 0) { 2038 2039 /* clear topmost word before copy */ 2040 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2041 2042 /* copy out data */ 2043 usbd_copy_out(td->pc, td->offset, 2044 sc->sc_tx_bounce_buffer, count); 2045 2046 /* transfer data into FIFO */ 2047 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2048 DOTG_DFIFO(td->ep_no), 2049 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2050 2051 td->tx_bytes -= count; 2052 td->remainder -= count; 2053 td->offset += count; 2054 td->npkt = cpkt; 2055 } 2056 if (td->tx_bytes != 0) 2057 goto not_complete; 2058 2059 /* check remainder */ 2060 if (td->remainder == 0) { 2061 if (td->short_pkt) 2062 return (0); /* complete */ 2063 2064 /* else we need to transmit a short packet */ 2065 } 2066 } 2067 2068 if (!to--) 2069 goto not_complete; 2070 2071 /* check if not all packets have been transferred */ 2072 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2073 2074 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2075 2076 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2077 "DIEPCTL=0x%08x\n", td->ep_no, 2078 DXEPTSIZ_GET_NPKT(temp), 2079 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2080 2081 goto not_complete; 2082 } 2083 2084 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2085 2086 /* try to optimise by sending more data */ 2087 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2088 2089 /* send multiple packets at the same time */ 2090 mpkt = max_buffer / td->max_packet_size; 2091 2092 if (mpkt > 0x3FE) 2093 mpkt = 0x3FE; 2094 2095 count = td->remainder; 2096 if (count > 0x7FFFFF) 2097 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2098 2099 td->npkt = count / td->max_packet_size; 2100 2101 /* 2102 * NOTE: We could use 0x3FE instead of "mpkt" in the 2103 * check below to get more throughput, but then we 2104 * have a dependency towards non-generic chip features 2105 * to disable the TX-FIFO-EMPTY interrupts on a per 2106 * endpoint basis. Increase the maximum buffer size of 2107 * the IN endpoint to increase the performance. 2108 */ 2109 if (td->npkt > mpkt) { 2110 td->npkt = mpkt; 2111 count = td->max_packet_size * mpkt; 2112 } else if ((count == 0) || (count % td->max_packet_size)) { 2113 /* we are transmitting a short packet */ 2114 td->npkt++; 2115 td->short_pkt = 1; 2116 } 2117 } else { 2118 /* send one packet at a time */ 2119 mpkt = 1; 2120 count = td->max_packet_size; 2121 if (td->remainder < count) { 2122 /* we have a short packet */ 2123 td->short_pkt = 1; 2124 count = td->remainder; 2125 } 2126 td->npkt = 1; 2127 } 2128 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2129 DXEPTSIZ_SET_MULTI(1) | 2130 DXEPTSIZ_SET_NPKT(td->npkt) | 2131 DXEPTSIZ_SET_NBYTES(count)); 2132 2133 /* make room for buffering */ 2134 td->npkt += mpkt; 2135 2136 temp = sc->sc_in_ctl[td->ep_no]; 2137 2138 /* must enable before writing data to FIFO */ 2139 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2140 DIEPCTL_EPENA | 2141 DIEPCTL_CNAK); 2142 2143 td->tx_bytes = count; 2144 2145 /* check remainder */ 2146 if (td->tx_bytes == 0 && 2147 td->remainder == 0) { 2148 if (td->short_pkt) 2149 return (0); /* complete */ 2150 2151 /* else we need to transmit a short packet */ 2152 } 2153 goto repeat; 2154 2155 not_complete: 2156 return (1); /* not complete */ 2157 } 2158 2159 static uint8_t 2160 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2161 { 2162 uint32_t temp; 2163 2164 /* 2165 * If all packets are transferred we are complete: 2166 */ 2167 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2168 2169 /* check that all packets have been transferred */ 2170 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2171 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2172 goto not_complete; 2173 } 2174 return (0); 2175 2176 not_complete: 2177 2178 /* we only want to know if there is a SETUP packet or free IN packet */ 2179 2180 temp = sc->sc_last_rx_status; 2181 2182 if ((td->ep_no == 0) && (temp != 0) && 2183 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2184 2185 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2186 GRXSTSRD_STP_DATA) { 2187 DPRINTFN(5, "faking complete\n"); 2188 /* 2189 * Race condition: We are complete! 2190 */ 2191 return (0); 2192 } else { 2193 /* dump data - wrong direction */ 2194 dwc_otg_common_rx_ack(sc); 2195 } 2196 } 2197 return (1); /* not complete */ 2198 } 2199 2200 static void 2201 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2202 { 2203 struct dwc_otg_td *td; 2204 uint8_t toggle; 2205 uint8_t tmr_val; 2206 uint8_t tmr_res; 2207 2208 DPRINTFN(9, "\n"); 2209 2210 td = xfer->td_transfer_cache; 2211 if (td == NULL) 2212 return; 2213 2214 while (1) { 2215 if ((td->func) (sc, td)) { 2216 /* operation in progress */ 2217 break; 2218 } 2219 if (((void *)td) == xfer->td_transfer_last) { 2220 goto done; 2221 } 2222 if (td->error_any) { 2223 goto done; 2224 } else if (td->remainder > 0) { 2225 /* 2226 * We had a short transfer. If there is no alternate 2227 * next, stop processing ! 2228 */ 2229 if (!td->alt_next) 2230 goto done; 2231 } 2232 2233 /* 2234 * Fetch the next transfer descriptor and transfer 2235 * some flags to the next transfer descriptor 2236 */ 2237 tmr_res = td->tmr_res; 2238 tmr_val = td->tmr_val; 2239 toggle = td->toggle; 2240 td = td->obj_next; 2241 xfer->td_transfer_cache = td; 2242 td->toggle = toggle; /* transfer toggle */ 2243 td->tmr_res = tmr_res; 2244 td->tmr_val = tmr_val; 2245 } 2246 return; 2247 2248 done: 2249 xfer->td_transfer_cache = NULL; 2250 sc->sc_xfer_complete = 1; 2251 } 2252 2253 static uint8_t 2254 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2255 { 2256 struct dwc_otg_td *td; 2257 2258 DPRINTFN(9, "\n"); 2259 2260 td = xfer->td_transfer_cache; 2261 if (td == NULL) { 2262 /* compute all actual lengths */ 2263 dwc_otg_standard_done(xfer); 2264 return (1); 2265 } 2266 return (0); 2267 } 2268 2269 static void 2270 dwc_otg_timer(void *_sc) 2271 { 2272 struct dwc_otg_softc *sc = _sc; 2273 struct usb_xfer *xfer; 2274 struct dwc_otg_td *td; 2275 2276 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2277 2278 DPRINTF("\n"); 2279 2280 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2281 2282 /* increment timer value */ 2283 sc->sc_tmr_val++; 2284 2285 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2286 td = xfer->td_transfer_cache; 2287 if (td != NULL) { 2288 /* reset NAK counter */ 2289 td->did_nak = 0; 2290 } 2291 } 2292 2293 /* enable SOF interrupt, which will poll jobs */ 2294 dwc_otg_enable_sof_irq(sc); 2295 2296 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2297 2298 if (sc->sc_timer_active) { 2299 /* restart timer */ 2300 usb_callout_reset(&sc->sc_timer, 2301 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2302 &dwc_otg_timer, sc); 2303 } 2304 } 2305 2306 static void 2307 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2308 { 2309 if (sc->sc_timer_active != 0) 2310 return; 2311 2312 sc->sc_timer_active = 1; 2313 2314 /* restart timer */ 2315 usb_callout_reset(&sc->sc_timer, 2316 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2317 &dwc_otg_timer, sc); 2318 } 2319 2320 static void 2321 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2322 { 2323 if (sc->sc_timer_active == 0) 2324 return; 2325 2326 sc->sc_timer_active = 0; 2327 2328 /* stop timer */ 2329 usb_callout_stop(&sc->sc_timer); 2330 } 2331 2332 static void 2333 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 2334 { 2335 uint32_t hcchar; 2336 2337 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 2338 2339 /* disable host channel, if any */ 2340 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 2341 /* disable channel */ 2342 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 2343 HCCHAR_CHENA | HCCHAR_CHDIS); 2344 /* wait for chip to get its brains in order */ 2345 sc->sc_chan_state[x].wait_sof = 2; 2346 } 2347 2348 /* release TX FIFO usage, if any */ 2349 sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size; 2350 sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size; 2351 2352 /* don't release TX FIFO usage twice */ 2353 sc->sc_chan_state[x].tx_p_size = 0; 2354 sc->sc_chan_state[x].tx_np_size = 0; 2355 } 2356 2357 static uint16_t 2358 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2359 { 2360 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2361 pinfo->slot_index++; 2362 return (pinfo->slot_index); 2363 } 2364 2365 static uint8_t 2366 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2367 { 2368 TAILQ_HEAD(, usb_xfer) head; 2369 struct usb_xfer *xfer; 2370 struct usb_xfer *xfer_next; 2371 struct dwc_otg_td *td; 2372 uint16_t temp; 2373 uint16_t slot; 2374 uint8_t x; 2375 2376 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2377 2378 if (sc->sc_last_frame_num == temp) 2379 return (0); 2380 2381 sc->sc_last_frame_num = temp; 2382 2383 TAILQ_INIT(&head); 2384 2385 for (x = 0; x != sc->sc_host_ch_max; x++) { 2386 if (sc->sc_chan_state[x].wait_sof == 0) 2387 continue; 2388 2389 sc->sc_needsof = 1; 2390 if (--(sc->sc_chan_state[x].wait_sof) == 0) 2391 dwc_otg_host_channel_disable(sc, x); 2392 } 2393 2394 if ((temp & 7) == 0) { 2395 2396 /* reset the schedule */ 2397 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2398 2399 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2400 td = xfer->td_transfer_cache; 2401 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2402 continue; 2403 2404 /* check for IN direction */ 2405 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2406 continue; 2407 2408 /* execute more frames */ 2409 td->tmr_val = 0; 2410 2411 sc->sc_needsof = 1; 2412 2413 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2414 continue; 2415 2416 /* compute slot */ 2417 slot = dwc_otg_compute_isoc_rx_tt_slot( 2418 sc->sc_tt_info + td->tt_index); 2419 if (slot > 3) { 2420 /* 2421 * Not enough time to get complete 2422 * split executed. 2423 */ 2424 continue; 2425 } 2426 /* Delayed start */ 2427 td->tt_start_slot = temp + slot; 2428 td->tt_scheduled = 1; 2429 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2430 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2431 } 2432 2433 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2434 td = xfer->td_transfer_cache; 2435 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2436 continue; 2437 2438 /* check for OUT direction */ 2439 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2440 continue; 2441 2442 /* execute more frames */ 2443 td->tmr_val = 0; 2444 2445 sc->sc_needsof = 1; 2446 2447 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2448 continue; 2449 2450 /* Start ASAP */ 2451 td->tt_start_slot = temp; 2452 td->tt_scheduled = 1; 2453 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2454 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2455 } 2456 2457 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2458 td = xfer->td_transfer_cache; 2459 if (td == NULL || td->ep_type != UE_INTERRUPT) 2460 continue; 2461 2462 if (td->tt_scheduled != 0) { 2463 sc->sc_needsof = 1; 2464 continue; 2465 } 2466 2467 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2468 continue; 2469 2470 if (td->hcsplt == 0) { 2471 sc->sc_needsof = 1; 2472 td->tt_scheduled = 1; 2473 continue; 2474 } 2475 2476 /* start ASAP */ 2477 td->tt_start_slot = temp; 2478 sc->sc_needsof = 1; 2479 td->tt_scheduled = 1; 2480 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2481 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2482 } 2483 2484 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2485 td = xfer->td_transfer_cache; 2486 if (td == NULL || 2487 td->ep_type != UE_CONTROL || 2488 td->did_nak >= DWC_OTG_NAK_MAX) { 2489 continue; 2490 } 2491 2492 sc->sc_needsof = 1; 2493 2494 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2495 continue; 2496 2497 /* start ASAP */ 2498 td->tt_start_slot = temp; 2499 td->tt_scheduled = 1; 2500 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2501 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2502 } 2503 } 2504 if ((temp & 7) < 6) { 2505 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2506 td = xfer->td_transfer_cache; 2507 if (td == NULL || 2508 td->ep_type != UE_BULK || 2509 td->did_nak >= DWC_OTG_NAK_MAX) { 2510 continue; 2511 } 2512 2513 sc->sc_needsof = 1; 2514 2515 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2516 continue; 2517 2518 /* start ASAP */ 2519 td->tt_start_slot = temp; 2520 td->tt_scheduled = 1; 2521 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2522 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2523 } 2524 } 2525 2526 /* Put TT transfers in execution order at the end */ 2527 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2528 2529 /* move all TT transfers in front, keeping the current order */ 2530 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2531 td = xfer->td_transfer_cache; 2532 if (td == NULL || td->hcsplt == 0) 2533 continue; 2534 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2535 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2536 } 2537 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2538 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2539 2540 /* put non-TT BULK transfers last */ 2541 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2542 td = xfer->td_transfer_cache; 2543 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2544 continue; 2545 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2546 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2547 } 2548 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2549 2550 if ((temp & 7) == 0) { 2551 2552 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2553 (int)temp, (int)sc->sc_needsof); 2554 2555 /* update SOF IRQ mask */ 2556 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2557 if (sc->sc_needsof == 0) { 2558 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2559 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2560 } 2561 } else { 2562 if (sc->sc_needsof != 0) { 2563 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2564 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2565 } 2566 } 2567 2568 /* clear need SOF flag */ 2569 sc->sc_needsof = 0; 2570 } 2571 return (1); 2572 } 2573 2574 static void 2575 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2576 { 2577 struct usb_xfer *xfer; 2578 uint32_t temp; 2579 uint8_t got_rx_status; 2580 uint8_t x; 2581 2582 repeat: 2583 /* get all channel interrupts */ 2584 for (x = 0; x != sc->sc_host_ch_max; x++) { 2585 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2586 if (temp != 0) { 2587 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2588 temp &= ~HCINT_SOFTWARE_ONLY; 2589 sc->sc_chan_state[x].hcint |= temp; 2590 } 2591 } 2592 2593 if (sc->sc_last_rx_status == 0) { 2594 2595 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2596 if (temp & GINTSTS_RXFLVL) { 2597 /* pop current status */ 2598 sc->sc_last_rx_status = 2599 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2600 } 2601 2602 if (sc->sc_last_rx_status != 0) { 2603 2604 uint8_t ep_no; 2605 2606 temp = sc->sc_last_rx_status & 2607 GRXSTSRD_PKTSTS_MASK; 2608 2609 /* non-data messages we simply skip */ 2610 if (temp != GRXSTSRD_STP_DATA && 2611 temp != GRXSTSRD_OUT_DATA) { 2612 dwc_otg_common_rx_ack(sc); 2613 goto repeat; 2614 } 2615 2616 temp = GRXSTSRD_BCNT_GET( 2617 sc->sc_last_rx_status); 2618 ep_no = GRXSTSRD_CHNUM_GET( 2619 sc->sc_last_rx_status); 2620 2621 /* receive data, if any */ 2622 if (temp != 0) { 2623 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2624 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2625 DOTG_DFIFO(ep_no), 2626 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2627 } 2628 2629 /* check if we should dump the data */ 2630 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2631 dwc_otg_common_rx_ack(sc); 2632 goto repeat; 2633 } 2634 2635 got_rx_status = 1; 2636 2637 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2638 sc->sc_last_rx_status, ep_no, 2639 (sc->sc_last_rx_status >> 15) & 3, 2640 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2641 (sc->sc_last_rx_status >> 17) & 15); 2642 } else { 2643 got_rx_status = 0; 2644 } 2645 } else { 2646 uint8_t ep_no; 2647 2648 ep_no = GRXSTSRD_CHNUM_GET( 2649 sc->sc_last_rx_status); 2650 2651 /* check if we should dump the data */ 2652 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2653 dwc_otg_common_rx_ack(sc); 2654 goto repeat; 2655 } 2656 2657 got_rx_status = 1; 2658 } 2659 2660 /* execute FIFOs */ 2661 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2662 dwc_otg_xfer_do_fifo(sc, xfer); 2663 2664 if (got_rx_status) { 2665 /* check if data was consumed */ 2666 if (sc->sc_last_rx_status == 0) 2667 goto repeat; 2668 2669 /* disable RX FIFO level interrupt */ 2670 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2671 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2672 } 2673 2674 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2675 /* update host transfer schedule, so that new transfers can be issued */ 2676 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2677 goto repeat; 2678 } 2679 } 2680 2681 static void 2682 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2683 { 2684 struct usb_xfer *xfer; 2685 repeat: 2686 /* scan for completion events */ 2687 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2688 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2689 goto repeat; 2690 } 2691 } 2692 2693 static void 2694 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2695 { 2696 DPRINTFN(5, "vbus = %u\n", is_on); 2697 2698 /* 2699 * If the USB host mode is forced, then assume VBUS is always 2700 * present else rely on the input to this function: 2701 */ 2702 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2703 2704 if (!sc->sc_flags.status_vbus) { 2705 sc->sc_flags.status_vbus = 1; 2706 2707 /* complete root HUB interrupt endpoint */ 2708 2709 dwc_otg_root_intr(sc); 2710 } 2711 } else { 2712 if (sc->sc_flags.status_vbus) { 2713 sc->sc_flags.status_vbus = 0; 2714 sc->sc_flags.status_bus_reset = 0; 2715 sc->sc_flags.status_suspend = 0; 2716 sc->sc_flags.change_suspend = 0; 2717 sc->sc_flags.change_connect = 1; 2718 2719 /* complete root HUB interrupt endpoint */ 2720 2721 dwc_otg_root_intr(sc); 2722 } 2723 } 2724 } 2725 2726 int 2727 dwc_otg_filter_interrupt(void *arg) 2728 { 2729 struct dwc_otg_softc *sc = arg; 2730 int retval = FILTER_HANDLED; 2731 uint32_t status; 2732 2733 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2734 2735 /* read and clear interrupt status */ 2736 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2737 2738 /* clear interrupts we are handling here */ 2739 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2740 2741 /* check for USB state change interrupts */ 2742 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2743 retval = FILTER_SCHEDULE_THREAD; 2744 2745 /* clear all IN endpoint interrupts */ 2746 if (status & GINTSTS_IEPINT) { 2747 uint32_t temp; 2748 uint8_t x; 2749 2750 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2751 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2752 if (temp & DIEPMSK_XFERCOMPLMSK) { 2753 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2754 DIEPMSK_XFERCOMPLMSK); 2755 } 2756 } 2757 } 2758 2759 /* poll FIFOs, if any */ 2760 dwc_otg_interrupt_poll_locked(sc); 2761 2762 if (sc->sc_xfer_complete != 0) 2763 retval = FILTER_SCHEDULE_THREAD; 2764 2765 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2766 2767 return (retval); 2768 } 2769 2770 void 2771 dwc_otg_interrupt(void *arg) 2772 { 2773 struct dwc_otg_softc *sc = arg; 2774 uint32_t status; 2775 2776 USB_BUS_LOCK(&sc->sc_bus); 2777 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2778 2779 /* read and clear interrupt status */ 2780 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2781 2782 /* clear interrupts we are handling here */ 2783 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2784 2785 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2786 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2787 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2788 2789 if (status & GINTSTS_USBRST) { 2790 2791 /* set correct state */ 2792 sc->sc_flags.status_device_mode = 1; 2793 sc->sc_flags.status_bus_reset = 0; 2794 sc->sc_flags.status_suspend = 0; 2795 sc->sc_flags.change_suspend = 0; 2796 sc->sc_flags.change_connect = 1; 2797 2798 /* Disable SOF interrupt */ 2799 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2800 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2801 2802 /* complete root HUB interrupt endpoint */ 2803 dwc_otg_root_intr(sc); 2804 } 2805 2806 /* check for any bus state change interrupts */ 2807 if (status & GINTSTS_ENUMDONE) { 2808 2809 uint32_t temp; 2810 2811 DPRINTFN(5, "end of reset\n"); 2812 2813 /* set correct state */ 2814 sc->sc_flags.status_device_mode = 1; 2815 sc->sc_flags.status_bus_reset = 1; 2816 sc->sc_flags.status_suspend = 0; 2817 sc->sc_flags.change_suspend = 0; 2818 sc->sc_flags.change_connect = 1; 2819 sc->sc_flags.status_low_speed = 0; 2820 sc->sc_flags.port_enabled = 1; 2821 2822 /* reset FIFOs */ 2823 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2824 2825 /* reset function address */ 2826 dwc_otg_set_address(sc, 0); 2827 2828 /* figure out enumeration speed */ 2829 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2830 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2831 sc->sc_flags.status_high_speed = 1; 2832 else 2833 sc->sc_flags.status_high_speed = 0; 2834 2835 /* 2836 * Disable resume and SOF interrupt, and enable 2837 * suspend and RX frame interrupt: 2838 */ 2839 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2840 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2841 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2842 2843 /* complete root HUB interrupt endpoint */ 2844 dwc_otg_root_intr(sc); 2845 } 2846 2847 if (status & GINTSTS_PRTINT) { 2848 uint32_t hprt; 2849 2850 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2851 2852 /* clear change bits */ 2853 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2854 HPRT_PRTPWR | HPRT_PRTENCHNG | 2855 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2856 sc->sc_hprt_val); 2857 2858 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2859 2860 sc->sc_flags.status_device_mode = 0; 2861 2862 if (hprt & HPRT_PRTCONNSTS) 2863 sc->sc_flags.status_bus_reset = 1; 2864 else 2865 sc->sc_flags.status_bus_reset = 0; 2866 2867 if (hprt & HPRT_PRTENCHNG) 2868 sc->sc_flags.change_enabled = 1; 2869 2870 if (hprt & HPRT_PRTENA) 2871 sc->sc_flags.port_enabled = 1; 2872 else 2873 sc->sc_flags.port_enabled = 0; 2874 2875 if (hprt & HPRT_PRTOVRCURRCHNG) 2876 sc->sc_flags.change_over_current = 1; 2877 2878 if (hprt & HPRT_PRTOVRCURRACT) 2879 sc->sc_flags.port_over_current = 1; 2880 else 2881 sc->sc_flags.port_over_current = 0; 2882 2883 if (hprt & HPRT_PRTPWR) 2884 sc->sc_flags.port_powered = 1; 2885 else 2886 sc->sc_flags.port_powered = 0; 2887 2888 if (((hprt & HPRT_PRTSPD_MASK) 2889 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2890 sc->sc_flags.status_low_speed = 1; 2891 else 2892 sc->sc_flags.status_low_speed = 0; 2893 2894 if (((hprt & HPRT_PRTSPD_MASK) 2895 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2896 sc->sc_flags.status_high_speed = 1; 2897 else 2898 sc->sc_flags.status_high_speed = 0; 2899 2900 if (hprt & HPRT_PRTCONNDET) 2901 sc->sc_flags.change_connect = 1; 2902 2903 if (hprt & HPRT_PRTSUSP) 2904 dwc_otg_suspend_irq(sc); 2905 else 2906 dwc_otg_resume_irq(sc); 2907 2908 /* complete root HUB interrupt endpoint */ 2909 dwc_otg_root_intr(sc); 2910 2911 /* update host frame interval */ 2912 dwc_otg_update_host_frame_interval(sc); 2913 } 2914 2915 /* 2916 * If resume and suspend is set at the same time we interpret 2917 * that like RESUME. Resume is set when there is at least 3 2918 * milliseconds of inactivity on the USB BUS. 2919 */ 2920 if (status & GINTSTS_WKUPINT) { 2921 2922 DPRINTFN(5, "resume interrupt\n"); 2923 2924 dwc_otg_resume_irq(sc); 2925 2926 } else if (status & GINTSTS_USBSUSP) { 2927 2928 DPRINTFN(5, "suspend interrupt\n"); 2929 2930 dwc_otg_suspend_irq(sc); 2931 } 2932 /* check VBUS */ 2933 if (status & (GINTSTS_USBSUSP | 2934 GINTSTS_USBRST | 2935 GINTMSK_OTGINTMSK | 2936 GINTSTS_SESSREQINT)) { 2937 uint32_t temp; 2938 2939 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2940 2941 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2942 2943 dwc_otg_vbus_interrupt(sc, 2944 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2945 } 2946 2947 if (sc->sc_xfer_complete != 0) { 2948 sc->sc_xfer_complete = 0; 2949 2950 /* complete FIFOs, if any */ 2951 dwc_otg_interrupt_complete_locked(sc); 2952 2953 if (sc->sc_flags.status_device_mode == 0) { 2954 /* update host transfer schedule, so that new transfers can be issued */ 2955 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2956 dwc_otg_interrupt_poll_locked(sc); 2957 } 2958 } 2959 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2960 USB_BUS_UNLOCK(&sc->sc_bus); 2961 } 2962 2963 static void 2964 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2965 { 2966 struct dwc_otg_td *td; 2967 2968 /* get current Transfer Descriptor */ 2969 td = temp->td_next; 2970 temp->td = td; 2971 2972 /* prepare for next TD */ 2973 temp->td_next = td->obj_next; 2974 2975 /* fill out the Transfer Descriptor */ 2976 td->func = temp->func; 2977 td->pc = temp->pc; 2978 td->offset = temp->offset; 2979 td->remainder = temp->len; 2980 td->tx_bytes = 0; 2981 td->error_any = 0; 2982 td->error_stall = 0; 2983 td->npkt = 0; 2984 td->did_stall = temp->did_stall; 2985 td->short_pkt = temp->short_pkt; 2986 td->alt_next = temp->setup_alt_next; 2987 td->set_toggle = 0; 2988 td->got_short = 0; 2989 td->did_nak = 0; 2990 td->channel = DWC_OTG_MAX_CHANNELS; 2991 td->state = 0; 2992 td->errcnt = 0; 2993 td->tt_scheduled = 0; 2994 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2995 } 2996 2997 static void 2998 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2999 { 3000 struct dwc_otg_std_temp temp; 3001 struct dwc_otg_td *td; 3002 uint32_t x; 3003 uint8_t need_sync; 3004 uint8_t is_host; 3005 3006 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3007 xfer->address, UE_GET_ADDR(xfer->endpointno), 3008 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3009 3010 temp.max_frame_size = xfer->max_frame_size; 3011 3012 td = xfer->td_start[0]; 3013 xfer->td_transfer_first = td; 3014 xfer->td_transfer_cache = td; 3015 3016 /* setup temp */ 3017 3018 temp.pc = NULL; 3019 temp.td = NULL; 3020 temp.td_next = xfer->td_start[0]; 3021 temp.offset = 0; 3022 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3023 xfer->flags_int.isochronous_xfr; 3024 temp.did_stall = !xfer->flags_int.control_stall; 3025 3026 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3027 3028 /* check if we should prepend a setup message */ 3029 3030 if (xfer->flags_int.control_xfr) { 3031 if (xfer->flags_int.control_hdr) { 3032 3033 if (is_host) 3034 temp.func = &dwc_otg_host_setup_tx; 3035 else 3036 temp.func = &dwc_otg_setup_rx; 3037 3038 temp.len = xfer->frlengths[0]; 3039 temp.pc = xfer->frbuffers + 0; 3040 temp.short_pkt = temp.len ? 1 : 0; 3041 3042 /* check for last frame */ 3043 if (xfer->nframes == 1) { 3044 /* no STATUS stage yet, SETUP is last */ 3045 if (xfer->flags_int.control_act) 3046 temp.setup_alt_next = 0; 3047 } 3048 3049 dwc_otg_setup_standard_chain_sub(&temp); 3050 } 3051 x = 1; 3052 } else { 3053 x = 0; 3054 } 3055 3056 if (x != xfer->nframes) { 3057 if (xfer->endpointno & UE_DIR_IN) { 3058 if (is_host) { 3059 temp.func = &dwc_otg_host_data_rx; 3060 need_sync = 0; 3061 } else { 3062 temp.func = &dwc_otg_data_tx; 3063 need_sync = 1; 3064 } 3065 } else { 3066 if (is_host) { 3067 temp.func = &dwc_otg_host_data_tx; 3068 need_sync = 0; 3069 } else { 3070 temp.func = &dwc_otg_data_rx; 3071 need_sync = 0; 3072 } 3073 } 3074 3075 /* setup "pc" pointer */ 3076 temp.pc = xfer->frbuffers + x; 3077 } else { 3078 need_sync = 0; 3079 } 3080 while (x != xfer->nframes) { 3081 3082 /* DATA0 / DATA1 message */ 3083 3084 temp.len = xfer->frlengths[x]; 3085 3086 x++; 3087 3088 if (x == xfer->nframes) { 3089 if (xfer->flags_int.control_xfr) { 3090 if (xfer->flags_int.control_act) { 3091 temp.setup_alt_next = 0; 3092 } 3093 } else { 3094 temp.setup_alt_next = 0; 3095 } 3096 } 3097 if (temp.len == 0) { 3098 3099 /* make sure that we send an USB packet */ 3100 3101 temp.short_pkt = 0; 3102 3103 } else { 3104 3105 /* regular data transfer */ 3106 3107 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3108 } 3109 3110 dwc_otg_setup_standard_chain_sub(&temp); 3111 3112 if (xfer->flags_int.isochronous_xfr) { 3113 temp.offset += temp.len; 3114 } else { 3115 /* get next Page Cache pointer */ 3116 temp.pc = xfer->frbuffers + x; 3117 } 3118 } 3119 3120 if (xfer->flags_int.control_xfr) { 3121 3122 /* always setup a valid "pc" pointer for status and sync */ 3123 temp.pc = xfer->frbuffers + 0; 3124 temp.len = 0; 3125 temp.short_pkt = 0; 3126 temp.setup_alt_next = 0; 3127 3128 /* check if we need to sync */ 3129 if (need_sync) { 3130 /* we need a SYNC point after TX */ 3131 temp.func = &dwc_otg_data_tx_sync; 3132 dwc_otg_setup_standard_chain_sub(&temp); 3133 } 3134 3135 /* check if we should append a status stage */ 3136 if (!xfer->flags_int.control_act) { 3137 3138 /* 3139 * Send a DATA1 message and invert the current 3140 * endpoint direction. 3141 */ 3142 if (xfer->endpointno & UE_DIR_IN) { 3143 if (is_host) { 3144 temp.func = &dwc_otg_host_data_tx; 3145 need_sync = 0; 3146 } else { 3147 temp.func = &dwc_otg_data_rx; 3148 need_sync = 0; 3149 } 3150 } else { 3151 if (is_host) { 3152 temp.func = &dwc_otg_host_data_rx; 3153 need_sync = 0; 3154 } else { 3155 temp.func = &dwc_otg_data_tx; 3156 need_sync = 1; 3157 } 3158 } 3159 3160 dwc_otg_setup_standard_chain_sub(&temp); 3161 3162 /* data toggle should be DATA1 */ 3163 td = temp.td; 3164 td->set_toggle = 1; 3165 3166 if (need_sync) { 3167 /* we need a SYNC point after TX */ 3168 temp.func = &dwc_otg_data_tx_sync; 3169 dwc_otg_setup_standard_chain_sub(&temp); 3170 } 3171 } 3172 } else { 3173 /* check if we need to sync */ 3174 if (need_sync) { 3175 3176 temp.pc = xfer->frbuffers + 0; 3177 temp.len = 0; 3178 temp.short_pkt = 0; 3179 temp.setup_alt_next = 0; 3180 3181 /* we need a SYNC point after TX */ 3182 temp.func = &dwc_otg_data_tx_sync; 3183 dwc_otg_setup_standard_chain_sub(&temp); 3184 } 3185 } 3186 3187 /* must have at least one frame! */ 3188 td = temp.td; 3189 xfer->td_transfer_last = td; 3190 3191 if (is_host) { 3192 3193 struct dwc_otg_softc *sc; 3194 uint32_t hcchar; 3195 uint32_t hcsplt; 3196 3197 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3198 3199 /* get first again */ 3200 td = xfer->td_transfer_first; 3201 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3202 3203 hcchar = 3204 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3205 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3206 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3207 HCCHAR_CHENA; 3208 3209 /* 3210 * We are not always able to meet the timing 3211 * requirements of the USB interrupt endpoint's 3212 * complete split token, when doing transfers going 3213 * via a transaction translator. Use the CONTROL 3214 * transfer type instead of the INTERRUPT transfer 3215 * type in general, as a means to workaround 3216 * that. This trick should work for both FULL and LOW 3217 * speed USB traffic going through a TT. For non-TT 3218 * traffic it works aswell. The reason for using 3219 * CONTROL type instead of BULK is that some TTs might 3220 * reject LOW speed BULK traffic. 3221 */ 3222 if (td->ep_type == UE_INTERRUPT) 3223 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3224 else 3225 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3226 3227 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3228 hcchar |= HCCHAR_LSPDDEV; 3229 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3230 hcchar |= HCCHAR_EPDIR_IN; 3231 3232 switch (xfer->xroot->udev->speed) { 3233 case USB_SPEED_FULL: 3234 case USB_SPEED_LOW: 3235 /* check if root HUB port is running High Speed */ 3236 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3237 hcsplt = HCSPLT_SPLTENA | 3238 (xfer->xroot->udev->hs_port_no << 3239 HCSPLT_PRTADDR_SHIFT) | 3240 (xfer->xroot->udev->hs_hub_addr << 3241 HCSPLT_HUBADDR_SHIFT); 3242 } else { 3243 hcsplt = 0; 3244 } 3245 if (td->ep_type == UE_INTERRUPT) { 3246 uint32_t ival; 3247 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3248 if (ival == 0) 3249 ival = 1; 3250 else if (ival > 127) 3251 ival = 127; 3252 td->tmr_val = sc->sc_tmr_val + ival; 3253 td->tmr_res = ival; 3254 } else if (td->ep_type == UE_ISOCHRONOUS) { 3255 td->tmr_val = 0; 3256 td->tmr_res = 1; 3257 } else { 3258 td->tmr_val = 0; 3259 td->tmr_res = 0; 3260 } 3261 break; 3262 case USB_SPEED_HIGH: 3263 hcsplt = 0; 3264 if (td->ep_type == UE_INTERRUPT) { 3265 uint32_t ival; 3266 #if 0 3267 hcchar |= ((xfer->max_packet_count & 3) 3268 << HCCHAR_MC_SHIFT); 3269 #endif 3270 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3271 if (ival == 0) 3272 ival = 1; 3273 else if (ival > 127) 3274 ival = 127; 3275 td->tmr_val = sc->sc_tmr_val + ival; 3276 td->tmr_res = ival; 3277 } else if (td->ep_type == UE_ISOCHRONOUS) { 3278 hcchar |= ((xfer->max_packet_count & 3) 3279 << HCCHAR_MC_SHIFT); 3280 td->tmr_val = 0; 3281 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3282 } else { 3283 td->tmr_val = 0; 3284 td->tmr_res = 0; 3285 } 3286 break; 3287 default: 3288 hcsplt = 0; 3289 td->tmr_val = 0; 3290 td->tmr_res = 0; 3291 break; 3292 } 3293 3294 /* store configuration in all TD's */ 3295 while (1) { 3296 td->hcchar = hcchar; 3297 td->hcsplt = hcsplt; 3298 3299 if (((void *)td) == xfer->td_transfer_last) 3300 break; 3301 3302 td = td->obj_next; 3303 } 3304 } 3305 } 3306 3307 static void 3308 dwc_otg_timeout(void *arg) 3309 { 3310 struct usb_xfer *xfer = arg; 3311 3312 DPRINTF("xfer=%p\n", xfer); 3313 3314 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3315 3316 /* transfer is transferred */ 3317 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3318 } 3319 3320 static void 3321 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3322 { 3323 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3324 struct usb_xfer_root *xroot; 3325 struct dwc_otg_td *td; 3326 3327 DPRINTFN(9, "\n"); 3328 3329 /* 3330 * Poll one time in device mode, which will turn on the 3331 * endpoint interrupts. Else wait for SOF interrupt in host 3332 * mode. 3333 */ 3334 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3335 3336 if (sc->sc_flags.status_device_mode != 0) { 3337 dwc_otg_xfer_do_fifo(sc, xfer); 3338 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3339 goto done; 3340 } 3341 3342 /* put transfer on interrupt queue */ 3343 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3344 3345 /* start timeout, if any */ 3346 if (xfer->timeout != 0) { 3347 usbd_transfer_timeout_ms(xfer, 3348 &dwc_otg_timeout, xfer->timeout); 3349 } 3350 3351 if (sc->sc_flags.status_device_mode != 0) 3352 goto done; 3353 3354 /* enable SOF interrupt, if any */ 3355 dwc_otg_enable_sof_irq(sc); 3356 3357 td = xfer->td_transfer_cache; 3358 if (td->ep_type != UE_BULK) 3359 goto done; 3360 3361 xroot = xfer->xroot; 3362 3363 /* 3364 * Optimise the ping-pong effect by waking up other BULK 3365 * transfers belonging to the same device group: 3366 */ 3367 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3368 td = xfer->td_transfer_cache; 3369 if (td == NULL || td->ep_type != UE_BULK || xfer->xroot != xroot) 3370 continue; 3371 /* reset NAK counter */ 3372 td->did_nak = 0; 3373 } 3374 done: 3375 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3376 } 3377 3378 static void 3379 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3380 { 3381 DPRINTFN(9, "\n"); 3382 3383 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3384 3385 /* set port bit */ 3386 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3387 3388 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3389 sizeof(sc->sc_hub_idata)); 3390 } 3391 3392 static usb_error_t 3393 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3394 { 3395 struct dwc_otg_td *td; 3396 uint32_t len; 3397 usb_error_t error; 3398 3399 DPRINTFN(9, "\n"); 3400 3401 td = xfer->td_transfer_cache; 3402 3403 do { 3404 len = td->remainder; 3405 3406 /* store last data toggle */ 3407 xfer->endpoint->toggle_next = td->toggle; 3408 3409 if (xfer->aframes != xfer->nframes) { 3410 /* 3411 * Verify the length and subtract 3412 * the remainder from "frlengths[]": 3413 */ 3414 if (len > xfer->frlengths[xfer->aframes]) { 3415 td->error_any = 1; 3416 } else { 3417 xfer->frlengths[xfer->aframes] -= len; 3418 } 3419 } 3420 /* Check for transfer error */ 3421 if (td->error_any) { 3422 /* the transfer is finished */ 3423 error = (td->error_stall ? 3424 USB_ERR_STALLED : USB_ERR_IOERROR); 3425 td = NULL; 3426 break; 3427 } 3428 /* Check for short transfer */ 3429 if (len > 0) { 3430 if (xfer->flags_int.short_frames_ok || 3431 xfer->flags_int.isochronous_xfr) { 3432 /* follow alt next */ 3433 if (td->alt_next) { 3434 td = td->obj_next; 3435 } else { 3436 td = NULL; 3437 } 3438 } else { 3439 /* the transfer is finished */ 3440 td = NULL; 3441 } 3442 error = 0; 3443 break; 3444 } 3445 td = td->obj_next; 3446 3447 /* this USB frame is complete */ 3448 error = 0; 3449 break; 3450 3451 } while (0); 3452 3453 /* update transfer cache */ 3454 3455 xfer->td_transfer_cache = td; 3456 3457 return (error); 3458 } 3459 3460 static void 3461 dwc_otg_standard_done(struct usb_xfer *xfer) 3462 { 3463 usb_error_t err = 0; 3464 3465 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3466 xfer, xfer->endpoint); 3467 3468 /* reset scanner */ 3469 3470 xfer->td_transfer_cache = xfer->td_transfer_first; 3471 3472 if (xfer->flags_int.control_xfr) { 3473 3474 if (xfer->flags_int.control_hdr) { 3475 3476 err = dwc_otg_standard_done_sub(xfer); 3477 } 3478 xfer->aframes = 1; 3479 3480 if (xfer->td_transfer_cache == NULL) { 3481 goto done; 3482 } 3483 } 3484 while (xfer->aframes != xfer->nframes) { 3485 3486 err = dwc_otg_standard_done_sub(xfer); 3487 xfer->aframes++; 3488 3489 if (xfer->td_transfer_cache == NULL) { 3490 goto done; 3491 } 3492 } 3493 3494 if (xfer->flags_int.control_xfr && 3495 !xfer->flags_int.control_act) { 3496 3497 err = dwc_otg_standard_done_sub(xfer); 3498 } 3499 done: 3500 dwc_otg_device_done(xfer, err); 3501 } 3502 3503 /*------------------------------------------------------------------------* 3504 * dwc_otg_device_done 3505 * 3506 * NOTE: this function can be called more than one time on the 3507 * same USB transfer! 3508 *------------------------------------------------------------------------*/ 3509 static void 3510 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3511 { 3512 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3513 3514 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3515 xfer, xfer->endpoint, error); 3516 3517 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3518 3519 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3520 /* Interrupts are cleared by the interrupt handler */ 3521 } else { 3522 struct dwc_otg_td *td; 3523 3524 td = xfer->td_transfer_cache; 3525 if (td != NULL) 3526 dwc_otg_host_channel_free(sc, td); 3527 } 3528 /* dequeue transfer and start next transfer */ 3529 usbd_transfer_done(xfer, error); 3530 3531 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3532 } 3533 3534 static void 3535 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3536 { 3537 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3538 } 3539 3540 static void 3541 dwc_otg_set_stall(struct usb_device *udev, 3542 struct usb_endpoint *ep, uint8_t *did_stall) 3543 { 3544 struct dwc_otg_softc *sc; 3545 uint32_t temp; 3546 uint32_t reg; 3547 uint8_t ep_no; 3548 3549 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3550 3551 /* check mode */ 3552 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3553 /* not supported */ 3554 return; 3555 } 3556 3557 sc = DWC_OTG_BUS2SC(udev->bus); 3558 3559 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3560 3561 /* get endpoint address */ 3562 ep_no = ep->edesc->bEndpointAddress; 3563 3564 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3565 3566 if (ep_no & UE_DIR_IN) { 3567 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3568 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3569 } else { 3570 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3571 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3572 } 3573 3574 /* disable and stall endpoint */ 3575 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3576 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3577 3578 /* clear active OUT ep */ 3579 if (!(ep_no & UE_DIR_IN)) { 3580 3581 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3582 3583 if (sc->sc_last_rx_status != 0 && 3584 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3585 sc->sc_last_rx_status)) { 3586 /* dump data */ 3587 dwc_otg_common_rx_ack(sc); 3588 /* poll interrupt */ 3589 dwc_otg_interrupt_poll_locked(sc); 3590 dwc_otg_interrupt_complete_locked(sc); 3591 } 3592 } 3593 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3594 } 3595 3596 static void 3597 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3598 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3599 { 3600 uint32_t reg; 3601 uint32_t temp; 3602 3603 if (ep_type == UE_CONTROL) { 3604 /* clearing stall is not needed */ 3605 return; 3606 } 3607 3608 if (ep_dir) { 3609 reg = DOTG_DIEPCTL(ep_no); 3610 } else { 3611 reg = DOTG_DOEPCTL(ep_no); 3612 sc->sc_active_rx_ep |= (1U << ep_no); 3613 } 3614 3615 /* round up and mask away the multiplier count */ 3616 mps = (mps + 3) & 0x7FC; 3617 3618 if (ep_type == UE_BULK) { 3619 temp = DIEPCTL_EPTYPE_SET( 3620 DIEPCTL_EPTYPE_BULK) | 3621 DIEPCTL_USBACTEP; 3622 } else if (ep_type == UE_INTERRUPT) { 3623 temp = DIEPCTL_EPTYPE_SET( 3624 DIEPCTL_EPTYPE_INTERRUPT) | 3625 DIEPCTL_USBACTEP; 3626 } else { 3627 temp = DIEPCTL_EPTYPE_SET( 3628 DIEPCTL_EPTYPE_ISOC) | 3629 DIEPCTL_USBACTEP; 3630 } 3631 3632 temp |= DIEPCTL_MPS_SET(mps); 3633 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3634 3635 if (ep_dir) 3636 sc->sc_in_ctl[ep_no] = temp; 3637 else 3638 sc->sc_out_ctl[ep_no] = temp; 3639 3640 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3641 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3642 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3643 3644 /* we only reset the transmit FIFO */ 3645 if (ep_dir) { 3646 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3647 GRSTCTL_TXFIFO(ep_no) | 3648 GRSTCTL_TXFFLSH); 3649 3650 DWC_OTG_WRITE_4(sc, 3651 DOTG_DIEPTSIZ(ep_no), 0); 3652 } 3653 3654 /* poll interrupt */ 3655 dwc_otg_interrupt_poll_locked(sc); 3656 dwc_otg_interrupt_complete_locked(sc); 3657 } 3658 3659 static void 3660 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3661 { 3662 struct dwc_otg_softc *sc; 3663 struct usb_endpoint_descriptor *ed; 3664 3665 DPRINTFN(5, "endpoint=%p\n", ep); 3666 3667 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3668 3669 /* check mode */ 3670 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3671 /* not supported */ 3672 return; 3673 } 3674 /* get softc */ 3675 sc = DWC_OTG_BUS2SC(udev->bus); 3676 3677 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3678 3679 /* get endpoint descriptor */ 3680 ed = ep->edesc; 3681 3682 /* reset endpoint */ 3683 dwc_otg_clear_stall_sub_locked(sc, 3684 UGETW(ed->wMaxPacketSize), 3685 (ed->bEndpointAddress & UE_ADDR), 3686 (ed->bmAttributes & UE_XFERTYPE), 3687 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3688 3689 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3690 } 3691 3692 static void 3693 dwc_otg_device_state_change(struct usb_device *udev) 3694 { 3695 struct dwc_otg_softc *sc; 3696 uint8_t x; 3697 3698 /* check mode */ 3699 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3700 /* not supported */ 3701 return; 3702 } 3703 3704 /* get softc */ 3705 sc = DWC_OTG_BUS2SC(udev->bus); 3706 3707 /* deactivate all other endpoint but the control endpoint */ 3708 if (udev->state == USB_STATE_CONFIGURED || 3709 udev->state == USB_STATE_ADDRESSED) { 3710 3711 USB_BUS_LOCK(&sc->sc_bus); 3712 3713 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3714 3715 if (x < sc->sc_dev_in_ep_max) { 3716 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3717 DIEPCTL_EPDIS); 3718 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3719 } 3720 3721 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3722 DOEPCTL_EPDIS); 3723 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3724 } 3725 USB_BUS_UNLOCK(&sc->sc_bus); 3726 } 3727 } 3728 3729 int 3730 dwc_otg_init(struct dwc_otg_softc *sc) 3731 { 3732 uint32_t temp; 3733 3734 DPRINTF("start\n"); 3735 3736 /* set up the bus structure */ 3737 sc->sc_bus.usbrev = USB_REV_2_0; 3738 sc->sc_bus.methods = &dwc_otg_bus_methods; 3739 3740 usb_callout_init_mtx(&sc->sc_timer, 3741 &sc->sc_bus.bus_mtx, 0); 3742 3743 USB_BUS_LOCK(&sc->sc_bus); 3744 3745 /* turn on clocks */ 3746 dwc_otg_clocks_on(sc); 3747 3748 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3749 DPRINTF("Version = 0x%08x\n", temp); 3750 3751 /* disconnect */ 3752 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3753 DCTL_SFTDISCON); 3754 3755 /* wait for host to detect disconnect */ 3756 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3757 3758 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3759 GRSTCTL_CSFTRST); 3760 3761 /* wait a little bit for block to reset */ 3762 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3763 3764 switch (sc->sc_mode) { 3765 case DWC_MODE_DEVICE: 3766 temp = GUSBCFG_FORCEDEVMODE; 3767 break; 3768 case DWC_MODE_HOST: 3769 temp = GUSBCFG_FORCEHOSTMODE; 3770 break; 3771 default: 3772 temp = 0; 3773 break; 3774 } 3775 3776 /* select HSIC, ULPI or internal PHY mode */ 3777 switch (dwc_otg_phy_type) { 3778 case DWC_OTG_PHY_HSIC: 3779 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3780 GUSBCFG_PHYIF | 3781 GUSBCFG_TRD_TIM_SET(5) | temp); 3782 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3783 0x000000EC); 3784 3785 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3786 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3787 temp & ~GLPMCFG_HSIC_CONN); 3788 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3789 temp | GLPMCFG_HSIC_CONN); 3790 break; 3791 case DWC_OTG_PHY_ULPI: 3792 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3793 GUSBCFG_ULPI_UTMI_SEL | 3794 GUSBCFG_TRD_TIM_SET(5) | temp); 3795 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3796 3797 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3798 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3799 temp & ~GLPMCFG_HSIC_CONN); 3800 break; 3801 case DWC_OTG_PHY_INTERNAL: 3802 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3803 GUSBCFG_PHYSEL | 3804 GUSBCFG_TRD_TIM_SET(5) | temp); 3805 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3806 3807 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3808 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3809 temp & ~GLPMCFG_HSIC_CONN); 3810 3811 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3812 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3813 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3814 DOTG_GGPIO_PWRDWN); 3815 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3816 break; 3817 default: 3818 break; 3819 } 3820 3821 /* clear global nak */ 3822 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3823 DCTL_CGOUTNAK | 3824 DCTL_CGNPINNAK); 3825 3826 /* disable USB port */ 3827 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3828 3829 /* wait 10ms */ 3830 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3831 3832 /* enable USB port */ 3833 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3834 3835 /* wait 10ms */ 3836 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3837 3838 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3839 3840 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3841 3842 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3843 3844 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3845 3846 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3847 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3848 3849 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3850 3851 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3852 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3853 3854 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3855 3856 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3857 3858 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3859 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3860 sc->sc_host_ch_max); 3861 3862 /* setup FIFO */ 3863 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3864 USB_BUS_UNLOCK(&sc->sc_bus); 3865 return (EINVAL); 3866 } 3867 3868 /* enable interrupts */ 3869 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3870 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3871 3872 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3873 3874 /* enable all endpoint interrupts */ 3875 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3876 if (temp & GHWCFG2_MPI) { 3877 uint8_t x; 3878 3879 DPRINTF("Multi Process Interrupts\n"); 3880 3881 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3882 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3883 DIEPMSK_XFERCOMPLMSK); 3884 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3885 } 3886 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3887 } else { 3888 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3889 DIEPMSK_XFERCOMPLMSK); 3890 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3891 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3892 } 3893 } 3894 3895 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3896 /* setup clocks */ 3897 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3898 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3899 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3900 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3901 } 3902 3903 /* only enable global IRQ */ 3904 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3905 GAHBCFG_GLBLINTRMSK); 3906 3907 /* turn off clocks */ 3908 dwc_otg_clocks_off(sc); 3909 3910 /* read initial VBUS state */ 3911 3912 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3913 3914 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3915 3916 dwc_otg_vbus_interrupt(sc, 3917 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3918 3919 USB_BUS_UNLOCK(&sc->sc_bus); 3920 3921 /* catch any lost interrupts */ 3922 3923 dwc_otg_do_poll(&sc->sc_bus); 3924 3925 return (0); /* success */ 3926 } 3927 3928 void 3929 dwc_otg_uninit(struct dwc_otg_softc *sc) 3930 { 3931 USB_BUS_LOCK(&sc->sc_bus); 3932 3933 /* stop host timer */ 3934 dwc_otg_timer_stop(sc); 3935 3936 /* set disconnect */ 3937 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3938 DCTL_SFTDISCON); 3939 3940 /* turn off global IRQ */ 3941 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3942 3943 sc->sc_flags.port_enabled = 0; 3944 sc->sc_flags.port_powered = 0; 3945 sc->sc_flags.status_vbus = 0; 3946 sc->sc_flags.status_bus_reset = 0; 3947 sc->sc_flags.status_suspend = 0; 3948 sc->sc_flags.change_suspend = 0; 3949 sc->sc_flags.change_connect = 1; 3950 3951 dwc_otg_pull_down(sc); 3952 dwc_otg_clocks_off(sc); 3953 3954 USB_BUS_UNLOCK(&sc->sc_bus); 3955 3956 usb_callout_drain(&sc->sc_timer); 3957 } 3958 3959 static void 3960 dwc_otg_suspend(struct dwc_otg_softc *sc) 3961 { 3962 return; 3963 } 3964 3965 static void 3966 dwc_otg_resume(struct dwc_otg_softc *sc) 3967 { 3968 return; 3969 } 3970 3971 static void 3972 dwc_otg_do_poll(struct usb_bus *bus) 3973 { 3974 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3975 3976 USB_BUS_LOCK(&sc->sc_bus); 3977 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3978 dwc_otg_interrupt_poll_locked(sc); 3979 dwc_otg_interrupt_complete_locked(sc); 3980 if (sc->sc_flags.status_device_mode == 0) { 3981 /* update host transfer schedule, so that new transfers can be issued */ 3982 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 3983 dwc_otg_interrupt_poll_locked(sc); 3984 } 3985 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3986 USB_BUS_UNLOCK(&sc->sc_bus); 3987 } 3988 3989 /*------------------------------------------------------------------------* 3990 * DWC OTG bulk support 3991 * DWC OTG control support 3992 * DWC OTG interrupt support 3993 *------------------------------------------------------------------------*/ 3994 static void 3995 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3996 { 3997 } 3998 3999 static void 4000 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4001 { 4002 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4003 } 4004 4005 static void 4006 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4007 { 4008 } 4009 4010 static void 4011 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4012 { 4013 /* setup TDs */ 4014 dwc_otg_setup_standard_chain(xfer); 4015 dwc_otg_start_standard_chain(xfer); 4016 } 4017 4018 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4019 { 4020 .open = dwc_otg_device_non_isoc_open, 4021 .close = dwc_otg_device_non_isoc_close, 4022 .enter = dwc_otg_device_non_isoc_enter, 4023 .start = dwc_otg_device_non_isoc_start, 4024 }; 4025 4026 /*------------------------------------------------------------------------* 4027 * DWC OTG full speed isochronous support 4028 *------------------------------------------------------------------------*/ 4029 static void 4030 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4031 { 4032 } 4033 4034 static void 4035 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4036 { 4037 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4038 } 4039 4040 static void 4041 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4042 { 4043 } 4044 4045 static void 4046 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4047 { 4048 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4049 uint32_t temp; 4050 uint32_t msframes; 4051 uint32_t framenum; 4052 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4053 4054 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4055 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4056 4057 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4058 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4059 4060 /* get the current frame index */ 4061 framenum = (temp & HFNUM_FRNUM_MASK); 4062 } else { 4063 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4064 4065 /* get the current frame index */ 4066 framenum = DSTS_SOFFN_GET(temp); 4067 } 4068 4069 if (xfer->xroot->udev->parent_hs_hub != NULL) 4070 framenum /= 8; 4071 4072 framenum &= DWC_OTG_FRAME_MASK; 4073 4074 /* 4075 * Compute number of milliseconds worth of data traffic for 4076 * this USB transfer: 4077 */ 4078 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4079 msframes = ((xfer->nframes << shift) + 7) / 8; 4080 else 4081 msframes = xfer->nframes; 4082 4083 /* 4084 * check if the frame index is within the window where the frames 4085 * will be inserted 4086 */ 4087 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4088 4089 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4090 /* 4091 * If there is data underflow or the pipe queue is 4092 * empty we schedule the transfer a few frames ahead 4093 * of the current frame position. Else two isochronous 4094 * transfers might overlap. 4095 */ 4096 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4097 xfer->endpoint->is_synced = 1; 4098 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4099 } 4100 /* 4101 * compute how many milliseconds the insertion is ahead of the 4102 * current frame position: 4103 */ 4104 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4105 4106 /* 4107 * pre-compute when the isochronous transfer will be finished: 4108 */ 4109 xfer->isoc_time_complete = 4110 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4111 4112 /* setup TDs */ 4113 dwc_otg_setup_standard_chain(xfer); 4114 4115 /* compute frame number for next insertion */ 4116 xfer->endpoint->isoc_next += msframes; 4117 4118 /* start TD chain */ 4119 dwc_otg_start_standard_chain(xfer); 4120 } 4121 4122 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4123 { 4124 .open = dwc_otg_device_isoc_open, 4125 .close = dwc_otg_device_isoc_close, 4126 .enter = dwc_otg_device_isoc_enter, 4127 .start = dwc_otg_device_isoc_start, 4128 }; 4129 4130 /*------------------------------------------------------------------------* 4131 * DWC OTG root control support 4132 *------------------------------------------------------------------------* 4133 * Simulate a hardware HUB by handling all the necessary requests. 4134 *------------------------------------------------------------------------*/ 4135 4136 static const struct usb_device_descriptor dwc_otg_devd = { 4137 .bLength = sizeof(struct usb_device_descriptor), 4138 .bDescriptorType = UDESC_DEVICE, 4139 .bcdUSB = {0x00, 0x02}, 4140 .bDeviceClass = UDCLASS_HUB, 4141 .bDeviceSubClass = UDSUBCLASS_HUB, 4142 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4143 .bMaxPacketSize = 64, 4144 .bcdDevice = {0x00, 0x01}, 4145 .iManufacturer = 1, 4146 .iProduct = 2, 4147 .bNumConfigurations = 1, 4148 }; 4149 4150 static const struct dwc_otg_config_desc dwc_otg_confd = { 4151 .confd = { 4152 .bLength = sizeof(struct usb_config_descriptor), 4153 .bDescriptorType = UDESC_CONFIG, 4154 .wTotalLength[0] = sizeof(dwc_otg_confd), 4155 .bNumInterface = 1, 4156 .bConfigurationValue = 1, 4157 .iConfiguration = 0, 4158 .bmAttributes = UC_SELF_POWERED, 4159 .bMaxPower = 0, 4160 }, 4161 .ifcd = { 4162 .bLength = sizeof(struct usb_interface_descriptor), 4163 .bDescriptorType = UDESC_INTERFACE, 4164 .bNumEndpoints = 1, 4165 .bInterfaceClass = UICLASS_HUB, 4166 .bInterfaceSubClass = UISUBCLASS_HUB, 4167 .bInterfaceProtocol = 0, 4168 }, 4169 .endpd = { 4170 .bLength = sizeof(struct usb_endpoint_descriptor), 4171 .bDescriptorType = UDESC_ENDPOINT, 4172 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4173 .bmAttributes = UE_INTERRUPT, 4174 .wMaxPacketSize[0] = 8, 4175 .bInterval = 255, 4176 }, 4177 }; 4178 4179 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4180 4181 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4182 .bDescLength = sizeof(dwc_otg_hubd), 4183 .bDescriptorType = UDESC_HUB, 4184 .bNbrPorts = 1, 4185 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4186 .bPwrOn2PwrGood = 50, 4187 .bHubContrCurrent = 0, 4188 .DeviceRemovable = {0}, /* port is removable */ 4189 }; 4190 4191 #define STRING_VENDOR \ 4192 "D\0W\0C\0O\0T\0G" 4193 4194 #define STRING_PRODUCT \ 4195 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4196 4197 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4198 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4199 4200 static usb_error_t 4201 dwc_otg_roothub_exec(struct usb_device *udev, 4202 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4203 { 4204 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4205 const void *ptr; 4206 uint16_t len; 4207 uint16_t value; 4208 uint16_t index; 4209 usb_error_t err; 4210 4211 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4212 4213 /* buffer reset */ 4214 ptr = (const void *)&sc->sc_hub_temp; 4215 len = 0; 4216 err = 0; 4217 4218 value = UGETW(req->wValue); 4219 index = UGETW(req->wIndex); 4220 4221 /* demultiplex the control request */ 4222 4223 switch (req->bmRequestType) { 4224 case UT_READ_DEVICE: 4225 switch (req->bRequest) { 4226 case UR_GET_DESCRIPTOR: 4227 goto tr_handle_get_descriptor; 4228 case UR_GET_CONFIG: 4229 goto tr_handle_get_config; 4230 case UR_GET_STATUS: 4231 goto tr_handle_get_status; 4232 default: 4233 goto tr_stalled; 4234 } 4235 break; 4236 4237 case UT_WRITE_DEVICE: 4238 switch (req->bRequest) { 4239 case UR_SET_ADDRESS: 4240 goto tr_handle_set_address; 4241 case UR_SET_CONFIG: 4242 goto tr_handle_set_config; 4243 case UR_CLEAR_FEATURE: 4244 goto tr_valid; /* nop */ 4245 case UR_SET_DESCRIPTOR: 4246 goto tr_valid; /* nop */ 4247 case UR_SET_FEATURE: 4248 default: 4249 goto tr_stalled; 4250 } 4251 break; 4252 4253 case UT_WRITE_ENDPOINT: 4254 switch (req->bRequest) { 4255 case UR_CLEAR_FEATURE: 4256 switch (UGETW(req->wValue)) { 4257 case UF_ENDPOINT_HALT: 4258 goto tr_handle_clear_halt; 4259 case UF_DEVICE_REMOTE_WAKEUP: 4260 goto tr_handle_clear_wakeup; 4261 default: 4262 goto tr_stalled; 4263 } 4264 break; 4265 case UR_SET_FEATURE: 4266 switch (UGETW(req->wValue)) { 4267 case UF_ENDPOINT_HALT: 4268 goto tr_handle_set_halt; 4269 case UF_DEVICE_REMOTE_WAKEUP: 4270 goto tr_handle_set_wakeup; 4271 default: 4272 goto tr_stalled; 4273 } 4274 break; 4275 case UR_SYNCH_FRAME: 4276 goto tr_valid; /* nop */ 4277 default: 4278 goto tr_stalled; 4279 } 4280 break; 4281 4282 case UT_READ_ENDPOINT: 4283 switch (req->bRequest) { 4284 case UR_GET_STATUS: 4285 goto tr_handle_get_ep_status; 4286 default: 4287 goto tr_stalled; 4288 } 4289 break; 4290 4291 case UT_WRITE_INTERFACE: 4292 switch (req->bRequest) { 4293 case UR_SET_INTERFACE: 4294 goto tr_handle_set_interface; 4295 case UR_CLEAR_FEATURE: 4296 goto tr_valid; /* nop */ 4297 case UR_SET_FEATURE: 4298 default: 4299 goto tr_stalled; 4300 } 4301 break; 4302 4303 case UT_READ_INTERFACE: 4304 switch (req->bRequest) { 4305 case UR_GET_INTERFACE: 4306 goto tr_handle_get_interface; 4307 case UR_GET_STATUS: 4308 goto tr_handle_get_iface_status; 4309 default: 4310 goto tr_stalled; 4311 } 4312 break; 4313 4314 case UT_WRITE_CLASS_INTERFACE: 4315 case UT_WRITE_VENDOR_INTERFACE: 4316 /* XXX forward */ 4317 break; 4318 4319 case UT_READ_CLASS_INTERFACE: 4320 case UT_READ_VENDOR_INTERFACE: 4321 /* XXX forward */ 4322 break; 4323 4324 case UT_WRITE_CLASS_DEVICE: 4325 switch (req->bRequest) { 4326 case UR_CLEAR_FEATURE: 4327 goto tr_valid; 4328 case UR_SET_DESCRIPTOR: 4329 case UR_SET_FEATURE: 4330 break; 4331 default: 4332 goto tr_stalled; 4333 } 4334 break; 4335 4336 case UT_WRITE_CLASS_OTHER: 4337 switch (req->bRequest) { 4338 case UR_CLEAR_FEATURE: 4339 goto tr_handle_clear_port_feature; 4340 case UR_SET_FEATURE: 4341 goto tr_handle_set_port_feature; 4342 case UR_CLEAR_TT_BUFFER: 4343 case UR_RESET_TT: 4344 case UR_STOP_TT: 4345 goto tr_valid; 4346 4347 default: 4348 goto tr_stalled; 4349 } 4350 break; 4351 4352 case UT_READ_CLASS_OTHER: 4353 switch (req->bRequest) { 4354 case UR_GET_TT_STATE: 4355 goto tr_handle_get_tt_state; 4356 case UR_GET_STATUS: 4357 goto tr_handle_get_port_status; 4358 default: 4359 goto tr_stalled; 4360 } 4361 break; 4362 4363 case UT_READ_CLASS_DEVICE: 4364 switch (req->bRequest) { 4365 case UR_GET_DESCRIPTOR: 4366 goto tr_handle_get_class_descriptor; 4367 case UR_GET_STATUS: 4368 goto tr_handle_get_class_status; 4369 4370 default: 4371 goto tr_stalled; 4372 } 4373 break; 4374 default: 4375 goto tr_stalled; 4376 } 4377 goto tr_valid; 4378 4379 tr_handle_get_descriptor: 4380 switch (value >> 8) { 4381 case UDESC_DEVICE: 4382 if (value & 0xff) { 4383 goto tr_stalled; 4384 } 4385 len = sizeof(dwc_otg_devd); 4386 ptr = (const void *)&dwc_otg_devd; 4387 goto tr_valid; 4388 case UDESC_CONFIG: 4389 if (value & 0xff) { 4390 goto tr_stalled; 4391 } 4392 len = sizeof(dwc_otg_confd); 4393 ptr = (const void *)&dwc_otg_confd; 4394 goto tr_valid; 4395 case UDESC_STRING: 4396 switch (value & 0xff) { 4397 case 0: /* Language table */ 4398 len = sizeof(usb_string_lang_en); 4399 ptr = (const void *)&usb_string_lang_en; 4400 goto tr_valid; 4401 4402 case 1: /* Vendor */ 4403 len = sizeof(dwc_otg_vendor); 4404 ptr = (const void *)&dwc_otg_vendor; 4405 goto tr_valid; 4406 4407 case 2: /* Product */ 4408 len = sizeof(dwc_otg_product); 4409 ptr = (const void *)&dwc_otg_product; 4410 goto tr_valid; 4411 default: 4412 break; 4413 } 4414 break; 4415 default: 4416 goto tr_stalled; 4417 } 4418 goto tr_stalled; 4419 4420 tr_handle_get_config: 4421 len = 1; 4422 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4423 goto tr_valid; 4424 4425 tr_handle_get_status: 4426 len = 2; 4427 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4428 goto tr_valid; 4429 4430 tr_handle_set_address: 4431 if (value & 0xFF00) { 4432 goto tr_stalled; 4433 } 4434 sc->sc_rt_addr = value; 4435 goto tr_valid; 4436 4437 tr_handle_set_config: 4438 if (value >= 2) { 4439 goto tr_stalled; 4440 } 4441 sc->sc_conf = value; 4442 goto tr_valid; 4443 4444 tr_handle_get_interface: 4445 len = 1; 4446 sc->sc_hub_temp.wValue[0] = 0; 4447 goto tr_valid; 4448 4449 tr_handle_get_tt_state: 4450 tr_handle_get_class_status: 4451 tr_handle_get_iface_status: 4452 tr_handle_get_ep_status: 4453 len = 2; 4454 USETW(sc->sc_hub_temp.wValue, 0); 4455 goto tr_valid; 4456 4457 tr_handle_set_halt: 4458 tr_handle_set_interface: 4459 tr_handle_set_wakeup: 4460 tr_handle_clear_wakeup: 4461 tr_handle_clear_halt: 4462 goto tr_valid; 4463 4464 tr_handle_clear_port_feature: 4465 if (index != 1) 4466 goto tr_stalled; 4467 4468 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4469 4470 switch (value) { 4471 case UHF_PORT_SUSPEND: 4472 dwc_otg_wakeup_peer(sc); 4473 break; 4474 4475 case UHF_PORT_ENABLE: 4476 if (sc->sc_flags.status_device_mode == 0) { 4477 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4478 sc->sc_hprt_val | HPRT_PRTENA); 4479 } 4480 sc->sc_flags.port_enabled = 0; 4481 break; 4482 4483 case UHF_C_PORT_RESET: 4484 sc->sc_flags.change_reset = 0; 4485 break; 4486 4487 case UHF_C_PORT_ENABLE: 4488 sc->sc_flags.change_enabled = 0; 4489 break; 4490 4491 case UHF_C_PORT_OVER_CURRENT: 4492 sc->sc_flags.change_over_current = 0; 4493 break; 4494 4495 case UHF_PORT_TEST: 4496 case UHF_PORT_INDICATOR: 4497 /* nops */ 4498 break; 4499 4500 case UHF_PORT_POWER: 4501 sc->sc_flags.port_powered = 0; 4502 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4503 sc->sc_hprt_val = 0; 4504 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4505 } 4506 dwc_otg_pull_down(sc); 4507 dwc_otg_clocks_off(sc); 4508 break; 4509 4510 case UHF_C_PORT_CONNECTION: 4511 /* clear connect change flag */ 4512 sc->sc_flags.change_connect = 0; 4513 break; 4514 4515 case UHF_C_PORT_SUSPEND: 4516 sc->sc_flags.change_suspend = 0; 4517 break; 4518 4519 default: 4520 err = USB_ERR_IOERROR; 4521 goto done; 4522 } 4523 goto tr_valid; 4524 4525 tr_handle_set_port_feature: 4526 if (index != 1) { 4527 goto tr_stalled; 4528 } 4529 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4530 4531 switch (value) { 4532 case UHF_PORT_ENABLE: 4533 break; 4534 4535 case UHF_PORT_SUSPEND: 4536 if (sc->sc_flags.status_device_mode == 0) { 4537 /* set suspend BIT */ 4538 sc->sc_hprt_val |= HPRT_PRTSUSP; 4539 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4540 4541 /* generate HUB suspend event */ 4542 dwc_otg_suspend_irq(sc); 4543 } 4544 break; 4545 4546 case UHF_PORT_RESET: 4547 if (sc->sc_flags.status_device_mode == 0) { 4548 4549 DPRINTF("PORT RESET\n"); 4550 4551 /* enable PORT reset */ 4552 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4553 4554 /* Wait 62.5ms for reset to complete */ 4555 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4556 4557 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4558 4559 /* Wait 62.5ms for reset to complete */ 4560 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4561 4562 /* reset FIFOs */ 4563 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4564 4565 sc->sc_flags.change_reset = 1; 4566 } else { 4567 err = USB_ERR_IOERROR; 4568 } 4569 break; 4570 4571 case UHF_PORT_TEST: 4572 case UHF_PORT_INDICATOR: 4573 /* nops */ 4574 break; 4575 case UHF_PORT_POWER: 4576 sc->sc_flags.port_powered = 1; 4577 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4578 sc->sc_hprt_val |= HPRT_PRTPWR; 4579 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4580 } 4581 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4582 /* pull up D+, if any */ 4583 dwc_otg_pull_up(sc); 4584 } 4585 break; 4586 default: 4587 err = USB_ERR_IOERROR; 4588 goto done; 4589 } 4590 goto tr_valid; 4591 4592 tr_handle_get_port_status: 4593 4594 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4595 4596 if (index != 1) 4597 goto tr_stalled; 4598 4599 if (sc->sc_flags.status_vbus) 4600 dwc_otg_clocks_on(sc); 4601 else 4602 dwc_otg_clocks_off(sc); 4603 4604 /* Select Device Side Mode */ 4605 4606 if (sc->sc_flags.status_device_mode) { 4607 value = UPS_PORT_MODE_DEVICE; 4608 dwc_otg_timer_stop(sc); 4609 } else { 4610 value = 0; 4611 dwc_otg_timer_start(sc); 4612 } 4613 4614 if (sc->sc_flags.status_high_speed) 4615 value |= UPS_HIGH_SPEED; 4616 else if (sc->sc_flags.status_low_speed) 4617 value |= UPS_LOW_SPEED; 4618 4619 if (sc->sc_flags.port_powered) 4620 value |= UPS_PORT_POWER; 4621 4622 if (sc->sc_flags.port_enabled) 4623 value |= UPS_PORT_ENABLED; 4624 4625 if (sc->sc_flags.port_over_current) 4626 value |= UPS_OVERCURRENT_INDICATOR; 4627 4628 if (sc->sc_flags.status_vbus && 4629 sc->sc_flags.status_bus_reset) 4630 value |= UPS_CURRENT_CONNECT_STATUS; 4631 4632 if (sc->sc_flags.status_suspend) 4633 value |= UPS_SUSPEND; 4634 4635 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4636 4637 value = 0; 4638 4639 if (sc->sc_flags.change_connect) 4640 value |= UPS_C_CONNECT_STATUS; 4641 if (sc->sc_flags.change_suspend) 4642 value |= UPS_C_SUSPEND; 4643 if (sc->sc_flags.change_reset) 4644 value |= UPS_C_PORT_RESET; 4645 if (sc->sc_flags.change_over_current) 4646 value |= UPS_C_OVERCURRENT_INDICATOR; 4647 4648 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4649 len = sizeof(sc->sc_hub_temp.ps); 4650 goto tr_valid; 4651 4652 tr_handle_get_class_descriptor: 4653 if (value & 0xFF) { 4654 goto tr_stalled; 4655 } 4656 ptr = (const void *)&dwc_otg_hubd; 4657 len = sizeof(dwc_otg_hubd); 4658 goto tr_valid; 4659 4660 tr_stalled: 4661 err = USB_ERR_STALLED; 4662 tr_valid: 4663 done: 4664 *plength = len; 4665 *pptr = ptr; 4666 return (err); 4667 } 4668 4669 static void 4670 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4671 { 4672 struct usb_xfer *xfer; 4673 void *last_obj; 4674 uint32_t ntd; 4675 uint32_t n; 4676 uint8_t ep_no; 4677 uint8_t ep_type; 4678 4679 xfer = parm->curr_xfer; 4680 4681 /* 4682 * NOTE: This driver does not use any of the parameters that 4683 * are computed from the following values. Just set some 4684 * reasonable dummies: 4685 */ 4686 parm->hc_max_packet_size = 0x500; 4687 parm->hc_max_packet_count = 3; 4688 parm->hc_max_frame_size = 3 * 0x500; 4689 4690 usbd_transfer_setup_sub(parm); 4691 4692 /* 4693 * compute maximum number of TDs 4694 */ 4695 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4696 4697 if (ep_type == UE_CONTROL) { 4698 4699 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4700 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4701 } else { 4702 4703 ntd = xfer->nframes + 1 /* SYNC */ ; 4704 } 4705 4706 /* 4707 * check if "usbd_transfer_setup_sub" set an error 4708 */ 4709 if (parm->err) 4710 return; 4711 4712 /* 4713 * allocate transfer descriptors 4714 */ 4715 last_obj = NULL; 4716 4717 ep_no = xfer->endpointno & UE_ADDR; 4718 4719 /* 4720 * Check for a valid endpoint profile in USB device mode: 4721 */ 4722 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4723 const struct usb_hw_ep_profile *pf; 4724 4725 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4726 4727 if (pf == NULL) { 4728 /* should not happen */ 4729 parm->err = USB_ERR_INVAL; 4730 return; 4731 } 4732 } 4733 4734 /* align data */ 4735 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4736 4737 for (n = 0; n != ntd; n++) { 4738 4739 struct dwc_otg_td *td; 4740 4741 if (parm->buf) { 4742 4743 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4744 4745 /* compute shared bandwidth resource index for TT */ 4746 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4747 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4748 td->tt_index = parm->udev->device_index; 4749 else 4750 td->tt_index = parm->udev->parent_hs_hub->device_index; 4751 } else { 4752 td->tt_index = parm->udev->device_index; 4753 } 4754 4755 /* init TD */ 4756 td->max_packet_size = xfer->max_packet_size; 4757 td->max_packet_count = xfer->max_packet_count; 4758 td->ep_no = ep_no; 4759 td->ep_type = ep_type; 4760 td->obj_next = last_obj; 4761 4762 last_obj = td; 4763 } 4764 parm->size[0] += sizeof(*td); 4765 } 4766 4767 xfer->td_start[0] = last_obj; 4768 } 4769 4770 static void 4771 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4772 { 4773 return; 4774 } 4775 4776 static void 4777 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4778 struct usb_endpoint *ep) 4779 { 4780 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4781 4782 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4783 ep, udev->address, 4784 edesc->bEndpointAddress, udev->flags.usb_mode, 4785 sc->sc_rt_addr, udev->device_index); 4786 4787 if (udev->device_index != sc->sc_rt_addr) { 4788 4789 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4790 if (udev->speed != USB_SPEED_FULL && 4791 udev->speed != USB_SPEED_HIGH) { 4792 /* not supported */ 4793 return; 4794 } 4795 } else { 4796 if (udev->speed == USB_SPEED_HIGH) { 4797 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4798 /* high bandwidth endpoint - not tested */ 4799 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4800 return; 4801 } 4802 } 4803 } 4804 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4805 ep->methods = &dwc_otg_device_isoc_methods; 4806 else 4807 ep->methods = &dwc_otg_device_non_isoc_methods; 4808 } 4809 } 4810 4811 static void 4812 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4813 { 4814 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4815 4816 switch (state) { 4817 case USB_HW_POWER_SUSPEND: 4818 dwc_otg_suspend(sc); 4819 break; 4820 case USB_HW_POWER_SHUTDOWN: 4821 dwc_otg_uninit(sc); 4822 break; 4823 case USB_HW_POWER_RESUME: 4824 dwc_otg_resume(sc); 4825 break; 4826 default: 4827 break; 4828 } 4829 } 4830 4831 static void 4832 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4833 { 4834 /* DMA delay - wait until any use of memory is finished */ 4835 *pus = (2125); /* microseconds */ 4836 } 4837 4838 static void 4839 dwc_otg_device_resume(struct usb_device *udev) 4840 { 4841 DPRINTF("\n"); 4842 4843 /* poll all transfers again to restart resumed ones */ 4844 dwc_otg_do_poll(udev->bus); 4845 } 4846 4847 static void 4848 dwc_otg_device_suspend(struct usb_device *udev) 4849 { 4850 DPRINTF("\n"); 4851 } 4852 4853 static const struct usb_bus_methods dwc_otg_bus_methods = 4854 { 4855 .endpoint_init = &dwc_otg_ep_init, 4856 .xfer_setup = &dwc_otg_xfer_setup, 4857 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4858 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4859 .xfer_stall = &dwc_otg_xfer_stall, 4860 .set_stall = &dwc_otg_set_stall, 4861 .clear_stall = &dwc_otg_clear_stall, 4862 .roothub_exec = &dwc_otg_roothub_exec, 4863 .xfer_poll = &dwc_otg_do_poll, 4864 .device_state_change = &dwc_otg_device_state_change, 4865 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4866 .get_dma_delay = &dwc_otg_get_dma_delay, 4867 .device_resume = &dwc_otg_device_resume, 4868 .device_suspend = &dwc_otg_device_suspend, 4869 }; 4870