1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 6 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. 7 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * This file contains the driver for the DesignWare series USB 2.0 OTG 33 * Controller. 34 */ 35 36 /* 37 * LIMITATION: Drivers must be bound to all OUT endpoints in the 38 * active configuration for this driver to work properly. Blocking any 39 * OUT endpoint will block all OUT endpoints including the control 40 * endpoint. Usually this is not a problem. 41 */ 42 43 /* 44 * NOTE: Writing to non-existing registers appears to cause an 45 * internal reset. 46 */ 47 48 #ifdef USB_GLOBAL_INCLUDE_FILE 49 #include USB_GLOBAL_INCLUDE_FILE 50 #else 51 #include <sys/stdint.h> 52 #include <sys/stddef.h> 53 #include <sys/param.h> 54 #include <sys/queue.h> 55 #include <sys/types.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/bus.h> 59 #include <sys/module.h> 60 #include <sys/lock.h> 61 #include <sys/mutex.h> 62 #include <sys/condvar.h> 63 #include <sys/sysctl.h> 64 #include <sys/sx.h> 65 #include <sys/unistd.h> 66 #include <sys/callout.h> 67 #include <sys/malloc.h> 68 #include <sys/priv.h> 69 #include <sys/rman.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 74 #define USB_DEBUG_VAR dwc_otg_debug 75 76 #include <dev/usb/usb_core.h> 77 #include <dev/usb/usb_debug.h> 78 #include <dev/usb/usb_busdma.h> 79 #include <dev/usb/usb_process.h> 80 #include <dev/usb/usb_transfer.h> 81 #include <dev/usb/usb_device.h> 82 #include <dev/usb/usb_hub.h> 83 #include <dev/usb/usb_util.h> 84 85 #include <dev/usb/usb_controller.h> 86 #include <dev/usb/usb_bus.h> 87 #endif /* USB_GLOBAL_INCLUDE_FILE */ 88 89 #include <dev/usb/controller/dwc_otg.h> 90 #include <dev/usb/controller/dwc_otgreg.h> 91 92 #define DWC_OTG_BUS2SC(bus) \ 93 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 94 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 95 96 #define DWC_OTG_PC2UDEV(pc) \ 97 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 98 99 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 100 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 101 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 102 GINTSTS_SESSREQINT) 103 104 #ifndef DWC_OTG_PHY_DEFAULT 105 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 106 #endif 107 108 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 109 110 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 111 "USB DWC OTG"); 112 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 113 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+"); 114 115 #ifdef USB_DEBUG 116 static int dwc_otg_debug = 0; 117 118 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 119 &dwc_otg_debug, 0, "DWC OTG debug level"); 120 #endif 121 122 #define DWC_OTG_INTR_ENDPT 1 123 124 /* prototypes */ 125 126 static const struct usb_bus_methods dwc_otg_bus_methods; 127 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 128 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 129 130 static dwc_otg_cmd_t dwc_otg_setup_rx; 131 static dwc_otg_cmd_t dwc_otg_data_rx; 132 static dwc_otg_cmd_t dwc_otg_data_tx; 133 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 134 135 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 136 static dwc_otg_cmd_t dwc_otg_host_data_tx; 137 static dwc_otg_cmd_t dwc_otg_host_data_rx; 138 139 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 140 static void dwc_otg_do_poll(struct usb_bus *); 141 static void dwc_otg_standard_done(struct usb_xfer *); 142 static void dwc_otg_root_intr(struct dwc_otg_softc *); 143 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 144 145 /* 146 * Here is a configuration that the chip supports. 147 */ 148 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 149 [0] = { 150 .max_in_frame_size = 64,/* fixed */ 151 .max_out_frame_size = 64, /* fixed */ 152 .is_simplex = 1, 153 .support_control = 1, 154 } 155 }; 156 157 static void 158 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 159 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 160 { 161 struct dwc_otg_softc *sc; 162 163 sc = DWC_OTG_BUS2SC(udev->bus); 164 165 if (ep_addr < sc->sc_dev_ep_max) 166 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 167 else 168 *ppf = NULL; 169 } 170 171 static void 172 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 173 uint32_t offset, uint32_t fifo, uint32_t count) 174 { 175 uint32_t temp; 176 177 /* round down length to nearest 4-bytes */ 178 temp = count & ~3; 179 180 /* check if we can write the data directly */ 181 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 182 struct usb_page_search buf_res; 183 184 /* pre-subtract length */ 185 count -= temp; 186 187 /* iterate buffer list */ 188 do { 189 /* get current buffer pointer */ 190 usbd_get_page(pc, offset, &buf_res); 191 192 if (buf_res.length > temp) 193 buf_res.length = temp; 194 195 /* transfer data into FIFO */ 196 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 197 fifo, buf_res.buffer, buf_res.length / 4); 198 199 offset += buf_res.length; 200 fifo += buf_res.length; 201 temp -= buf_res.length; 202 } while (temp != 0); 203 } 204 205 /* check for remainder */ 206 if (count != 0) { 207 /* clear topmost word before copy */ 208 sc->sc_bounce_buffer[(count - 1) / 4] = 0; 209 210 /* copy out data */ 211 usbd_copy_out(pc, offset, 212 sc->sc_bounce_buffer, count); 213 214 /* transfer data into FIFO */ 215 bus_space_write_region_4(sc->sc_io_tag, 216 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, 217 (count + 3) / 4); 218 } 219 } 220 221 static void 222 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 223 uint32_t offset, uint32_t count) 224 { 225 uint32_t temp; 226 227 /* round down length to nearest 4-bytes */ 228 temp = count & ~3; 229 230 /* check if we can read the data directly */ 231 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 232 struct usb_page_search buf_res; 233 234 /* pre-subtract length */ 235 count -= temp; 236 237 /* iterate buffer list */ 238 do { 239 /* get current buffer pointer */ 240 usbd_get_page(pc, offset, &buf_res); 241 242 if (buf_res.length > temp) 243 buf_res.length = temp; 244 245 /* transfer data from FIFO */ 246 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 247 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); 248 249 offset += buf_res.length; 250 sc->sc_current_rx_fifo += buf_res.length; 251 sc->sc_current_rx_bytes -= buf_res.length; 252 temp -= buf_res.length; 253 } while (temp != 0); 254 } 255 256 /* check for remainder */ 257 if (count != 0) { 258 /* read data into bounce buffer */ 259 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 260 sc->sc_current_rx_fifo, 261 sc->sc_bounce_buffer, (count + 3) / 4); 262 263 /* store data into proper buffer */ 264 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); 265 266 /* round length up to nearest 4 bytes */ 267 count = (count + 3) & ~3; 268 269 /* update counters */ 270 sc->sc_current_rx_bytes -= count; 271 sc->sc_current_rx_fifo += count; 272 } 273 } 274 275 static void 276 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 277 { 278 uint32_t temp; 279 280 /* reset FIFO */ 281 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 282 283 /* wait for reset to complete */ 284 for (temp = 0; temp != 16; temp++) { 285 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 286 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 287 break; 288 } 289 } 290 291 static int 292 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 293 { 294 struct dwc_otg_profile *pf; 295 uint32_t fifo_size; 296 uint32_t fifo_regs; 297 uint32_t tx_start; 298 uint8_t x; 299 300 fifo_size = sc->sc_fifo_size; 301 302 /* 303 * NOTE: Reserved fixed size area at end of RAM, which must 304 * not be allocated to the FIFOs: 305 */ 306 fifo_regs = 4 * 16; 307 308 if (fifo_size < fifo_regs) { 309 DPRINTF("Too little FIFO\n"); 310 return (EINVAL); 311 } 312 313 /* subtract FIFO regs from total once */ 314 fifo_size -= fifo_regs; 315 316 /* split equally for IN and OUT */ 317 fifo_size /= 2; 318 319 /* Align to 4 bytes boundary (refer to PGM) */ 320 fifo_size &= ~3; 321 322 /* set global receive FIFO size */ 323 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 324 325 tx_start = fifo_size; 326 327 if (fifo_size < 64) { 328 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 329 return (EINVAL); 330 } 331 332 if (mode == DWC_MODE_HOST) { 333 /* reset active endpoints */ 334 sc->sc_active_rx_ep = 0; 335 336 /* split equally for periodic and non-periodic */ 337 fifo_size /= 2; 338 339 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 340 341 /* align to 4 bytes boundary */ 342 fifo_size &= ~3; 343 344 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 345 ((fifo_size / 4) << 16) | 346 (tx_start / 4)); 347 348 tx_start += fifo_size; 349 350 for (x = 0; x != sc->sc_host_ch_max; x++) { 351 /* enable all host interrupts */ 352 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 353 HCINT_DEFAULT_MASK); 354 } 355 356 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 357 ((fifo_size / 4) << 16) | 358 (tx_start / 4)); 359 360 /* reset host channel state */ 361 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 362 363 /* enable all host channel interrupts */ 364 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 365 (1U << sc->sc_host_ch_max) - 1U); 366 367 /* enable proper host channel interrupts */ 368 sc->sc_irq_mask |= GINTMSK_HCHINTMSK; 369 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; 370 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 371 } 372 373 if (mode == DWC_MODE_DEVICE) { 374 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 375 (0x10 << 16) | (tx_start / 4)); 376 fifo_size -= 0x40; 377 tx_start += 0x40; 378 379 /* setup control endpoint profile */ 380 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 381 382 /* reset active endpoints */ 383 sc->sc_active_rx_ep = 1; 384 385 for (x = 1; x != sc->sc_dev_ep_max; x++) { 386 pf = sc->sc_hw_ep_profile + x; 387 388 pf->usb.max_out_frame_size = 1024 * 3; 389 pf->usb.is_simplex = 0; /* assume duplex */ 390 pf->usb.support_bulk = 1; 391 pf->usb.support_interrupt = 1; 392 pf->usb.support_isochronous = 1; 393 pf->usb.support_out = 1; 394 395 if (x < sc->sc_dev_in_ep_max) { 396 uint32_t limit; 397 398 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 399 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 400 DWC_OTG_TX_MAX_FIFO_SIZE); 401 402 /* see if there is enough FIFO space */ 403 if (limit <= fifo_size) { 404 pf->max_buffer = limit; 405 pf->usb.support_in = 1; 406 } else { 407 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 408 if (limit <= fifo_size) { 409 pf->usb.support_in = 1; 410 } else { 411 pf->usb.is_simplex = 1; 412 limit = 0; 413 } 414 } 415 /* set FIFO size */ 416 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 417 ((limit / 4) << 16) | (tx_start / 4)); 418 tx_start += limit; 419 fifo_size -= limit; 420 pf->usb.max_in_frame_size = limit; 421 } else { 422 pf->usb.is_simplex = 1; 423 } 424 425 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 426 pf->usb.max_in_frame_size, 427 pf->usb.max_out_frame_size); 428 } 429 430 /* enable proper device channel interrupts */ 431 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; 432 sc->sc_irq_mask |= GINTMSK_IEPINTMSK; 433 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 434 } 435 436 /* reset RX FIFO */ 437 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 438 439 if (mode != DWC_MODE_OTG) { 440 /* reset all TX FIFOs */ 441 dwc_otg_tx_fifo_reset(sc, 442 GRSTCTL_TXFIFO(0x10) | 443 GRSTCTL_TXFFLSH); 444 } else { 445 /* reset active endpoints */ 446 sc->sc_active_rx_ep = 0; 447 448 /* reset host channel state */ 449 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 450 } 451 return (0); 452 } 453 454 static uint8_t 455 dwc_otg_uses_split(struct usb_device *udev) 456 { 457 /* 458 * When a LOW or FULL speed device is connected directly to 459 * the USB port we don't use split transactions: 460 */ 461 return (udev->speed != USB_SPEED_HIGH && 462 udev->parent_hs_hub != NULL && 463 udev->parent_hs_hub->parent_hub != NULL); 464 } 465 466 static void 467 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 468 { 469 470 /* 471 * Disabled until further. Assuming that the register is already 472 * programmed correctly by the boot loader. 473 */ 474 #if 0 475 uint32_t temp; 476 477 /* setup HOST frame interval register, based on existing value */ 478 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 479 if (temp >= 10000) 480 temp /= 1000; 481 else 482 temp /= 125; 483 484 /* figure out nearest X-tal value */ 485 if (temp >= 54) 486 temp = 60; /* MHz */ 487 else if (temp >= 39) 488 temp = 48; /* MHz */ 489 else 490 temp = 30; /* MHz */ 491 492 if (sc->sc_flags.status_high_speed) 493 temp *= 125; 494 else 495 temp *= 1000; 496 497 DPRINTF("HFIR=0x%08x\n", temp); 498 499 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 500 #endif 501 } 502 503 static void 504 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 505 { 506 if (sc->sc_flags.clocks_off && 507 sc->sc_flags.port_powered) { 508 DPRINTFN(5, "\n"); 509 510 /* TODO - platform specific */ 511 512 sc->sc_flags.clocks_off = 0; 513 } 514 } 515 516 static void 517 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 518 { 519 if (!sc->sc_flags.clocks_off) { 520 DPRINTFN(5, "\n"); 521 522 /* TODO - platform specific */ 523 524 sc->sc_flags.clocks_off = 1; 525 } 526 } 527 528 static void 529 dwc_otg_pull_up(struct dwc_otg_softc *sc) 530 { 531 uint32_t temp; 532 533 /* pullup D+, if possible */ 534 535 if (!sc->sc_flags.d_pulled_up && 536 sc->sc_flags.port_powered) { 537 sc->sc_flags.d_pulled_up = 1; 538 539 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 540 temp &= ~DCTL_SFTDISCON; 541 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 542 } 543 } 544 545 static void 546 dwc_otg_pull_down(struct dwc_otg_softc *sc) 547 { 548 uint32_t temp; 549 550 /* pulldown D+, if possible */ 551 552 if (sc->sc_flags.d_pulled_up) { 553 sc->sc_flags.d_pulled_up = 0; 554 555 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 556 temp |= DCTL_SFTDISCON; 557 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 558 } 559 } 560 561 static void 562 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 563 { 564 /* In device mode we don't use the SOF interrupt */ 565 if (sc->sc_flags.status_device_mode != 0) 566 return; 567 /* Ensure the SOF interrupt is not disabled */ 568 sc->sc_needsof = 1; 569 /* Check if the SOF interrupt is already enabled */ 570 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 571 return; 572 sc->sc_irq_mask |= GINTMSK_SOFMSK; 573 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 574 } 575 576 static void 577 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 578 { 579 if (sc->sc_flags.status_suspend) { 580 /* update status bits */ 581 sc->sc_flags.status_suspend = 0; 582 sc->sc_flags.change_suspend = 1; 583 584 if (sc->sc_flags.status_device_mode) { 585 /* 586 * Disable resume interrupt and enable suspend 587 * interrupt: 588 */ 589 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 590 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 591 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 592 } 593 594 /* complete root HUB interrupt endpoint */ 595 dwc_otg_root_intr(sc); 596 } 597 } 598 599 static void 600 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 601 { 602 if (!sc->sc_flags.status_suspend) { 603 /* update status bits */ 604 sc->sc_flags.status_suspend = 1; 605 sc->sc_flags.change_suspend = 1; 606 607 if (sc->sc_flags.status_device_mode) { 608 /* 609 * Disable suspend interrupt and enable resume 610 * interrupt: 611 */ 612 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 613 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 614 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 615 } 616 617 /* complete root HUB interrupt endpoint */ 618 dwc_otg_root_intr(sc); 619 } 620 } 621 622 static void 623 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 624 { 625 if (!sc->sc_flags.status_suspend) 626 return; 627 628 DPRINTFN(5, "Remote wakeup\n"); 629 630 if (sc->sc_flags.status_device_mode) { 631 uint32_t temp; 632 633 /* enable remote wakeup signalling */ 634 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 635 temp |= DCTL_RMTWKUPSIG; 636 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 637 638 /* Wait 8ms for remote wakeup to complete. */ 639 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 640 641 temp &= ~DCTL_RMTWKUPSIG; 642 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 643 } else { 644 /* enable USB port */ 645 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 646 647 /* wait 10ms */ 648 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 649 650 /* resume port */ 651 sc->sc_hprt_val |= HPRT_PRTRES; 652 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 653 654 /* Wait 100ms for resume signalling to complete. */ 655 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 656 657 /* clear suspend and resume */ 658 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 659 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 660 661 /* Wait 4ms */ 662 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 663 } 664 665 /* need to fake resume IRQ */ 666 dwc_otg_resume_irq(sc); 667 } 668 669 static void 670 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 671 { 672 uint32_t temp; 673 674 DPRINTFN(5, "addr=%d\n", addr); 675 676 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 677 temp &= ~DCFG_DEVADDR_SET(0x7F); 678 temp |= DCFG_DEVADDR_SET(addr); 679 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 680 } 681 682 static void 683 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 684 { 685 DPRINTFN(5, "RX status clear\n"); 686 687 /* enable RX FIFO level interrupt */ 688 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 689 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 690 691 if (sc->sc_current_rx_bytes != 0) { 692 /* need to dump remaining data */ 693 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 694 sc->sc_current_rx_fifo, sc->sc_bounce_buffer, 695 sc->sc_current_rx_bytes / 4); 696 /* clear number of active bytes to receive */ 697 sc->sc_current_rx_bytes = 0; 698 } 699 /* clear cached status */ 700 sc->sc_last_rx_status = 0; 701 } 702 703 static void 704 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 705 { 706 uint32_t hcint; 707 708 /* clear all pending interrupts */ 709 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 710 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 711 712 /* clear buffered interrupts */ 713 sc->sc_chan_state[x].hcint = 0; 714 } 715 716 static uint8_t 717 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 718 { 719 uint32_t temp; 720 721 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 722 723 if (td->ep_type == UE_ISOCHRONOUS) { 724 /* 725 * NOTE: USB INTERRUPT transactions are executed like 726 * USB CONTROL transactions! See the setup standard 727 * chain function for more information. 728 */ 729 if (!(temp & GINTSTS_PTXFEMP)) { 730 DPRINTF("Periodic TX FIFO is not empty\n"); 731 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 732 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 733 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 734 } 735 return (1); /* busy */ 736 } 737 } else { 738 if (!(temp & GINTSTS_NPTXFEMP)) { 739 DPRINTF("Non-periodic TX FIFO is not empty\n"); 740 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 741 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 742 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 743 } 744 return (1); /* busy */ 745 } 746 } 747 return (0); /* ready for transmit */ 748 } 749 750 static uint8_t 751 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 752 struct dwc_otg_td *td, uint8_t is_out) 753 { 754 uint8_t x; 755 uint8_t y; 756 uint8_t z; 757 758 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) 759 return (0); /* already allocated */ 760 761 /* check if device is suspended */ 762 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 763 return (1); /* busy - cannot transfer data */ 764 765 /* compute needed TX FIFO size */ 766 if (is_out != 0) { 767 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) 768 return (1); /* busy - cannot transfer data */ 769 } 770 z = td->max_packet_count; 771 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 772 /* check if channel is allocated */ 773 if (sc->sc_chan_state[x].allocated != 0) 774 continue; 775 /* check if channel is still enabled */ 776 if (sc->sc_chan_state[x].wait_halted != 0) 777 continue; 778 /* store channel number */ 779 td->channel[y++] = x; 780 /* check if we got all channels */ 781 if (y == z) 782 break; 783 } 784 if (y != z) { 785 /* reset channel variable */ 786 td->channel[0] = DWC_OTG_MAX_CHANNELS; 787 td->channel[1] = DWC_OTG_MAX_CHANNELS; 788 td->channel[2] = DWC_OTG_MAX_CHANNELS; 789 /* wait a bit */ 790 dwc_otg_enable_sof_irq(sc); 791 return (1); /* busy - not enough channels */ 792 } 793 794 for (y = 0; y != z; y++) { 795 x = td->channel[y]; 796 797 /* set allocated */ 798 sc->sc_chan_state[x].allocated = 1; 799 800 /* set wait halted */ 801 sc->sc_chan_state[x].wait_halted = 1; 802 803 /* clear interrupts */ 804 dwc_otg_clear_hcint(sc, x); 805 806 DPRINTF("CH=%d HCCHAR=0x%08x " 807 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 808 809 /* set active channel */ 810 sc->sc_active_rx_ep |= (1 << x); 811 } 812 return (0); /* allocated */ 813 } 814 815 static void 816 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) 817 { 818 uint32_t hcchar; 819 uint8_t x; 820 821 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) 822 return; /* already freed */ 823 824 /* free channel */ 825 x = td->channel[index]; 826 td->channel[index] = DWC_OTG_MAX_CHANNELS; 827 828 DPRINTF("CH=%d\n", x); 829 830 /* 831 * We need to let programmed host channels run till complete 832 * else the host channel will stop functioning. 833 */ 834 sc->sc_chan_state[x].allocated = 0; 835 836 /* ack any pending messages */ 837 if (sc->sc_last_rx_status != 0 && 838 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 839 dwc_otg_common_rx_ack(sc); 840 } 841 842 /* clear active channel */ 843 sc->sc_active_rx_ep &= ~(1 << x); 844 845 /* check if already halted */ 846 if (sc->sc_chan_state[x].wait_halted == 0) 847 return; 848 849 /* disable host channel */ 850 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 851 if (hcchar & HCCHAR_CHENA) { 852 DPRINTF("Halting channel %d\n", x); 853 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 854 hcchar | HCCHAR_CHDIS); 855 /* don't write HCCHAR until the channel is halted */ 856 } else { 857 sc->sc_chan_state[x].wait_halted = 0; 858 } 859 } 860 861 static void 862 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 863 { 864 uint8_t x; 865 for (x = 0; x != td->max_packet_count; x++) 866 dwc_otg_host_channel_free_sub(sc, td, x); 867 } 868 869 static void 870 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 871 { 872 uint8_t x; 873 /* dump any pending messages */ 874 if (sc->sc_last_rx_status == 0) 875 return; 876 for (x = 0; x != td->max_packet_count; x++) { 877 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || 878 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) 879 continue; 880 dwc_otg_common_rx_ack(sc); 881 break; 882 } 883 } 884 885 static uint8_t 886 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 887 { 888 struct usb_device_request req __aligned(4); 889 uint32_t hcint; 890 uint32_t hcchar; 891 uint8_t delta; 892 893 dwc_otg_host_dump_rx(sc, td); 894 895 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 896 hcint = sc->sc_chan_state[td->channel[0]].hcint; 897 898 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 899 td->channel[0], td->state, hcint, 900 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 901 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 902 } else { 903 hcint = 0; 904 goto check_state; 905 } 906 907 if (hcint & (HCINT_RETRY | 908 HCINT_ACK | HCINT_NYET)) { 909 /* give success bits priority over failure bits */ 910 } else if (hcint & HCINT_STALL) { 911 DPRINTF("CH=%d STALL\n", td->channel[0]); 912 td->error_stall = 1; 913 td->error_any = 1; 914 goto complete; 915 } else if (hcint & HCINT_ERRORS) { 916 DPRINTF("CH=%d ERROR\n", td->channel[0]); 917 td->errcnt++; 918 if (td->hcsplt != 0 || td->errcnt >= 3) { 919 td->error_any = 1; 920 goto complete; 921 } 922 } 923 924 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 925 HCINT_ACK | HCINT_NYET)) { 926 if (!(hcint & HCINT_ERRORS)) 927 td->errcnt = 0; 928 } 929 930 check_state: 931 switch (td->state) { 932 case DWC_CHAN_ST_START: 933 goto send_pkt; 934 935 case DWC_CHAN_ST_WAIT_ANE: 936 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 937 td->did_nak = 1; 938 td->tt_scheduled = 0; 939 goto send_pkt; 940 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 941 td->offset += td->tx_bytes; 942 td->remainder -= td->tx_bytes; 943 td->toggle = 1; 944 td->tt_scheduled = 0; 945 goto complete; 946 } 947 break; 948 949 case DWC_CHAN_ST_WAIT_S_ANE: 950 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 951 td->did_nak = 1; 952 td->tt_scheduled = 0; 953 goto send_pkt; 954 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 955 goto send_cpkt; 956 } 957 break; 958 959 case DWC_CHAN_ST_WAIT_C_ANE: 960 if (hcint & HCINT_NYET) { 961 goto send_cpkt; 962 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 963 td->did_nak = 1; 964 td->tt_scheduled = 0; 965 goto send_pkt; 966 } else if (hcint & HCINT_ACK) { 967 td->offset += td->tx_bytes; 968 td->remainder -= td->tx_bytes; 969 td->toggle = 1; 970 goto complete; 971 } 972 break; 973 974 case DWC_CHAN_ST_WAIT_C_PKT: 975 goto send_cpkt; 976 977 default: 978 break; 979 } 980 goto busy; 981 982 send_pkt: 983 /* free existing channel, if any */ 984 dwc_otg_host_channel_free(sc, td); 985 986 if (sizeof(req) != td->remainder) { 987 td->error_any = 1; 988 goto complete; 989 } 990 991 if (td->hcsplt != 0) { 992 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 993 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 994 td->state = DWC_CHAN_ST_START; 995 goto busy; 996 } 997 delta = sc->sc_last_frame_num - td->tt_start_slot; 998 if (delta > 5) { 999 /* missed it */ 1000 td->tt_scheduled = 0; 1001 td->state = DWC_CHAN_ST_START; 1002 goto busy; 1003 } 1004 } 1005 1006 /* allocate a new channel */ 1007 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1008 td->state = DWC_CHAN_ST_START; 1009 goto busy; 1010 } 1011 1012 if (td->hcsplt != 0) { 1013 td->hcsplt &= ~HCSPLT_COMPSPLT; 1014 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1015 } else { 1016 td->state = DWC_CHAN_ST_WAIT_ANE; 1017 } 1018 1019 /* copy out control request */ 1020 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1021 1022 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1023 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 1024 (1 << HCTSIZ_PKTCNT_SHIFT) | 1025 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1026 1027 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1028 1029 hcchar = td->hcchar; 1030 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1031 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1032 1033 /* must enable channel before writing data to FIFO */ 1034 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1035 1036 /* transfer data into FIFO */ 1037 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1038 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 1039 1040 /* wait until next slot before trying complete split */ 1041 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1042 1043 /* store number of bytes transmitted */ 1044 td->tx_bytes = sizeof(req); 1045 goto busy; 1046 1047 send_cpkt: 1048 /* free existing channel, if any */ 1049 dwc_otg_host_channel_free(sc, td); 1050 1051 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1052 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1053 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1054 goto busy; 1055 } 1056 delta = sc->sc_last_frame_num - td->tt_start_slot; 1057 if (delta > DWC_OTG_TT_SLOT_MAX) { 1058 /* we missed the service interval */ 1059 if (td->ep_type != UE_ISOCHRONOUS) 1060 td->error_any = 1; 1061 goto complete; 1062 } 1063 /* allocate a new channel */ 1064 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1065 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1066 goto busy; 1067 } 1068 1069 /* wait until next slot before trying complete split */ 1070 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1071 1072 td->hcsplt |= HCSPLT_COMPSPLT; 1073 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1074 1075 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1076 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1077 1078 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1079 1080 hcchar = td->hcchar; 1081 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1082 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1083 1084 /* must enable channel before writing data to FIFO */ 1085 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1086 1087 busy: 1088 return (1); /* busy */ 1089 1090 complete: 1091 dwc_otg_host_channel_free(sc, td); 1092 return (0); /* complete */ 1093 } 1094 1095 static uint8_t 1096 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1097 { 1098 struct usb_device_request req __aligned(4); 1099 uint32_t temp; 1100 uint16_t count; 1101 1102 /* check endpoint status */ 1103 1104 if (sc->sc_last_rx_status == 0) 1105 goto not_complete; 1106 1107 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 1108 goto not_complete; 1109 1110 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1111 GRXSTSRD_STP_DATA) { 1112 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1113 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 1114 /* release FIFO */ 1115 dwc_otg_common_rx_ack(sc); 1116 goto not_complete; 1117 } 1118 /* release FIFO */ 1119 dwc_otg_common_rx_ack(sc); 1120 return (0); /* complete */ 1121 } 1122 1123 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1124 GRXSTSRD_DPID_DATA0) { 1125 /* release FIFO */ 1126 dwc_otg_common_rx_ack(sc); 1127 goto not_complete; 1128 } 1129 1130 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 1131 1132 /* clear did stall */ 1133 td->did_stall = 0; 1134 1135 /* get the packet byte count */ 1136 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1137 1138 if (count != sizeof(req)) { 1139 DPRINTFN(0, "Unsupported SETUP packet " 1140 "length, %d bytes\n", count); 1141 /* release FIFO */ 1142 dwc_otg_common_rx_ack(sc); 1143 goto not_complete; 1144 } 1145 1146 /* read FIFO */ 1147 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); 1148 1149 /* copy out control request */ 1150 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1151 1152 td->offset = sizeof(req); 1153 td->remainder = 0; 1154 1155 /* sneak peek the set address */ 1156 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1157 (req.bRequest == UR_SET_ADDRESS)) { 1158 /* must write address before ZLP */ 1159 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1160 } 1161 1162 /* don't send any data by default */ 1163 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1164 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1165 1166 /* reset IN endpoint buffer */ 1167 dwc_otg_tx_fifo_reset(sc, 1168 GRSTCTL_TXFIFO(0) | 1169 GRSTCTL_TXFFLSH); 1170 1171 /* acknowledge RX status */ 1172 dwc_otg_common_rx_ack(sc); 1173 td->did_stall = 1; 1174 1175 not_complete: 1176 /* abort any ongoing transfer, before enabling again */ 1177 if (!td->did_stall) { 1178 td->did_stall = 1; 1179 1180 DPRINTFN(5, "stalling IN and OUT direction\n"); 1181 1182 temp = sc->sc_out_ctl[0]; 1183 1184 /* set stall after enabling endpoint */ 1185 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1186 temp | DOEPCTL_STALL); 1187 1188 temp = sc->sc_in_ctl[0]; 1189 1190 /* set stall assuming endpoint is enabled */ 1191 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1192 temp | DIEPCTL_STALL); 1193 } 1194 return (1); /* not complete */ 1195 } 1196 1197 static uint8_t 1198 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1199 { 1200 uint8_t delta; 1201 1202 delta = sc->sc_tmr_val - td->tmr_val; 1203 if (delta >= 128) 1204 return (1); /* busy */ 1205 1206 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1207 1208 /* set toggle, if any */ 1209 if (td->set_toggle) { 1210 td->set_toggle = 0; 1211 td->toggle = 1; 1212 } 1213 return (0); 1214 } 1215 1216 static uint8_t 1217 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1218 { 1219 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1220 1221 if (td->ep_type == UE_ISOCHRONOUS) { 1222 /* non TT isochronous traffic */ 1223 if (frame_num & (td->tmr_res - 1)) 1224 goto busy; 1225 if ((frame_num ^ td->tmr_val) & td->tmr_res) 1226 goto busy; 1227 td->tmr_val = td->tmr_res + sc->sc_last_frame_num; 1228 td->toggle = 0; 1229 return (0); 1230 } else if (td->ep_type == UE_INTERRUPT) { 1231 if (!td->tt_scheduled) 1232 goto busy; 1233 td->tt_scheduled = 0; 1234 return (0); 1235 } else if (td->did_nak != 0) { 1236 /* check if we should pause sending queries for 125us */ 1237 if (td->tmr_res == frame_num) { 1238 /* wait a bit */ 1239 dwc_otg_enable_sof_irq(sc); 1240 goto busy; 1241 } 1242 } else if (td->set_toggle) { 1243 td->set_toggle = 0; 1244 td->toggle = 1; 1245 } 1246 /* query for data one more time */ 1247 td->tmr_res = frame_num; 1248 td->did_nak = 0; 1249 return (0); 1250 busy: 1251 return (1); 1252 } 1253 1254 static uint8_t 1255 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, 1256 uint8_t channel) 1257 { 1258 uint32_t count; 1259 1260 /* check endpoint status */ 1261 if (sc->sc_last_rx_status == 0) 1262 goto busy; 1263 1264 if (channel >= DWC_OTG_MAX_CHANNELS) 1265 goto busy; 1266 1267 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1268 goto busy; 1269 1270 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1271 case GRXSTSRH_IN_DATA: 1272 1273 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1274 (int)td->state, (int)sc->sc_last_rx_status); 1275 1276 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1277 /* 1278 * When using SPLIT transactions on interrupt 1279 * endpoints, sometimes data occurs twice. 1280 */ 1281 DPRINTF("Data already received\n"); 1282 break; 1283 } 1284 1285 /* get the packet byte count */ 1286 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1287 1288 /* check for ISOCHRONOUS endpoint */ 1289 if (td->ep_type == UE_ISOCHRONOUS) { 1290 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1291 GRXSTSRD_DPID_DATA0) { 1292 /* more data to be received */ 1293 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1294 } else { 1295 /* all data received */ 1296 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1297 /* verify the packet byte count */ 1298 if (count != td->remainder) { 1299 /* we have a short packet */ 1300 td->short_pkt = 1; 1301 td->got_short = 1; 1302 } 1303 } 1304 } else { 1305 /* verify the packet byte count */ 1306 if (count != td->max_packet_size) { 1307 if (count < td->max_packet_size) { 1308 /* we have a short packet */ 1309 td->short_pkt = 1; 1310 td->got_short = 1; 1311 } else { 1312 /* invalid USB packet */ 1313 td->error_any = 1; 1314 1315 /* release FIFO */ 1316 dwc_otg_common_rx_ack(sc); 1317 goto complete; 1318 } 1319 } 1320 td->toggle ^= 1; 1321 td->tt_scheduled = 0; 1322 } 1323 1324 /* verify the packet byte count */ 1325 if (count > td->remainder) { 1326 /* invalid USB packet */ 1327 td->error_any = 1; 1328 1329 /* release FIFO */ 1330 dwc_otg_common_rx_ack(sc); 1331 goto complete; 1332 } 1333 1334 /* read data from FIFO */ 1335 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1336 1337 td->remainder -= count; 1338 td->offset += count; 1339 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1340 break; 1341 default: 1342 break; 1343 } 1344 /* release FIFO */ 1345 dwc_otg_common_rx_ack(sc); 1346 busy: 1347 return (0); 1348 complete: 1349 return (1); 1350 } 1351 1352 static uint8_t 1353 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1354 { 1355 uint32_t hcint = 0; 1356 uint32_t hcchar; 1357 uint8_t delta; 1358 uint8_t channel; 1359 uint8_t x; 1360 1361 for (x = 0; x != td->max_packet_count; x++) { 1362 channel = td->channel[x]; 1363 if (channel >= DWC_OTG_MAX_CHANNELS) 1364 continue; 1365 hcint |= sc->sc_chan_state[channel].hcint; 1366 1367 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1368 channel, td->state, hcint, 1369 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1370 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1371 1372 /* check interrupt bits */ 1373 if (hcint & (HCINT_RETRY | 1374 HCINT_ACK | HCINT_NYET)) { 1375 /* give success bits priority over failure bits */ 1376 } else if (hcint & HCINT_STALL) { 1377 DPRINTF("CH=%d STALL\n", channel); 1378 td->error_stall = 1; 1379 td->error_any = 1; 1380 goto complete; 1381 } else if (hcint & HCINT_ERRORS) { 1382 DPRINTF("CH=%d ERROR\n", channel); 1383 td->errcnt++; 1384 if (td->hcsplt != 0 || td->errcnt >= 3) { 1385 if (td->ep_type != UE_ISOCHRONOUS) { 1386 td->error_any = 1; 1387 goto complete; 1388 } 1389 } 1390 } 1391 1392 /* check channels for data, if any */ 1393 if (dwc_otg_host_data_rx_sub(sc, td, channel)) 1394 goto complete; 1395 1396 /* refresh interrupt status */ 1397 hcint |= sc->sc_chan_state[channel].hcint; 1398 1399 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1400 HCINT_ACK | HCINT_NYET)) { 1401 if (!(hcint & HCINT_ERRORS)) 1402 td->errcnt = 0; 1403 } 1404 } 1405 1406 switch (td->state) { 1407 case DWC_CHAN_ST_START: 1408 if (td->hcsplt != 0) 1409 goto receive_spkt; 1410 else 1411 goto receive_pkt; 1412 1413 case DWC_CHAN_ST_WAIT_ANE: 1414 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1415 if (td->ep_type == UE_INTERRUPT) { 1416 /* 1417 * The USB specification does not 1418 * mandate a particular data toggle 1419 * value for USB INTERRUPT 1420 * transfers. Switch the data toggle 1421 * value to receive the packet 1422 * correctly: 1423 */ 1424 if (hcint & HCINT_DATATGLERR) { 1425 DPRINTF("Retrying packet due to " 1426 "data toggle error\n"); 1427 td->toggle ^= 1; 1428 goto receive_pkt; 1429 } 1430 } else if (td->ep_type == UE_ISOCHRONOUS) { 1431 if (td->hcsplt != 0) { 1432 /* 1433 * Sometimes the complete 1434 * split packet may be queued 1435 * too early and the 1436 * transaction translator will 1437 * return a NAK. Ignore 1438 * this message and retry the 1439 * complete split instead. 1440 */ 1441 DPRINTF("Retrying complete split\n"); 1442 goto receive_pkt; 1443 } 1444 goto complete; 1445 } 1446 td->did_nak = 1; 1447 td->tt_scheduled = 0; 1448 if (td->hcsplt != 0) 1449 goto receive_spkt; 1450 else 1451 goto receive_pkt; 1452 } else if (hcint & HCINT_NYET) { 1453 if (td->hcsplt != 0) { 1454 /* try again */ 1455 goto receive_pkt; 1456 } else { 1457 /* not a valid token for IN endpoints */ 1458 td->error_any = 1; 1459 goto complete; 1460 } 1461 } else if (hcint & HCINT_ACK) { 1462 /* wait for data - ACK arrived first */ 1463 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1464 goto busy; 1465 1466 if (td->ep_type == UE_ISOCHRONOUS) { 1467 /* check if we are complete */ 1468 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1469 goto complete; 1470 } else if (td->hcsplt != 0) { 1471 goto receive_pkt; 1472 } else { 1473 /* get more packets */ 1474 goto busy; 1475 } 1476 } else { 1477 /* check if we are complete */ 1478 if ((td->remainder == 0) || (td->got_short != 0)) { 1479 if (td->short_pkt) 1480 goto complete; 1481 1482 /* 1483 * Else need to receive a zero length 1484 * packet. 1485 */ 1486 } 1487 td->tt_scheduled = 0; 1488 td->did_nak = 0; 1489 if (td->hcsplt != 0) 1490 goto receive_spkt; 1491 else 1492 goto receive_pkt; 1493 } 1494 } 1495 break; 1496 1497 case DWC_CHAN_ST_WAIT_S_ANE: 1498 /* 1499 * NOTE: The DWC OTG hardware provides a fake ACK in 1500 * case of interrupt and isochronous transfers: 1501 */ 1502 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1503 td->did_nak = 1; 1504 td->tt_scheduled = 0; 1505 goto receive_spkt; 1506 } else if (hcint & HCINT_NYET) { 1507 td->tt_scheduled = 0; 1508 goto receive_spkt; 1509 } else if (hcint & HCINT_ACK) { 1510 td->did_nak = 0; 1511 goto receive_pkt; 1512 } 1513 break; 1514 1515 case DWC_CHAN_ST_WAIT_C_PKT: 1516 goto receive_pkt; 1517 1518 default: 1519 break; 1520 } 1521 goto busy; 1522 1523 receive_pkt: 1524 /* free existing channel, if any */ 1525 dwc_otg_host_channel_free(sc, td); 1526 1527 if (td->hcsplt != 0) { 1528 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1529 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1530 if (td->ep_type != UE_ISOCHRONOUS) { 1531 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1532 goto busy; 1533 } 1534 } 1535 delta = sc->sc_last_frame_num - td->tt_start_slot; 1536 if (delta > DWC_OTG_TT_SLOT_MAX) { 1537 if (td->ep_type != UE_ISOCHRONOUS) { 1538 /* we missed the service interval */ 1539 td->error_any = 1; 1540 } 1541 goto complete; 1542 } 1543 /* complete split */ 1544 td->hcsplt |= HCSPLT_COMPSPLT; 1545 } else if (dwc_otg_host_rate_check(sc, td)) { 1546 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1547 goto busy; 1548 } 1549 1550 /* allocate a new channel */ 1551 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1552 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1553 goto busy; 1554 } 1555 1556 /* set toggle, if any */ 1557 if (td->set_toggle) { 1558 td->set_toggle = 0; 1559 td->toggle = 1; 1560 } 1561 1562 td->state = DWC_CHAN_ST_WAIT_ANE; 1563 1564 for (x = 0; x != td->max_packet_count; x++) { 1565 channel = td->channel[x]; 1566 1567 /* receive one packet */ 1568 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1569 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1570 (1 << HCTSIZ_PKTCNT_SHIFT) | 1571 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1572 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1573 1574 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1575 1576 hcchar = td->hcchar; 1577 hcchar |= HCCHAR_EPDIR_IN; 1578 1579 if (td->ep_type == UE_ISOCHRONOUS) { 1580 if (td->hcsplt != 0) { 1581 /* continously buffer */ 1582 if (sc->sc_last_frame_num & 1) 1583 hcchar &= ~HCCHAR_ODDFRM; 1584 else 1585 hcchar |= HCCHAR_ODDFRM; 1586 } else { 1587 /* multi buffer, if any */ 1588 if (sc->sc_last_frame_num & 1) 1589 hcchar |= HCCHAR_ODDFRM; 1590 else 1591 hcchar &= ~HCCHAR_ODDFRM; 1592 } 1593 } else { 1594 hcchar &= ~HCCHAR_ODDFRM; 1595 } 1596 1597 /* must enable channel before data can be received */ 1598 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1599 } 1600 /* wait until next slot before trying complete split */ 1601 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1602 1603 goto busy; 1604 1605 receive_spkt: 1606 /* free existing channel(s), if any */ 1607 dwc_otg_host_channel_free(sc, td); 1608 1609 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1610 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1611 td->state = DWC_CHAN_ST_START; 1612 goto busy; 1613 } 1614 delta = sc->sc_last_frame_num - td->tt_start_slot; 1615 if (delta > 5) { 1616 /* missed it */ 1617 td->tt_scheduled = 0; 1618 td->state = DWC_CHAN_ST_START; 1619 goto busy; 1620 } 1621 1622 /* allocate a new channel */ 1623 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1624 td->state = DWC_CHAN_ST_START; 1625 goto busy; 1626 } 1627 1628 channel = td->channel[0]; 1629 1630 td->hcsplt &= ~HCSPLT_COMPSPLT; 1631 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1632 1633 /* receive one packet */ 1634 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1635 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1636 1637 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1638 1639 /* send after next SOF event */ 1640 if ((sc->sc_last_frame_num & 1) == 0 && 1641 td->ep_type == UE_ISOCHRONOUS) 1642 td->hcchar |= HCCHAR_ODDFRM; 1643 else 1644 td->hcchar &= ~HCCHAR_ODDFRM; 1645 1646 hcchar = td->hcchar; 1647 hcchar |= HCCHAR_EPDIR_IN; 1648 1649 /* wait until next slot before trying complete split */ 1650 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1651 1652 /* must enable channel before data can be received */ 1653 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1654 busy: 1655 return (1); /* busy */ 1656 1657 complete: 1658 dwc_otg_host_channel_free(sc, td); 1659 return (0); /* complete */ 1660 } 1661 1662 static uint8_t 1663 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1664 { 1665 uint32_t temp; 1666 uint16_t count; 1667 uint8_t got_short; 1668 1669 got_short = 0; 1670 1671 /* check endpoint status */ 1672 if (sc->sc_last_rx_status == 0) 1673 goto not_complete; 1674 1675 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1676 goto not_complete; 1677 1678 /* check for SETUP packet */ 1679 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1680 GRXSTSRD_STP_DATA || 1681 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1682 GRXSTSRD_STP_COMPLETE) { 1683 if (td->remainder == 0) { 1684 /* 1685 * We are actually complete and have 1686 * received the next SETUP 1687 */ 1688 DPRINTFN(5, "faking complete\n"); 1689 return (0); /* complete */ 1690 } 1691 /* 1692 * USB Host Aborted the transfer. 1693 */ 1694 td->error_any = 1; 1695 return (0); /* complete */ 1696 } 1697 1698 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1699 GRXSTSRD_OUT_DATA) { 1700 /* release FIFO */ 1701 dwc_otg_common_rx_ack(sc); 1702 goto not_complete; 1703 } 1704 1705 /* get the packet byte count */ 1706 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1707 1708 /* verify the packet byte count */ 1709 if (count != td->max_packet_size) { 1710 if (count < td->max_packet_size) { 1711 /* we have a short packet */ 1712 td->short_pkt = 1; 1713 got_short = 1; 1714 } else { 1715 /* invalid USB packet */ 1716 td->error_any = 1; 1717 1718 /* release FIFO */ 1719 dwc_otg_common_rx_ack(sc); 1720 return (0); /* we are complete */ 1721 } 1722 } 1723 /* verify the packet byte count */ 1724 if (count > td->remainder) { 1725 /* invalid USB packet */ 1726 td->error_any = 1; 1727 1728 /* release FIFO */ 1729 dwc_otg_common_rx_ack(sc); 1730 return (0); /* we are complete */ 1731 } 1732 1733 /* read data from FIFO */ 1734 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1735 1736 td->remainder -= count; 1737 td->offset += count; 1738 1739 /* release FIFO */ 1740 dwc_otg_common_rx_ack(sc); 1741 1742 temp = sc->sc_out_ctl[td->ep_no]; 1743 1744 /* check for isochronous mode */ 1745 if ((temp & DIEPCTL_EPTYPE_MASK) == 1746 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1747 /* toggle odd or even frame bit */ 1748 if (temp & DIEPCTL_SETD1PID) { 1749 temp &= ~DIEPCTL_SETD1PID; 1750 temp |= DIEPCTL_SETD0PID; 1751 } else { 1752 temp &= ~DIEPCTL_SETD0PID; 1753 temp |= DIEPCTL_SETD1PID; 1754 } 1755 sc->sc_out_ctl[td->ep_no] = temp; 1756 } 1757 1758 /* check if we are complete */ 1759 if ((td->remainder == 0) || got_short) { 1760 if (td->short_pkt) { 1761 /* we are complete */ 1762 return (0); 1763 } 1764 /* else need to receive a zero length packet */ 1765 } 1766 1767 not_complete: 1768 1769 /* enable SETUP and transfer complete interrupt */ 1770 if (td->ep_no == 0) { 1771 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1772 DXEPTSIZ_SET_MULTI(3) | 1773 DXEPTSIZ_SET_NPKT(1) | 1774 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1775 } else { 1776 /* allow reception of multiple packets */ 1777 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1778 DXEPTSIZ_SET_MULTI(1) | 1779 DXEPTSIZ_SET_NPKT(4) | 1780 DXEPTSIZ_SET_NBYTES(4 * 1781 ((td->max_packet_size + 3) & ~3))); 1782 } 1783 temp = sc->sc_out_ctl[td->ep_no]; 1784 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1785 DOEPCTL_EPENA | DOEPCTL_CNAK); 1786 1787 return (1); /* not complete */ 1788 } 1789 1790 static uint8_t 1791 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1792 { 1793 uint32_t count; 1794 uint32_t hcint; 1795 uint32_t hcchar; 1796 uint8_t delta; 1797 uint8_t channel; 1798 uint8_t x; 1799 1800 dwc_otg_host_dump_rx(sc, td); 1801 1802 /* check that last channel is complete */ 1803 channel = td->channel[td->npkt]; 1804 1805 if (channel < DWC_OTG_MAX_CHANNELS) { 1806 hcint = sc->sc_chan_state[channel].hcint; 1807 1808 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1809 channel, td->state, hcint, 1810 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1811 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1812 1813 if (hcint & (HCINT_RETRY | 1814 HCINT_ACK | HCINT_NYET)) { 1815 /* give success bits priority over failure bits */ 1816 } else if (hcint & HCINT_STALL) { 1817 DPRINTF("CH=%d STALL\n", channel); 1818 td->error_stall = 1; 1819 td->error_any = 1; 1820 goto complete; 1821 } else if (hcint & HCINT_ERRORS) { 1822 DPRINTF("CH=%d ERROR\n", channel); 1823 td->errcnt++; 1824 if (td->hcsplt != 0 || td->errcnt >= 3) { 1825 td->error_any = 1; 1826 goto complete; 1827 } 1828 } 1829 1830 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1831 HCINT_ACK | HCINT_NYET)) { 1832 if (!(hcint & HCINT_ERRORS)) 1833 td->errcnt = 0; 1834 } 1835 } else { 1836 hcint = 0; 1837 } 1838 1839 switch (td->state) { 1840 case DWC_CHAN_ST_START: 1841 goto send_pkt; 1842 1843 case DWC_CHAN_ST_WAIT_ANE: 1844 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1845 td->did_nak = 1; 1846 td->tt_scheduled = 0; 1847 goto send_pkt; 1848 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1849 td->offset += td->tx_bytes; 1850 td->remainder -= td->tx_bytes; 1851 td->toggle ^= 1; 1852 /* check if next response will be a NAK */ 1853 if (hcint & HCINT_NYET) 1854 td->did_nak = 1; 1855 else 1856 td->did_nak = 0; 1857 td->tt_scheduled = 0; 1858 1859 /* check remainder */ 1860 if (td->remainder == 0) { 1861 if (td->short_pkt) 1862 goto complete; 1863 1864 /* 1865 * Else we need to transmit a short 1866 * packet: 1867 */ 1868 } 1869 goto send_pkt; 1870 } 1871 break; 1872 1873 case DWC_CHAN_ST_WAIT_S_ANE: 1874 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1875 td->did_nak = 1; 1876 td->tt_scheduled = 0; 1877 goto send_pkt; 1878 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1879 td->did_nak = 0; 1880 goto send_cpkt; 1881 } 1882 break; 1883 1884 case DWC_CHAN_ST_WAIT_C_ANE: 1885 if (hcint & HCINT_NYET) { 1886 goto send_cpkt; 1887 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1888 td->did_nak = 1; 1889 td->tt_scheduled = 0; 1890 goto send_pkt; 1891 } else if (hcint & HCINT_ACK) { 1892 td->offset += td->tx_bytes; 1893 td->remainder -= td->tx_bytes; 1894 td->toggle ^= 1; 1895 td->did_nak = 0; 1896 td->tt_scheduled = 0; 1897 1898 /* check remainder */ 1899 if (td->remainder == 0) { 1900 if (td->short_pkt) 1901 goto complete; 1902 1903 /* else we need to transmit a short packet */ 1904 } 1905 goto send_pkt; 1906 } 1907 break; 1908 1909 case DWC_CHAN_ST_WAIT_C_PKT: 1910 goto send_cpkt; 1911 1912 case DWC_CHAN_ST_TX_WAIT_ISOC: 1913 /* Check if ISOCHRONOUS OUT traffic is complete */ 1914 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1915 break; 1916 1917 td->offset += td->tx_bytes; 1918 td->remainder -= td->tx_bytes; 1919 goto complete; 1920 default: 1921 break; 1922 } 1923 goto busy; 1924 1925 send_pkt: 1926 /* free existing channel(s), if any */ 1927 dwc_otg_host_channel_free(sc, td); 1928 1929 if (td->hcsplt != 0) { 1930 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1931 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1932 td->state = DWC_CHAN_ST_START; 1933 goto busy; 1934 } 1935 delta = sc->sc_last_frame_num - td->tt_start_slot; 1936 if (delta > 5) { 1937 /* missed it */ 1938 td->tt_scheduled = 0; 1939 td->state = DWC_CHAN_ST_START; 1940 goto busy; 1941 } 1942 } else if (dwc_otg_host_rate_check(sc, td)) { 1943 td->state = DWC_CHAN_ST_START; 1944 goto busy; 1945 } 1946 1947 /* allocate a new channel */ 1948 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1949 td->state = DWC_CHAN_ST_START; 1950 goto busy; 1951 } 1952 1953 /* set toggle, if any */ 1954 if (td->set_toggle) { 1955 td->set_toggle = 0; 1956 td->toggle = 1; 1957 } 1958 1959 if (td->ep_type == UE_ISOCHRONOUS) { 1960 /* ISOCHRONOUS OUT transfers don't have any ACKs */ 1961 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1962 td->hcsplt &= ~HCSPLT_COMPSPLT; 1963 if (td->hcsplt != 0) { 1964 /* get maximum transfer length */ 1965 count = td->remainder; 1966 if (count > HCSPLT_XACTLEN_BURST) { 1967 DPRINTF("TT overflow\n"); 1968 td->error_any = 1; 1969 goto complete; 1970 } 1971 /* Update transaction position */ 1972 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1973 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1974 } 1975 } else if (td->hcsplt != 0) { 1976 td->hcsplt &= ~HCSPLT_COMPSPLT; 1977 /* Wait for ACK/NAK/ERR from TT */ 1978 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1979 } else { 1980 /* Wait for ACK/NAK/STALL from device */ 1981 td->state = DWC_CHAN_ST_WAIT_ANE; 1982 } 1983 1984 td->tx_bytes = 0; 1985 1986 for (x = 0; x != td->max_packet_count; x++) { 1987 uint32_t rem_bytes; 1988 1989 channel = td->channel[x]; 1990 1991 /* send one packet at a time */ 1992 count = td->max_packet_size; 1993 rem_bytes = td->remainder - td->tx_bytes; 1994 if (rem_bytes < count) { 1995 /* we have a short packet */ 1996 td->short_pkt = 1; 1997 count = rem_bytes; 1998 } 1999 if (count == rem_bytes) { 2000 /* last packet */ 2001 switch (x) { 2002 case 0: 2003 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2004 (count << HCTSIZ_XFERSIZE_SHIFT) | 2005 (1 << HCTSIZ_PKTCNT_SHIFT) | 2006 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2007 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2008 break; 2009 case 1: 2010 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2011 (count << HCTSIZ_XFERSIZE_SHIFT) | 2012 (1 << HCTSIZ_PKTCNT_SHIFT) | 2013 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 2014 break; 2015 default: 2016 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2017 (count << HCTSIZ_XFERSIZE_SHIFT) | 2018 (1 << HCTSIZ_PKTCNT_SHIFT) | 2019 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 2020 break; 2021 } 2022 } else if (td->ep_type == UE_ISOCHRONOUS && 2023 td->max_packet_count > 1) { 2024 /* ISOCHRONOUS multi packet */ 2025 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2026 (count << HCTSIZ_XFERSIZE_SHIFT) | 2027 (1 << HCTSIZ_PKTCNT_SHIFT) | 2028 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 2029 } else { 2030 /* TODO: HCTSIZ_DOPNG */ 2031 /* standard BULK/INTERRUPT/CONTROL packet */ 2032 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2033 (count << HCTSIZ_XFERSIZE_SHIFT) | 2034 (1 << HCTSIZ_PKTCNT_SHIFT) | 2035 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2036 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2037 } 2038 2039 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2040 2041 hcchar = td->hcchar; 2042 hcchar &= ~HCCHAR_EPDIR_IN; 2043 2044 /* send after next SOF event */ 2045 if ((sc->sc_last_frame_num & 1) == 0 && 2046 td->ep_type == UE_ISOCHRONOUS) 2047 hcchar |= HCCHAR_ODDFRM; 2048 else 2049 hcchar &= ~HCCHAR_ODDFRM; 2050 2051 /* must enable before writing data to FIFO */ 2052 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2053 2054 if (count != 0) { 2055 /* write data into FIFO */ 2056 dwc_otg_write_fifo(sc, td->pc, td->offset + 2057 td->tx_bytes, DOTG_DFIFO(channel), count); 2058 } 2059 2060 /* store number of bytes transmitted */ 2061 td->tx_bytes += count; 2062 2063 /* store last packet index */ 2064 td->npkt = x; 2065 2066 /* check for last packet */ 2067 if (count == rem_bytes) 2068 break; 2069 } 2070 goto busy; 2071 2072 send_cpkt: 2073 /* free existing channel, if any */ 2074 dwc_otg_host_channel_free(sc, td); 2075 2076 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 2077 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 2078 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2079 goto busy; 2080 } 2081 delta = sc->sc_last_frame_num - td->tt_start_slot; 2082 if (delta > DWC_OTG_TT_SLOT_MAX) { 2083 /* we missed the service interval */ 2084 if (td->ep_type != UE_ISOCHRONOUS) 2085 td->error_any = 1; 2086 goto complete; 2087 } 2088 2089 /* allocate a new channel */ 2090 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 2091 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2092 goto busy; 2093 } 2094 2095 channel = td->channel[0]; 2096 2097 td->hcsplt |= HCSPLT_COMPSPLT; 2098 td->state = DWC_CHAN_ST_WAIT_C_ANE; 2099 2100 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2101 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 2102 2103 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2104 2105 hcchar = td->hcchar; 2106 hcchar &= ~HCCHAR_EPDIR_IN; 2107 2108 /* receive complete split ASAP */ 2109 if ((sc->sc_last_frame_num & 1) != 0 && 2110 td->ep_type == UE_ISOCHRONOUS) 2111 hcchar |= HCCHAR_ODDFRM; 2112 else 2113 hcchar &= ~HCCHAR_ODDFRM; 2114 2115 /* must enable channel before data can be received */ 2116 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2117 2118 /* wait until next slot before trying complete split */ 2119 td->tt_complete_slot = sc->sc_last_frame_num + 1; 2120 busy: 2121 return (1); /* busy */ 2122 2123 complete: 2124 dwc_otg_host_channel_free(sc, td); 2125 return (0); /* complete */ 2126 } 2127 2128 static uint8_t 2129 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2130 { 2131 uint32_t max_buffer; 2132 uint32_t count; 2133 uint32_t fifo_left; 2134 uint32_t mpkt; 2135 uint32_t temp; 2136 uint8_t to; 2137 2138 to = 3; /* don't loop forever! */ 2139 2140 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2141 2142 repeat: 2143 /* check for for endpoint 0 data */ 2144 2145 temp = sc->sc_last_rx_status; 2146 2147 if ((td->ep_no == 0) && (temp != 0) && 2148 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2149 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2150 GRXSTSRD_STP_DATA && 2151 (temp & GRXSTSRD_PKTSTS_MASK) != 2152 GRXSTSRD_STP_COMPLETE) { 2153 /* dump data - wrong direction */ 2154 dwc_otg_common_rx_ack(sc); 2155 } else { 2156 /* 2157 * The current transfer was cancelled 2158 * by the USB Host: 2159 */ 2160 td->error_any = 1; 2161 return (0); /* complete */ 2162 } 2163 } 2164 2165 /* fill in more TX data, if possible */ 2166 if (td->tx_bytes != 0) { 2167 uint16_t cpkt; 2168 2169 /* check if packets have been transferred */ 2170 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2171 2172 /* get current packet number */ 2173 cpkt = DXEPTSIZ_GET_NPKT(temp); 2174 2175 if (cpkt >= td->npkt) { 2176 fifo_left = 0; 2177 } else { 2178 if (max_buffer != 0) { 2179 fifo_left = (td->npkt - cpkt) * 2180 td->max_packet_size; 2181 2182 if (fifo_left > max_buffer) 2183 fifo_left = max_buffer; 2184 } else { 2185 fifo_left = td->max_packet_size; 2186 } 2187 } 2188 2189 count = td->tx_bytes; 2190 if (count > fifo_left) 2191 count = fifo_left; 2192 2193 if (count != 0) { 2194 /* write data into FIFO */ 2195 dwc_otg_write_fifo(sc, td->pc, td->offset, 2196 DOTG_DFIFO(td->ep_no), count); 2197 2198 td->tx_bytes -= count; 2199 td->remainder -= count; 2200 td->offset += count; 2201 td->npkt = cpkt; 2202 } 2203 if (td->tx_bytes != 0) 2204 goto not_complete; 2205 2206 /* check remainder */ 2207 if (td->remainder == 0) { 2208 if (td->short_pkt) 2209 return (0); /* complete */ 2210 2211 /* else we need to transmit a short packet */ 2212 } 2213 } 2214 2215 if (!to--) 2216 goto not_complete; 2217 2218 /* check if not all packets have been transferred */ 2219 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2220 2221 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2222 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2223 "DIEPCTL=0x%08x\n", td->ep_no, 2224 DXEPTSIZ_GET_NPKT(temp), 2225 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2226 2227 goto not_complete; 2228 } 2229 2230 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2231 2232 /* try to optimise by sending more data */ 2233 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2234 /* send multiple packets at the same time */ 2235 mpkt = max_buffer / td->max_packet_size; 2236 2237 if (mpkt > 0x3FE) 2238 mpkt = 0x3FE; 2239 2240 count = td->remainder; 2241 if (count > 0x7FFFFF) 2242 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2243 2244 td->npkt = count / td->max_packet_size; 2245 2246 /* 2247 * NOTE: We could use 0x3FE instead of "mpkt" in the 2248 * check below to get more throughput, but then we 2249 * have a dependency towards non-generic chip features 2250 * to disable the TX-FIFO-EMPTY interrupts on a per 2251 * endpoint basis. Increase the maximum buffer size of 2252 * the IN endpoint to increase the performance. 2253 */ 2254 if (td->npkt > mpkt) { 2255 td->npkt = mpkt; 2256 count = td->max_packet_size * mpkt; 2257 } else if ((count == 0) || (count % td->max_packet_size)) { 2258 /* we are transmitting a short packet */ 2259 td->npkt++; 2260 td->short_pkt = 1; 2261 } 2262 } else { 2263 /* send one packet at a time */ 2264 mpkt = 1; 2265 count = td->max_packet_size; 2266 if (td->remainder < count) { 2267 /* we have a short packet */ 2268 td->short_pkt = 1; 2269 count = td->remainder; 2270 } 2271 td->npkt = 1; 2272 } 2273 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2274 DXEPTSIZ_SET_MULTI(1) | 2275 DXEPTSIZ_SET_NPKT(td->npkt) | 2276 DXEPTSIZ_SET_NBYTES(count)); 2277 2278 /* make room for buffering */ 2279 td->npkt += mpkt; 2280 2281 temp = sc->sc_in_ctl[td->ep_no]; 2282 2283 /* check for isochronous mode */ 2284 if ((temp & DIEPCTL_EPTYPE_MASK) == 2285 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2286 /* toggle odd or even frame bit */ 2287 if (temp & DIEPCTL_SETD1PID) { 2288 temp &= ~DIEPCTL_SETD1PID; 2289 temp |= DIEPCTL_SETD0PID; 2290 } else { 2291 temp &= ~DIEPCTL_SETD0PID; 2292 temp |= DIEPCTL_SETD1PID; 2293 } 2294 sc->sc_in_ctl[td->ep_no] = temp; 2295 } 2296 2297 /* must enable before writing data to FIFO */ 2298 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2299 DIEPCTL_EPENA | DIEPCTL_CNAK); 2300 2301 td->tx_bytes = count; 2302 2303 /* check remainder */ 2304 if (td->tx_bytes == 0 && 2305 td->remainder == 0) { 2306 if (td->short_pkt) 2307 return (0); /* complete */ 2308 2309 /* else we need to transmit a short packet */ 2310 } 2311 goto repeat; 2312 2313 not_complete: 2314 return (1); /* not complete */ 2315 } 2316 2317 static uint8_t 2318 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2319 { 2320 uint32_t temp; 2321 2322 /* 2323 * If all packets are transferred we are complete: 2324 */ 2325 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2326 2327 /* check that all packets have been transferred */ 2328 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2329 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2330 goto not_complete; 2331 } 2332 return (0); 2333 2334 not_complete: 2335 2336 /* we only want to know if there is a SETUP packet or free IN packet */ 2337 2338 temp = sc->sc_last_rx_status; 2339 2340 if ((td->ep_no == 0) && (temp != 0) && 2341 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2342 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2343 GRXSTSRD_STP_DATA || 2344 (temp & GRXSTSRD_PKTSTS_MASK) == 2345 GRXSTSRD_STP_COMPLETE) { 2346 DPRINTFN(5, "faking complete\n"); 2347 /* 2348 * Race condition: We are complete! 2349 */ 2350 return (0); 2351 } else { 2352 /* dump data - wrong direction */ 2353 dwc_otg_common_rx_ack(sc); 2354 } 2355 } 2356 return (1); /* not complete */ 2357 } 2358 2359 static void 2360 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2361 { 2362 struct dwc_otg_td *td; 2363 uint8_t toggle; 2364 uint8_t tmr_val; 2365 uint8_t tmr_res; 2366 2367 DPRINTFN(9, "\n"); 2368 2369 td = xfer->td_transfer_cache; 2370 if (td == NULL) 2371 return; 2372 2373 while (1) { 2374 if ((td->func) (sc, td)) { 2375 /* operation in progress */ 2376 break; 2377 } 2378 if (((void *)td) == xfer->td_transfer_last) { 2379 goto done; 2380 } 2381 if (td->error_any) { 2382 goto done; 2383 } else if (td->remainder > 0) { 2384 /* 2385 * We had a short transfer. If there is no alternate 2386 * next, stop processing ! 2387 */ 2388 if (!td->alt_next) 2389 goto done; 2390 } 2391 2392 /* 2393 * Fetch the next transfer descriptor and transfer 2394 * some flags to the next transfer descriptor 2395 */ 2396 tmr_res = td->tmr_res; 2397 tmr_val = td->tmr_val; 2398 toggle = td->toggle; 2399 td = td->obj_next; 2400 xfer->td_transfer_cache = td; 2401 td->toggle = toggle; /* transfer toggle */ 2402 td->tmr_res = tmr_res; 2403 td->tmr_val = tmr_val; 2404 } 2405 return; 2406 2407 done: 2408 xfer->td_transfer_cache = NULL; 2409 sc->sc_xfer_complete = 1; 2410 } 2411 2412 static uint8_t 2413 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2414 { 2415 struct dwc_otg_td *td; 2416 2417 DPRINTFN(9, "\n"); 2418 2419 td = xfer->td_transfer_cache; 2420 if (td == NULL) { 2421 /* compute all actual lengths */ 2422 dwc_otg_standard_done(xfer); 2423 return (1); 2424 } 2425 return (0); 2426 } 2427 2428 static void 2429 dwc_otg_timer(void *_sc) 2430 { 2431 struct dwc_otg_softc *sc = _sc; 2432 2433 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2434 2435 DPRINTF("\n"); 2436 2437 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2438 2439 /* increment timer value */ 2440 sc->sc_tmr_val++; 2441 2442 /* enable SOF interrupt, which will poll jobs */ 2443 dwc_otg_enable_sof_irq(sc); 2444 2445 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2446 2447 if (sc->sc_timer_active) { 2448 /* restart timer */ 2449 usb_callout_reset(&sc->sc_timer, 2450 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2451 &dwc_otg_timer, sc); 2452 } 2453 } 2454 2455 static void 2456 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2457 { 2458 if (sc->sc_timer_active != 0) 2459 return; 2460 2461 sc->sc_timer_active = 1; 2462 2463 /* restart timer */ 2464 usb_callout_reset(&sc->sc_timer, 2465 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2466 &dwc_otg_timer, sc); 2467 } 2468 2469 static void 2470 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2471 { 2472 if (sc->sc_timer_active == 0) 2473 return; 2474 2475 sc->sc_timer_active = 0; 2476 2477 /* stop timer */ 2478 usb_callout_stop(&sc->sc_timer); 2479 } 2480 2481 static uint16_t 2482 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2483 { 2484 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2485 pinfo->slot_index++; 2486 return (pinfo->slot_index); 2487 } 2488 2489 static uint8_t 2490 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2491 { 2492 TAILQ_HEAD(, usb_xfer) head; 2493 struct usb_xfer *xfer; 2494 struct usb_xfer *xfer_next; 2495 struct dwc_otg_td *td; 2496 uint16_t temp; 2497 uint16_t slot; 2498 2499 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2500 2501 if (sc->sc_last_frame_num == temp) 2502 return (0); 2503 2504 sc->sc_last_frame_num = temp; 2505 2506 TAILQ_INIT(&head); 2507 2508 if ((temp & 7) == 0) { 2509 /* reset the schedule */ 2510 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2511 2512 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2513 td = xfer->td_transfer_cache; 2514 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2515 continue; 2516 2517 /* check for IN direction */ 2518 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2519 continue; 2520 2521 sc->sc_needsof = 1; 2522 2523 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2524 continue; 2525 2526 /* compute slot */ 2527 slot = dwc_otg_compute_isoc_rx_tt_slot( 2528 sc->sc_tt_info + td->tt_index); 2529 if (slot > 3) { 2530 /* 2531 * Not enough time to get complete 2532 * split executed. 2533 */ 2534 continue; 2535 } 2536 /* Delayed start */ 2537 td->tt_start_slot = temp + slot; 2538 td->tt_scheduled = 1; 2539 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2540 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2541 } 2542 2543 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2544 td = xfer->td_transfer_cache; 2545 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2546 continue; 2547 2548 /* check for OUT direction */ 2549 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2550 continue; 2551 2552 sc->sc_needsof = 1; 2553 2554 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2555 continue; 2556 2557 /* Start ASAP */ 2558 td->tt_start_slot = temp; 2559 td->tt_scheduled = 1; 2560 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2561 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2562 } 2563 2564 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2565 td = xfer->td_transfer_cache; 2566 if (td == NULL || td->ep_type != UE_INTERRUPT) 2567 continue; 2568 2569 if (td->tt_scheduled != 0) { 2570 sc->sc_needsof = 1; 2571 continue; 2572 } 2573 2574 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2575 continue; 2576 2577 if (td->hcsplt == 0) { 2578 sc->sc_needsof = 1; 2579 td->tt_scheduled = 1; 2580 continue; 2581 } 2582 2583 /* start ASAP */ 2584 td->tt_start_slot = temp; 2585 sc->sc_needsof = 1; 2586 td->tt_scheduled = 1; 2587 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2588 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2589 } 2590 2591 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2592 td = xfer->td_transfer_cache; 2593 if (td == NULL || 2594 td->ep_type != UE_CONTROL) { 2595 continue; 2596 } 2597 2598 sc->sc_needsof = 1; 2599 2600 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2601 continue; 2602 2603 /* start ASAP */ 2604 td->tt_start_slot = temp; 2605 td->tt_scheduled = 1; 2606 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2607 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2608 } 2609 } 2610 if ((temp & 7) < 6) { 2611 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2612 td = xfer->td_transfer_cache; 2613 if (td == NULL || 2614 td->ep_type != UE_BULK) { 2615 continue; 2616 } 2617 2618 sc->sc_needsof = 1; 2619 2620 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2621 continue; 2622 2623 /* start ASAP */ 2624 td->tt_start_slot = temp; 2625 td->tt_scheduled = 1; 2626 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2627 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2628 } 2629 } 2630 2631 /* Put TT transfers in execution order at the end */ 2632 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2633 2634 /* move all TT transfers in front, keeping the current order */ 2635 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2636 td = xfer->td_transfer_cache; 2637 if (td == NULL || td->hcsplt == 0) 2638 continue; 2639 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2640 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2641 } 2642 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2643 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2644 2645 /* put non-TT non-ISOCHRONOUS transfers last */ 2646 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2647 td = xfer->td_transfer_cache; 2648 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) 2649 continue; 2650 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2651 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2652 } 2653 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2654 2655 if ((temp & 7) == 0) { 2656 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2657 (int)temp, (int)sc->sc_needsof); 2658 2659 /* update SOF IRQ mask */ 2660 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2661 if (sc->sc_needsof == 0) { 2662 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2663 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2664 } 2665 } else { 2666 if (sc->sc_needsof != 0) { 2667 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2668 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2669 } 2670 } 2671 2672 /* clear need SOF flag */ 2673 sc->sc_needsof = 0; 2674 } 2675 return (1); 2676 } 2677 2678 static void 2679 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2680 { 2681 struct usb_xfer *xfer; 2682 uint32_t count; 2683 uint32_t temp; 2684 uint32_t haint; 2685 uint8_t got_rx_status; 2686 uint8_t x; 2687 2688 if (sc->sc_flags.status_device_mode == 0) { 2689 /* 2690 * Update host transfer schedule, so that new 2691 * transfers can be issued: 2692 */ 2693 dwc_otg_update_host_transfer_schedule_locked(sc); 2694 } 2695 count = 0; 2696 repeat: 2697 if (++count == 16) { 2698 /* give other interrupts a chance */ 2699 DPRINTF("Yield\n"); 2700 return; 2701 } 2702 2703 /* get all host channel interrupts */ 2704 haint = DWC_OTG_READ_4(sc, DOTG_HAINT); 2705 while (1) { 2706 x = ffs(haint) - 1; 2707 if (x >= sc->sc_host_ch_max) 2708 break; 2709 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2710 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2711 temp &= ~HCINT_SOFTWARE_ONLY; 2712 sc->sc_chan_state[x].hcint |= temp; 2713 haint &= ~(1U << x); 2714 } 2715 2716 if (sc->sc_last_rx_status == 0) { 2717 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2718 if (temp & GINTSTS_RXFLVL) { 2719 /* pop current status */ 2720 sc->sc_last_rx_status = 2721 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2722 } 2723 2724 if (sc->sc_last_rx_status != 0) { 2725 uint8_t ep_no; 2726 2727 temp = sc->sc_last_rx_status & 2728 GRXSTSRD_PKTSTS_MASK; 2729 2730 /* non-data messages we simply skip */ 2731 if (temp != GRXSTSRD_STP_DATA && 2732 temp != GRXSTSRD_STP_COMPLETE && 2733 temp != GRXSTSRD_OUT_DATA) { 2734 /* check for halted channel */ 2735 if (temp == GRXSTSRH_HALTED) { 2736 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2737 sc->sc_chan_state[ep_no].wait_halted = 0; 2738 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2739 } 2740 /* store bytes and FIFO offset */ 2741 sc->sc_current_rx_bytes = 0; 2742 sc->sc_current_rx_fifo = 0; 2743 2744 /* acknowledge status */ 2745 dwc_otg_common_rx_ack(sc); 2746 goto repeat; 2747 } 2748 2749 temp = GRXSTSRD_BCNT_GET( 2750 sc->sc_last_rx_status); 2751 ep_no = GRXSTSRD_CHNUM_GET( 2752 sc->sc_last_rx_status); 2753 2754 /* store bytes and FIFO offset */ 2755 sc->sc_current_rx_bytes = (temp + 3) & ~3; 2756 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); 2757 2758 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2759 2760 /* check if we should dump the data */ 2761 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2762 dwc_otg_common_rx_ack(sc); 2763 goto repeat; 2764 } 2765 2766 got_rx_status = 1; 2767 2768 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2769 sc->sc_last_rx_status, ep_no, 2770 (sc->sc_last_rx_status >> 15) & 3, 2771 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2772 (sc->sc_last_rx_status >> 17) & 15); 2773 } else { 2774 got_rx_status = 0; 2775 } 2776 } else { 2777 uint8_t ep_no; 2778 2779 ep_no = GRXSTSRD_CHNUM_GET( 2780 sc->sc_last_rx_status); 2781 2782 /* check if we should dump the data */ 2783 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2784 dwc_otg_common_rx_ack(sc); 2785 goto repeat; 2786 } 2787 2788 got_rx_status = 1; 2789 } 2790 2791 /* execute FIFOs */ 2792 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2793 dwc_otg_xfer_do_fifo(sc, xfer); 2794 2795 if (got_rx_status) { 2796 /* check if data was consumed */ 2797 if (sc->sc_last_rx_status == 0) 2798 goto repeat; 2799 2800 /* disable RX FIFO level interrupt */ 2801 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2802 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2803 } 2804 } 2805 2806 static void 2807 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2808 { 2809 struct usb_xfer *xfer; 2810 repeat: 2811 /* scan for completion events */ 2812 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2813 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2814 goto repeat; 2815 } 2816 } 2817 2818 static void 2819 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2820 { 2821 DPRINTFN(5, "vbus = %u\n", is_on); 2822 2823 /* 2824 * If the USB host mode is forced, then assume VBUS is always 2825 * present else rely on the input to this function: 2826 */ 2827 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2828 if (!sc->sc_flags.status_vbus) { 2829 sc->sc_flags.status_vbus = 1; 2830 2831 /* complete root HUB interrupt endpoint */ 2832 2833 dwc_otg_root_intr(sc); 2834 } 2835 } else { 2836 if (sc->sc_flags.status_vbus) { 2837 sc->sc_flags.status_vbus = 0; 2838 sc->sc_flags.status_bus_reset = 0; 2839 sc->sc_flags.status_suspend = 0; 2840 sc->sc_flags.change_suspend = 0; 2841 sc->sc_flags.change_connect = 1; 2842 2843 /* complete root HUB interrupt endpoint */ 2844 2845 dwc_otg_root_intr(sc); 2846 } 2847 } 2848 } 2849 2850 int 2851 dwc_otg_filter_interrupt(void *arg) 2852 { 2853 struct dwc_otg_softc *sc = arg; 2854 int retval = FILTER_HANDLED; 2855 uint32_t status; 2856 2857 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2858 2859 /* read and clear interrupt status */ 2860 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2861 2862 /* clear interrupts we are handling here */ 2863 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2864 2865 /* check for USB state change interrupts */ 2866 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2867 retval = FILTER_SCHEDULE_THREAD; 2868 2869 /* clear FIFO empty interrupts */ 2870 if (status & sc->sc_irq_mask & 2871 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2872 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2873 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2874 } 2875 /* clear all IN endpoint interrupts */ 2876 if (status & GINTSTS_IEPINT) { 2877 uint32_t temp; 2878 uint8_t x; 2879 2880 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2881 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2882 /* 2883 * NOTE: Need to clear all interrupt bits, 2884 * because some appears to be unmaskable and 2885 * can cause an interrupt loop: 2886 */ 2887 if (temp != 0) 2888 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); 2889 } 2890 } 2891 2892 /* poll FIFOs, if any */ 2893 dwc_otg_interrupt_poll_locked(sc); 2894 2895 if (sc->sc_xfer_complete != 0) 2896 retval = FILTER_SCHEDULE_THREAD; 2897 2898 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2899 2900 return (retval); 2901 } 2902 2903 void 2904 dwc_otg_interrupt(void *arg) 2905 { 2906 struct dwc_otg_softc *sc = arg; 2907 uint32_t status; 2908 2909 USB_BUS_LOCK(&sc->sc_bus); 2910 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2911 2912 /* read and clear interrupt status */ 2913 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2914 2915 /* clear interrupts we are handling here */ 2916 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2917 2918 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2919 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2920 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2921 2922 if (status & GINTSTS_USBRST) { 2923 /* set correct state */ 2924 sc->sc_flags.status_device_mode = 1; 2925 sc->sc_flags.status_bus_reset = 0; 2926 sc->sc_flags.status_suspend = 0; 2927 sc->sc_flags.change_suspend = 0; 2928 sc->sc_flags.change_connect = 1; 2929 2930 /* Disable SOF interrupt */ 2931 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2932 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2933 2934 /* complete root HUB interrupt endpoint */ 2935 dwc_otg_root_intr(sc); 2936 } 2937 2938 /* check for any bus state change interrupts */ 2939 if (status & GINTSTS_ENUMDONE) { 2940 uint32_t temp; 2941 2942 DPRINTFN(5, "end of reset\n"); 2943 2944 /* set correct state */ 2945 sc->sc_flags.status_device_mode = 1; 2946 sc->sc_flags.status_bus_reset = 1; 2947 sc->sc_flags.status_suspend = 0; 2948 sc->sc_flags.change_suspend = 0; 2949 sc->sc_flags.change_connect = 1; 2950 sc->sc_flags.status_low_speed = 0; 2951 sc->sc_flags.port_enabled = 1; 2952 2953 /* reset FIFOs */ 2954 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2955 2956 /* reset function address */ 2957 dwc_otg_set_address(sc, 0); 2958 2959 /* figure out enumeration speed */ 2960 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2961 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2962 sc->sc_flags.status_high_speed = 1; 2963 else 2964 sc->sc_flags.status_high_speed = 0; 2965 2966 /* 2967 * Disable resume and SOF interrupt, and enable 2968 * suspend and RX frame interrupt: 2969 */ 2970 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2971 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2972 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2973 2974 /* complete root HUB interrupt endpoint */ 2975 dwc_otg_root_intr(sc); 2976 } 2977 2978 if (status & GINTSTS_PRTINT) { 2979 uint32_t hprt; 2980 2981 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2982 2983 /* clear change bits */ 2984 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2985 HPRT_PRTPWR | HPRT_PRTENCHNG | 2986 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2987 sc->sc_hprt_val); 2988 2989 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2990 2991 sc->sc_flags.status_device_mode = 0; 2992 2993 if (hprt & HPRT_PRTCONNSTS) 2994 sc->sc_flags.status_bus_reset = 1; 2995 else 2996 sc->sc_flags.status_bus_reset = 0; 2997 2998 if ((hprt & HPRT_PRTENCHNG) && 2999 (hprt & HPRT_PRTENA) == 0) 3000 sc->sc_flags.change_enabled = 1; 3001 3002 if (hprt & HPRT_PRTENA) 3003 sc->sc_flags.port_enabled = 1; 3004 else 3005 sc->sc_flags.port_enabled = 0; 3006 3007 if (hprt & HPRT_PRTOVRCURRCHNG) 3008 sc->sc_flags.change_over_current = 1; 3009 3010 if (hprt & HPRT_PRTOVRCURRACT) 3011 sc->sc_flags.port_over_current = 1; 3012 else 3013 sc->sc_flags.port_over_current = 0; 3014 3015 if (hprt & HPRT_PRTPWR) 3016 sc->sc_flags.port_powered = 1; 3017 else 3018 sc->sc_flags.port_powered = 0; 3019 3020 if (((hprt & HPRT_PRTSPD_MASK) 3021 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 3022 sc->sc_flags.status_low_speed = 1; 3023 else 3024 sc->sc_flags.status_low_speed = 0; 3025 3026 if (((hprt & HPRT_PRTSPD_MASK) 3027 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 3028 sc->sc_flags.status_high_speed = 1; 3029 else 3030 sc->sc_flags.status_high_speed = 0; 3031 3032 if (hprt & HPRT_PRTCONNDET) 3033 sc->sc_flags.change_connect = 1; 3034 3035 if (hprt & HPRT_PRTSUSP) 3036 dwc_otg_suspend_irq(sc); 3037 else 3038 dwc_otg_resume_irq(sc); 3039 3040 /* complete root HUB interrupt endpoint */ 3041 dwc_otg_root_intr(sc); 3042 3043 /* update host frame interval */ 3044 dwc_otg_update_host_frame_interval(sc); 3045 } 3046 3047 /* 3048 * If resume and suspend is set at the same time we interpret 3049 * that like RESUME. Resume is set when there is at least 3 3050 * milliseconds of inactivity on the USB BUS. 3051 */ 3052 if (status & GINTSTS_WKUPINT) { 3053 DPRINTFN(5, "resume interrupt\n"); 3054 3055 dwc_otg_resume_irq(sc); 3056 3057 } else if (status & GINTSTS_USBSUSP) { 3058 DPRINTFN(5, "suspend interrupt\n"); 3059 3060 dwc_otg_suspend_irq(sc); 3061 } 3062 /* check VBUS */ 3063 if (status & (GINTSTS_USBSUSP | 3064 GINTSTS_USBRST | 3065 GINTMSK_OTGINTMSK | 3066 GINTSTS_SESSREQINT)) { 3067 uint32_t temp; 3068 3069 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3070 3071 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 3072 3073 dwc_otg_vbus_interrupt(sc, 3074 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3075 } 3076 3077 if (sc->sc_xfer_complete != 0) { 3078 sc->sc_xfer_complete = 0; 3079 3080 /* complete FIFOs, if any */ 3081 dwc_otg_interrupt_complete_locked(sc); 3082 } 3083 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3084 USB_BUS_UNLOCK(&sc->sc_bus); 3085 } 3086 3087 static void 3088 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 3089 { 3090 struct dwc_otg_td *td; 3091 3092 /* get current Transfer Descriptor */ 3093 td = temp->td_next; 3094 temp->td = td; 3095 3096 /* prepare for next TD */ 3097 temp->td_next = td->obj_next; 3098 3099 /* fill out the Transfer Descriptor */ 3100 td->func = temp->func; 3101 td->pc = temp->pc; 3102 td->offset = temp->offset; 3103 td->remainder = temp->len; 3104 td->tx_bytes = 0; 3105 td->error_any = 0; 3106 td->error_stall = 0; 3107 td->npkt = 0; 3108 td->did_stall = temp->did_stall; 3109 td->short_pkt = temp->short_pkt; 3110 td->alt_next = temp->setup_alt_next; 3111 td->set_toggle = 0; 3112 td->got_short = 0; 3113 td->did_nak = 0; 3114 td->channel[0] = DWC_OTG_MAX_CHANNELS; 3115 td->channel[1] = DWC_OTG_MAX_CHANNELS; 3116 td->channel[2] = DWC_OTG_MAX_CHANNELS; 3117 td->state = 0; 3118 td->errcnt = 0; 3119 td->tt_scheduled = 0; 3120 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3121 } 3122 3123 static void 3124 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3125 { 3126 struct dwc_otg_std_temp temp; 3127 struct dwc_otg_td *td; 3128 uint32_t x; 3129 uint8_t need_sync; 3130 uint8_t is_host; 3131 3132 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3133 xfer->address, UE_GET_ADDR(xfer->endpointno), 3134 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3135 3136 temp.max_frame_size = xfer->max_frame_size; 3137 3138 td = xfer->td_start[0]; 3139 xfer->td_transfer_first = td; 3140 xfer->td_transfer_cache = td; 3141 3142 /* setup temp */ 3143 3144 temp.pc = NULL; 3145 temp.td = NULL; 3146 temp.td_next = xfer->td_start[0]; 3147 temp.offset = 0; 3148 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3149 xfer->flags_int.isochronous_xfr; 3150 temp.did_stall = !xfer->flags_int.control_stall; 3151 3152 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3153 3154 /* check if we should prepend a setup message */ 3155 3156 if (xfer->flags_int.control_xfr) { 3157 if (xfer->flags_int.control_hdr) { 3158 if (is_host) 3159 temp.func = &dwc_otg_host_setup_tx; 3160 else 3161 temp.func = &dwc_otg_setup_rx; 3162 3163 temp.len = xfer->frlengths[0]; 3164 temp.pc = xfer->frbuffers + 0; 3165 temp.short_pkt = temp.len ? 1 : 0; 3166 3167 /* check for last frame */ 3168 if (xfer->nframes == 1) { 3169 /* no STATUS stage yet, SETUP is last */ 3170 if (xfer->flags_int.control_act) 3171 temp.setup_alt_next = 0; 3172 } 3173 3174 dwc_otg_setup_standard_chain_sub(&temp); 3175 } 3176 x = 1; 3177 } else { 3178 x = 0; 3179 } 3180 3181 if (x != xfer->nframes) { 3182 if (xfer->endpointno & UE_DIR_IN) { 3183 if (is_host) { 3184 temp.func = &dwc_otg_host_data_rx; 3185 need_sync = 0; 3186 } else { 3187 temp.func = &dwc_otg_data_tx; 3188 need_sync = 1; 3189 } 3190 } else { 3191 if (is_host) { 3192 temp.func = &dwc_otg_host_data_tx; 3193 need_sync = 0; 3194 } else { 3195 temp.func = &dwc_otg_data_rx; 3196 need_sync = 0; 3197 } 3198 } 3199 3200 /* setup "pc" pointer */ 3201 temp.pc = xfer->frbuffers + x; 3202 } else { 3203 need_sync = 0; 3204 } 3205 while (x != xfer->nframes) { 3206 /* DATA0 / DATA1 message */ 3207 3208 temp.len = xfer->frlengths[x]; 3209 3210 x++; 3211 3212 if (x == xfer->nframes) { 3213 if (xfer->flags_int.control_xfr) { 3214 if (xfer->flags_int.control_act) { 3215 temp.setup_alt_next = 0; 3216 } 3217 } else { 3218 temp.setup_alt_next = 0; 3219 } 3220 } 3221 if (temp.len == 0) { 3222 /* make sure that we send an USB packet */ 3223 3224 temp.short_pkt = 0; 3225 3226 } else { 3227 /* regular data transfer */ 3228 3229 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3230 } 3231 3232 dwc_otg_setup_standard_chain_sub(&temp); 3233 3234 if (xfer->flags_int.isochronous_xfr) { 3235 temp.offset += temp.len; 3236 } else { 3237 /* get next Page Cache pointer */ 3238 temp.pc = xfer->frbuffers + x; 3239 } 3240 } 3241 3242 if (xfer->flags_int.control_xfr) { 3243 /* always setup a valid "pc" pointer for status and sync */ 3244 temp.pc = xfer->frbuffers + 0; 3245 temp.len = 0; 3246 temp.short_pkt = 0; 3247 temp.setup_alt_next = 0; 3248 3249 /* check if we need to sync */ 3250 if (need_sync) { 3251 /* we need a SYNC point after TX */ 3252 temp.func = &dwc_otg_data_tx_sync; 3253 dwc_otg_setup_standard_chain_sub(&temp); 3254 } 3255 3256 /* check if we should append a status stage */ 3257 if (!xfer->flags_int.control_act) { 3258 /* 3259 * Send a DATA1 message and invert the current 3260 * endpoint direction. 3261 */ 3262 if (xfer->endpointno & UE_DIR_IN) { 3263 if (is_host) { 3264 temp.func = &dwc_otg_host_data_tx; 3265 need_sync = 0; 3266 } else { 3267 temp.func = &dwc_otg_data_rx; 3268 need_sync = 0; 3269 } 3270 } else { 3271 if (is_host) { 3272 temp.func = &dwc_otg_host_data_rx; 3273 need_sync = 0; 3274 } else { 3275 temp.func = &dwc_otg_data_tx; 3276 need_sync = 1; 3277 } 3278 } 3279 3280 dwc_otg_setup_standard_chain_sub(&temp); 3281 3282 /* data toggle should be DATA1 */ 3283 td = temp.td; 3284 td->set_toggle = 1; 3285 3286 if (need_sync) { 3287 /* we need a SYNC point after TX */ 3288 temp.func = &dwc_otg_data_tx_sync; 3289 dwc_otg_setup_standard_chain_sub(&temp); 3290 } 3291 } 3292 } else { 3293 /* check if we need to sync */ 3294 if (need_sync) { 3295 temp.pc = xfer->frbuffers + 0; 3296 temp.len = 0; 3297 temp.short_pkt = 0; 3298 temp.setup_alt_next = 0; 3299 3300 /* we need a SYNC point after TX */ 3301 temp.func = &dwc_otg_data_tx_sync; 3302 dwc_otg_setup_standard_chain_sub(&temp); 3303 } 3304 } 3305 3306 /* must have at least one frame! */ 3307 td = temp.td; 3308 xfer->td_transfer_last = td; 3309 3310 if (is_host) { 3311 struct dwc_otg_softc *sc; 3312 uint32_t hcchar; 3313 uint32_t hcsplt; 3314 3315 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3316 3317 /* get first again */ 3318 td = xfer->td_transfer_first; 3319 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3320 3321 hcchar = 3322 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3323 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3324 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3325 HCCHAR_CHENA; 3326 3327 /* 3328 * We are not always able to meet the timing 3329 * requirements of the USB interrupt endpoint's 3330 * complete split token, when doing transfers going 3331 * via a transaction translator. Use the CONTROL 3332 * transfer type instead of the INTERRUPT transfer 3333 * type in general, as a means to workaround 3334 * that. This trick should work for both FULL and LOW 3335 * speed USB traffic going through a TT. For non-TT 3336 * traffic it works as well. The reason for using 3337 * CONTROL type instead of BULK is that some TTs might 3338 * reject LOW speed BULK traffic. 3339 */ 3340 if (td->ep_type == UE_INTERRUPT) 3341 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3342 else 3343 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3344 3345 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3346 hcchar |= HCCHAR_EPDIR_IN; 3347 3348 switch (xfer->xroot->udev->speed) { 3349 case USB_SPEED_LOW: 3350 hcchar |= HCCHAR_LSPDDEV; 3351 /* FALLTHROUGH */ 3352 case USB_SPEED_FULL: 3353 /* check if root HUB port is running High Speed */ 3354 if (dwc_otg_uses_split(xfer->xroot->udev)) { 3355 hcsplt = HCSPLT_SPLTENA | 3356 (xfer->xroot->udev->hs_port_no << 3357 HCSPLT_PRTADDR_SHIFT) | 3358 (xfer->xroot->udev->hs_hub_addr << 3359 HCSPLT_HUBADDR_SHIFT); 3360 } else { 3361 hcsplt = 0; 3362 } 3363 if (td->ep_type == UE_INTERRUPT) { 3364 uint32_t ival; 3365 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3366 if (ival == 0) 3367 ival = 1; 3368 else if (ival > 127) 3369 ival = 127; 3370 td->tmr_val = sc->sc_tmr_val + ival; 3371 td->tmr_res = ival; 3372 } else if (td->ep_type == UE_ISOCHRONOUS) { 3373 td->tmr_res = 1; 3374 td->tmr_val = sc->sc_last_frame_num; 3375 if (td->hcchar & HCCHAR_EPDIR_IN) 3376 td->tmr_val++; 3377 } else { 3378 td->tmr_val = 0; 3379 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3380 } 3381 break; 3382 case USB_SPEED_HIGH: 3383 hcsplt = 0; 3384 if (td->ep_type == UE_INTERRUPT) { 3385 uint32_t ival; 3386 hcchar |= ((xfer->max_packet_count & 3) 3387 << HCCHAR_MC_SHIFT); 3388 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3389 if (ival == 0) 3390 ival = 1; 3391 else if (ival > 127) 3392 ival = 127; 3393 td->tmr_val = sc->sc_tmr_val + ival; 3394 td->tmr_res = ival; 3395 } else if (td->ep_type == UE_ISOCHRONOUS) { 3396 hcchar |= ((xfer->max_packet_count & 3) 3397 << HCCHAR_MC_SHIFT); 3398 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3399 td->tmr_val = sc->sc_last_frame_num; 3400 if (td->hcchar & HCCHAR_EPDIR_IN) 3401 td->tmr_val += td->tmr_res; 3402 3403 } else { 3404 td->tmr_val = 0; 3405 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3406 } 3407 break; 3408 default: 3409 hcsplt = 0; 3410 td->tmr_val = 0; 3411 td->tmr_res = 0; 3412 break; 3413 } 3414 3415 /* store configuration in all TD's */ 3416 while (1) { 3417 td->hcchar = hcchar; 3418 td->hcsplt = hcsplt; 3419 3420 if (((void *)td) == xfer->td_transfer_last) 3421 break; 3422 3423 td = td->obj_next; 3424 } 3425 } 3426 } 3427 3428 static void 3429 dwc_otg_timeout(void *arg) 3430 { 3431 struct usb_xfer *xfer = arg; 3432 3433 DPRINTF("xfer=%p\n", xfer); 3434 3435 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3436 3437 /* transfer is transferred */ 3438 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3439 } 3440 3441 static void 3442 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3443 { 3444 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3445 3446 DPRINTFN(9, "\n"); 3447 3448 /* 3449 * Poll one time in device mode, which will turn on the 3450 * endpoint interrupts. Else wait for SOF interrupt in host 3451 * mode. 3452 */ 3453 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3454 3455 if (sc->sc_flags.status_device_mode != 0) { 3456 dwc_otg_xfer_do_fifo(sc, xfer); 3457 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3458 goto done; 3459 } else { 3460 struct dwc_otg_td *td = xfer->td_transfer_cache; 3461 if (td->ep_type == UE_ISOCHRONOUS && 3462 (td->hcchar & HCCHAR_EPDIR_IN) == 0) { 3463 /* 3464 * Need to start ISOCHRONOUS OUT transfer ASAP 3465 * because execution is delayed by one 125us 3466 * microframe: 3467 */ 3468 dwc_otg_xfer_do_fifo(sc, xfer); 3469 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3470 goto done; 3471 } 3472 } 3473 3474 /* put transfer on interrupt queue */ 3475 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3476 3477 /* start timeout, if any */ 3478 if (xfer->timeout != 0) { 3479 usbd_transfer_timeout_ms(xfer, 3480 &dwc_otg_timeout, xfer->timeout); 3481 } 3482 3483 if (sc->sc_flags.status_device_mode != 0) 3484 goto done; 3485 3486 /* enable SOF interrupt, if any */ 3487 dwc_otg_enable_sof_irq(sc); 3488 done: 3489 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3490 } 3491 3492 static void 3493 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3494 { 3495 DPRINTFN(9, "\n"); 3496 3497 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3498 3499 /* set port bit */ 3500 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3501 3502 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3503 sizeof(sc->sc_hub_idata)); 3504 } 3505 3506 static usb_error_t 3507 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3508 { 3509 struct dwc_otg_td *td; 3510 uint32_t len; 3511 usb_error_t error; 3512 3513 DPRINTFN(9, "\n"); 3514 3515 td = xfer->td_transfer_cache; 3516 3517 do { 3518 len = td->remainder; 3519 3520 /* store last data toggle */ 3521 xfer->endpoint->toggle_next = td->toggle; 3522 3523 if (xfer->aframes != xfer->nframes) { 3524 /* 3525 * Verify the length and subtract 3526 * the remainder from "frlengths[]": 3527 */ 3528 if (len > xfer->frlengths[xfer->aframes]) { 3529 td->error_any = 1; 3530 } else { 3531 xfer->frlengths[xfer->aframes] -= len; 3532 } 3533 } 3534 /* Check for transfer error */ 3535 if (td->error_any) { 3536 /* the transfer is finished */ 3537 error = (td->error_stall ? 3538 USB_ERR_STALLED : USB_ERR_IOERROR); 3539 td = NULL; 3540 break; 3541 } 3542 /* Check for short transfer */ 3543 if (len > 0) { 3544 if (xfer->flags_int.short_frames_ok || 3545 xfer->flags_int.isochronous_xfr) { 3546 /* follow alt next */ 3547 if (td->alt_next) { 3548 td = td->obj_next; 3549 } else { 3550 td = NULL; 3551 } 3552 } else { 3553 /* the transfer is finished */ 3554 td = NULL; 3555 } 3556 error = 0; 3557 break; 3558 } 3559 td = td->obj_next; 3560 3561 /* this USB frame is complete */ 3562 error = 0; 3563 break; 3564 3565 } while (0); 3566 3567 /* update transfer cache */ 3568 3569 xfer->td_transfer_cache = td; 3570 3571 return (error); 3572 } 3573 3574 static void 3575 dwc_otg_standard_done(struct usb_xfer *xfer) 3576 { 3577 usb_error_t err = 0; 3578 3579 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3580 xfer, xfer->endpoint); 3581 3582 /* reset scanner */ 3583 3584 xfer->td_transfer_cache = xfer->td_transfer_first; 3585 3586 if (xfer->flags_int.control_xfr) { 3587 if (xfer->flags_int.control_hdr) { 3588 err = dwc_otg_standard_done_sub(xfer); 3589 } 3590 xfer->aframes = 1; 3591 3592 if (xfer->td_transfer_cache == NULL) { 3593 goto done; 3594 } 3595 } 3596 while (xfer->aframes != xfer->nframes) { 3597 err = dwc_otg_standard_done_sub(xfer); 3598 xfer->aframes++; 3599 3600 if (xfer->td_transfer_cache == NULL) { 3601 goto done; 3602 } 3603 } 3604 3605 if (xfer->flags_int.control_xfr && 3606 !xfer->flags_int.control_act) { 3607 err = dwc_otg_standard_done_sub(xfer); 3608 } 3609 done: 3610 dwc_otg_device_done(xfer, err); 3611 } 3612 3613 /*------------------------------------------------------------------------* 3614 * dwc_otg_device_done 3615 * 3616 * NOTE: this function can be called more than one time on the 3617 * same USB transfer! 3618 *------------------------------------------------------------------------*/ 3619 static void 3620 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3621 { 3622 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3623 3624 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3625 xfer, xfer->endpoint, error); 3626 3627 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3628 3629 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3630 /* Interrupts are cleared by the interrupt handler */ 3631 } else { 3632 struct dwc_otg_td *td; 3633 3634 td = xfer->td_transfer_cache; 3635 if (td != NULL) 3636 dwc_otg_host_channel_free(sc, td); 3637 } 3638 /* dequeue transfer and start next transfer */ 3639 usbd_transfer_done(xfer, error); 3640 3641 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3642 } 3643 3644 static void 3645 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3646 { 3647 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3648 } 3649 3650 static void 3651 dwc_otg_set_stall(struct usb_device *udev, 3652 struct usb_endpoint *ep, uint8_t *did_stall) 3653 { 3654 struct dwc_otg_softc *sc; 3655 uint32_t temp; 3656 uint32_t reg; 3657 uint8_t ep_no; 3658 3659 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3660 3661 /* check mode */ 3662 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3663 /* not supported */ 3664 return; 3665 } 3666 3667 sc = DWC_OTG_BUS2SC(udev->bus); 3668 3669 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3670 3671 /* get endpoint address */ 3672 ep_no = ep->edesc->bEndpointAddress; 3673 3674 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3675 3676 if (ep_no & UE_DIR_IN) { 3677 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3678 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3679 } else { 3680 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3681 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3682 } 3683 3684 /* disable and stall endpoint */ 3685 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3686 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3687 3688 /* clear active OUT ep */ 3689 if (!(ep_no & UE_DIR_IN)) { 3690 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3691 3692 if (sc->sc_last_rx_status != 0 && 3693 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3694 sc->sc_last_rx_status)) { 3695 /* dump data */ 3696 dwc_otg_common_rx_ack(sc); 3697 /* poll interrupt */ 3698 dwc_otg_interrupt_poll_locked(sc); 3699 dwc_otg_interrupt_complete_locked(sc); 3700 } 3701 } 3702 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3703 } 3704 3705 static void 3706 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3707 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3708 { 3709 uint32_t reg; 3710 uint32_t temp; 3711 3712 if (ep_type == UE_CONTROL) { 3713 /* clearing stall is not needed */ 3714 return; 3715 } 3716 3717 if (ep_dir) { 3718 reg = DOTG_DIEPCTL(ep_no); 3719 } else { 3720 reg = DOTG_DOEPCTL(ep_no); 3721 sc->sc_active_rx_ep |= (1U << ep_no); 3722 } 3723 3724 /* round up and mask away the multiplier count */ 3725 mps = (mps + 3) & 0x7FC; 3726 3727 if (ep_type == UE_BULK) { 3728 temp = DIEPCTL_EPTYPE_SET( 3729 DIEPCTL_EPTYPE_BULK) | 3730 DIEPCTL_USBACTEP; 3731 } else if (ep_type == UE_INTERRUPT) { 3732 temp = DIEPCTL_EPTYPE_SET( 3733 DIEPCTL_EPTYPE_INTERRUPT) | 3734 DIEPCTL_USBACTEP; 3735 } else { 3736 temp = DIEPCTL_EPTYPE_SET( 3737 DIEPCTL_EPTYPE_ISOC) | 3738 DIEPCTL_USBACTEP; 3739 } 3740 3741 temp |= DIEPCTL_MPS_SET(mps); 3742 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3743 3744 if (ep_dir) 3745 sc->sc_in_ctl[ep_no] = temp; 3746 else 3747 sc->sc_out_ctl[ep_no] = temp; 3748 3749 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3750 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3751 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3752 3753 /* we only reset the transmit FIFO */ 3754 if (ep_dir) { 3755 dwc_otg_tx_fifo_reset(sc, 3756 GRSTCTL_TXFIFO(ep_no) | 3757 GRSTCTL_TXFFLSH); 3758 3759 DWC_OTG_WRITE_4(sc, 3760 DOTG_DIEPTSIZ(ep_no), 0); 3761 } 3762 3763 /* poll interrupt */ 3764 dwc_otg_interrupt_poll_locked(sc); 3765 dwc_otg_interrupt_complete_locked(sc); 3766 } 3767 3768 static void 3769 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3770 { 3771 struct dwc_otg_softc *sc; 3772 struct usb_endpoint_descriptor *ed; 3773 3774 DPRINTFN(5, "endpoint=%p\n", ep); 3775 3776 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3777 3778 /* check mode */ 3779 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3780 /* not supported */ 3781 return; 3782 } 3783 /* get softc */ 3784 sc = DWC_OTG_BUS2SC(udev->bus); 3785 3786 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3787 3788 /* get endpoint descriptor */ 3789 ed = ep->edesc; 3790 3791 /* reset endpoint */ 3792 dwc_otg_clear_stall_sub_locked(sc, 3793 UGETW(ed->wMaxPacketSize), 3794 (ed->bEndpointAddress & UE_ADDR), 3795 (ed->bmAttributes & UE_XFERTYPE), 3796 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3797 3798 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3799 } 3800 3801 static void 3802 dwc_otg_device_state_change(struct usb_device *udev) 3803 { 3804 struct dwc_otg_softc *sc; 3805 uint8_t x; 3806 3807 /* check mode */ 3808 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3809 /* not supported */ 3810 return; 3811 } 3812 3813 /* get softc */ 3814 sc = DWC_OTG_BUS2SC(udev->bus); 3815 3816 /* deactivate all other endpoint but the control endpoint */ 3817 if (udev->state == USB_STATE_CONFIGURED || 3818 udev->state == USB_STATE_ADDRESSED) { 3819 USB_BUS_LOCK(&sc->sc_bus); 3820 3821 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3822 if (x < sc->sc_dev_in_ep_max) { 3823 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3824 DIEPCTL_EPDIS); 3825 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3826 } 3827 3828 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3829 DOEPCTL_EPDIS); 3830 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3831 } 3832 USB_BUS_UNLOCK(&sc->sc_bus); 3833 } 3834 } 3835 3836 int 3837 dwc_otg_init(struct dwc_otg_softc *sc) 3838 { 3839 uint32_t temp; 3840 int err; 3841 3842 DPRINTF("start\n"); 3843 3844 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 3845 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 3846 sc->sc_io_size = rman_get_size(sc->sc_io_res); 3847 3848 /* set up the bus structure */ 3849 sc->sc_bus.devices = sc->sc_devices; 3850 sc->sc_bus.devices_max = DWC_OTG_MAX_DEVICES; 3851 sc->sc_bus.dma_bits = 32; 3852 sc->sc_bus.usbrev = USB_REV_2_0; 3853 sc->sc_bus.methods = &dwc_otg_bus_methods; 3854 3855 /* get all DMA memory */ 3856 if (usb_bus_mem_alloc_all(&sc->sc_bus, 3857 USB_GET_DMA_TAG(sc->sc_bus.parent), NULL)) { 3858 return (ENOMEM); 3859 } 3860 3861 sc->sc_bus.bdev = device_add_child(sc->sc_bus.parent, "usbus", -1); 3862 if (sc->sc_bus.bdev == NULL) 3863 return (ENXIO); 3864 3865 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 3866 3867 err = bus_setup_intr(sc->sc_bus.parent, sc->sc_irq_res, 3868 INTR_TYPE_TTY | INTR_MPSAFE, &dwc_otg_filter_interrupt, 3869 &dwc_otg_interrupt, sc, &sc->sc_intr_hdl); 3870 if (err) { 3871 sc->sc_intr_hdl = NULL; 3872 return (ENXIO); 3873 } 3874 3875 usb_callout_init_mtx(&sc->sc_timer, 3876 &sc->sc_bus.bus_mtx, 0); 3877 3878 USB_BUS_LOCK(&sc->sc_bus); 3879 3880 /* turn on clocks */ 3881 dwc_otg_clocks_on(sc); 3882 3883 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3884 DPRINTF("Version = 0x%08x\n", temp); 3885 3886 /* disconnect */ 3887 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3888 DCTL_SFTDISCON); 3889 3890 /* wait for host to detect disconnect */ 3891 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3892 3893 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3894 GRSTCTL_CSFTRST); 3895 3896 /* wait a little bit for block to reset */ 3897 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3898 3899 switch (sc->sc_mode) { 3900 case DWC_MODE_DEVICE: 3901 temp = GUSBCFG_FORCEDEVMODE; 3902 break; 3903 case DWC_MODE_HOST: 3904 temp = GUSBCFG_FORCEHOSTMODE; 3905 break; 3906 default: 3907 temp = 0; 3908 break; 3909 } 3910 3911 if (sc->sc_phy_type == 0) 3912 sc->sc_phy_type = dwc_otg_phy_type + 1; 3913 if (sc->sc_phy_bits == 0) 3914 sc->sc_phy_bits = 16; 3915 3916 /* select HSIC, ULPI, UTMI+ or internal PHY mode */ 3917 switch (sc->sc_phy_type) { 3918 case DWC_OTG_PHY_HSIC: 3919 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3920 GUSBCFG_PHYIF | 3921 GUSBCFG_TRD_TIM_SET(5) | temp); 3922 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3923 0x000000EC); 3924 3925 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3926 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3927 temp & ~GLPMCFG_HSIC_CONN); 3928 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3929 temp | GLPMCFG_HSIC_CONN); 3930 break; 3931 case DWC_OTG_PHY_ULPI: 3932 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3933 GUSBCFG_ULPI_UTMI_SEL | 3934 GUSBCFG_TRD_TIM_SET(5) | temp); 3935 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3936 3937 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3938 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3939 temp & ~GLPMCFG_HSIC_CONN); 3940 break; 3941 case DWC_OTG_PHY_UTMI: 3942 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3943 (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) | 3944 GUSBCFG_TRD_TIM_SET(5) | temp); 3945 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3946 3947 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3948 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3949 temp & ~GLPMCFG_HSIC_CONN); 3950 break; 3951 case DWC_OTG_PHY_INTERNAL: 3952 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3953 GUSBCFG_PHYSEL | 3954 GUSBCFG_TRD_TIM_SET(5) | temp); 3955 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3956 3957 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3958 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3959 temp & ~GLPMCFG_HSIC_CONN); 3960 3961 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3962 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3963 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3964 DOTG_GGPIO_PWRDWN); 3965 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3966 break; 3967 default: 3968 break; 3969 } 3970 3971 /* clear global nak */ 3972 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3973 DCTL_CGOUTNAK | 3974 DCTL_CGNPINNAK); 3975 3976 /* disable USB port */ 3977 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3978 3979 /* wait 10ms */ 3980 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3981 3982 /* enable USB port */ 3983 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3984 3985 /* wait 10ms */ 3986 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3987 3988 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3989 3990 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3991 3992 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3993 3994 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3995 3996 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3997 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3998 3999 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 4000 4001 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 4002 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 4003 4004 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 4005 4006 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 4007 4008 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 4009 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 4010 sc->sc_host_ch_max); 4011 4012 /* setup FIFO */ 4013 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 4014 USB_BUS_UNLOCK(&sc->sc_bus); 4015 return (EINVAL); 4016 } 4017 4018 /* enable interrupts */ 4019 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; 4020 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 4021 4022 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 4023 /* enable all endpoint interrupts */ 4024 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 4025 if (temp & GHWCFG2_MPI) { 4026 uint8_t x; 4027 4028 DPRINTF("Disable Multi Process Interrupts\n"); 4029 4030 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 4031 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 4032 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 4033 } 4034 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 4035 } 4036 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 4037 DIEPMSK_XFERCOMPLMSK); 4038 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 4039 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 4040 } 4041 4042 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 4043 /* setup clocks */ 4044 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 4045 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 4046 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 4047 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 4048 } 4049 4050 /* only enable global IRQ */ 4051 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 4052 GAHBCFG_GLBLINTRMSK); 4053 4054 /* turn off clocks */ 4055 dwc_otg_clocks_off(sc); 4056 4057 /* read initial VBUS state */ 4058 4059 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 4060 4061 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 4062 4063 dwc_otg_vbus_interrupt(sc, 4064 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 4065 4066 USB_BUS_UNLOCK(&sc->sc_bus); 4067 4068 /* catch any lost interrupts */ 4069 4070 dwc_otg_do_poll(&sc->sc_bus); 4071 4072 return (0); /* success */ 4073 } 4074 4075 void 4076 dwc_otg_uninit(struct dwc_otg_softc *sc) 4077 { 4078 USB_BUS_LOCK(&sc->sc_bus); 4079 4080 /* stop host timer */ 4081 dwc_otg_timer_stop(sc); 4082 4083 /* set disconnect */ 4084 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 4085 DCTL_SFTDISCON); 4086 4087 /* turn off global IRQ */ 4088 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 4089 4090 sc->sc_flags.port_enabled = 0; 4091 sc->sc_flags.port_powered = 0; 4092 sc->sc_flags.status_vbus = 0; 4093 sc->sc_flags.status_bus_reset = 0; 4094 sc->sc_flags.status_suspend = 0; 4095 sc->sc_flags.change_suspend = 0; 4096 sc->sc_flags.change_connect = 1; 4097 4098 dwc_otg_pull_down(sc); 4099 dwc_otg_clocks_off(sc); 4100 4101 USB_BUS_UNLOCK(&sc->sc_bus); 4102 4103 usb_callout_drain(&sc->sc_timer); 4104 } 4105 4106 static void 4107 dwc_otg_suspend(struct dwc_otg_softc *sc) 4108 { 4109 return; 4110 } 4111 4112 static void 4113 dwc_otg_resume(struct dwc_otg_softc *sc) 4114 { 4115 return; 4116 } 4117 4118 static void 4119 dwc_otg_do_poll(struct usb_bus *bus) 4120 { 4121 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4122 4123 USB_BUS_LOCK(&sc->sc_bus); 4124 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4125 dwc_otg_interrupt_poll_locked(sc); 4126 dwc_otg_interrupt_complete_locked(sc); 4127 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4128 USB_BUS_UNLOCK(&sc->sc_bus); 4129 } 4130 4131 /*------------------------------------------------------------------------* 4132 * DWC OTG bulk support 4133 * DWC OTG control support 4134 * DWC OTG interrupt support 4135 *------------------------------------------------------------------------*/ 4136 static void 4137 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4138 { 4139 } 4140 4141 static void 4142 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4143 { 4144 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4145 } 4146 4147 static void 4148 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4149 { 4150 } 4151 4152 static void 4153 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4154 { 4155 /* setup TDs */ 4156 dwc_otg_setup_standard_chain(xfer); 4157 dwc_otg_start_standard_chain(xfer); 4158 } 4159 4160 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4161 { 4162 .open = dwc_otg_device_non_isoc_open, 4163 .close = dwc_otg_device_non_isoc_close, 4164 .enter = dwc_otg_device_non_isoc_enter, 4165 .start = dwc_otg_device_non_isoc_start, 4166 }; 4167 4168 /*------------------------------------------------------------------------* 4169 * DWC OTG full speed isochronous support 4170 *------------------------------------------------------------------------*/ 4171 static void 4172 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4173 { 4174 } 4175 4176 static void 4177 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4178 { 4179 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4180 } 4181 4182 static void 4183 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4184 { 4185 } 4186 4187 static void 4188 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4189 { 4190 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4191 uint32_t temp; 4192 uint32_t msframes; 4193 uint32_t framenum; 4194 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4195 4196 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4197 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4198 4199 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4200 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4201 4202 /* get the current frame index */ 4203 framenum = (temp & HFNUM_FRNUM_MASK); 4204 } else { 4205 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4206 4207 /* get the current frame index */ 4208 framenum = DSTS_SOFFN_GET(temp); 4209 } 4210 4211 /* 4212 * Check if port is doing 8000 or 1000 frames per second: 4213 */ 4214 if (sc->sc_flags.status_high_speed) 4215 framenum /= 8; 4216 4217 framenum &= DWC_OTG_FRAME_MASK; 4218 4219 /* 4220 * Compute number of milliseconds worth of data traffic for 4221 * this USB transfer: 4222 */ 4223 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4224 msframes = ((xfer->nframes << shift) + 7) / 8; 4225 else 4226 msframes = xfer->nframes; 4227 4228 /* 4229 * check if the frame index is within the window where the frames 4230 * will be inserted 4231 */ 4232 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4233 4234 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4235 /* 4236 * If there is data underflow or the pipe queue is 4237 * empty we schedule the transfer a few frames ahead 4238 * of the current frame position. Else two isochronous 4239 * transfers might overlap. 4240 */ 4241 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4242 xfer->endpoint->is_synced = 1; 4243 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4244 } 4245 /* 4246 * compute how many milliseconds the insertion is ahead of the 4247 * current frame position: 4248 */ 4249 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4250 4251 /* 4252 * pre-compute when the isochronous transfer will be finished: 4253 */ 4254 xfer->isoc_time_complete = 4255 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4256 4257 /* setup TDs */ 4258 dwc_otg_setup_standard_chain(xfer); 4259 4260 /* compute frame number for next insertion */ 4261 xfer->endpoint->isoc_next += msframes; 4262 4263 /* start TD chain */ 4264 dwc_otg_start_standard_chain(xfer); 4265 } 4266 4267 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4268 { 4269 .open = dwc_otg_device_isoc_open, 4270 .close = dwc_otg_device_isoc_close, 4271 .enter = dwc_otg_device_isoc_enter, 4272 .start = dwc_otg_device_isoc_start, 4273 }; 4274 4275 /*------------------------------------------------------------------------* 4276 * DWC OTG root control support 4277 *------------------------------------------------------------------------* 4278 * Simulate a hardware HUB by handling all the necessary requests. 4279 *------------------------------------------------------------------------*/ 4280 4281 static const struct usb_device_descriptor dwc_otg_devd = { 4282 .bLength = sizeof(struct usb_device_descriptor), 4283 .bDescriptorType = UDESC_DEVICE, 4284 .bcdUSB = {0x00, 0x02}, 4285 .bDeviceClass = UDCLASS_HUB, 4286 .bDeviceSubClass = UDSUBCLASS_HUB, 4287 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4288 .bMaxPacketSize = 64, 4289 .bcdDevice = {0x00, 0x01}, 4290 .iManufacturer = 1, 4291 .iProduct = 2, 4292 .bNumConfigurations = 1, 4293 }; 4294 4295 static const struct dwc_otg_config_desc dwc_otg_confd = { 4296 .confd = { 4297 .bLength = sizeof(struct usb_config_descriptor), 4298 .bDescriptorType = UDESC_CONFIG, 4299 .wTotalLength[0] = sizeof(dwc_otg_confd), 4300 .bNumInterface = 1, 4301 .bConfigurationValue = 1, 4302 .iConfiguration = 0, 4303 .bmAttributes = UC_SELF_POWERED, 4304 .bMaxPower = 0, 4305 }, 4306 .ifcd = { 4307 .bLength = sizeof(struct usb_interface_descriptor), 4308 .bDescriptorType = UDESC_INTERFACE, 4309 .bNumEndpoints = 1, 4310 .bInterfaceClass = UICLASS_HUB, 4311 .bInterfaceSubClass = UISUBCLASS_HUB, 4312 .bInterfaceProtocol = 0, 4313 }, 4314 .endpd = { 4315 .bLength = sizeof(struct usb_endpoint_descriptor), 4316 .bDescriptorType = UDESC_ENDPOINT, 4317 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4318 .bmAttributes = UE_INTERRUPT, 4319 .wMaxPacketSize[0] = 8, 4320 .bInterval = 255, 4321 }, 4322 }; 4323 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4324 4325 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4326 .bDescLength = sizeof(dwc_otg_hubd), 4327 .bDescriptorType = UDESC_HUB, 4328 .bNbrPorts = 1, 4329 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4330 .bPwrOn2PwrGood = 50, 4331 .bHubContrCurrent = 0, 4332 .DeviceRemovable = {0}, /* port is removable */ 4333 }; 4334 4335 #define STRING_VENDOR \ 4336 "D\0W\0C\0O\0T\0G" 4337 4338 #define STRING_PRODUCT \ 4339 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4340 4341 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4342 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4343 4344 static usb_error_t 4345 dwc_otg_roothub_exec(struct usb_device *udev, 4346 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4347 { 4348 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4349 const void *ptr; 4350 uint16_t len; 4351 uint16_t value; 4352 uint16_t index; 4353 usb_error_t err; 4354 4355 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4356 4357 /* buffer reset */ 4358 ptr = (const void *)&sc->sc_hub_temp; 4359 len = 0; 4360 err = 0; 4361 4362 value = UGETW(req->wValue); 4363 index = UGETW(req->wIndex); 4364 4365 /* demultiplex the control request */ 4366 4367 switch (req->bmRequestType) { 4368 case UT_READ_DEVICE: 4369 switch (req->bRequest) { 4370 case UR_GET_DESCRIPTOR: 4371 goto tr_handle_get_descriptor; 4372 case UR_GET_CONFIG: 4373 goto tr_handle_get_config; 4374 case UR_GET_STATUS: 4375 goto tr_handle_get_status; 4376 default: 4377 goto tr_stalled; 4378 } 4379 break; 4380 4381 case UT_WRITE_DEVICE: 4382 switch (req->bRequest) { 4383 case UR_SET_ADDRESS: 4384 goto tr_handle_set_address; 4385 case UR_SET_CONFIG: 4386 goto tr_handle_set_config; 4387 case UR_CLEAR_FEATURE: 4388 goto tr_valid; /* nop */ 4389 case UR_SET_DESCRIPTOR: 4390 goto tr_valid; /* nop */ 4391 case UR_SET_FEATURE: 4392 default: 4393 goto tr_stalled; 4394 } 4395 break; 4396 4397 case UT_WRITE_ENDPOINT: 4398 switch (req->bRequest) { 4399 case UR_CLEAR_FEATURE: 4400 switch (UGETW(req->wValue)) { 4401 case UF_ENDPOINT_HALT: 4402 goto tr_handle_clear_halt; 4403 case UF_DEVICE_REMOTE_WAKEUP: 4404 goto tr_handle_clear_wakeup; 4405 default: 4406 goto tr_stalled; 4407 } 4408 break; 4409 case UR_SET_FEATURE: 4410 switch (UGETW(req->wValue)) { 4411 case UF_ENDPOINT_HALT: 4412 goto tr_handle_set_halt; 4413 case UF_DEVICE_REMOTE_WAKEUP: 4414 goto tr_handle_set_wakeup; 4415 default: 4416 goto tr_stalled; 4417 } 4418 break; 4419 case UR_SYNCH_FRAME: 4420 goto tr_valid; /* nop */ 4421 default: 4422 goto tr_stalled; 4423 } 4424 break; 4425 4426 case UT_READ_ENDPOINT: 4427 switch (req->bRequest) { 4428 case UR_GET_STATUS: 4429 goto tr_handle_get_ep_status; 4430 default: 4431 goto tr_stalled; 4432 } 4433 break; 4434 4435 case UT_WRITE_INTERFACE: 4436 switch (req->bRequest) { 4437 case UR_SET_INTERFACE: 4438 goto tr_handle_set_interface; 4439 case UR_CLEAR_FEATURE: 4440 goto tr_valid; /* nop */ 4441 case UR_SET_FEATURE: 4442 default: 4443 goto tr_stalled; 4444 } 4445 break; 4446 4447 case UT_READ_INTERFACE: 4448 switch (req->bRequest) { 4449 case UR_GET_INTERFACE: 4450 goto tr_handle_get_interface; 4451 case UR_GET_STATUS: 4452 goto tr_handle_get_iface_status; 4453 default: 4454 goto tr_stalled; 4455 } 4456 break; 4457 4458 case UT_WRITE_CLASS_INTERFACE: 4459 case UT_WRITE_VENDOR_INTERFACE: 4460 /* XXX forward */ 4461 break; 4462 4463 case UT_READ_CLASS_INTERFACE: 4464 case UT_READ_VENDOR_INTERFACE: 4465 /* XXX forward */ 4466 break; 4467 4468 case UT_WRITE_CLASS_DEVICE: 4469 switch (req->bRequest) { 4470 case UR_CLEAR_FEATURE: 4471 goto tr_valid; 4472 case UR_SET_DESCRIPTOR: 4473 case UR_SET_FEATURE: 4474 break; 4475 default: 4476 goto tr_stalled; 4477 } 4478 break; 4479 4480 case UT_WRITE_CLASS_OTHER: 4481 switch (req->bRequest) { 4482 case UR_CLEAR_FEATURE: 4483 goto tr_handle_clear_port_feature; 4484 case UR_SET_FEATURE: 4485 goto tr_handle_set_port_feature; 4486 case UR_CLEAR_TT_BUFFER: 4487 case UR_RESET_TT: 4488 case UR_STOP_TT: 4489 goto tr_valid; 4490 4491 default: 4492 goto tr_stalled; 4493 } 4494 break; 4495 4496 case UT_READ_CLASS_OTHER: 4497 switch (req->bRequest) { 4498 case UR_GET_TT_STATE: 4499 goto tr_handle_get_tt_state; 4500 case UR_GET_STATUS: 4501 goto tr_handle_get_port_status; 4502 default: 4503 goto tr_stalled; 4504 } 4505 break; 4506 4507 case UT_READ_CLASS_DEVICE: 4508 switch (req->bRequest) { 4509 case UR_GET_DESCRIPTOR: 4510 goto tr_handle_get_class_descriptor; 4511 case UR_GET_STATUS: 4512 goto tr_handle_get_class_status; 4513 4514 default: 4515 goto tr_stalled; 4516 } 4517 break; 4518 default: 4519 goto tr_stalled; 4520 } 4521 goto tr_valid; 4522 4523 tr_handle_get_descriptor: 4524 switch (value >> 8) { 4525 case UDESC_DEVICE: 4526 if (value & 0xff) { 4527 goto tr_stalled; 4528 } 4529 len = sizeof(dwc_otg_devd); 4530 ptr = (const void *)&dwc_otg_devd; 4531 goto tr_valid; 4532 case UDESC_CONFIG: 4533 if (value & 0xff) { 4534 goto tr_stalled; 4535 } 4536 len = sizeof(dwc_otg_confd); 4537 ptr = (const void *)&dwc_otg_confd; 4538 goto tr_valid; 4539 case UDESC_STRING: 4540 switch (value & 0xff) { 4541 case 0: /* Language table */ 4542 len = sizeof(usb_string_lang_en); 4543 ptr = (const void *)&usb_string_lang_en; 4544 goto tr_valid; 4545 4546 case 1: /* Vendor */ 4547 len = sizeof(dwc_otg_vendor); 4548 ptr = (const void *)&dwc_otg_vendor; 4549 goto tr_valid; 4550 4551 case 2: /* Product */ 4552 len = sizeof(dwc_otg_product); 4553 ptr = (const void *)&dwc_otg_product; 4554 goto tr_valid; 4555 default: 4556 break; 4557 } 4558 break; 4559 default: 4560 goto tr_stalled; 4561 } 4562 goto tr_stalled; 4563 4564 tr_handle_get_config: 4565 len = 1; 4566 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4567 goto tr_valid; 4568 4569 tr_handle_get_status: 4570 len = 2; 4571 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4572 goto tr_valid; 4573 4574 tr_handle_set_address: 4575 if (value & 0xFF00) { 4576 goto tr_stalled; 4577 } 4578 sc->sc_rt_addr = value; 4579 goto tr_valid; 4580 4581 tr_handle_set_config: 4582 if (value >= 2) { 4583 goto tr_stalled; 4584 } 4585 sc->sc_conf = value; 4586 goto tr_valid; 4587 4588 tr_handle_get_interface: 4589 len = 1; 4590 sc->sc_hub_temp.wValue[0] = 0; 4591 goto tr_valid; 4592 4593 tr_handle_get_tt_state: 4594 tr_handle_get_class_status: 4595 tr_handle_get_iface_status: 4596 tr_handle_get_ep_status: 4597 len = 2; 4598 USETW(sc->sc_hub_temp.wValue, 0); 4599 goto tr_valid; 4600 4601 tr_handle_set_halt: 4602 tr_handle_set_interface: 4603 tr_handle_set_wakeup: 4604 tr_handle_clear_wakeup: 4605 tr_handle_clear_halt: 4606 goto tr_valid; 4607 4608 tr_handle_clear_port_feature: 4609 if (index != 1) 4610 goto tr_stalled; 4611 4612 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4613 4614 switch (value) { 4615 case UHF_PORT_SUSPEND: 4616 dwc_otg_wakeup_peer(sc); 4617 break; 4618 4619 case UHF_PORT_ENABLE: 4620 if (sc->sc_flags.status_device_mode == 0) { 4621 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4622 sc->sc_hprt_val | HPRT_PRTENA); 4623 } 4624 sc->sc_flags.port_enabled = 0; 4625 break; 4626 4627 case UHF_C_PORT_RESET: 4628 sc->sc_flags.change_reset = 0; 4629 break; 4630 4631 case UHF_C_PORT_ENABLE: 4632 sc->sc_flags.change_enabled = 0; 4633 break; 4634 4635 case UHF_C_PORT_OVER_CURRENT: 4636 sc->sc_flags.change_over_current = 0; 4637 break; 4638 4639 case UHF_PORT_TEST: 4640 case UHF_PORT_INDICATOR: 4641 /* nops */ 4642 break; 4643 4644 case UHF_PORT_POWER: 4645 sc->sc_flags.port_powered = 0; 4646 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4647 sc->sc_hprt_val = 0; 4648 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4649 } 4650 dwc_otg_pull_down(sc); 4651 dwc_otg_clocks_off(sc); 4652 break; 4653 4654 case UHF_C_PORT_CONNECTION: 4655 /* clear connect change flag */ 4656 sc->sc_flags.change_connect = 0; 4657 break; 4658 4659 case UHF_C_PORT_SUSPEND: 4660 sc->sc_flags.change_suspend = 0; 4661 break; 4662 4663 default: 4664 err = USB_ERR_IOERROR; 4665 goto done; 4666 } 4667 goto tr_valid; 4668 4669 tr_handle_set_port_feature: 4670 if (index != 1) { 4671 goto tr_stalled; 4672 } 4673 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4674 4675 switch (value) { 4676 case UHF_PORT_ENABLE: 4677 break; 4678 4679 case UHF_PORT_SUSPEND: 4680 if (sc->sc_flags.status_device_mode == 0) { 4681 /* set suspend BIT */ 4682 sc->sc_hprt_val |= HPRT_PRTSUSP; 4683 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4684 4685 /* generate HUB suspend event */ 4686 dwc_otg_suspend_irq(sc); 4687 } 4688 break; 4689 4690 case UHF_PORT_RESET: 4691 if (sc->sc_flags.status_device_mode == 0) { 4692 DPRINTF("PORT RESET\n"); 4693 4694 /* enable PORT reset */ 4695 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4696 4697 /* Wait 62.5ms for reset to complete */ 4698 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4699 4700 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4701 4702 /* Wait 62.5ms for reset to complete */ 4703 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4704 4705 /* reset FIFOs */ 4706 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4707 4708 sc->sc_flags.change_reset = 1; 4709 } else { 4710 err = USB_ERR_IOERROR; 4711 } 4712 break; 4713 4714 case UHF_PORT_TEST: 4715 case UHF_PORT_INDICATOR: 4716 /* nops */ 4717 break; 4718 case UHF_PORT_POWER: 4719 sc->sc_flags.port_powered = 1; 4720 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4721 sc->sc_hprt_val |= HPRT_PRTPWR; 4722 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4723 } 4724 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4725 /* pull up D+, if any */ 4726 dwc_otg_pull_up(sc); 4727 } 4728 break; 4729 default: 4730 err = USB_ERR_IOERROR; 4731 goto done; 4732 } 4733 goto tr_valid; 4734 4735 tr_handle_get_port_status: 4736 4737 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4738 4739 if (index != 1) 4740 goto tr_stalled; 4741 4742 if (sc->sc_flags.status_vbus) 4743 dwc_otg_clocks_on(sc); 4744 else 4745 dwc_otg_clocks_off(sc); 4746 4747 /* Select Device Side Mode */ 4748 4749 if (sc->sc_flags.status_device_mode) { 4750 value = UPS_PORT_MODE_DEVICE; 4751 dwc_otg_timer_stop(sc); 4752 } else { 4753 value = 0; 4754 dwc_otg_timer_start(sc); 4755 } 4756 4757 if (sc->sc_flags.status_high_speed) 4758 value |= UPS_HIGH_SPEED; 4759 else if (sc->sc_flags.status_low_speed) 4760 value |= UPS_LOW_SPEED; 4761 4762 if (sc->sc_flags.port_powered) 4763 value |= UPS_PORT_POWER; 4764 4765 if (sc->sc_flags.port_enabled) 4766 value |= UPS_PORT_ENABLED; 4767 4768 if (sc->sc_flags.port_over_current) 4769 value |= UPS_OVERCURRENT_INDICATOR; 4770 4771 if (sc->sc_flags.status_vbus && 4772 sc->sc_flags.status_bus_reset) 4773 value |= UPS_CURRENT_CONNECT_STATUS; 4774 4775 if (sc->sc_flags.status_suspend) 4776 value |= UPS_SUSPEND; 4777 4778 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4779 4780 value = 0; 4781 4782 if (sc->sc_flags.change_enabled) 4783 value |= UPS_C_PORT_ENABLED; 4784 if (sc->sc_flags.change_connect) 4785 value |= UPS_C_CONNECT_STATUS; 4786 if (sc->sc_flags.change_suspend) 4787 value |= UPS_C_SUSPEND; 4788 if (sc->sc_flags.change_reset) 4789 value |= UPS_C_PORT_RESET; 4790 if (sc->sc_flags.change_over_current) 4791 value |= UPS_C_OVERCURRENT_INDICATOR; 4792 4793 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4794 len = sizeof(sc->sc_hub_temp.ps); 4795 goto tr_valid; 4796 4797 tr_handle_get_class_descriptor: 4798 if (value & 0xFF) { 4799 goto tr_stalled; 4800 } 4801 ptr = (const void *)&dwc_otg_hubd; 4802 len = sizeof(dwc_otg_hubd); 4803 goto tr_valid; 4804 4805 tr_stalled: 4806 err = USB_ERR_STALLED; 4807 tr_valid: 4808 done: 4809 *plength = len; 4810 *pptr = ptr; 4811 return (err); 4812 } 4813 4814 static void 4815 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4816 { 4817 struct usb_xfer *xfer; 4818 void *last_obj; 4819 uint32_t ntd; 4820 uint32_t n; 4821 uint8_t ep_no; 4822 uint8_t ep_type; 4823 4824 xfer = parm->curr_xfer; 4825 4826 /* 4827 * NOTE: This driver does not use any of the parameters that 4828 * are computed from the following values. Just set some 4829 * reasonable dummies: 4830 */ 4831 parm->hc_max_packet_size = 0x500; 4832 parm->hc_max_packet_count = 3; 4833 parm->hc_max_frame_size = 3 * 0x500; 4834 4835 usbd_transfer_setup_sub(parm); 4836 4837 /* 4838 * compute maximum number of TDs 4839 */ 4840 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4841 4842 if (ep_type == UE_CONTROL) { 4843 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4844 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4845 } else { 4846 ntd = xfer->nframes + 1 /* SYNC */ ; 4847 } 4848 4849 /* 4850 * check if "usbd_transfer_setup_sub" set an error 4851 */ 4852 if (parm->err) 4853 return; 4854 4855 /* 4856 * allocate transfer descriptors 4857 */ 4858 last_obj = NULL; 4859 4860 ep_no = xfer->endpointno & UE_ADDR; 4861 4862 /* 4863 * Check for a valid endpoint profile in USB device mode: 4864 */ 4865 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4866 const struct usb_hw_ep_profile *pf; 4867 4868 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4869 4870 if (pf == NULL) { 4871 /* should not happen */ 4872 parm->err = USB_ERR_INVAL; 4873 return; 4874 } 4875 } 4876 4877 /* align data */ 4878 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4879 4880 for (n = 0; n != ntd; n++) { 4881 struct dwc_otg_td *td; 4882 4883 if (parm->buf) { 4884 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4885 4886 /* compute shared bandwidth resource index for TT */ 4887 if (dwc_otg_uses_split(parm->udev)) { 4888 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4889 td->tt_index = parm->udev->device_index; 4890 else 4891 td->tt_index = parm->udev->parent_hs_hub->device_index; 4892 } else { 4893 td->tt_index = parm->udev->device_index; 4894 } 4895 4896 /* init TD */ 4897 td->max_packet_size = xfer->max_packet_size; 4898 td->max_packet_count = xfer->max_packet_count; 4899 /* range check */ 4900 if (td->max_packet_count == 0 || td->max_packet_count > 3) 4901 td->max_packet_count = 1; 4902 td->ep_no = ep_no; 4903 td->ep_type = ep_type; 4904 td->obj_next = last_obj; 4905 4906 last_obj = td; 4907 } 4908 parm->size[0] += sizeof(*td); 4909 } 4910 4911 xfer->td_start[0] = last_obj; 4912 } 4913 4914 static void 4915 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4916 { 4917 return; 4918 } 4919 4920 static void 4921 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4922 struct usb_endpoint *ep) 4923 { 4924 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4925 4926 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4927 ep, udev->address, 4928 edesc->bEndpointAddress, udev->flags.usb_mode, 4929 sc->sc_rt_addr, udev->device_index); 4930 4931 if (udev->device_index != sc->sc_rt_addr) { 4932 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4933 if (udev->speed != USB_SPEED_FULL && 4934 udev->speed != USB_SPEED_HIGH) { 4935 /* not supported */ 4936 return; 4937 } 4938 } else { 4939 if (udev->speed == USB_SPEED_HIGH && 4940 (edesc->wMaxPacketSize[1] & 0x18) != 0 && 4941 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4942 /* not supported */ 4943 DPRINTFN(-1, "Non-isochronous high bandwidth " 4944 "endpoint not supported\n"); 4945 return; 4946 } 4947 } 4948 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4949 ep->methods = &dwc_otg_device_isoc_methods; 4950 else 4951 ep->methods = &dwc_otg_device_non_isoc_methods; 4952 } 4953 } 4954 4955 static void 4956 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4957 { 4958 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4959 4960 switch (state) { 4961 case USB_HW_POWER_SUSPEND: 4962 dwc_otg_suspend(sc); 4963 break; 4964 case USB_HW_POWER_SHUTDOWN: 4965 dwc_otg_uninit(sc); 4966 break; 4967 case USB_HW_POWER_RESUME: 4968 dwc_otg_resume(sc); 4969 break; 4970 default: 4971 break; 4972 } 4973 } 4974 4975 static void 4976 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4977 { 4978 /* DMA delay - wait until any use of memory is finished */ 4979 *pus = (2125); /* microseconds */ 4980 } 4981 4982 static void 4983 dwc_otg_device_resume(struct usb_device *udev) 4984 { 4985 DPRINTF("\n"); 4986 4987 /* poll all transfers again to restart resumed ones */ 4988 dwc_otg_do_poll(udev->bus); 4989 } 4990 4991 static void 4992 dwc_otg_device_suspend(struct usb_device *udev) 4993 { 4994 DPRINTF("\n"); 4995 } 4996 4997 static const struct usb_bus_methods dwc_otg_bus_methods = 4998 { 4999 .endpoint_init = &dwc_otg_ep_init, 5000 .xfer_setup = &dwc_otg_xfer_setup, 5001 .xfer_unsetup = &dwc_otg_xfer_unsetup, 5002 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 5003 .xfer_stall = &dwc_otg_xfer_stall, 5004 .set_stall = &dwc_otg_set_stall, 5005 .clear_stall = &dwc_otg_clear_stall, 5006 .roothub_exec = &dwc_otg_roothub_exec, 5007 .xfer_poll = &dwc_otg_do_poll, 5008 .device_state_change = &dwc_otg_device_state_change, 5009 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 5010 .get_dma_delay = &dwc_otg_get_dma_delay, 5011 .device_resume = &dwc_otg_device_resume, 5012 .device_suspend = &dwc_otg_device_suspend, 5013 }; 5014