1/* 2 * Copyright (c) 2010 The FreeBSD Foundation 3 * Copyright (c) 2010-2011 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Marvell DB-78460 Device Tree Source. 28 */ 29 30/dts-v1/; 31 32/ { 33 model = "mrvl,DB-78460"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 aliases { 38 serial0 = &serial0; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 cpu@0 { 46 device_type = "cpu"; 47 compatible = "ARM,88VS584"; 48 reg = <0x0>; 49 d-cache-line-size = <32>; // 32 bytes 50 i-cache-line-size = <32>; // 32 bytes 51 d-cache-size = <0x8000>; // L1, 32K 52 i-cache-size = <0x8000>; // L1, 32K 53 timebase-frequency = <0>; 54 bus-frequency = <200000000>; 55 clock-frequency = <0>; 56 }; 57 }; 58 59 memory { 60 device_type = "memory"; 61 reg = <0x0 0x80000000>; // 2G at 0x0 62 }; 63 64 soc78460@d0000000 { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "simple-bus"; 68 ranges = <0x0 0xd0000000 0x00100000>; 69 bus-frequency = <0>; 70 71 72 MPIC: mpic@20a00 { 73 interrupt-controller; 74 #address-cells = <0>; 75 #interrupt-cells = <1>; 76 reg = <0x20a00 0x500 0x21870 0x58 0x20400 0x100>; 77 compatible = "mrvl,mpic"; 78 }; 79 80 rtc@10300 { 81 compatible = "mrvl,rtc"; 82 reg = <0x10300 0x08>; 83 }; 84 85 timer@21840 { 86 compatible = "marvell,armada-xp-timer"; 87 reg = <0x21840 0x30>; 88 interrupts = <5>; 89 interrupt-parent = <&MPIC>; 90 mrvl,has-wdt; 91 }; 92 93 twsi@11000 { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 compatible = "mrvl,twsi"; 97 reg = <0x11000 0x20>; 98 interrupts = <31>; 99 interrupt-parent = <&MPIC>; 100 }; 101 102 twsi@11100 { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 compatible = "mrvl,twsi"; 106 reg = <0x11100 0x20>; 107 interrupts = <32>; 108 interrupt-parent = <&MPIC>; 109 }; 110 111 serial0: serial@12000 { 112 compatible = "snps,dw-apb-uart"; 113 reg = <0x12000 0x20>; 114 reg-shift = <2>; 115 current-speed = <115200>; 116 clock-frequency = <0>; 117 interrupts = <41>; 118 interrupt-parent = <&MPIC>; 119 }; 120 121 serial1: serial@12100 { 122 compatible = "snps,dw-apb-uart"; 123 reg = <0x12100 0x20>; 124 reg-shift = <2>; 125 current-speed = <115200>; 126 clock-frequency = <0>; 127 interrupts = <42>; 128 interrupt-parent = <&MPIC>; 129 }; 130 131 serial2: serial@12200 { 132 compatible = "snps,dw-apb-uart"; 133 reg = <0x12200 0x20>; 134 reg-shift = <2>; 135 current-speed = <115200>; 136 clock-frequency = <0>; 137 interrupts = <43>; 138 interrupt-parent = <&MPIC>; 139 }; 140 141 serial3: serial@12300 { 142 compatible = "snps,dw-apb-uart"; 143 reg = <0x12300 0x20>; 144 reg-shift = <2>; 145 current-speed = <115200>; 146 clock-frequency = <0>; 147 interrupts = <44>; 148 interrupt-parent = <&MPIC>; 149 }; 150 151 MPP: mpp@10000 { 152 #pin-cells = <2>; 153 compatible = "mrvl,mpp"; 154 reg = <0x18000 0x34>; 155 pin-count = <68>; 156 pin-map = < 157 0 1 /* MPP[0]: GE1_TXCLK */ 158 1 1 /* MPP[1]: GE1_TXCTL */ 159 2 1 /* MPP[2]: GE1_RXCTL */ 160 3 1 /* MPP[3]: GE1_RXCLK */ 161 4 1 /* MPP[4]: GE1_TXD[0] */ 162 5 1 /* MPP[5]: GE1_TXD[1] */ 163 6 1 /* MPP[6]: GE1_TXD[2] */ 164 7 1 /* MPP[7]: GE1_TXD[3] */ 165 8 1 /* MPP[8]: GE1_RXD[0] */ 166 9 1 /* MPP[9]: GE1_RXD[1] */ 167 10 1 /* MPP[10]: GE1_RXD[2] */ 168 11 1 /* MPP[11]: GE1_RXD[3] */ 169 12 2 /* MPP[13]: SYSRST_OUTn */ 170 13 2 /* MPP[13]: SYSRST_OUTn */ 171 14 2 /* MPP[14]: SATA1_ACTn */ 172 15 2 /* MPP[15]: SATA0_ACTn */ 173 16 2 /* MPP[16]: UA2_TXD */ 174 17 2 /* MPP[17]: UA2_RXD */ 175 18 2 /* MPP[18]: <UNKNOWN> */ 176 19 2 /* MPP[19]: <UNKNOWN> */ 177 20 2 /* MPP[20]: <UNKNOWN> */ 178 21 2 /* MPP[21]: <UNKNOWN> */ 179 22 2 /* MPP[22]: UA3_TXD */ 180 23 2 181 24 0 182 25 0 183 26 0 184 27 0 185 28 4 186 29 0 187 30 1 188 31 1 189 32 1 190 33 1 191 34 1 192 35 1 193 36 1 194 37 1 195 38 1 196 39 1 197 40 0 198 41 3 199 42 1 200 43 1 201 44 2 202 45 2 203 46 4 204 47 3 205 48 0 206 49 1 207 50 1 208 51 1 209 52 1 210 53 1 211 54 1 212 55 1 213 56 1 214 57 0 215 58 1 216 59 1 217 60 1 218 61 1 219 62 1 220 63 1 221 64 1 222 65 1 223 66 1 224 67 2 >; 225 }; 226 227 usb@50000 { 228 compatible = "mrvl,usb-ehci", "usb-ehci"; 229 reg = <0x50000 0x1000>; 230 interrupts = <124 45>; 231 interrupt-parent = <&MPIC>; 232 }; 233 234 usb@51000 { 235 compatible = "mrvl,usb-ehci", "usb-ehci"; 236 reg = <0x51000 0x1000>; 237 interrupts = <124 46>; 238 interrupt-parent = <&MPIC>; 239 }; 240 241 usb@52000 { 242 compatible = "mrvl,usb-ehci", "usb-ehci"; 243 reg = <0x52000 0x1000>; 244 interrupts = <124 47>; 245 interrupt-parent = <&MPIC>; 246 }; 247 248 enet0: ethernet@72000 { 249 #address-cells = <1>; 250 #size-cells = <1>; 251 model = "V2"; 252 compatible = "mrvl,ge"; 253 reg = <0x72000 0x2000>; 254 ranges = <0x0 0x72000 0x2000>; 255 local-mac-address = [ 00 04 01 07 84 60 ]; 256 interrupts = <67 68 122 >; 257 interrupt-parent = <&MPIC>; 258 phy-handle = <&phy0>; 259 has-neta; 260 261 mdio@0 { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 compatible = "mrvl,mdio"; 265 266 phy0: ethernet-phy@0 { 267 reg = <0x0>; 268 }; 269 phy1: ethernet-phy@1 { 270 reg = <0x1>; 271 }; 272 phy2: ethernet-phy@2 { 273 reg = <0x19>; 274 }; 275 phy3: ethernet-phy@3 { 276 reg = <0x1b>; 277 }; 278 }; 279 }; 280 281 sata@A0000 { 282 compatible = "mrvl,sata"; 283 reg = <0xA0000 0x6000>; 284 interrupts = <55>; 285 interrupt-parent = <&MPIC>; 286 }; 287 }; 288 289 pci0: pcie@d0040000 { 290 compatible = "mrvl,pcie"; 291 device_type = "pci"; 292 #interrupt-cells = <1>; 293 #size-cells = <2>; 294 #address-cells = <3>; 295 reg = <0xd0040000 0x2000>; 296 bus-range = <0 255>; 297 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 298 0x01000000 0x0 0x00000000 0xa0000000 0x0 0x08000000>; 299 clock-frequency = <33333333>; 300 interrupt-parent = <&MPIC>; 301 interrupts = <120>; 302 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 303 interrupt-map = < 304 0x0800 0x0 0x0 0x1 &MPIC 0x3A 305 0x0800 0x0 0x0 0x2 &MPIC 0x3A 306 0x0800 0x0 0x0 0x3 &MPIC 0x3A 307 0x0800 0x0 0x0 0x4 &MPIC 0x3A 308 >; 309 }; 310 311 sram@ffff0000 { 312 compatible = "mrvl,cesa-sram"; 313 reg = <0xffff0000 0x00010000>; 314 }; 315 316 chosen { 317 stdin = "serial0"; 318 stdout = "serial0"; 319 stddbg = "serial0"; 320 }; 321}; 322