1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2006 Michael Lorenz
5 * Copyright 2008 by Nathan Whitehorn
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/module.h>
36 #include <sys/bus.h>
37 #include <sys/conf.h>
38 #include <sys/eventhandler.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/clock.h>
43 #include <sys/reboot.h>
44
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/openfirm.h>
47
48 #include <machine/bus.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/pio.h>
52 #include <machine/resource.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <sys/rman.h>
58
59 #include <dev/adb/adb.h>
60
61 #include "clock_if.h"
62 #include "cudavar.h"
63 #include "viareg.h"
64
65 /*
66 * MacIO interface
67 */
68 static int cuda_probe(device_t);
69 static int cuda_attach(device_t);
70 static int cuda_detach(device_t);
71
72 static u_int cuda_adb_send(device_t dev, u_char command_byte, int len,
73 u_char *data, u_char poll);
74 static u_int cuda_adb_autopoll(device_t dev, uint16_t mask);
75 static u_int cuda_poll(device_t dev);
76 static void cuda_send_inbound(struct cuda_softc *sc);
77 static void cuda_send_outbound(struct cuda_softc *sc);
78 static void cuda_shutdown(void *xsc, int howto);
79
80 /*
81 * Clock interface
82 */
83 static int cuda_gettime(device_t dev, struct timespec *ts);
84 static int cuda_settime(device_t dev, struct timespec *ts);
85
86 static device_method_t cuda_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, cuda_probe),
89 DEVMETHOD(device_attach, cuda_attach),
90 DEVMETHOD(device_detach, cuda_detach),
91 DEVMETHOD(device_shutdown, bus_generic_shutdown),
92 DEVMETHOD(device_suspend, bus_generic_suspend),
93 DEVMETHOD(device_resume, bus_generic_resume),
94
95 /* ADB bus interface */
96 DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send),
97 DEVMETHOD(adb_hb_controller_poll, cuda_poll),
98 DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll),
99
100 /* Clock interface */
101 DEVMETHOD(clock_gettime, cuda_gettime),
102 DEVMETHOD(clock_settime, cuda_settime),
103
104 DEVMETHOD_END
105 };
106
107 static driver_t cuda_driver = {
108 "cuda",
109 cuda_methods,
110 sizeof(struct cuda_softc),
111 };
112
113 DRIVER_MODULE(cuda, macio, cuda_driver, 0, 0);
114 DRIVER_MODULE(adb, cuda, adb_driver, 0, 0);
115
116 static void cuda_intr(void *arg);
117 static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
118 static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
119 static void cuda_idle(struct cuda_softc *);
120 static void cuda_tip(struct cuda_softc *);
121 static void cuda_clear_tip(struct cuda_softc *);
122 static void cuda_in(struct cuda_softc *);
123 static void cuda_out(struct cuda_softc *);
124 static void cuda_toggle_ack(struct cuda_softc *);
125 static void cuda_ack_off(struct cuda_softc *);
126 static int cuda_intr_state(struct cuda_softc *);
127
128 static int
cuda_probe(device_t dev)129 cuda_probe(device_t dev)
130 {
131 const char *type = ofw_bus_get_type(dev);
132
133 if (strcmp(type, "via-cuda") != 0)
134 return (ENXIO);
135
136 device_set_desc(dev, CUDA_DEVSTR);
137 return (0);
138 }
139
140 static int
cuda_attach(device_t dev)141 cuda_attach(device_t dev)
142 {
143 struct cuda_softc *sc;
144
145 volatile int i;
146 uint8_t reg;
147 phandle_t node,child;
148
149 sc = device_get_softc(dev);
150 sc->sc_dev = dev;
151
152 sc->sc_memrid = 0;
153 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
154 &sc->sc_memrid, RF_ACTIVE);
155
156 if (sc->sc_memr == NULL) {
157 device_printf(dev, "Could not alloc mem resource!\n");
158 return (ENXIO);
159 }
160
161 sc->sc_irqrid = 0;
162 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
163 RF_ACTIVE);
164 if (sc->sc_irq == NULL) {
165 device_printf(dev, "could not allocate interrupt\n");
166 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
167 sc->sc_memr);
168 return (ENXIO);
169 }
170
171 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
172 | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
173 device_printf(dev, "could not setup interrupt\n");
174 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
175 sc->sc_memr);
176 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
177 sc->sc_irq);
178 return (ENXIO);
179 }
180
181 mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
182
183 sc->sc_sent = 0;
184 sc->sc_received = 0;
185 sc->sc_waiting = 0;
186 sc->sc_polling = 0;
187 sc->sc_state = CUDA_NOTREADY;
188 sc->sc_autopoll = 0;
189 sc->sc_rtc = -1;
190
191 STAILQ_INIT(&sc->sc_inq);
192 STAILQ_INIT(&sc->sc_outq);
193 STAILQ_INIT(&sc->sc_freeq);
194
195 for (i = 0; i < CUDA_MAXPACKETS; i++)
196 STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
197
198 /* Init CUDA */
199
200 reg = cuda_read_reg(sc, vDirB);
201 reg |= 0x30; /* register B bits 4 and 5: outputs */
202 cuda_write_reg(sc, vDirB, reg);
203
204 reg = cuda_read_reg(sc, vDirB);
205 reg &= 0xf7; /* register B bit 3: input */
206 cuda_write_reg(sc, vDirB, reg);
207
208 reg = cuda_read_reg(sc, vACR);
209 reg &= ~vSR_OUT; /* make sure SR is set to IN */
210 cuda_write_reg(sc, vACR, reg);
211
212 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
213
214 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
215
216 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
217
218 cuda_idle(sc); /* reset ADB */
219
220 /* Reset CUDA */
221
222 i = cuda_read_reg(sc, vSR); /* clear interrupt */
223 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
224 cuda_idle(sc); /* reset state to idle */
225 DELAY(150);
226 cuda_tip(sc); /* signal start of frame */
227 DELAY(150);
228 cuda_toggle_ack(sc);
229 DELAY(150);
230 cuda_clear_tip(sc);
231 DELAY(150);
232 cuda_idle(sc); /* back to idle state */
233 i = cuda_read_reg(sc, vSR); /* clear interrupt */
234 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
235
236 /* Initialize child buses (ADB) */
237 node = ofw_bus_get_node(dev);
238
239 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
240 char name[32];
241
242 memset(name, 0, sizeof(name));
243 OF_getprop(child, "name", name, sizeof(name));
244
245 if (bootverbose)
246 device_printf(dev, "CUDA child <%s>\n",name);
247
248 if (strncmp(name, "adb", 4) == 0) {
249 sc->adb_bus = device_add_child(dev,"adb",-1);
250 }
251 }
252
253 clock_register(dev, 1000);
254 EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
255 SHUTDOWN_PRI_LAST);
256
257 return (bus_generic_attach(dev));
258 }
259
cuda_detach(device_t dev)260 static int cuda_detach(device_t dev) {
261 struct cuda_softc *sc;
262
263 sc = device_get_softc(dev);
264
265 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
266 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
267 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
268 mtx_destroy(&sc->sc_mutex);
269
270 return (bus_generic_detach(dev));
271 }
272
273 static uint8_t
cuda_read_reg(struct cuda_softc * sc,u_int offset)274 cuda_read_reg(struct cuda_softc *sc, u_int offset) {
275 return (bus_read_1(sc->sc_memr, offset));
276 }
277
278 static void
cuda_write_reg(struct cuda_softc * sc,u_int offset,uint8_t value)279 cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
280 bus_write_1(sc->sc_memr, offset, value);
281 }
282
283 static void
cuda_idle(struct cuda_softc * sc)284 cuda_idle(struct cuda_softc *sc)
285 {
286 uint8_t reg;
287
288 reg = cuda_read_reg(sc, vBufB);
289 reg |= (vPB4 | vPB5);
290 cuda_write_reg(sc, vBufB, reg);
291 }
292
293 static void
cuda_tip(struct cuda_softc * sc)294 cuda_tip(struct cuda_softc *sc)
295 {
296 uint8_t reg;
297
298 reg = cuda_read_reg(sc, vBufB);
299 reg &= ~vPB5;
300 cuda_write_reg(sc, vBufB, reg);
301 }
302
303 static void
cuda_clear_tip(struct cuda_softc * sc)304 cuda_clear_tip(struct cuda_softc *sc)
305 {
306 uint8_t reg;
307
308 reg = cuda_read_reg(sc, vBufB);
309 reg |= vPB5;
310 cuda_write_reg(sc, vBufB, reg);
311 }
312
313 static void
cuda_in(struct cuda_softc * sc)314 cuda_in(struct cuda_softc *sc)
315 {
316 uint8_t reg;
317
318 reg = cuda_read_reg(sc, vACR);
319 reg &= ~vSR_OUT;
320 cuda_write_reg(sc, vACR, reg);
321 }
322
323 static void
cuda_out(struct cuda_softc * sc)324 cuda_out(struct cuda_softc *sc)
325 {
326 uint8_t reg;
327
328 reg = cuda_read_reg(sc, vACR);
329 reg |= vSR_OUT;
330 cuda_write_reg(sc, vACR, reg);
331 }
332
333 static void
cuda_toggle_ack(struct cuda_softc * sc)334 cuda_toggle_ack(struct cuda_softc *sc)
335 {
336 uint8_t reg;
337
338 reg = cuda_read_reg(sc, vBufB);
339 reg ^= vPB4;
340 cuda_write_reg(sc, vBufB, reg);
341 }
342
343 static void
cuda_ack_off(struct cuda_softc * sc)344 cuda_ack_off(struct cuda_softc *sc)
345 {
346 uint8_t reg;
347
348 reg = cuda_read_reg(sc, vBufB);
349 reg |= vPB4;
350 cuda_write_reg(sc, vBufB, reg);
351 }
352
353 static int
cuda_intr_state(struct cuda_softc * sc)354 cuda_intr_state(struct cuda_softc *sc)
355 {
356 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
357 }
358
359 static int
cuda_send(void * cookie,int poll,int length,uint8_t * msg)360 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
361 {
362 struct cuda_softc *sc = cookie;
363 device_t dev = sc->sc_dev;
364 struct cuda_packet *pkt;
365
366 if (sc->sc_state == CUDA_NOTREADY)
367 return (-1);
368
369 mtx_lock(&sc->sc_mutex);
370
371 pkt = STAILQ_FIRST(&sc->sc_freeq);
372 if (pkt == NULL) {
373 mtx_unlock(&sc->sc_mutex);
374 return (-1);
375 }
376
377 pkt->len = length - 1;
378 pkt->type = msg[0];
379 memcpy(pkt->data, &msg[1], pkt->len);
380
381 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
382 STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
383
384 /*
385 * If we already are sending a packet, we should bail now that this
386 * one has been added to the queue.
387 */
388
389 if (sc->sc_waiting) {
390 mtx_unlock(&sc->sc_mutex);
391 return (0);
392 }
393
394 cuda_send_outbound(sc);
395 mtx_unlock(&sc->sc_mutex);
396
397 if (sc->sc_polling || poll || cold)
398 cuda_poll(dev);
399
400 return (0);
401 }
402
403 static void
cuda_send_outbound(struct cuda_softc * sc)404 cuda_send_outbound(struct cuda_softc *sc)
405 {
406 struct cuda_packet *pkt;
407
408 mtx_assert(&sc->sc_mutex, MA_OWNED);
409
410 pkt = STAILQ_FIRST(&sc->sc_outq);
411 if (pkt == NULL)
412 return;
413
414 sc->sc_out_length = pkt->len + 1;
415 memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
416 sc->sc_sent = 0;
417
418 STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
419 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
420
421 sc->sc_waiting = 1;
422
423 cuda_poll(sc->sc_dev);
424
425 DELAY(150);
426
427 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
428 sc->sc_state = CUDA_OUT;
429 cuda_out(sc);
430 cuda_write_reg(sc, vSR, sc->sc_out[0]);
431 cuda_ack_off(sc);
432 cuda_tip(sc);
433 }
434 }
435
436 static void
cuda_send_inbound(struct cuda_softc * sc)437 cuda_send_inbound(struct cuda_softc *sc)
438 {
439 device_t dev;
440 struct cuda_packet *pkt;
441
442 dev = sc->sc_dev;
443
444 mtx_lock(&sc->sc_mutex);
445
446 while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
447 STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
448
449 mtx_unlock(&sc->sc_mutex);
450
451 /* check if we have a handler for this message */
452 switch (pkt->type) {
453 case CUDA_ADB:
454 if (pkt->len > 2) {
455 adb_receive_raw_packet(sc->adb_bus,
456 pkt->data[0],pkt->data[1],
457 pkt->len - 2,&pkt->data[2]);
458 } else {
459 adb_receive_raw_packet(sc->adb_bus,
460 pkt->data[0],pkt->data[1],0,NULL);
461 }
462 break;
463 case CUDA_PSEUDO:
464 mtx_lock(&sc->sc_mutex);
465 switch (pkt->data[1]) {
466 case CMD_AUTOPOLL:
467 sc->sc_autopoll = 1;
468 break;
469 case CMD_READ_RTC:
470 memcpy(&sc->sc_rtc, &pkt->data[2],
471 sizeof(sc->sc_rtc));
472 wakeup(&sc->sc_rtc);
473 break;
474 case CMD_WRITE_RTC:
475 break;
476 }
477 mtx_unlock(&sc->sc_mutex);
478 break;
479 case CUDA_ERROR:
480 /*
481 * CUDA will throw errors if we miss a race between
482 * sending and receiving packets. This is already
483 * handled when we abort packet output to handle
484 * this packet in cuda_intr(). Thus, we ignore
485 * these messages.
486 */
487 break;
488 default:
489 device_printf(dev,"unknown CUDA command %d\n",
490 pkt->type);
491 break;
492 }
493
494 mtx_lock(&sc->sc_mutex);
495
496 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
497 }
498
499 mtx_unlock(&sc->sc_mutex);
500 }
501
502 static u_int
cuda_poll(device_t dev)503 cuda_poll(device_t dev)
504 {
505 struct cuda_softc *sc = device_get_softc(dev);
506
507 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
508 !sc->sc_waiting)
509 return (0);
510
511 cuda_intr(dev);
512 return (0);
513 }
514
515 static void
cuda_intr(void * arg)516 cuda_intr(void *arg)
517 {
518 device_t dev;
519 struct cuda_softc *sc;
520 int ending, process_inbound;
521 uint8_t reg;
522
523 dev = (device_t)arg;
524 sc = device_get_softc(dev);
525
526 mtx_lock(&sc->sc_mutex);
527
528 process_inbound = 0;
529 reg = cuda_read_reg(sc, vIFR);
530 if ((reg & vSR_INT) != vSR_INT) {
531 mtx_unlock(&sc->sc_mutex);
532 return;
533 }
534
535 cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
536
537 switch_start:
538 switch (sc->sc_state) {
539 case CUDA_IDLE:
540 /*
541 * This is an unexpected packet, so grab the first (dummy)
542 * byte, set up the proper vars, and tell the chip we are
543 * starting to receive the packet by setting the TIP bit.
544 */
545 sc->sc_in[1] = cuda_read_reg(sc, vSR);
546
547 if (cuda_intr_state(sc) == 0) {
548 /* must have been a fake start */
549
550 if (sc->sc_waiting) {
551 /* start over */
552 DELAY(150);
553 sc->sc_state = CUDA_OUT;
554 sc->sc_sent = 0;
555 cuda_out(sc);
556 cuda_write_reg(sc, vSR, sc->sc_out[1]);
557 cuda_ack_off(sc);
558 cuda_tip(sc);
559 }
560 break;
561 }
562
563 cuda_in(sc);
564 cuda_tip(sc);
565
566 sc->sc_received = 1;
567 sc->sc_state = CUDA_IN;
568 break;
569
570 case CUDA_IN:
571 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
572 ending = 0;
573
574 if (sc->sc_received > 255) {
575 /* bitch only once */
576 if (sc->sc_received == 256) {
577 device_printf(dev,"input overflow\n");
578 ending = 1;
579 }
580 } else
581 sc->sc_received++;
582
583 /* intr off means this is the last byte (end of frame) */
584 if (cuda_intr_state(sc) == 0) {
585 ending = 1;
586 } else {
587 cuda_toggle_ack(sc);
588 }
589
590 if (ending == 1) { /* end of message? */
591 struct cuda_packet *pkt;
592
593 /* reset vars and signal the end of this frame */
594 cuda_idle(sc);
595
596 /* Queue up the packet */
597 pkt = STAILQ_FIRST(&sc->sc_freeq);
598 if (pkt != NULL) {
599 /* If we have a free packet, process it */
600
601 pkt->len = sc->sc_received - 2;
602 pkt->type = sc->sc_in[1];
603 memcpy(pkt->data, &sc->sc_in[2], pkt->len);
604
605 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
606 STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
607
608 process_inbound = 1;
609 }
610
611 sc->sc_state = CUDA_IDLE;
612 sc->sc_received = 0;
613
614 /*
615 * If there is something waiting to be sent out,
616 * set everything up and send the first byte.
617 */
618 if (sc->sc_waiting == 1) {
619 DELAY(1500); /* required */
620 sc->sc_sent = 0;
621 sc->sc_state = CUDA_OUT;
622
623 /*
624 * If the interrupt is on, we were too slow
625 * and the chip has already started to send
626 * something to us, so back out of the write
627 * and start a read cycle.
628 */
629 if (cuda_intr_state(sc)) {
630 cuda_in(sc);
631 cuda_idle(sc);
632 sc->sc_sent = 0;
633 sc->sc_state = CUDA_IDLE;
634 sc->sc_received = 0;
635 DELAY(150);
636 goto switch_start;
637 }
638
639 /*
640 * If we got here, it's ok to start sending
641 * so load the first byte and tell the chip
642 * we want to send.
643 */
644 cuda_out(sc);
645 cuda_write_reg(sc, vSR,
646 sc->sc_out[sc->sc_sent]);
647 cuda_ack_off(sc);
648 cuda_tip(sc);
649 }
650 }
651 break;
652
653 case CUDA_OUT:
654 cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
655
656 sc->sc_sent++;
657 if (cuda_intr_state(sc)) { /* ADB intr low during write */
658 cuda_in(sc); /* make sure SR is set to IN */
659 cuda_idle(sc);
660 sc->sc_sent = 0; /* must start all over */
661 sc->sc_state = CUDA_IDLE; /* new state */
662 sc->sc_received = 0;
663 sc->sc_waiting = 1; /* must retry when done with
664 * read */
665 DELAY(150);
666 goto switch_start; /* process next state right
667 * now */
668 break;
669 }
670 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
671 sc->sc_waiting = 0; /* done writing */
672 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
673 cuda_in(sc);
674 cuda_idle(sc);
675 } else {
676 /* send next byte */
677 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
678 cuda_toggle_ack(sc); /* signal byte ready to
679 * shift */
680 }
681 break;
682
683 case CUDA_NOTREADY:
684 break;
685
686 default:
687 break;
688 }
689
690 mtx_unlock(&sc->sc_mutex);
691
692 if (process_inbound)
693 cuda_send_inbound(sc);
694
695 mtx_lock(&sc->sc_mutex);
696 /* If we have another packet waiting, set it up */
697 if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
698 cuda_send_outbound(sc);
699
700 mtx_unlock(&sc->sc_mutex);
701
702 }
703
704 static u_int
cuda_adb_send(device_t dev,u_char command_byte,int len,u_char * data,u_char poll)705 cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
706 u_char poll)
707 {
708 struct cuda_softc *sc = device_get_softc(dev);
709 uint8_t packet[16];
710 int i;
711
712 /* construct an ADB command packet and send it */
713 packet[0] = CUDA_ADB;
714 packet[1] = command_byte;
715 for (i = 0; i < len; i++)
716 packet[i + 2] = data[i];
717
718 cuda_send(sc, poll, len + 2, packet);
719
720 return (0);
721 }
722
723 static u_int
cuda_adb_autopoll(device_t dev,uint16_t mask)724 cuda_adb_autopoll(device_t dev, uint16_t mask) {
725 struct cuda_softc *sc = device_get_softc(dev);
726
727 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
728
729 mtx_lock(&sc->sc_mutex);
730
731 if (cmd[2] == sc->sc_autopoll) {
732 mtx_unlock(&sc->sc_mutex);
733 return (0);
734 }
735
736 sc->sc_autopoll = -1;
737 cuda_send(sc, 1, 3, cmd);
738
739 mtx_unlock(&sc->sc_mutex);
740
741 return (0);
742 }
743
744 static void
cuda_shutdown(void * xsc,int howto)745 cuda_shutdown(void *xsc, int howto)
746 {
747 struct cuda_softc *sc = xsc;
748 uint8_t cmd[] = {CUDA_PSEUDO, 0};
749
750 if ((howto & RB_POWEROFF) != 0)
751 cmd[1] = CMD_POWEROFF;
752 else if ((howto & RB_HALT) == 0)
753 cmd[1] = CMD_RESET;
754 else
755 return;
756
757 cuda_poll(sc->sc_dev);
758 cuda_send(sc, 1, 2, cmd);
759
760 while (1)
761 cuda_poll(sc->sc_dev);
762 }
763
764 #define DIFF19041970 2082844800
765
766 static int
cuda_gettime(device_t dev,struct timespec * ts)767 cuda_gettime(device_t dev, struct timespec *ts)
768 {
769 struct cuda_softc *sc = device_get_softc(dev);
770 uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
771
772 mtx_lock(&sc->sc_mutex);
773 sc->sc_rtc = -1;
774 cuda_send(sc, 1, 2, cmd);
775 if (sc->sc_rtc == -1)
776 mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
777
778 ts->tv_sec = sc->sc_rtc - DIFF19041970;
779 ts->tv_nsec = 0;
780 mtx_unlock(&sc->sc_mutex);
781
782 return (0);
783 }
784
785 static int
cuda_settime(device_t dev,struct timespec * ts)786 cuda_settime(device_t dev, struct timespec *ts)
787 {
788 struct cuda_softc *sc = device_get_softc(dev);
789 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
790 uint32_t sec;
791
792 sec = ts->tv_sec + DIFF19041970;
793 memcpy(&cmd[2], &sec, sizeof(sec));
794
795 mtx_lock(&sc->sc_mutex);
796 cuda_send(sc, 0, 6, cmd);
797 mtx_unlock(&sc->sc_mutex);
798
799 return (0);
800 }
801