1b4dbc599SNathan Whitehorn /*-
271e3c308SPedro F. Giffuni * SPDX-License-Identifier: BSD-3-Clause
371e3c308SPedro F. Giffuni *
4b4dbc599SNathan Whitehorn * Copyright (c) 2006 Michael Lorenz
5b4dbc599SNathan Whitehorn * Copyright 2008 by Nathan Whitehorn
6b4dbc599SNathan Whitehorn * All rights reserved.
7b4dbc599SNathan Whitehorn *
8b4dbc599SNathan Whitehorn * Redistribution and use in source and binary forms, with or without
9b4dbc599SNathan Whitehorn * modification, are permitted provided that the following conditions
10b4dbc599SNathan Whitehorn * are met:
11b4dbc599SNathan Whitehorn * 1. Redistributions of source code must retain the above copyright
12b4dbc599SNathan Whitehorn * notice, this list of conditions and the following disclaimer.
13b4dbc599SNathan Whitehorn * 2. Redistributions in binary form must reproduce the above copyright
14b4dbc599SNathan Whitehorn * notice, this list of conditions and the following disclaimer in the
15b4dbc599SNathan Whitehorn * documentation and/or other materials provided with the distribution.
16b4dbc599SNathan Whitehorn * 3. The name of the author may not be used to endorse or promote products
17b4dbc599SNathan Whitehorn * derived from this software without specific prior written permission.
18b4dbc599SNathan Whitehorn *
19b4dbc599SNathan Whitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20b4dbc599SNathan Whitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21b4dbc599SNathan Whitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22b4dbc599SNathan Whitehorn * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23b4dbc599SNathan Whitehorn * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24b4dbc599SNathan Whitehorn * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25b4dbc599SNathan Whitehorn * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26b4dbc599SNathan Whitehorn * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27b4dbc599SNathan Whitehorn * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28b4dbc599SNathan Whitehorn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29b4dbc599SNathan Whitehorn * SUCH DAMAGE.
30b4dbc599SNathan Whitehorn *
31b4dbc599SNathan Whitehorn */
32b4dbc599SNathan Whitehorn
33b4dbc599SNathan Whitehorn #include <sys/param.h>
34b4dbc599SNathan Whitehorn #include <sys/systm.h>
35b4dbc599SNathan Whitehorn #include <sys/module.h>
36b4dbc599SNathan Whitehorn #include <sys/bus.h>
37b4dbc599SNathan Whitehorn #include <sys/conf.h>
38e2e050c8SConrad Meyer #include <sys/eventhandler.h>
39b4dbc599SNathan Whitehorn #include <sys/kernel.h>
40e2e050c8SConrad Meyer #include <sys/lock.h>
41e2e050c8SConrad Meyer #include <sys/mutex.h>
423df9e037SNathan Whitehorn #include <sys/clock.h>
43b2a237beSNathan Whitehorn #include <sys/reboot.h>
44b4dbc599SNathan Whitehorn
45b4dbc599SNathan Whitehorn #include <dev/ofw/ofw_bus.h>
46b4dbc599SNathan Whitehorn #include <dev/ofw/openfirm.h>
47b4dbc599SNathan Whitehorn
48b4dbc599SNathan Whitehorn #include <machine/bus.h>
49b4dbc599SNathan Whitehorn #include <machine/intr_machdep.h>
50b4dbc599SNathan Whitehorn #include <machine/md_var.h>
51b4dbc599SNathan Whitehorn #include <machine/pio.h>
52b4dbc599SNathan Whitehorn #include <machine/resource.h>
53b4dbc599SNathan Whitehorn
54b4dbc599SNathan Whitehorn #include <vm/vm.h>
55b4dbc599SNathan Whitehorn #include <vm/pmap.h>
56b4dbc599SNathan Whitehorn
57b4dbc599SNathan Whitehorn #include <sys/rman.h>
58b4dbc599SNathan Whitehorn
59b4dbc599SNathan Whitehorn #include <dev/adb/adb.h>
60b4dbc599SNathan Whitehorn
613df9e037SNathan Whitehorn #include "clock_if.h"
62b4dbc599SNathan Whitehorn #include "cudavar.h"
63b4dbc599SNathan Whitehorn #include "viareg.h"
64b4dbc599SNathan Whitehorn
65b4dbc599SNathan Whitehorn /*
66b4dbc599SNathan Whitehorn * MacIO interface
67b4dbc599SNathan Whitehorn */
68b4dbc599SNathan Whitehorn static int cuda_probe(device_t);
69b4dbc599SNathan Whitehorn static int cuda_attach(device_t);
70b4dbc599SNathan Whitehorn static int cuda_detach(device_t);
71b4dbc599SNathan Whitehorn
72b4dbc599SNathan Whitehorn static u_int cuda_adb_send(device_t dev, u_char command_byte, int len,
73b4dbc599SNathan Whitehorn u_char *data, u_char poll);
74b4dbc599SNathan Whitehorn static u_int cuda_adb_autopoll(device_t dev, uint16_t mask);
7565f44679SAndriy Gapon static u_int cuda_poll(device_t dev);
76582434bdSNathan Whitehorn static void cuda_send_inbound(struct cuda_softc *sc);
77582434bdSNathan Whitehorn static void cuda_send_outbound(struct cuda_softc *sc);
78b2a237beSNathan Whitehorn static void cuda_shutdown(void *xsc, int howto);
79b4dbc599SNathan Whitehorn
803df9e037SNathan Whitehorn /*
813df9e037SNathan Whitehorn * Clock interface
823df9e037SNathan Whitehorn */
833df9e037SNathan Whitehorn static int cuda_gettime(device_t dev, struct timespec *ts);
843df9e037SNathan Whitehorn static int cuda_settime(device_t dev, struct timespec *ts);
853df9e037SNathan Whitehorn
86b4dbc599SNathan Whitehorn static device_method_t cuda_methods[] = {
87b4dbc599SNathan Whitehorn /* Device interface */
88b4dbc599SNathan Whitehorn DEVMETHOD(device_probe, cuda_probe),
89b4dbc599SNathan Whitehorn DEVMETHOD(device_attach, cuda_attach),
90b4dbc599SNathan Whitehorn DEVMETHOD(device_detach, cuda_detach),
91b4dbc599SNathan Whitehorn DEVMETHOD(device_shutdown, bus_generic_shutdown),
92b4dbc599SNathan Whitehorn DEVMETHOD(device_suspend, bus_generic_suspend),
93b4dbc599SNathan Whitehorn DEVMETHOD(device_resume, bus_generic_resume),
94b4dbc599SNathan Whitehorn
95b4dbc599SNathan Whitehorn /* ADB bus interface */
96b4dbc599SNathan Whitehorn DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send),
97b4dbc599SNathan Whitehorn DEVMETHOD(adb_hb_controller_poll, cuda_poll),
98b4dbc599SNathan Whitehorn DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll),
99b4dbc599SNathan Whitehorn
1003df9e037SNathan Whitehorn /* Clock interface */
1013df9e037SNathan Whitehorn DEVMETHOD(clock_gettime, cuda_gettime),
1023df9e037SNathan Whitehorn DEVMETHOD(clock_settime, cuda_settime),
1033df9e037SNathan Whitehorn
1044b7ec270SMarius Strobl DEVMETHOD_END
105b4dbc599SNathan Whitehorn };
106b4dbc599SNathan Whitehorn
107b4dbc599SNathan Whitehorn static driver_t cuda_driver = {
108b4dbc599SNathan Whitehorn "cuda",
109b4dbc599SNathan Whitehorn cuda_methods,
110b4dbc599SNathan Whitehorn sizeof(struct cuda_softc),
111b4dbc599SNathan Whitehorn };
112b4dbc599SNathan Whitehorn
113992ae60bSJohn Baldwin DRIVER_MODULE(cuda, macio, cuda_driver, 0, 0);
11442f777fcSJohn Baldwin DRIVER_MODULE(adb, cuda, adb_driver, 0, 0);
115b4dbc599SNathan Whitehorn
116b4dbc599SNathan Whitehorn static void cuda_intr(void *arg);
117b4dbc599SNathan Whitehorn static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
118b4dbc599SNathan Whitehorn static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
119b4dbc599SNathan Whitehorn static void cuda_idle(struct cuda_softc *);
120b4dbc599SNathan Whitehorn static void cuda_tip(struct cuda_softc *);
121b4dbc599SNathan Whitehorn static void cuda_clear_tip(struct cuda_softc *);
122b4dbc599SNathan Whitehorn static void cuda_in(struct cuda_softc *);
123b4dbc599SNathan Whitehorn static void cuda_out(struct cuda_softc *);
124b4dbc599SNathan Whitehorn static void cuda_toggle_ack(struct cuda_softc *);
125b4dbc599SNathan Whitehorn static void cuda_ack_off(struct cuda_softc *);
126b4dbc599SNathan Whitehorn static int cuda_intr_state(struct cuda_softc *);
127b4dbc599SNathan Whitehorn
128b4dbc599SNathan Whitehorn static int
cuda_probe(device_t dev)129b4dbc599SNathan Whitehorn cuda_probe(device_t dev)
130b4dbc599SNathan Whitehorn {
131b4dbc599SNathan Whitehorn const char *type = ofw_bus_get_type(dev);
132b4dbc599SNathan Whitehorn
133b4dbc599SNathan Whitehorn if (strcmp(type, "via-cuda") != 0)
134b4dbc599SNathan Whitehorn return (ENXIO);
135b4dbc599SNathan Whitehorn
136b4dbc599SNathan Whitehorn device_set_desc(dev, CUDA_DEVSTR);
137b4dbc599SNathan Whitehorn return (0);
138b4dbc599SNathan Whitehorn }
139b4dbc599SNathan Whitehorn
140b4dbc599SNathan Whitehorn static int
cuda_attach(device_t dev)141b4dbc599SNathan Whitehorn cuda_attach(device_t dev)
142b4dbc599SNathan Whitehorn {
143b4dbc599SNathan Whitehorn struct cuda_softc *sc;
144b4dbc599SNathan Whitehorn
145b4dbc599SNathan Whitehorn volatile int i;
146b4dbc599SNathan Whitehorn uint8_t reg;
147b4dbc599SNathan Whitehorn phandle_t node,child;
148b4dbc599SNathan Whitehorn
149b4dbc599SNathan Whitehorn sc = device_get_softc(dev);
150b4dbc599SNathan Whitehorn sc->sc_dev = dev;
151b4dbc599SNathan Whitehorn
152b4dbc599SNathan Whitehorn sc->sc_memrid = 0;
153b4dbc599SNathan Whitehorn sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
154b4dbc599SNathan Whitehorn &sc->sc_memrid, RF_ACTIVE);
155b4dbc599SNathan Whitehorn
156b4dbc599SNathan Whitehorn if (sc->sc_memr == NULL) {
157b4dbc599SNathan Whitehorn device_printf(dev, "Could not alloc mem resource!\n");
158b4dbc599SNathan Whitehorn return (ENXIO);
159b4dbc599SNathan Whitehorn }
160b4dbc599SNathan Whitehorn
161b4dbc599SNathan Whitehorn sc->sc_irqrid = 0;
162b4dbc599SNathan Whitehorn sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
163b4dbc599SNathan Whitehorn RF_ACTIVE);
164b4dbc599SNathan Whitehorn if (sc->sc_irq == NULL) {
165b4dbc599SNathan Whitehorn device_printf(dev, "could not allocate interrupt\n");
166596e6adeSAlexander Motin bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
167596e6adeSAlexander Motin sc->sc_memr);
168b4dbc599SNathan Whitehorn return (ENXIO);
169b4dbc599SNathan Whitehorn }
170b4dbc599SNathan Whitehorn
171b4dbc599SNathan Whitehorn if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
172b4dbc599SNathan Whitehorn | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
173b4dbc599SNathan Whitehorn device_printf(dev, "could not setup interrupt\n");
174596e6adeSAlexander Motin bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
175596e6adeSAlexander Motin sc->sc_memr);
176b4dbc599SNathan Whitehorn bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
177b4dbc599SNathan Whitehorn sc->sc_irq);
178b4dbc599SNathan Whitehorn return (ENXIO);
179b4dbc599SNathan Whitehorn }
180b4dbc599SNathan Whitehorn
181b4dbc599SNathan Whitehorn mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
182b4dbc599SNathan Whitehorn
183b4dbc599SNathan Whitehorn sc->sc_sent = 0;
184b4dbc599SNathan Whitehorn sc->sc_received = 0;
185b4dbc599SNathan Whitehorn sc->sc_waiting = 0;
186b4dbc599SNathan Whitehorn sc->sc_polling = 0;
187b4dbc599SNathan Whitehorn sc->sc_state = CUDA_NOTREADY;
188b4dbc599SNathan Whitehorn sc->sc_autopoll = 0;
1893df9e037SNathan Whitehorn sc->sc_rtc = -1;
190b4dbc599SNathan Whitehorn
191582434bdSNathan Whitehorn STAILQ_INIT(&sc->sc_inq);
192582434bdSNathan Whitehorn STAILQ_INIT(&sc->sc_outq);
193011ad8e7SNathan Whitehorn STAILQ_INIT(&sc->sc_freeq);
194011ad8e7SNathan Whitehorn
195011ad8e7SNathan Whitehorn for (i = 0; i < CUDA_MAXPACKETS; i++)
196011ad8e7SNathan Whitehorn STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
197582434bdSNathan Whitehorn
198b4dbc599SNathan Whitehorn /* Init CUDA */
199b4dbc599SNathan Whitehorn
200b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vDirB);
201b4dbc599SNathan Whitehorn reg |= 0x30; /* register B bits 4 and 5: outputs */
202b4dbc599SNathan Whitehorn cuda_write_reg(sc, vDirB, reg);
203b4dbc599SNathan Whitehorn
204b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vDirB);
205b4dbc599SNathan Whitehorn reg &= 0xf7; /* register B bit 3: input */
206b4dbc599SNathan Whitehorn cuda_write_reg(sc, vDirB, reg);
207b4dbc599SNathan Whitehorn
208b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vACR);
209b4dbc599SNathan Whitehorn reg &= ~vSR_OUT; /* make sure SR is set to IN */
210b4dbc599SNathan Whitehorn cuda_write_reg(sc, vACR, reg);
211b4dbc599SNathan Whitehorn
212b4dbc599SNathan Whitehorn cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
213b4dbc599SNathan Whitehorn
214b4dbc599SNathan Whitehorn sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
215b4dbc599SNathan Whitehorn
216b4dbc599SNathan Whitehorn cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
217b4dbc599SNathan Whitehorn
218b4dbc599SNathan Whitehorn cuda_idle(sc); /* reset ADB */
219b4dbc599SNathan Whitehorn
220b4dbc599SNathan Whitehorn /* Reset CUDA */
221b4dbc599SNathan Whitehorn
222b4dbc599SNathan Whitehorn i = cuda_read_reg(sc, vSR); /* clear interrupt */
223b4dbc599SNathan Whitehorn cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
224b4dbc599SNathan Whitehorn cuda_idle(sc); /* reset state to idle */
225b4dbc599SNathan Whitehorn DELAY(150);
226b4dbc599SNathan Whitehorn cuda_tip(sc); /* signal start of frame */
227b4dbc599SNathan Whitehorn DELAY(150);
228b4dbc599SNathan Whitehorn cuda_toggle_ack(sc);
229b4dbc599SNathan Whitehorn DELAY(150);
230b4dbc599SNathan Whitehorn cuda_clear_tip(sc);
231b4dbc599SNathan Whitehorn DELAY(150);
232b4dbc599SNathan Whitehorn cuda_idle(sc); /* back to idle state */
233b4dbc599SNathan Whitehorn i = cuda_read_reg(sc, vSR); /* clear interrupt */
234b4dbc599SNathan Whitehorn cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
235b4dbc599SNathan Whitehorn
236b4dbc599SNathan Whitehorn /* Initialize child buses (ADB) */
237b4dbc599SNathan Whitehorn node = ofw_bus_get_node(dev);
238b4dbc599SNathan Whitehorn
239b4dbc599SNathan Whitehorn for (child = OF_child(node); child != 0; child = OF_peer(child)) {
240b4dbc599SNathan Whitehorn char name[32];
241b4dbc599SNathan Whitehorn
242b4dbc599SNathan Whitehorn memset(name, 0, sizeof(name));
243b4dbc599SNathan Whitehorn OF_getprop(child, "name", name, sizeof(name));
244b4dbc599SNathan Whitehorn
245b4dbc599SNathan Whitehorn if (bootverbose)
246b4dbc599SNathan Whitehorn device_printf(dev, "CUDA child <%s>\n",name);
247b4dbc599SNathan Whitehorn
248b4dbc599SNathan Whitehorn if (strncmp(name, "adb", 4) == 0) {
249b4dbc599SNathan Whitehorn sc->adb_bus = device_add_child(dev,"adb",-1);
250b4dbc599SNathan Whitehorn }
251b4dbc599SNathan Whitehorn }
252b4dbc599SNathan Whitehorn
2533df9e037SNathan Whitehorn clock_register(dev, 1000);
254b2a237beSNathan Whitehorn EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
255b2a237beSNathan Whitehorn SHUTDOWN_PRI_LAST);
2563df9e037SNathan Whitehorn
257b4dbc599SNathan Whitehorn return (bus_generic_attach(dev));
258b4dbc599SNathan Whitehorn }
259b4dbc599SNathan Whitehorn
cuda_detach(device_t dev)260b4dbc599SNathan Whitehorn static int cuda_detach(device_t dev) {
261b4dbc599SNathan Whitehorn struct cuda_softc *sc;
262b4dbc599SNathan Whitehorn
263b4dbc599SNathan Whitehorn sc = device_get_softc(dev);
264b4dbc599SNathan Whitehorn
265b4dbc599SNathan Whitehorn bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
266b4dbc599SNathan Whitehorn bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
267b4dbc599SNathan Whitehorn bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
268b4dbc599SNathan Whitehorn mtx_destroy(&sc->sc_mutex);
269b4dbc599SNathan Whitehorn
270b4dbc599SNathan Whitehorn return (bus_generic_detach(dev));
271b4dbc599SNathan Whitehorn }
272b4dbc599SNathan Whitehorn
273b4dbc599SNathan Whitehorn static uint8_t
cuda_read_reg(struct cuda_softc * sc,u_int offset)274b4dbc599SNathan Whitehorn cuda_read_reg(struct cuda_softc *sc, u_int offset) {
275b4dbc599SNathan Whitehorn return (bus_read_1(sc->sc_memr, offset));
276b4dbc599SNathan Whitehorn }
277b4dbc599SNathan Whitehorn
278b4dbc599SNathan Whitehorn static void
cuda_write_reg(struct cuda_softc * sc,u_int offset,uint8_t value)279b4dbc599SNathan Whitehorn cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
280b4dbc599SNathan Whitehorn bus_write_1(sc->sc_memr, offset, value);
281b4dbc599SNathan Whitehorn }
282b4dbc599SNathan Whitehorn
283b4dbc599SNathan Whitehorn static void
cuda_idle(struct cuda_softc * sc)284b4dbc599SNathan Whitehorn cuda_idle(struct cuda_softc *sc)
285b4dbc599SNathan Whitehorn {
286b4dbc599SNathan Whitehorn uint8_t reg;
287b4dbc599SNathan Whitehorn
288b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vBufB);
289b4dbc599SNathan Whitehorn reg |= (vPB4 | vPB5);
290b4dbc599SNathan Whitehorn cuda_write_reg(sc, vBufB, reg);
291b4dbc599SNathan Whitehorn }
292b4dbc599SNathan Whitehorn
293b4dbc599SNathan Whitehorn static void
cuda_tip(struct cuda_softc * sc)294b4dbc599SNathan Whitehorn cuda_tip(struct cuda_softc *sc)
295b4dbc599SNathan Whitehorn {
296b4dbc599SNathan Whitehorn uint8_t reg;
297b4dbc599SNathan Whitehorn
298b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vBufB);
299b4dbc599SNathan Whitehorn reg &= ~vPB5;
300b4dbc599SNathan Whitehorn cuda_write_reg(sc, vBufB, reg);
301b4dbc599SNathan Whitehorn }
302b4dbc599SNathan Whitehorn
303b4dbc599SNathan Whitehorn static void
cuda_clear_tip(struct cuda_softc * sc)304b4dbc599SNathan Whitehorn cuda_clear_tip(struct cuda_softc *sc)
305b4dbc599SNathan Whitehorn {
306b4dbc599SNathan Whitehorn uint8_t reg;
307b4dbc599SNathan Whitehorn
308b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vBufB);
309b4dbc599SNathan Whitehorn reg |= vPB5;
310b4dbc599SNathan Whitehorn cuda_write_reg(sc, vBufB, reg);
311b4dbc599SNathan Whitehorn }
312b4dbc599SNathan Whitehorn
313b4dbc599SNathan Whitehorn static void
cuda_in(struct cuda_softc * sc)314b4dbc599SNathan Whitehorn cuda_in(struct cuda_softc *sc)
315b4dbc599SNathan Whitehorn {
316b4dbc599SNathan Whitehorn uint8_t reg;
317b4dbc599SNathan Whitehorn
318b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vACR);
319b4dbc599SNathan Whitehorn reg &= ~vSR_OUT;
320b4dbc599SNathan Whitehorn cuda_write_reg(sc, vACR, reg);
321b4dbc599SNathan Whitehorn }
322b4dbc599SNathan Whitehorn
323b4dbc599SNathan Whitehorn static void
cuda_out(struct cuda_softc * sc)324b4dbc599SNathan Whitehorn cuda_out(struct cuda_softc *sc)
325b4dbc599SNathan Whitehorn {
326b4dbc599SNathan Whitehorn uint8_t reg;
327b4dbc599SNathan Whitehorn
328b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vACR);
329b4dbc599SNathan Whitehorn reg |= vSR_OUT;
330b4dbc599SNathan Whitehorn cuda_write_reg(sc, vACR, reg);
331b4dbc599SNathan Whitehorn }
332b4dbc599SNathan Whitehorn
333b4dbc599SNathan Whitehorn static void
cuda_toggle_ack(struct cuda_softc * sc)334b4dbc599SNathan Whitehorn cuda_toggle_ack(struct cuda_softc *sc)
335b4dbc599SNathan Whitehorn {
336b4dbc599SNathan Whitehorn uint8_t reg;
337b4dbc599SNathan Whitehorn
338b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vBufB);
339b4dbc599SNathan Whitehorn reg ^= vPB4;
340b4dbc599SNathan Whitehorn cuda_write_reg(sc, vBufB, reg);
341b4dbc599SNathan Whitehorn }
342b4dbc599SNathan Whitehorn
343b4dbc599SNathan Whitehorn static void
cuda_ack_off(struct cuda_softc * sc)344b4dbc599SNathan Whitehorn cuda_ack_off(struct cuda_softc *sc)
345b4dbc599SNathan Whitehorn {
346b4dbc599SNathan Whitehorn uint8_t reg;
347b4dbc599SNathan Whitehorn
348b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vBufB);
349b4dbc599SNathan Whitehorn reg |= vPB4;
350b4dbc599SNathan Whitehorn cuda_write_reg(sc, vBufB, reg);
351b4dbc599SNathan Whitehorn }
352b4dbc599SNathan Whitehorn
353b4dbc599SNathan Whitehorn static int
cuda_intr_state(struct cuda_softc * sc)354b4dbc599SNathan Whitehorn cuda_intr_state(struct cuda_softc *sc)
355b4dbc599SNathan Whitehorn {
356b4dbc599SNathan Whitehorn return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
357b4dbc599SNathan Whitehorn }
358b4dbc599SNathan Whitehorn
359b4dbc599SNathan Whitehorn static int
cuda_send(void * cookie,int poll,int length,uint8_t * msg)360b4dbc599SNathan Whitehorn cuda_send(void *cookie, int poll, int length, uint8_t *msg)
361b4dbc599SNathan Whitehorn {
362b4dbc599SNathan Whitehorn struct cuda_softc *sc = cookie;
363b4dbc599SNathan Whitehorn device_t dev = sc->sc_dev;
364582434bdSNathan Whitehorn struct cuda_packet *pkt;
365b4dbc599SNathan Whitehorn
366b4dbc599SNathan Whitehorn if (sc->sc_state == CUDA_NOTREADY)
367582434bdSNathan Whitehorn return (-1);
368b4dbc599SNathan Whitehorn
369b4dbc599SNathan Whitehorn mtx_lock(&sc->sc_mutex);
370b4dbc599SNathan Whitehorn
371011ad8e7SNathan Whitehorn pkt = STAILQ_FIRST(&sc->sc_freeq);
372011ad8e7SNathan Whitehorn if (pkt == NULL) {
373011ad8e7SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
374011ad8e7SNathan Whitehorn return (-1);
375011ad8e7SNathan Whitehorn }
376011ad8e7SNathan Whitehorn
377582434bdSNathan Whitehorn pkt->len = length - 1;
378582434bdSNathan Whitehorn pkt->type = msg[0];
379582434bdSNathan Whitehorn memcpy(pkt->data, &msg[1], pkt->len);
380582434bdSNathan Whitehorn
381011ad8e7SNathan Whitehorn STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
382582434bdSNathan Whitehorn STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
383582434bdSNathan Whitehorn
384582434bdSNathan Whitehorn /*
385582434bdSNathan Whitehorn * If we already are sending a packet, we should bail now that this
386582434bdSNathan Whitehorn * one has been added to the queue.
387582434bdSNathan Whitehorn */
388582434bdSNathan Whitehorn
389582434bdSNathan Whitehorn if (sc->sc_waiting) {
390b4dbc599SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
391582434bdSNathan Whitehorn return (0);
392b4dbc599SNathan Whitehorn }
393b4dbc599SNathan Whitehorn
394582434bdSNathan Whitehorn cuda_send_outbound(sc);
395582434bdSNathan Whitehorn mtx_unlock(&sc->sc_mutex);
396582434bdSNathan Whitehorn
397582434bdSNathan Whitehorn if (sc->sc_polling || poll || cold)
398582434bdSNathan Whitehorn cuda_poll(dev);
399582434bdSNathan Whitehorn
400582434bdSNathan Whitehorn return (0);
401582434bdSNathan Whitehorn }
402582434bdSNathan Whitehorn
403582434bdSNathan Whitehorn static void
cuda_send_outbound(struct cuda_softc * sc)404582434bdSNathan Whitehorn cuda_send_outbound(struct cuda_softc *sc)
405582434bdSNathan Whitehorn {
406582434bdSNathan Whitehorn struct cuda_packet *pkt;
407582434bdSNathan Whitehorn
408582434bdSNathan Whitehorn mtx_assert(&sc->sc_mutex, MA_OWNED);
409582434bdSNathan Whitehorn
410582434bdSNathan Whitehorn pkt = STAILQ_FIRST(&sc->sc_outq);
411582434bdSNathan Whitehorn if (pkt == NULL)
412582434bdSNathan Whitehorn return;
413582434bdSNathan Whitehorn
414582434bdSNathan Whitehorn sc->sc_out_length = pkt->len + 1;
415582434bdSNathan Whitehorn memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
416b4dbc599SNathan Whitehorn sc->sc_sent = 0;
417b4dbc599SNathan Whitehorn
418582434bdSNathan Whitehorn STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
419011ad8e7SNathan Whitehorn STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
420582434bdSNathan Whitehorn
421582434bdSNathan Whitehorn sc->sc_waiting = 1;
422582434bdSNathan Whitehorn
423582434bdSNathan Whitehorn cuda_poll(sc->sc_dev);
424582434bdSNathan Whitehorn
425b4dbc599SNathan Whitehorn DELAY(150);
426582434bdSNathan Whitehorn
427582434bdSNathan Whitehorn if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
428b4dbc599SNathan Whitehorn sc->sc_state = CUDA_OUT;
429b4dbc599SNathan Whitehorn cuda_out(sc);
430b4dbc599SNathan Whitehorn cuda_write_reg(sc, vSR, sc->sc_out[0]);
431b4dbc599SNathan Whitehorn cuda_ack_off(sc);
432b4dbc599SNathan Whitehorn cuda_tip(sc);
433b4dbc599SNathan Whitehorn }
434b4dbc599SNathan Whitehorn }
435b4dbc599SNathan Whitehorn
436582434bdSNathan Whitehorn static void
cuda_send_inbound(struct cuda_softc * sc)437582434bdSNathan Whitehorn cuda_send_inbound(struct cuda_softc *sc)
438582434bdSNathan Whitehorn {
439582434bdSNathan Whitehorn device_t dev;
440582434bdSNathan Whitehorn struct cuda_packet *pkt;
441582434bdSNathan Whitehorn
442582434bdSNathan Whitehorn dev = sc->sc_dev;
443582434bdSNathan Whitehorn
444582434bdSNathan Whitehorn mtx_lock(&sc->sc_mutex);
445582434bdSNathan Whitehorn
446582434bdSNathan Whitehorn while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
447582434bdSNathan Whitehorn STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
448582434bdSNathan Whitehorn
449582434bdSNathan Whitehorn mtx_unlock(&sc->sc_mutex);
450582434bdSNathan Whitehorn
451582434bdSNathan Whitehorn /* check if we have a handler for this message */
452582434bdSNathan Whitehorn switch (pkt->type) {
453582434bdSNathan Whitehorn case CUDA_ADB:
454582434bdSNathan Whitehorn if (pkt->len > 2) {
455582434bdSNathan Whitehorn adb_receive_raw_packet(sc->adb_bus,
456582434bdSNathan Whitehorn pkt->data[0],pkt->data[1],
457582434bdSNathan Whitehorn pkt->len - 2,&pkt->data[2]);
458582434bdSNathan Whitehorn } else {
459582434bdSNathan Whitehorn adb_receive_raw_packet(sc->adb_bus,
460582434bdSNathan Whitehorn pkt->data[0],pkt->data[1],0,NULL);
461582434bdSNathan Whitehorn }
462582434bdSNathan Whitehorn break;
463582434bdSNathan Whitehorn case CUDA_PSEUDO:
464582434bdSNathan Whitehorn mtx_lock(&sc->sc_mutex);
4653df9e037SNathan Whitehorn switch (pkt->data[1]) {
4663df9e037SNathan Whitehorn case CMD_AUTOPOLL:
467582434bdSNathan Whitehorn sc->sc_autopoll = 1;
4683df9e037SNathan Whitehorn break;
4693df9e037SNathan Whitehorn case CMD_READ_RTC:
4703df9e037SNathan Whitehorn memcpy(&sc->sc_rtc, &pkt->data[2],
4713df9e037SNathan Whitehorn sizeof(sc->sc_rtc));
4723df9e037SNathan Whitehorn wakeup(&sc->sc_rtc);
4733df9e037SNathan Whitehorn break;
4743df9e037SNathan Whitehorn case CMD_WRITE_RTC:
4753df9e037SNathan Whitehorn break;
4763df9e037SNathan Whitehorn }
477582434bdSNathan Whitehorn mtx_unlock(&sc->sc_mutex);
478582434bdSNathan Whitehorn break;
479582434bdSNathan Whitehorn case CUDA_ERROR:
480582434bdSNathan Whitehorn /*
481582434bdSNathan Whitehorn * CUDA will throw errors if we miss a race between
482582434bdSNathan Whitehorn * sending and receiving packets. This is already
483582434bdSNathan Whitehorn * handled when we abort packet output to handle
484582434bdSNathan Whitehorn * this packet in cuda_intr(). Thus, we ignore
485582434bdSNathan Whitehorn * these messages.
486582434bdSNathan Whitehorn */
487582434bdSNathan Whitehorn break;
488582434bdSNathan Whitehorn default:
489582434bdSNathan Whitehorn device_printf(dev,"unknown CUDA command %d\n",
490582434bdSNathan Whitehorn pkt->type);
491582434bdSNathan Whitehorn break;
492582434bdSNathan Whitehorn }
493582434bdSNathan Whitehorn
494582434bdSNathan Whitehorn mtx_lock(&sc->sc_mutex);
495011ad8e7SNathan Whitehorn
496011ad8e7SNathan Whitehorn STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
497582434bdSNathan Whitehorn }
498582434bdSNathan Whitehorn
499582434bdSNathan Whitehorn mtx_unlock(&sc->sc_mutex);
500b4dbc599SNathan Whitehorn }
501b4dbc599SNathan Whitehorn
50265f44679SAndriy Gapon static u_int
cuda_poll(device_t dev)503b4dbc599SNathan Whitehorn cuda_poll(device_t dev)
504b4dbc599SNathan Whitehorn {
505b4dbc599SNathan Whitehorn struct cuda_softc *sc = device_get_softc(dev);
506b4dbc599SNathan Whitehorn
50701418697SNathan Whitehorn if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
50801418697SNathan Whitehorn !sc->sc_waiting)
50965f44679SAndriy Gapon return (0);
51001418697SNathan Whitehorn
511b4dbc599SNathan Whitehorn cuda_intr(dev);
51265f44679SAndriy Gapon return (0);
513b4dbc599SNathan Whitehorn }
514b4dbc599SNathan Whitehorn
515b4dbc599SNathan Whitehorn static void
cuda_intr(void * arg)516b4dbc599SNathan Whitehorn cuda_intr(void *arg)
517b4dbc599SNathan Whitehorn {
518b4dbc599SNathan Whitehorn device_t dev;
519b4dbc599SNathan Whitehorn struct cuda_softc *sc;
5209c861e93SJohn Baldwin int ending, process_inbound;
521b4dbc599SNathan Whitehorn uint8_t reg;
522b4dbc599SNathan Whitehorn
523b4dbc599SNathan Whitehorn dev = (device_t)arg;
524b4dbc599SNathan Whitehorn sc = device_get_softc(dev);
525b4dbc599SNathan Whitehorn
526b4dbc599SNathan Whitehorn mtx_lock(&sc->sc_mutex);
527b4dbc599SNathan Whitehorn
528582434bdSNathan Whitehorn process_inbound = 0;
529b4dbc599SNathan Whitehorn reg = cuda_read_reg(sc, vIFR);
530582434bdSNathan Whitehorn if ((reg & vSR_INT) != vSR_INT) {
531582434bdSNathan Whitehorn mtx_unlock(&sc->sc_mutex);
532582434bdSNathan Whitehorn return;
533582434bdSNathan Whitehorn }
534582434bdSNathan Whitehorn
535b4dbc599SNathan Whitehorn cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
536b4dbc599SNathan Whitehorn
537b4dbc599SNathan Whitehorn switch_start:
538b4dbc599SNathan Whitehorn switch (sc->sc_state) {
539b4dbc599SNathan Whitehorn case CUDA_IDLE:
540b4dbc599SNathan Whitehorn /*
541b4dbc599SNathan Whitehorn * This is an unexpected packet, so grab the first (dummy)
542b4dbc599SNathan Whitehorn * byte, set up the proper vars, and tell the chip we are
543b4dbc599SNathan Whitehorn * starting to receive the packet by setting the TIP bit.
544b4dbc599SNathan Whitehorn */
545b4dbc599SNathan Whitehorn sc->sc_in[1] = cuda_read_reg(sc, vSR);
546b4dbc599SNathan Whitehorn
547b4dbc599SNathan Whitehorn if (cuda_intr_state(sc) == 0) {
548b4dbc599SNathan Whitehorn /* must have been a fake start */
549b4dbc599SNathan Whitehorn
550b4dbc599SNathan Whitehorn if (sc->sc_waiting) {
551b4dbc599SNathan Whitehorn /* start over */
552b4dbc599SNathan Whitehorn DELAY(150);
553b4dbc599SNathan Whitehorn sc->sc_state = CUDA_OUT;
554b4dbc599SNathan Whitehorn sc->sc_sent = 0;
555b4dbc599SNathan Whitehorn cuda_out(sc);
556b4dbc599SNathan Whitehorn cuda_write_reg(sc, vSR, sc->sc_out[1]);
557b4dbc599SNathan Whitehorn cuda_ack_off(sc);
558b4dbc599SNathan Whitehorn cuda_tip(sc);
559b4dbc599SNathan Whitehorn }
560b4dbc599SNathan Whitehorn break;
561b4dbc599SNathan Whitehorn }
562b4dbc599SNathan Whitehorn
563b4dbc599SNathan Whitehorn cuda_in(sc);
564b4dbc599SNathan Whitehorn cuda_tip(sc);
565b4dbc599SNathan Whitehorn
566b4dbc599SNathan Whitehorn sc->sc_received = 1;
567b4dbc599SNathan Whitehorn sc->sc_state = CUDA_IN;
568b4dbc599SNathan Whitehorn break;
569b4dbc599SNathan Whitehorn
570b4dbc599SNathan Whitehorn case CUDA_IN:
571b4dbc599SNathan Whitehorn sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
572b4dbc599SNathan Whitehorn ending = 0;
573b4dbc599SNathan Whitehorn
574b4dbc599SNathan Whitehorn if (sc->sc_received > 255) {
575b4dbc599SNathan Whitehorn /* bitch only once */
576b4dbc599SNathan Whitehorn if (sc->sc_received == 256) {
577b4dbc599SNathan Whitehorn device_printf(dev,"input overflow\n");
578b4dbc599SNathan Whitehorn ending = 1;
579b4dbc599SNathan Whitehorn }
580b4dbc599SNathan Whitehorn } else
581b4dbc599SNathan Whitehorn sc->sc_received++;
582b4dbc599SNathan Whitehorn
583b4dbc599SNathan Whitehorn /* intr off means this is the last byte (end of frame) */
584b4dbc599SNathan Whitehorn if (cuda_intr_state(sc) == 0) {
585b4dbc599SNathan Whitehorn ending = 1;
586b4dbc599SNathan Whitehorn } else {
587b4dbc599SNathan Whitehorn cuda_toggle_ack(sc);
588b4dbc599SNathan Whitehorn }
589b4dbc599SNathan Whitehorn
590b4dbc599SNathan Whitehorn if (ending == 1) { /* end of message? */
591582434bdSNathan Whitehorn struct cuda_packet *pkt;
592b4dbc599SNathan Whitehorn
593b4dbc599SNathan Whitehorn /* reset vars and signal the end of this frame */
594b4dbc599SNathan Whitehorn cuda_idle(sc);
595b4dbc599SNathan Whitehorn
596582434bdSNathan Whitehorn /* Queue up the packet */
597011ad8e7SNathan Whitehorn pkt = STAILQ_FIRST(&sc->sc_freeq);
598011ad8e7SNathan Whitehorn if (pkt != NULL) {
599011ad8e7SNathan Whitehorn /* If we have a free packet, process it */
600b4dbc599SNathan Whitehorn
601582434bdSNathan Whitehorn pkt->len = sc->sc_received - 2;
602582434bdSNathan Whitehorn pkt->type = sc->sc_in[1];
603582434bdSNathan Whitehorn memcpy(pkt->data, &sc->sc_in[2], pkt->len);
604582434bdSNathan Whitehorn
605011ad8e7SNathan Whitehorn STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
606582434bdSNathan Whitehorn STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
607b4dbc599SNathan Whitehorn
608011ad8e7SNathan Whitehorn process_inbound = 1;
609011ad8e7SNathan Whitehorn }
610011ad8e7SNathan Whitehorn
611b4dbc599SNathan Whitehorn sc->sc_state = CUDA_IDLE;
612b4dbc599SNathan Whitehorn sc->sc_received = 0;
613b4dbc599SNathan Whitehorn
614b4dbc599SNathan Whitehorn /*
615b4dbc599SNathan Whitehorn * If there is something waiting to be sent out,
616b4dbc599SNathan Whitehorn * set everything up and send the first byte.
617b4dbc599SNathan Whitehorn */
618b4dbc599SNathan Whitehorn if (sc->sc_waiting == 1) {
619b4dbc599SNathan Whitehorn DELAY(1500); /* required */
620b4dbc599SNathan Whitehorn sc->sc_sent = 0;
621b4dbc599SNathan Whitehorn sc->sc_state = CUDA_OUT;
622b4dbc599SNathan Whitehorn
623b4dbc599SNathan Whitehorn /*
624b4dbc599SNathan Whitehorn * If the interrupt is on, we were too slow
625b4dbc599SNathan Whitehorn * and the chip has already started to send
626b4dbc599SNathan Whitehorn * something to us, so back out of the write
627b4dbc599SNathan Whitehorn * and start a read cycle.
628b4dbc599SNathan Whitehorn */
629b4dbc599SNathan Whitehorn if (cuda_intr_state(sc)) {
630b4dbc599SNathan Whitehorn cuda_in(sc);
631b4dbc599SNathan Whitehorn cuda_idle(sc);
632b4dbc599SNathan Whitehorn sc->sc_sent = 0;
633b4dbc599SNathan Whitehorn sc->sc_state = CUDA_IDLE;
634b4dbc599SNathan Whitehorn sc->sc_received = 0;
635b4dbc599SNathan Whitehorn DELAY(150);
636b4dbc599SNathan Whitehorn goto switch_start;
637b4dbc599SNathan Whitehorn }
638582434bdSNathan Whitehorn
639b4dbc599SNathan Whitehorn /*
640b4dbc599SNathan Whitehorn * If we got here, it's ok to start sending
641b4dbc599SNathan Whitehorn * so load the first byte and tell the chip
642b4dbc599SNathan Whitehorn * we want to send.
643b4dbc599SNathan Whitehorn */
644b4dbc599SNathan Whitehorn cuda_out(sc);
645b4dbc599SNathan Whitehorn cuda_write_reg(sc, vSR,
646b4dbc599SNathan Whitehorn sc->sc_out[sc->sc_sent]);
647b4dbc599SNathan Whitehorn cuda_ack_off(sc);
648b4dbc599SNathan Whitehorn cuda_tip(sc);
649b4dbc599SNathan Whitehorn }
650b4dbc599SNathan Whitehorn }
651b4dbc599SNathan Whitehorn break;
652b4dbc599SNathan Whitehorn
653b4dbc599SNathan Whitehorn case CUDA_OUT:
6549c861e93SJohn Baldwin cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
655b4dbc599SNathan Whitehorn
656b4dbc599SNathan Whitehorn sc->sc_sent++;
657b4dbc599SNathan Whitehorn if (cuda_intr_state(sc)) { /* ADB intr low during write */
658b4dbc599SNathan Whitehorn cuda_in(sc); /* make sure SR is set to IN */
659b4dbc599SNathan Whitehorn cuda_idle(sc);
660b4dbc599SNathan Whitehorn sc->sc_sent = 0; /* must start all over */
661b4dbc599SNathan Whitehorn sc->sc_state = CUDA_IDLE; /* new state */
662b4dbc599SNathan Whitehorn sc->sc_received = 0;
663b4dbc599SNathan Whitehorn sc->sc_waiting = 1; /* must retry when done with
664b4dbc599SNathan Whitehorn * read */
665b4dbc599SNathan Whitehorn DELAY(150);
666b4dbc599SNathan Whitehorn goto switch_start; /* process next state right
667b4dbc599SNathan Whitehorn * now */
668b4dbc599SNathan Whitehorn break;
669b4dbc599SNathan Whitehorn }
670b4dbc599SNathan Whitehorn if (sc->sc_out_length == sc->sc_sent) { /* check for done */
671b4dbc599SNathan Whitehorn sc->sc_waiting = 0; /* done writing */
672b4dbc599SNathan Whitehorn sc->sc_state = CUDA_IDLE; /* signal bus is idle */
673b4dbc599SNathan Whitehorn cuda_in(sc);
674b4dbc599SNathan Whitehorn cuda_idle(sc);
675b4dbc599SNathan Whitehorn } else {
676b4dbc599SNathan Whitehorn /* send next byte */
677b4dbc599SNathan Whitehorn cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
678b4dbc599SNathan Whitehorn cuda_toggle_ack(sc); /* signal byte ready to
679b4dbc599SNathan Whitehorn * shift */
680b4dbc599SNathan Whitehorn }
681b4dbc599SNathan Whitehorn break;
682b4dbc599SNathan Whitehorn
683b4dbc599SNathan Whitehorn case CUDA_NOTREADY:
684b4dbc599SNathan Whitehorn break;
685b4dbc599SNathan Whitehorn
686b4dbc599SNathan Whitehorn default:
687b4dbc599SNathan Whitehorn break;
688b4dbc599SNathan Whitehorn }
689b4dbc599SNathan Whitehorn
690b4dbc599SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
691582434bdSNathan Whitehorn
692582434bdSNathan Whitehorn if (process_inbound)
693582434bdSNathan Whitehorn cuda_send_inbound(sc);
694582434bdSNathan Whitehorn
695582434bdSNathan Whitehorn mtx_lock(&sc->sc_mutex);
696582434bdSNathan Whitehorn /* If we have another packet waiting, set it up */
697582434bdSNathan Whitehorn if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
698582434bdSNathan Whitehorn cuda_send_outbound(sc);
699582434bdSNathan Whitehorn
700582434bdSNathan Whitehorn mtx_unlock(&sc->sc_mutex);
701582434bdSNathan Whitehorn
702b4dbc599SNathan Whitehorn }
703b4dbc599SNathan Whitehorn
704b4dbc599SNathan Whitehorn static u_int
cuda_adb_send(device_t dev,u_char command_byte,int len,u_char * data,u_char poll)705582434bdSNathan Whitehorn cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
706582434bdSNathan Whitehorn u_char poll)
707b4dbc599SNathan Whitehorn {
708b4dbc599SNathan Whitehorn struct cuda_softc *sc = device_get_softc(dev);
709b4dbc599SNathan Whitehorn uint8_t packet[16];
710582434bdSNathan Whitehorn int i;
711b4dbc599SNathan Whitehorn
712b4dbc599SNathan Whitehorn /* construct an ADB command packet and send it */
713b4dbc599SNathan Whitehorn packet[0] = CUDA_ADB;
714b4dbc599SNathan Whitehorn packet[1] = command_byte;
715b4dbc599SNathan Whitehorn for (i = 0; i < len; i++)
716b4dbc599SNathan Whitehorn packet[i + 2] = data[i];
717b4dbc599SNathan Whitehorn
718b4dbc599SNathan Whitehorn cuda_send(sc, poll, len + 2, packet);
719b4dbc599SNathan Whitehorn
720582434bdSNathan Whitehorn return (0);
721b4dbc599SNathan Whitehorn }
722b4dbc599SNathan Whitehorn
723b4dbc599SNathan Whitehorn static u_int
cuda_adb_autopoll(device_t dev,uint16_t mask)724b4dbc599SNathan Whitehorn cuda_adb_autopoll(device_t dev, uint16_t mask) {
725b4dbc599SNathan Whitehorn struct cuda_softc *sc = device_get_softc(dev);
726b4dbc599SNathan Whitehorn
727b4dbc599SNathan Whitehorn uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
728b4dbc599SNathan Whitehorn
729b4dbc599SNathan Whitehorn mtx_lock(&sc->sc_mutex);
73001418697SNathan Whitehorn
731b4dbc599SNathan Whitehorn if (cmd[2] == sc->sc_autopoll) {
732b4dbc599SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
733582434bdSNathan Whitehorn return (0);
734b4dbc599SNathan Whitehorn }
735b4dbc599SNathan Whitehorn
736b4dbc599SNathan Whitehorn sc->sc_autopoll = -1;
737582434bdSNathan Whitehorn cuda_send(sc, 1, 3, cmd);
738b4dbc599SNathan Whitehorn
739b4dbc599SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
740b4dbc599SNathan Whitehorn
741582434bdSNathan Whitehorn return (0);
742b4dbc599SNathan Whitehorn }
743b4dbc599SNathan Whitehorn
744b2a237beSNathan Whitehorn static void
cuda_shutdown(void * xsc,int howto)745b2a237beSNathan Whitehorn cuda_shutdown(void *xsc, int howto)
746b2a237beSNathan Whitehorn {
747b2a237beSNathan Whitehorn struct cuda_softc *sc = xsc;
748b2a237beSNathan Whitehorn uint8_t cmd[] = {CUDA_PSEUDO, 0};
749b2a237beSNathan Whitehorn
750*41e26e82SMitchell Horne if ((howto & RB_POWEROFF) != 0)
751*41e26e82SMitchell Horne cmd[1] = CMD_POWEROFF;
752*41e26e82SMitchell Horne else if ((howto & RB_HALT) == 0)
753*41e26e82SMitchell Horne cmd[1] = CMD_RESET;
754*41e26e82SMitchell Horne else
755*41e26e82SMitchell Horne return;
756*41e26e82SMitchell Horne
757b2a237beSNathan Whitehorn cuda_poll(sc->sc_dev);
758b2a237beSNathan Whitehorn cuda_send(sc, 1, 2, cmd);
759b2a237beSNathan Whitehorn
760b2a237beSNathan Whitehorn while (1)
761b2a237beSNathan Whitehorn cuda_poll(sc->sc_dev);
762b2a237beSNathan Whitehorn }
763b2a237beSNathan Whitehorn
7643df9e037SNathan Whitehorn #define DIFF19041970 2082844800
7653df9e037SNathan Whitehorn
7663df9e037SNathan Whitehorn static int
cuda_gettime(device_t dev,struct timespec * ts)7673df9e037SNathan Whitehorn cuda_gettime(device_t dev, struct timespec *ts)
7683df9e037SNathan Whitehorn {
7693df9e037SNathan Whitehorn struct cuda_softc *sc = device_get_softc(dev);
7703df9e037SNathan Whitehorn uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
7713df9e037SNathan Whitehorn
7723df9e037SNathan Whitehorn mtx_lock(&sc->sc_mutex);
7733df9e037SNathan Whitehorn sc->sc_rtc = -1;
7743df9e037SNathan Whitehorn cuda_send(sc, 1, 2, cmd);
7753df9e037SNathan Whitehorn if (sc->sc_rtc == -1)
7763df9e037SNathan Whitehorn mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
7773df9e037SNathan Whitehorn
7783df9e037SNathan Whitehorn ts->tv_sec = sc->sc_rtc - DIFF19041970;
7793df9e037SNathan Whitehorn ts->tv_nsec = 0;
7803df9e037SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
7813df9e037SNathan Whitehorn
7823df9e037SNathan Whitehorn return (0);
7833df9e037SNathan Whitehorn }
7843df9e037SNathan Whitehorn
7853df9e037SNathan Whitehorn static int
cuda_settime(device_t dev,struct timespec * ts)7863df9e037SNathan Whitehorn cuda_settime(device_t dev, struct timespec *ts)
7873df9e037SNathan Whitehorn {
7883df9e037SNathan Whitehorn struct cuda_softc *sc = device_get_softc(dev);
7893df9e037SNathan Whitehorn uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
7903df9e037SNathan Whitehorn uint32_t sec;
7913df9e037SNathan Whitehorn
7923df9e037SNathan Whitehorn sec = ts->tv_sec + DIFF19041970;
7933df9e037SNathan Whitehorn memcpy(&cmd[2], &sec, sizeof(sec));
7943df9e037SNathan Whitehorn
7953df9e037SNathan Whitehorn mtx_lock(&sc->sc_mutex);
7963df9e037SNathan Whitehorn cuda_send(sc, 0, 6, cmd);
7973df9e037SNathan Whitehorn mtx_unlock(&sc->sc_mutex);
7983df9e037SNathan Whitehorn
7993df9e037SNathan Whitehorn return (0);
8003df9e037SNathan Whitehorn }
801