1dd7d207dSJung-uk Kim /*- 2dd7d207dSJung-uk Kim * Copyright (c) 1998-2003 Poul-Henning Kamp 3dd7d207dSJung-uk Kim * All rights reserved. 4dd7d207dSJung-uk Kim * 5dd7d207dSJung-uk Kim * Redistribution and use in source and binary forms, with or without 6dd7d207dSJung-uk Kim * modification, are permitted provided that the following conditions 7dd7d207dSJung-uk Kim * are met: 8dd7d207dSJung-uk Kim * 1. Redistributions of source code must retain the above copyright 9dd7d207dSJung-uk Kim * notice, this list of conditions and the following disclaimer. 10dd7d207dSJung-uk Kim * 2. Redistributions in binary form must reproduce the above copyright 11dd7d207dSJung-uk Kim * notice, this list of conditions and the following disclaimer in the 12dd7d207dSJung-uk Kim * documentation and/or other materials provided with the distribution. 13dd7d207dSJung-uk Kim * 14dd7d207dSJung-uk Kim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15dd7d207dSJung-uk Kim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16dd7d207dSJung-uk Kim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17dd7d207dSJung-uk Kim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18dd7d207dSJung-uk Kim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19dd7d207dSJung-uk Kim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20dd7d207dSJung-uk Kim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21dd7d207dSJung-uk Kim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22dd7d207dSJung-uk Kim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23dd7d207dSJung-uk Kim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24dd7d207dSJung-uk Kim * SUCH DAMAGE. 25dd7d207dSJung-uk Kim */ 26dd7d207dSJung-uk Kim 27dd7d207dSJung-uk Kim #include <sys/cdefs.h> 28dd7d207dSJung-uk Kim __FBSDID("$FreeBSD$"); 29dd7d207dSJung-uk Kim 30aea81038SKonstantin Belousov #include "opt_compat.h" 31dd7d207dSJung-uk Kim #include "opt_clock.h" 32dd7d207dSJung-uk Kim 33dd7d207dSJung-uk Kim #include <sys/param.h> 34dd7d207dSJung-uk Kim #include <sys/bus.h> 35dd7d207dSJung-uk Kim #include <sys/cpu.h> 365da5812bSJung-uk Kim #include <sys/limits.h> 37dd7d207dSJung-uk Kim #include <sys/malloc.h> 38dd7d207dSJung-uk Kim #include <sys/systm.h> 39dd7d207dSJung-uk Kim #include <sys/sysctl.h> 40dd7d207dSJung-uk Kim #include <sys/time.h> 41dd7d207dSJung-uk Kim #include <sys/timetc.h> 42dd7d207dSJung-uk Kim #include <sys/kernel.h> 43dd7d207dSJung-uk Kim #include <sys/power.h> 44dd7d207dSJung-uk Kim #include <sys/smp.h> 45aea81038SKonstantin Belousov #include <sys/vdso.h> 46dd7d207dSJung-uk Kim #include <machine/clock.h> 47dd7d207dSJung-uk Kim #include <machine/cputypes.h> 48dd7d207dSJung-uk Kim #include <machine/md_var.h> 49dd7d207dSJung-uk Kim #include <machine/specialreg.h> 5001e1933dSJohn Baldwin #include <x86/vmware.h> 51dd7d207dSJung-uk Kim 52dd7d207dSJung-uk Kim #include "cpufreq_if.h" 53dd7d207dSJung-uk Kim 54dd7d207dSJung-uk Kim uint64_t tsc_freq; 55dd7d207dSJung-uk Kim int tsc_is_invariant; 56155094d7SJung-uk Kim int tsc_perf_stat; 57155094d7SJung-uk Kim 58dd7d207dSJung-uk Kim static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag; 59dd7d207dSJung-uk Kim 60dd7d207dSJung-uk Kim SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN, 61dd7d207dSJung-uk Kim &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant"); 62dd7d207dSJung-uk Kim 63dd7d207dSJung-uk Kim #ifdef SMP 641472b87fSNeel Natu int smp_tsc; 65dd7d207dSJung-uk Kim SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0, 66dd7d207dSJung-uk Kim "Indicates whether the TSC is safe to use in SMP mode"); 67b2c63698SAlexander Motin 68b2c63698SAlexander Motin int smp_tsc_adjust = 0; 69b2c63698SAlexander Motin SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN, 70b2c63698SAlexander Motin &smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP"); 71dd7d207dSJung-uk Kim #endif 72dd7d207dSJung-uk Kim 73e7f1427dSKonstantin Belousov static int tsc_shift = 1; 74e7f1427dSKonstantin Belousov SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN, 75e7f1427dSKonstantin Belousov &tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency"); 76e7f1427dSKonstantin Belousov 7779422085SJung-uk Kim static int tsc_disabled; 7879422085SJung-uk Kim SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0, 7979422085SJung-uk Kim "Disable x86 Time Stamp Counter"); 8079422085SJung-uk Kim 81a4e4127fSJung-uk Kim static int tsc_skip_calibration; 82a4e4127fSJung-uk Kim SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN, 83a4e4127fSJung-uk Kim &tsc_skip_calibration, 0, "Disable TSC frequency calibration"); 84a4e4127fSJung-uk Kim 85dd7d207dSJung-uk Kim static void tsc_freq_changed(void *arg, const struct cf_level *level, 86dd7d207dSJung-uk Kim int status); 87dd7d207dSJung-uk Kim static void tsc_freq_changing(void *arg, const struct cf_level *level, 88dd7d207dSJung-uk Kim int *status); 89dd7d207dSJung-uk Kim static unsigned tsc_get_timecount(struct timecounter *tc); 90814124c3SKonstantin Belousov static inline unsigned tsc_get_timecount_low(struct timecounter *tc); 91814124c3SKonstantin Belousov static unsigned tsc_get_timecount_lfence(struct timecounter *tc); 92814124c3SKonstantin Belousov static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc); 93814124c3SKonstantin Belousov static unsigned tsc_get_timecount_mfence(struct timecounter *tc); 94814124c3SKonstantin Belousov static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc); 95dd7d207dSJung-uk Kim static void tsc_levels_changed(void *arg, int unit); 96dd7d207dSJung-uk Kim 97dd7d207dSJung-uk Kim static struct timecounter tsc_timecounter = { 98dd7d207dSJung-uk Kim tsc_get_timecount, /* get_timecount */ 99dd7d207dSJung-uk Kim 0, /* no poll_pps */ 100dd7d207dSJung-uk Kim ~0u, /* counter_mask */ 101dd7d207dSJung-uk Kim 0, /* frequency */ 102dd7d207dSJung-uk Kim "TSC", /* name */ 103dd7d207dSJung-uk Kim 800, /* quality (adjusted in code) */ 104dd7d207dSJung-uk Kim }; 105dd7d207dSJung-uk Kim 10601e1933dSJohn Baldwin static void 1075da5812bSJung-uk Kim tsc_freq_vmware(void) 1085da5812bSJung-uk Kim { 1095da5812bSJung-uk Kim u_int regs[4]; 1105da5812bSJung-uk Kim 1115da5812bSJung-uk Kim if (hv_high >= 0x40000010) { 1125da5812bSJung-uk Kim do_cpuid(0x40000010, regs); 1135da5812bSJung-uk Kim tsc_freq = regs[0] * 1000; 1145da5812bSJung-uk Kim } else { 1155da5812bSJung-uk Kim vmware_hvcall(VMW_HVCMD_GETHZ, regs); 1165da5812bSJung-uk Kim if (regs[1] != UINT_MAX) 1175da5812bSJung-uk Kim tsc_freq = regs[0] | ((uint64_t)regs[1] << 32); 1185da5812bSJung-uk Kim } 1195da5812bSJung-uk Kim tsc_is_invariant = 1; 1205da5812bSJung-uk Kim } 1215da5812bSJung-uk Kim 122a4e4127fSJung-uk Kim static void 123a4e4127fSJung-uk Kim tsc_freq_intel(void) 124dd7d207dSJung-uk Kim { 125a4e4127fSJung-uk Kim char brand[48]; 126a4e4127fSJung-uk Kim u_int regs[4]; 127a4e4127fSJung-uk Kim uint64_t freq; 128a4e4127fSJung-uk Kim char *p; 129a4e4127fSJung-uk Kim u_int i; 130dd7d207dSJung-uk Kim 131a4e4127fSJung-uk Kim /* 132a4e4127fSJung-uk Kim * Intel Processor Identification and the CPUID Instruction 133a4e4127fSJung-uk Kim * Application Note 485. 134a4e4127fSJung-uk Kim * http://www.intel.com/assets/pdf/appnote/241618.pdf 135a4e4127fSJung-uk Kim */ 136a4e4127fSJung-uk Kim if (cpu_exthigh >= 0x80000004) { 137a4e4127fSJung-uk Kim p = brand; 138a4e4127fSJung-uk Kim for (i = 0x80000002; i < 0x80000005; i++) { 139a4e4127fSJung-uk Kim do_cpuid(i, regs); 140a4e4127fSJung-uk Kim memcpy(p, regs, sizeof(regs)); 141a4e4127fSJung-uk Kim p += sizeof(regs); 142a4e4127fSJung-uk Kim } 143a4e4127fSJung-uk Kim p = NULL; 144a4e4127fSJung-uk Kim for (i = 0; i < sizeof(brand) - 1; i++) 145a4e4127fSJung-uk Kim if (brand[i] == 'H' && brand[i + 1] == 'z') 146a4e4127fSJung-uk Kim p = brand + i; 147a4e4127fSJung-uk Kim if (p != NULL) { 148a4e4127fSJung-uk Kim p -= 5; 149a4e4127fSJung-uk Kim switch (p[4]) { 150a4e4127fSJung-uk Kim case 'M': 151a4e4127fSJung-uk Kim i = 1; 152a4e4127fSJung-uk Kim break; 153a4e4127fSJung-uk Kim case 'G': 154a4e4127fSJung-uk Kim i = 1000; 155a4e4127fSJung-uk Kim break; 156a4e4127fSJung-uk Kim case 'T': 157a4e4127fSJung-uk Kim i = 1000000; 158a4e4127fSJung-uk Kim break; 159a4e4127fSJung-uk Kim default: 160dd7d207dSJung-uk Kim return; 161a4e4127fSJung-uk Kim } 162a4e4127fSJung-uk Kim #define C2D(c) ((c) - '0') 163a4e4127fSJung-uk Kim if (p[1] == '.') { 164a4e4127fSJung-uk Kim freq = C2D(p[0]) * 1000; 165a4e4127fSJung-uk Kim freq += C2D(p[2]) * 100; 166a4e4127fSJung-uk Kim freq += C2D(p[3]) * 10; 167a4e4127fSJung-uk Kim freq *= i * 1000; 168a4e4127fSJung-uk Kim } else { 169a4e4127fSJung-uk Kim freq = C2D(p[0]) * 1000; 170a4e4127fSJung-uk Kim freq += C2D(p[1]) * 100; 171a4e4127fSJung-uk Kim freq += C2D(p[2]) * 10; 172a4e4127fSJung-uk Kim freq += C2D(p[3]); 173a4e4127fSJung-uk Kim freq *= i * 1000000; 174a4e4127fSJung-uk Kim } 175a4e4127fSJung-uk Kim #undef C2D 176a4e4127fSJung-uk Kim tsc_freq = freq; 177a4e4127fSJung-uk Kim } 178a4e4127fSJung-uk Kim } 179a4e4127fSJung-uk Kim } 180dd7d207dSJung-uk Kim 181a4e4127fSJung-uk Kim static void 182a4e4127fSJung-uk Kim probe_tsc_freq(void) 183a4e4127fSJung-uk Kim { 184155094d7SJung-uk Kim u_int regs[4]; 185a4e4127fSJung-uk Kim uint64_t tsc1, tsc2; 186dd7d207dSJung-uk Kim 1875da5812bSJung-uk Kim if (cpu_high >= 6) { 1885da5812bSJung-uk Kim do_cpuid(6, regs); 1895da5812bSJung-uk Kim if ((regs[2] & CPUID_PERF_STAT) != 0) { 1905da5812bSJung-uk Kim /* 1915da5812bSJung-uk Kim * XXX Some emulators expose host CPUID without actual 1925da5812bSJung-uk Kim * support for these MSRs. We must test whether they 1935da5812bSJung-uk Kim * really work. 1945da5812bSJung-uk Kim */ 1955da5812bSJung-uk Kim wrmsr(MSR_MPERF, 0); 1965da5812bSJung-uk Kim wrmsr(MSR_APERF, 0); 1975da5812bSJung-uk Kim DELAY(10); 1985da5812bSJung-uk Kim if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0) 1995da5812bSJung-uk Kim tsc_perf_stat = 1; 2005da5812bSJung-uk Kim } 2015da5812bSJung-uk Kim } 2025da5812bSJung-uk Kim 20301e1933dSJohn Baldwin if (vm_guest == VM_GUEST_VMWARE) { 20401e1933dSJohn Baldwin tsc_freq_vmware(); 2055da5812bSJung-uk Kim return; 20601e1933dSJohn Baldwin } 2075da5812bSJung-uk Kim 208dd7d207dSJung-uk Kim switch (cpu_vendor_id) { 209dd7d207dSJung-uk Kim case CPU_VENDOR_AMD: 210a106a27cSJung-uk Kim if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 211a106a27cSJung-uk Kim (vm_guest == VM_GUEST_NO && 212a106a27cSJung-uk Kim CPUID_TO_FAMILY(cpu_id) >= 0x10)) 213dd7d207dSJung-uk Kim tsc_is_invariant = 1; 214814124c3SKonstantin Belousov if (cpu_feature & CPUID_SSE2) { 215814124c3SKonstantin Belousov tsc_timecounter.tc_get_timecount = 216814124c3SKonstantin Belousov tsc_get_timecount_mfence; 217814124c3SKonstantin Belousov } 218dd7d207dSJung-uk Kim break; 219dd7d207dSJung-uk Kim case CPU_VENDOR_INTEL: 220a106a27cSJung-uk Kim if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 221a106a27cSJung-uk Kim (vm_guest == VM_GUEST_NO && 222a106a27cSJung-uk Kim ((CPUID_TO_FAMILY(cpu_id) == 0x6 && 223dd7d207dSJung-uk Kim CPUID_TO_MODEL(cpu_id) >= 0xe) || 224dd7d207dSJung-uk Kim (CPUID_TO_FAMILY(cpu_id) == 0xf && 225a106a27cSJung-uk Kim CPUID_TO_MODEL(cpu_id) >= 0x3)))) 226dd7d207dSJung-uk Kim tsc_is_invariant = 1; 227814124c3SKonstantin Belousov if (cpu_feature & CPUID_SSE2) { 228814124c3SKonstantin Belousov tsc_timecounter.tc_get_timecount = 229814124c3SKonstantin Belousov tsc_get_timecount_lfence; 230814124c3SKonstantin Belousov } 231dd7d207dSJung-uk Kim break; 232dd7d207dSJung-uk Kim case CPU_VENDOR_CENTAUR: 233a106a27cSJung-uk Kim if (vm_guest == VM_GUEST_NO && 234a106a27cSJung-uk Kim CPUID_TO_FAMILY(cpu_id) == 0x6 && 235dd7d207dSJung-uk Kim CPUID_TO_MODEL(cpu_id) >= 0xf && 236dd7d207dSJung-uk Kim (rdmsr(0x1203) & 0x100000000ULL) == 0) 237dd7d207dSJung-uk Kim tsc_is_invariant = 1; 238814124c3SKonstantin Belousov if (cpu_feature & CPUID_SSE2) { 239814124c3SKonstantin Belousov tsc_timecounter.tc_get_timecount = 240814124c3SKonstantin Belousov tsc_get_timecount_lfence; 241814124c3SKonstantin Belousov } 242dd7d207dSJung-uk Kim break; 243dd7d207dSJung-uk Kim } 244dd7d207dSJung-uk Kim 245a4e4127fSJung-uk Kim if (tsc_skip_calibration) { 246a4e4127fSJung-uk Kim if (cpu_vendor_id == CPU_VENDOR_INTEL) 247a4e4127fSJung-uk Kim tsc_freq_intel(); 248a4e4127fSJung-uk Kim return; 249a4e4127fSJung-uk Kim } 250a4e4127fSJung-uk Kim 251a4e4127fSJung-uk Kim if (bootverbose) 252a4e4127fSJung-uk Kim printf("Calibrating TSC clock ... "); 253a4e4127fSJung-uk Kim tsc1 = rdtsc(); 254a4e4127fSJung-uk Kim DELAY(1000000); 255a4e4127fSJung-uk Kim tsc2 = rdtsc(); 256a4e4127fSJung-uk Kim tsc_freq = tsc2 - tsc1; 257a4e4127fSJung-uk Kim if (bootverbose) 258a4e4127fSJung-uk Kim printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq); 259a4e4127fSJung-uk Kim } 260a4e4127fSJung-uk Kim 261a4e4127fSJung-uk Kim void 262a4e4127fSJung-uk Kim init_TSC(void) 263a4e4127fSJung-uk Kim { 264a4e4127fSJung-uk Kim 265a4e4127fSJung-uk Kim if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) 266a4e4127fSJung-uk Kim return; 267a4e4127fSJung-uk Kim 268fe760cfaSJohn Baldwin #ifdef __i386__ 269fe760cfaSJohn Baldwin /* The TSC is known to be broken on certain CPUs. */ 270fe760cfaSJohn Baldwin switch (cpu_vendor_id) { 271fe760cfaSJohn Baldwin case CPU_VENDOR_AMD: 272fe760cfaSJohn Baldwin switch (cpu_id & 0xFF0) { 273fe760cfaSJohn Baldwin case 0x500: 274fe760cfaSJohn Baldwin /* K5 Model 0 */ 275fe760cfaSJohn Baldwin return; 276fe760cfaSJohn Baldwin } 277fe760cfaSJohn Baldwin break; 278fe760cfaSJohn Baldwin case CPU_VENDOR_CENTAUR: 279fe760cfaSJohn Baldwin switch (cpu_id & 0xff0) { 280fe760cfaSJohn Baldwin case 0x540: 281fe760cfaSJohn Baldwin /* 282fe760cfaSJohn Baldwin * http://www.centtech.com/c6_data_sheet.pdf 283fe760cfaSJohn Baldwin * 284fe760cfaSJohn Baldwin * I-12 RDTSC may return incoherent values in EDX:EAX 285fe760cfaSJohn Baldwin * I-13 RDTSC hangs when certain event counters are used 286fe760cfaSJohn Baldwin */ 287fe760cfaSJohn Baldwin return; 288fe760cfaSJohn Baldwin } 289fe760cfaSJohn Baldwin break; 290fe760cfaSJohn Baldwin case CPU_VENDOR_NSC: 291fe760cfaSJohn Baldwin switch (cpu_id & 0xff0) { 292fe760cfaSJohn Baldwin case 0x540: 293fe760cfaSJohn Baldwin if ((cpu_id & CPUID_STEPPING) == 0) 294fe760cfaSJohn Baldwin return; 295fe760cfaSJohn Baldwin break; 296fe760cfaSJohn Baldwin } 297fe760cfaSJohn Baldwin break; 298fe760cfaSJohn Baldwin } 299fe760cfaSJohn Baldwin #endif 300fe760cfaSJohn Baldwin 301a4e4127fSJung-uk Kim probe_tsc_freq(); 302a4e4127fSJung-uk Kim 303dd7d207dSJung-uk Kim /* 304dd7d207dSJung-uk Kim * Inform CPU accounting about our boot-time clock rate. This will 305dd7d207dSJung-uk Kim * be updated if someone loads a cpufreq driver after boot that 306dd7d207dSJung-uk Kim * discovers a new max frequency. 307dd7d207dSJung-uk Kim */ 308a4e4127fSJung-uk Kim if (tsc_freq != 0) 3095ac44f72SJung-uk Kim set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant); 310dd7d207dSJung-uk Kim 311dd7d207dSJung-uk Kim if (tsc_is_invariant) 312dd7d207dSJung-uk Kim return; 313dd7d207dSJung-uk Kim 314dd7d207dSJung-uk Kim /* Register to find out about changes in CPU frequency. */ 315dd7d207dSJung-uk Kim tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change, 316dd7d207dSJung-uk Kim tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST); 317dd7d207dSJung-uk Kim tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 318dd7d207dSJung-uk Kim tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST); 319dd7d207dSJung-uk Kim tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed, 320dd7d207dSJung-uk Kim tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY); 321dd7d207dSJung-uk Kim } 322dd7d207dSJung-uk Kim 32365e7d70bSJung-uk Kim #ifdef SMP 32465e7d70bSJung-uk Kim 325814124c3SKonstantin Belousov /* 326814124c3SKonstantin Belousov * RDTSC is not a serializing instruction, and does not drain 327814124c3SKonstantin Belousov * instruction stream, so we need to drain the stream before executing 328814124c3SKonstantin Belousov * it. It could be fixed by use of RDTSCP, except the instruction is 329814124c3SKonstantin Belousov * not available everywhere. 330814124c3SKonstantin Belousov * 331814124c3SKonstantin Belousov * Use CPUID for draining in the boot-time SMP constistency test. The 332814124c3SKonstantin Belousov * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel 333814124c3SKonstantin Belousov * and VIA) when SSE2 is present, and nothing on older machines which 334814124c3SKonstantin Belousov * also do not issue RDTSC prematurely. There, testing for SSE2 and 335e1a18e46SKonstantin Belousov * vendor is too cumbersome, and we learn about TSC presence from CPUID. 336814124c3SKonstantin Belousov * 337814124c3SKonstantin Belousov * Do not use do_cpuid(), since we do not need CPUID results, which 338814124c3SKonstantin Belousov * have to be written into memory with do_cpuid(). 339814124c3SKonstantin Belousov */ 34065e7d70bSJung-uk Kim #define TSC_READ(x) \ 34165e7d70bSJung-uk Kim static void \ 34265e7d70bSJung-uk Kim tsc_read_##x(void *arg) \ 34365e7d70bSJung-uk Kim { \ 3447bfcb3bbSJim Harris uint64_t *tsc = arg; \ 34565e7d70bSJung-uk Kim u_int cpu = PCPU_GET(cpuid); \ 34665e7d70bSJung-uk Kim \ 347814124c3SKonstantin Belousov __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx"); \ 3487bfcb3bbSJim Harris tsc[cpu * 3 + x] = rdtsc(); \ 34965e7d70bSJung-uk Kim } 35065e7d70bSJung-uk Kim TSC_READ(0) 35165e7d70bSJung-uk Kim TSC_READ(1) 35265e7d70bSJung-uk Kim TSC_READ(2) 35365e7d70bSJung-uk Kim #undef TSC_READ 35465e7d70bSJung-uk Kim 35565e7d70bSJung-uk Kim #define N 1000 35665e7d70bSJung-uk Kim 35765e7d70bSJung-uk Kim static void 35865e7d70bSJung-uk Kim comp_smp_tsc(void *arg) 35965e7d70bSJung-uk Kim { 3607bfcb3bbSJim Harris uint64_t *tsc; 3617bfcb3bbSJim Harris int64_t d1, d2; 36265e7d70bSJung-uk Kim u_int cpu = PCPU_GET(cpuid); 36365e7d70bSJung-uk Kim u_int i, j, size; 36465e7d70bSJung-uk Kim 36565e7d70bSJung-uk Kim size = (mp_maxid + 1) * 3; 36665e7d70bSJung-uk Kim for (i = 0, tsc = arg; i < N; i++, tsc += size) 36765e7d70bSJung-uk Kim CPU_FOREACH(j) { 36865e7d70bSJung-uk Kim if (j == cpu) 36965e7d70bSJung-uk Kim continue; 37065e7d70bSJung-uk Kim d1 = tsc[cpu * 3 + 1] - tsc[j * 3]; 37165e7d70bSJung-uk Kim d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1]; 37265e7d70bSJung-uk Kim if (d1 <= 0 || d2 <= 0) { 37365e7d70bSJung-uk Kim smp_tsc = 0; 37465e7d70bSJung-uk Kim return; 37565e7d70bSJung-uk Kim } 37665e7d70bSJung-uk Kim } 37765e7d70bSJung-uk Kim } 37865e7d70bSJung-uk Kim 379b2c63698SAlexander Motin static void 380b2c63698SAlexander Motin adj_smp_tsc(void *arg) 381b2c63698SAlexander Motin { 382b2c63698SAlexander Motin uint64_t *tsc; 383b2c63698SAlexander Motin int64_t d, min, max; 384b2c63698SAlexander Motin u_int cpu = PCPU_GET(cpuid); 385b2c63698SAlexander Motin u_int first, i, size; 386b2c63698SAlexander Motin 387b2c63698SAlexander Motin first = CPU_FIRST(); 388b2c63698SAlexander Motin if (cpu == first) 389b2c63698SAlexander Motin return; 390b2c63698SAlexander Motin min = INT64_MIN; 391b2c63698SAlexander Motin max = INT64_MAX; 392b2c63698SAlexander Motin size = (mp_maxid + 1) * 3; 393b2c63698SAlexander Motin for (i = 0, tsc = arg; i < N; i++, tsc += size) { 394b2c63698SAlexander Motin d = tsc[first * 3] - tsc[cpu * 3 + 1]; 395b2c63698SAlexander Motin if (d > min) 396b2c63698SAlexander Motin min = d; 397b2c63698SAlexander Motin d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2]; 398b2c63698SAlexander Motin if (d > min) 399b2c63698SAlexander Motin min = d; 400b2c63698SAlexander Motin d = tsc[first * 3 + 1] - tsc[cpu * 3]; 401b2c63698SAlexander Motin if (d < max) 402b2c63698SAlexander Motin max = d; 403b2c63698SAlexander Motin d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1]; 404b2c63698SAlexander Motin if (d < max) 405b2c63698SAlexander Motin max = d; 406b2c63698SAlexander Motin } 407b2c63698SAlexander Motin if (min > max) 408b2c63698SAlexander Motin return; 409b2c63698SAlexander Motin d = min / 2 + max / 2; 410b2c63698SAlexander Motin __asm __volatile ( 411b2c63698SAlexander Motin "movl $0x10, %%ecx\n\t" 412b2c63698SAlexander Motin "rdmsr\n\t" 413b2c63698SAlexander Motin "addl %%edi, %%eax\n\t" 414b2c63698SAlexander Motin "adcl %%esi, %%edx\n\t" 415b2c63698SAlexander Motin "wrmsr\n" 416b2c63698SAlexander Motin : /* No output */ 417b2c63698SAlexander Motin : "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32)) 418b2c63698SAlexander Motin : "ax", "cx", "dx", "cc" 419b2c63698SAlexander Motin ); 420b2c63698SAlexander Motin } 421b2c63698SAlexander Motin 42265e7d70bSJung-uk Kim static int 423e7f1427dSKonstantin Belousov test_tsc(void) 42465e7d70bSJung-uk Kim { 4257bfcb3bbSJim Harris uint64_t *data, *tsc; 426b2c63698SAlexander Motin u_int i, size, adj; 42765e7d70bSJung-uk Kim 428e7f1427dSKonstantin Belousov if ((!smp_tsc && !tsc_is_invariant) || vm_guest) 42965e7d70bSJung-uk Kim return (-100); 43065e7d70bSJung-uk Kim size = (mp_maxid + 1) * 3; 43165e7d70bSJung-uk Kim data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK); 432b2c63698SAlexander Motin adj = 0; 433b2c63698SAlexander Motin retry: 43465e7d70bSJung-uk Kim for (i = 0, tsc = data; i < N; i++, tsc += size) 43565e7d70bSJung-uk Kim smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc); 43665e7d70bSJung-uk Kim smp_tsc = 1; /* XXX */ 43765e7d70bSJung-uk Kim smp_rendezvous(smp_no_rendevous_barrier, comp_smp_tsc, 43865e7d70bSJung-uk Kim smp_no_rendevous_barrier, data); 439b2c63698SAlexander Motin if (!smp_tsc && adj < smp_tsc_adjust) { 440b2c63698SAlexander Motin adj++; 441b2c63698SAlexander Motin smp_rendezvous(smp_no_rendevous_barrier, adj_smp_tsc, 442b2c63698SAlexander Motin smp_no_rendevous_barrier, data); 443b2c63698SAlexander Motin goto retry; 444b2c63698SAlexander Motin } 44565e7d70bSJung-uk Kim free(data, M_TEMP); 44665e7d70bSJung-uk Kim if (bootverbose) 447b2c63698SAlexander Motin printf("SMP: %sed TSC synchronization test%s\n", 448b2c63698SAlexander Motin smp_tsc ? "pass" : "fail", 449b2c63698SAlexander Motin adj > 0 ? " after adjustment" : ""); 45026e6537aSJung-uk Kim if (smp_tsc && tsc_is_invariant) { 45126e6537aSJung-uk Kim switch (cpu_vendor_id) { 45226e6537aSJung-uk Kim case CPU_VENDOR_AMD: 45326e6537aSJung-uk Kim /* 45426e6537aSJung-uk Kim * Starting with Family 15h processors, TSC clock 45526e6537aSJung-uk Kim * source is in the north bridge. Check whether 45626e6537aSJung-uk Kim * we have a single-socket/multi-core platform. 45726e6537aSJung-uk Kim * XXX Need more work for complex cases. 45826e6537aSJung-uk Kim */ 45926e6537aSJung-uk Kim if (CPUID_TO_FAMILY(cpu_id) < 0x15 || 46026e6537aSJung-uk Kim (amd_feature2 & AMDID2_CMP) == 0 || 46126e6537aSJung-uk Kim smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1) 46226e6537aSJung-uk Kim break; 46326e6537aSJung-uk Kim return (1000); 46426e6537aSJung-uk Kim case CPU_VENDOR_INTEL: 46526e6537aSJung-uk Kim /* 46626e6537aSJung-uk Kim * XXX Assume Intel platforms have synchronized TSCs. 46726e6537aSJung-uk Kim */ 46826e6537aSJung-uk Kim return (1000); 46926e6537aSJung-uk Kim } 47026e6537aSJung-uk Kim return (800); 47126e6537aSJung-uk Kim } 47226e6537aSJung-uk Kim return (-100); 47365e7d70bSJung-uk Kim } 47465e7d70bSJung-uk Kim 47565e7d70bSJung-uk Kim #undef N 47665e7d70bSJung-uk Kim 477e7f1427dSKonstantin Belousov #else 478e7f1427dSKonstantin Belousov 479e7f1427dSKonstantin Belousov /* 480e7f1427dSKonstantin Belousov * The function is not called, it is provided to avoid linking failure 481e7f1427dSKonstantin Belousov * on uniprocessor kernel. 482e7f1427dSKonstantin Belousov */ 483e7f1427dSKonstantin Belousov static int 484e7f1427dSKonstantin Belousov test_tsc(void) 485e7f1427dSKonstantin Belousov { 486e7f1427dSKonstantin Belousov 487e7f1427dSKonstantin Belousov return (0); 488e7f1427dSKonstantin Belousov } 489e7f1427dSKonstantin Belousov 49065e7d70bSJung-uk Kim #endif /* SMP */ 49165e7d70bSJung-uk Kim 49265e7d70bSJung-uk Kim static void 493dd7d207dSJung-uk Kim init_TSC_tc(void) 494dd7d207dSJung-uk Kim { 49595f2f098SJung-uk Kim uint64_t max_freq; 49695f2f098SJung-uk Kim int shift; 497dd7d207dSJung-uk Kim 49838b8542cSJung-uk Kim if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) 499dd7d207dSJung-uk Kim return; 500dd7d207dSJung-uk Kim 501dd7d207dSJung-uk Kim /* 50295f2f098SJung-uk Kim * Limit timecounter frequency to fit in an int and prevent it from 50395f2f098SJung-uk Kim * overflowing too fast. 50495f2f098SJung-uk Kim */ 50595f2f098SJung-uk Kim max_freq = UINT_MAX; 50695f2f098SJung-uk Kim 50795f2f098SJung-uk Kim /* 508dd7d207dSJung-uk Kim * We can not use the TSC if we support APM. Precise timekeeping 509dd7d207dSJung-uk Kim * on an APM'ed machine is at best a fools pursuit, since 510dd7d207dSJung-uk Kim * any and all of the time spent in various SMM code can't 511dd7d207dSJung-uk Kim * be reliably accounted for. Reading the RTC is your only 512dd7d207dSJung-uk Kim * source of reliable time info. The i8254 loses too, of course, 513dd7d207dSJung-uk Kim * but we need to have some kind of time... 514dd7d207dSJung-uk Kim * We don't know at this point whether APM is going to be used 515dd7d207dSJung-uk Kim * or not, nor when it might be activated. Play it safe. 516dd7d207dSJung-uk Kim */ 517dd7d207dSJung-uk Kim if (power_pm_get_type() == POWER_PM_TYPE_APM) { 518dd7d207dSJung-uk Kim tsc_timecounter.tc_quality = -1000; 519dd7d207dSJung-uk Kim if (bootverbose) 520dd7d207dSJung-uk Kim printf("TSC timecounter disabled: APM enabled.\n"); 52165e7d70bSJung-uk Kim goto init; 522dd7d207dSJung-uk Kim } 523dd7d207dSJung-uk Kim 524a49399a9SJung-uk Kim /* 52592597e06SJohn Baldwin * We cannot use the TSC if it stops incrementing while idle. 52692597e06SJohn Baldwin * Intel CPUs without a C-state invariant TSC can stop the TSC 52792597e06SJohn Baldwin * in either C2 or C3. 528a49399a9SJung-uk Kim */ 52992597e06SJohn Baldwin if (cpu_deepest_sleep >= 2 && cpu_vendor_id == CPU_VENDOR_INTEL && 530a49399a9SJung-uk Kim (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) { 531a49399a9SJung-uk Kim tsc_timecounter.tc_quality = -1000; 53292597e06SJohn Baldwin tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP; 533a49399a9SJung-uk Kim if (bootverbose) 53492597e06SJohn Baldwin printf("TSC timecounter disabled: C2/C3 may halt it.\n"); 535a49399a9SJung-uk Kim goto init; 536a49399a9SJung-uk Kim } 537a49399a9SJung-uk Kim 538dd7d207dSJung-uk Kim /* 539e7f1427dSKonstantin Belousov * We can not use the TSC in SMP mode unless the TSCs on all CPUs 540e7f1427dSKonstantin Belousov * are synchronized. If the user is sure that the system has 541e7f1427dSKonstantin Belousov * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a 542e7f1427dSKonstantin Belousov * non-zero value. The TSC seems unreliable in virtualized SMP 5435cf8ac1bSMike Silbersack * environments, so it is set to a negative quality in those cases. 544dd7d207dSJung-uk Kim */ 545e7f1427dSKonstantin Belousov if (mp_ncpus > 1) 546e7f1427dSKonstantin Belousov tsc_timecounter.tc_quality = test_tsc(); 547e7f1427dSKonstantin Belousov else if (tsc_is_invariant) 54826e6537aSJung-uk Kim tsc_timecounter.tc_quality = 1000; 549e7f1427dSKonstantin Belousov max_freq >>= tsc_shift; 55026e6537aSJung-uk Kim 55165e7d70bSJung-uk Kim init: 552e7f1427dSKonstantin Belousov for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++) 55395f2f098SJung-uk Kim ; 554e7f1427dSKonstantin Belousov if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) { 555814124c3SKonstantin Belousov if (cpu_vendor_id == CPU_VENDOR_AMD) { 556e7f1427dSKonstantin Belousov tsc_timecounter.tc_get_timecount = shift > 0 ? 557e7f1427dSKonstantin Belousov tsc_get_timecount_low_mfence : 558e7f1427dSKonstantin Belousov tsc_get_timecount_mfence; 559814124c3SKonstantin Belousov } else { 560e7f1427dSKonstantin Belousov tsc_timecounter.tc_get_timecount = shift > 0 ? 561e7f1427dSKonstantin Belousov tsc_get_timecount_low_lfence : 562e7f1427dSKonstantin Belousov tsc_get_timecount_lfence; 563814124c3SKonstantin Belousov } 564e7f1427dSKonstantin Belousov } else { 565e7f1427dSKonstantin Belousov tsc_timecounter.tc_get_timecount = shift > 0 ? 566e7f1427dSKonstantin Belousov tsc_get_timecount_low : tsc_get_timecount; 567e7f1427dSKonstantin Belousov } 568e7f1427dSKonstantin Belousov if (shift > 0) { 56995f2f098SJung-uk Kim tsc_timecounter.tc_name = "TSC-low"; 57095f2f098SJung-uk Kim if (bootverbose) 571bc8e4ad2SJung-uk Kim printf("TSC timecounter discards lower %d bit(s)\n", 57295f2f098SJung-uk Kim shift); 57395f2f098SJung-uk Kim } 574bc34c87eSJung-uk Kim if (tsc_freq != 0) { 57595f2f098SJung-uk Kim tsc_timecounter.tc_frequency = tsc_freq >> shift; 57695f2f098SJung-uk Kim tsc_timecounter.tc_priv = (void *)(intptr_t)shift; 577dd7d207dSJung-uk Kim tc_init(&tsc_timecounter); 578dd7d207dSJung-uk Kim } 579dd7d207dSJung-uk Kim } 58065e7d70bSJung-uk Kim SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL); 581dd7d207dSJung-uk Kim 582dd7d207dSJung-uk Kim /* 583dd7d207dSJung-uk Kim * When cpufreq levels change, find out about the (new) max frequency. We 584dd7d207dSJung-uk Kim * use this to update CPU accounting in case it got a lower estimate at boot. 585dd7d207dSJung-uk Kim */ 586dd7d207dSJung-uk Kim static void 587dd7d207dSJung-uk Kim tsc_levels_changed(void *arg, int unit) 588dd7d207dSJung-uk Kim { 589dd7d207dSJung-uk Kim device_t cf_dev; 590dd7d207dSJung-uk Kim struct cf_level *levels; 591dd7d207dSJung-uk Kim int count, error; 592dd7d207dSJung-uk Kim uint64_t max_freq; 593dd7d207dSJung-uk Kim 594dd7d207dSJung-uk Kim /* Only use values from the first CPU, assuming all are equal. */ 595dd7d207dSJung-uk Kim if (unit != 0) 596dd7d207dSJung-uk Kim return; 597dd7d207dSJung-uk Kim 598dd7d207dSJung-uk Kim /* Find the appropriate cpufreq device instance. */ 599dd7d207dSJung-uk Kim cf_dev = devclass_get_device(devclass_find("cpufreq"), unit); 600dd7d207dSJung-uk Kim if (cf_dev == NULL) { 601dd7d207dSJung-uk Kim printf("tsc_levels_changed() called but no cpufreq device?\n"); 602dd7d207dSJung-uk Kim return; 603dd7d207dSJung-uk Kim } 604dd7d207dSJung-uk Kim 605dd7d207dSJung-uk Kim /* Get settings from the device and find the max frequency. */ 606dd7d207dSJung-uk Kim count = 64; 607dd7d207dSJung-uk Kim levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT); 608dd7d207dSJung-uk Kim if (levels == NULL) 609dd7d207dSJung-uk Kim return; 610dd7d207dSJung-uk Kim error = CPUFREQ_LEVELS(cf_dev, levels, &count); 611dd7d207dSJung-uk Kim if (error == 0 && count != 0) { 612dd7d207dSJung-uk Kim max_freq = (uint64_t)levels[0].total_set.freq * 1000000; 613dd7d207dSJung-uk Kim set_cputicker(rdtsc, max_freq, 1); 614dd7d207dSJung-uk Kim } else 615dd7d207dSJung-uk Kim printf("tsc_levels_changed: no max freq found\n"); 616dd7d207dSJung-uk Kim free(levels, M_TEMP); 617dd7d207dSJung-uk Kim } 618dd7d207dSJung-uk Kim 619dd7d207dSJung-uk Kim /* 620dd7d207dSJung-uk Kim * If the TSC timecounter is in use, veto the pending change. It may be 621dd7d207dSJung-uk Kim * possible in the future to handle a dynamically-changing timecounter rate. 622dd7d207dSJung-uk Kim */ 623dd7d207dSJung-uk Kim static void 624dd7d207dSJung-uk Kim tsc_freq_changing(void *arg, const struct cf_level *level, int *status) 625dd7d207dSJung-uk Kim { 626dd7d207dSJung-uk Kim 627dd7d207dSJung-uk Kim if (*status != 0 || timecounter != &tsc_timecounter) 628dd7d207dSJung-uk Kim return; 629dd7d207dSJung-uk Kim 630dd7d207dSJung-uk Kim printf("timecounter TSC must not be in use when " 631dd7d207dSJung-uk Kim "changing frequencies; change denied\n"); 632dd7d207dSJung-uk Kim *status = EBUSY; 633dd7d207dSJung-uk Kim } 634dd7d207dSJung-uk Kim 635dd7d207dSJung-uk Kim /* Update TSC freq with the value indicated by the caller. */ 636dd7d207dSJung-uk Kim static void 637dd7d207dSJung-uk Kim tsc_freq_changed(void *arg, const struct cf_level *level, int status) 638dd7d207dSJung-uk Kim { 6393453537fSJung-uk Kim uint64_t freq; 640dd7d207dSJung-uk Kim 641dd7d207dSJung-uk Kim /* If there was an error during the transition, don't do anything. */ 64279422085SJung-uk Kim if (tsc_disabled || status != 0) 643dd7d207dSJung-uk Kim return; 644dd7d207dSJung-uk Kim 645dd7d207dSJung-uk Kim /* Total setting for this level gives the new frequency in MHz. */ 6463453537fSJung-uk Kim freq = (uint64_t)level->total_set.freq * 1000000; 6473453537fSJung-uk Kim atomic_store_rel_64(&tsc_freq, freq); 64895f2f098SJung-uk Kim tsc_timecounter.tc_frequency = 64995f2f098SJung-uk Kim freq >> (int)(intptr_t)tsc_timecounter.tc_priv; 650dd7d207dSJung-uk Kim } 651dd7d207dSJung-uk Kim 652dd7d207dSJung-uk Kim static int 653dd7d207dSJung-uk Kim sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 654dd7d207dSJung-uk Kim { 655dd7d207dSJung-uk Kim int error; 656dd7d207dSJung-uk Kim uint64_t freq; 657dd7d207dSJung-uk Kim 6583453537fSJung-uk Kim freq = atomic_load_acq_64(&tsc_freq); 6593453537fSJung-uk Kim if (freq == 0) 660dd7d207dSJung-uk Kim return (EOPNOTSUPP); 661cbc134adSMatthew D Fleming error = sysctl_handle_64(oidp, &freq, 0, req); 6627ebbcb21SJung-uk Kim if (error == 0 && req->newptr != NULL) { 6633453537fSJung-uk Kim atomic_store_rel_64(&tsc_freq, freq); 664bc8e4ad2SJung-uk Kim atomic_store_rel_64(&tsc_timecounter.tc_frequency, 665bc8e4ad2SJung-uk Kim freq >> (int)(intptr_t)tsc_timecounter.tc_priv); 6667ebbcb21SJung-uk Kim } 667dd7d207dSJung-uk Kim return (error); 668dd7d207dSJung-uk Kim } 669dd7d207dSJung-uk Kim 670cbc134adSMatthew D Fleming SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_U64 | CTLFLAG_RW, 6715331d61dSJung-uk Kim 0, 0, sysctl_machdep_tsc_freq, "QU", "Time Stamp Counter frequency"); 672dd7d207dSJung-uk Kim 673727c7b2dSJung-uk Kim static u_int 67495f2f098SJung-uk Kim tsc_get_timecount(struct timecounter *tc __unused) 675dd7d207dSJung-uk Kim { 676727c7b2dSJung-uk Kim 677727c7b2dSJung-uk Kim return (rdtsc32()); 678dd7d207dSJung-uk Kim } 67995f2f098SJung-uk Kim 680814124c3SKonstantin Belousov static inline u_int 681bc8e4ad2SJung-uk Kim tsc_get_timecount_low(struct timecounter *tc) 68295f2f098SJung-uk Kim { 6835df88f46SJung-uk Kim uint32_t rv; 68495f2f098SJung-uk Kim 6855df88f46SJung-uk Kim __asm __volatile("rdtsc; shrd %%cl, %%edx, %0" 6865df88f46SJung-uk Kim : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx"); 6875df88f46SJung-uk Kim return (rv); 68895f2f098SJung-uk Kim } 689aea81038SKonstantin Belousov 690814124c3SKonstantin Belousov static u_int 691814124c3SKonstantin Belousov tsc_get_timecount_lfence(struct timecounter *tc __unused) 692814124c3SKonstantin Belousov { 693814124c3SKonstantin Belousov 694814124c3SKonstantin Belousov lfence(); 695814124c3SKonstantin Belousov return (rdtsc32()); 696814124c3SKonstantin Belousov } 697814124c3SKonstantin Belousov 698814124c3SKonstantin Belousov static u_int 699814124c3SKonstantin Belousov tsc_get_timecount_low_lfence(struct timecounter *tc) 700814124c3SKonstantin Belousov { 701814124c3SKonstantin Belousov 702814124c3SKonstantin Belousov lfence(); 703814124c3SKonstantin Belousov return (tsc_get_timecount_low(tc)); 704814124c3SKonstantin Belousov } 705814124c3SKonstantin Belousov 706814124c3SKonstantin Belousov static u_int 707814124c3SKonstantin Belousov tsc_get_timecount_mfence(struct timecounter *tc __unused) 708814124c3SKonstantin Belousov { 709814124c3SKonstantin Belousov 710814124c3SKonstantin Belousov mfence(); 711814124c3SKonstantin Belousov return (rdtsc32()); 712814124c3SKonstantin Belousov } 713814124c3SKonstantin Belousov 714814124c3SKonstantin Belousov static u_int 715814124c3SKonstantin Belousov tsc_get_timecount_low_mfence(struct timecounter *tc) 716814124c3SKonstantin Belousov { 717814124c3SKonstantin Belousov 718814124c3SKonstantin Belousov mfence(); 719814124c3SKonstantin Belousov return (tsc_get_timecount_low(tc)); 720814124c3SKonstantin Belousov } 721814124c3SKonstantin Belousov 722aea81038SKonstantin Belousov uint32_t 723aea81038SKonstantin Belousov cpu_fill_vdso_timehands(struct vdso_timehands *vdso_th) 724aea81038SKonstantin Belousov { 725aea81038SKonstantin Belousov 726aea81038SKonstantin Belousov vdso_th->th_x86_shift = (int)(intptr_t)timecounter->tc_priv; 727aea81038SKonstantin Belousov bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 728aea81038SKonstantin Belousov return (timecounter == &tsc_timecounter); 729aea81038SKonstantin Belousov } 730aea81038SKonstantin Belousov 731aea81038SKonstantin Belousov #ifdef COMPAT_FREEBSD32 732aea81038SKonstantin Belousov uint32_t 733aea81038SKonstantin Belousov cpu_fill_vdso_timehands32(struct vdso_timehands32 *vdso_th32) 734aea81038SKonstantin Belousov { 735aea81038SKonstantin Belousov 736aea81038SKonstantin Belousov vdso_th32->th_x86_shift = (int)(intptr_t)timecounter->tc_priv; 737aea81038SKonstantin Belousov bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 738aea81038SKonstantin Belousov return (timecounter == &tsc_timecounter); 739aea81038SKonstantin Belousov } 740aea81038SKonstantin Belousov #endif 741