1dd7d207dSJung-uk Kim /*- 2ebf5747bSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3ebf5747bSPedro F. Giffuni * 4dd7d207dSJung-uk Kim * Copyright (c) 1998-2003 Poul-Henning Kamp 5dd7d207dSJung-uk Kim * All rights reserved. 6dd7d207dSJung-uk Kim * 7dd7d207dSJung-uk Kim * Redistribution and use in source and binary forms, with or without 8dd7d207dSJung-uk Kim * modification, are permitted provided that the following conditions 9dd7d207dSJung-uk Kim * are met: 10dd7d207dSJung-uk Kim * 1. Redistributions of source code must retain the above copyright 11dd7d207dSJung-uk Kim * notice, this list of conditions and the following disclaimer. 12dd7d207dSJung-uk Kim * 2. Redistributions in binary form must reproduce the above copyright 13dd7d207dSJung-uk Kim * notice, this list of conditions and the following disclaimer in the 14dd7d207dSJung-uk Kim * documentation and/or other materials provided with the distribution. 15dd7d207dSJung-uk Kim * 16dd7d207dSJung-uk Kim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17dd7d207dSJung-uk Kim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18dd7d207dSJung-uk Kim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19dd7d207dSJung-uk Kim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20dd7d207dSJung-uk Kim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21dd7d207dSJung-uk Kim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22dd7d207dSJung-uk Kim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23dd7d207dSJung-uk Kim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24dd7d207dSJung-uk Kim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25dd7d207dSJung-uk Kim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26dd7d207dSJung-uk Kim * SUCH DAMAGE. 27dd7d207dSJung-uk Kim */ 28dd7d207dSJung-uk Kim 29dd7d207dSJung-uk Kim #include <sys/cdefs.h> 30dd7d207dSJung-uk Kim __FBSDID("$FreeBSD$"); 31dd7d207dSJung-uk Kim 32aea81038SKonstantin Belousov #include "opt_compat.h" 33dd7d207dSJung-uk Kim #include "opt_clock.h" 34dd7d207dSJung-uk Kim 35dd7d207dSJung-uk Kim #include <sys/param.h> 36dd7d207dSJung-uk Kim #include <sys/bus.h> 37dd7d207dSJung-uk Kim #include <sys/cpu.h> 385da5812bSJung-uk Kim #include <sys/limits.h> 39dd7d207dSJung-uk Kim #include <sys/malloc.h> 40dd7d207dSJung-uk Kim #include <sys/systm.h> 41dd7d207dSJung-uk Kim #include <sys/sysctl.h> 42dd7d207dSJung-uk Kim #include <sys/time.h> 43dd7d207dSJung-uk Kim #include <sys/timetc.h> 44dd7d207dSJung-uk Kim #include <sys/kernel.h> 45dd7d207dSJung-uk Kim #include <sys/power.h> 46dd7d207dSJung-uk Kim #include <sys/smp.h> 47aea81038SKonstantin Belousov #include <sys/vdso.h> 48dd7d207dSJung-uk Kim #include <machine/clock.h> 49dd7d207dSJung-uk Kim #include <machine/cputypes.h> 50dd7d207dSJung-uk Kim #include <machine/md_var.h> 51dd7d207dSJung-uk Kim #include <machine/specialreg.h> 5201e1933dSJohn Baldwin #include <x86/vmware.h> 5316808549SKonstantin Belousov #include <dev/acpica/acpi_hpet.h> 54dd7d207dSJung-uk Kim 55dd7d207dSJung-uk Kim #include "cpufreq_if.h" 56dd7d207dSJung-uk Kim 57dd7d207dSJung-uk Kim uint64_t tsc_freq; 58dd7d207dSJung-uk Kim int tsc_is_invariant; 59155094d7SJung-uk Kim int tsc_perf_stat; 60155094d7SJung-uk Kim 61dd7d207dSJung-uk Kim static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag; 62dd7d207dSJung-uk Kim 63dd7d207dSJung-uk Kim SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN, 64dd7d207dSJung-uk Kim &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant"); 65dd7d207dSJung-uk Kim 66dd7d207dSJung-uk Kim #ifdef SMP 671472b87fSNeel Natu int smp_tsc; 68dd7d207dSJung-uk Kim SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0, 69dd7d207dSJung-uk Kim "Indicates whether the TSC is safe to use in SMP mode"); 70b2c63698SAlexander Motin 71b2c63698SAlexander Motin int smp_tsc_adjust = 0; 72b2c63698SAlexander Motin SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN, 73b2c63698SAlexander Motin &smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP"); 74dd7d207dSJung-uk Kim #endif 75dd7d207dSJung-uk Kim 76e7f1427dSKonstantin Belousov static int tsc_shift = 1; 77e7f1427dSKonstantin Belousov SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN, 78e7f1427dSKonstantin Belousov &tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency"); 79e7f1427dSKonstantin Belousov 8079422085SJung-uk Kim static int tsc_disabled; 8179422085SJung-uk Kim SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0, 8279422085SJung-uk Kim "Disable x86 Time Stamp Counter"); 8379422085SJung-uk Kim 84a4e4127fSJung-uk Kim static int tsc_skip_calibration; 85a4e4127fSJung-uk Kim SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN, 86a4e4127fSJung-uk Kim &tsc_skip_calibration, 0, "Disable TSC frequency calibration"); 87a4e4127fSJung-uk Kim 88dd7d207dSJung-uk Kim static void tsc_freq_changed(void *arg, const struct cf_level *level, 89dd7d207dSJung-uk Kim int status); 90dd7d207dSJung-uk Kim static void tsc_freq_changing(void *arg, const struct cf_level *level, 91dd7d207dSJung-uk Kim int *status); 92dd7d207dSJung-uk Kim static unsigned tsc_get_timecount(struct timecounter *tc); 93814124c3SKonstantin Belousov static inline unsigned tsc_get_timecount_low(struct timecounter *tc); 94814124c3SKonstantin Belousov static unsigned tsc_get_timecount_lfence(struct timecounter *tc); 95814124c3SKonstantin Belousov static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc); 96814124c3SKonstantin Belousov static unsigned tsc_get_timecount_mfence(struct timecounter *tc); 97814124c3SKonstantin Belousov static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc); 98dd7d207dSJung-uk Kim static void tsc_levels_changed(void *arg, int unit); 9916808549SKonstantin Belousov static uint32_t x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, 10016808549SKonstantin Belousov struct timecounter *tc); 10116808549SKonstantin Belousov #ifdef COMPAT_FREEBSD32 10216808549SKonstantin Belousov static uint32_t x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 10316808549SKonstantin Belousov struct timecounter *tc); 10416808549SKonstantin Belousov #endif 105dd7d207dSJung-uk Kim 106dd7d207dSJung-uk Kim static struct timecounter tsc_timecounter = { 10716808549SKonstantin Belousov .tc_get_timecount = tsc_get_timecount, 10816808549SKonstantin Belousov .tc_counter_mask = ~0u, 10916808549SKonstantin Belousov .tc_name = "TSC", 11016808549SKonstantin Belousov .tc_quality = 800, /* adjusted in code */ 11116808549SKonstantin Belousov .tc_fill_vdso_timehands = x86_tsc_vdso_timehands, 11216808549SKonstantin Belousov #ifdef COMPAT_FREEBSD32 11316808549SKonstantin Belousov .tc_fill_vdso_timehands32 = x86_tsc_vdso_timehands32, 11416808549SKonstantin Belousov #endif 115dd7d207dSJung-uk Kim }; 116dd7d207dSJung-uk Kim 11701e1933dSJohn Baldwin static void 1185da5812bSJung-uk Kim tsc_freq_vmware(void) 1195da5812bSJung-uk Kim { 1205da5812bSJung-uk Kim u_int regs[4]; 1215da5812bSJung-uk Kim 1225da5812bSJung-uk Kim if (hv_high >= 0x40000010) { 1235da5812bSJung-uk Kim do_cpuid(0x40000010, regs); 1245da5812bSJung-uk Kim tsc_freq = regs[0] * 1000; 1255da5812bSJung-uk Kim } else { 1265da5812bSJung-uk Kim vmware_hvcall(VMW_HVCMD_GETHZ, regs); 1275da5812bSJung-uk Kim if (regs[1] != UINT_MAX) 1285da5812bSJung-uk Kim tsc_freq = regs[0] | ((uint64_t)regs[1] << 32); 1295da5812bSJung-uk Kim } 1305da5812bSJung-uk Kim tsc_is_invariant = 1; 1315da5812bSJung-uk Kim } 1325da5812bSJung-uk Kim 133a4e4127fSJung-uk Kim static void 134a4e4127fSJung-uk Kim tsc_freq_intel(void) 135dd7d207dSJung-uk Kim { 136a4e4127fSJung-uk Kim char brand[48]; 137a4e4127fSJung-uk Kim u_int regs[4]; 138a4e4127fSJung-uk Kim uint64_t freq; 139a4e4127fSJung-uk Kim char *p; 140a4e4127fSJung-uk Kim u_int i; 141dd7d207dSJung-uk Kim 142a4e4127fSJung-uk Kim /* 143a4e4127fSJung-uk Kim * Intel Processor Identification and the CPUID Instruction 144a4e4127fSJung-uk Kim * Application Note 485. 145a4e4127fSJung-uk Kim * http://www.intel.com/assets/pdf/appnote/241618.pdf 146a4e4127fSJung-uk Kim */ 147a4e4127fSJung-uk Kim if (cpu_exthigh >= 0x80000004) { 148a4e4127fSJung-uk Kim p = brand; 149a4e4127fSJung-uk Kim for (i = 0x80000002; i < 0x80000005; i++) { 150a4e4127fSJung-uk Kim do_cpuid(i, regs); 151a4e4127fSJung-uk Kim memcpy(p, regs, sizeof(regs)); 152a4e4127fSJung-uk Kim p += sizeof(regs); 153a4e4127fSJung-uk Kim } 154a4e4127fSJung-uk Kim p = NULL; 155a4e4127fSJung-uk Kim for (i = 0; i < sizeof(brand) - 1; i++) 156a4e4127fSJung-uk Kim if (brand[i] == 'H' && brand[i + 1] == 'z') 157a4e4127fSJung-uk Kim p = brand + i; 158a4e4127fSJung-uk Kim if (p != NULL) { 159a4e4127fSJung-uk Kim p -= 5; 160a4e4127fSJung-uk Kim switch (p[4]) { 161a4e4127fSJung-uk Kim case 'M': 162a4e4127fSJung-uk Kim i = 1; 163a4e4127fSJung-uk Kim break; 164a4e4127fSJung-uk Kim case 'G': 165a4e4127fSJung-uk Kim i = 1000; 166a4e4127fSJung-uk Kim break; 167a4e4127fSJung-uk Kim case 'T': 168a4e4127fSJung-uk Kim i = 1000000; 169a4e4127fSJung-uk Kim break; 170a4e4127fSJung-uk Kim default: 171dd7d207dSJung-uk Kim return; 172a4e4127fSJung-uk Kim } 173a4e4127fSJung-uk Kim #define C2D(c) ((c) - '0') 174a4e4127fSJung-uk Kim if (p[1] == '.') { 175a4e4127fSJung-uk Kim freq = C2D(p[0]) * 1000; 176a4e4127fSJung-uk Kim freq += C2D(p[2]) * 100; 177a4e4127fSJung-uk Kim freq += C2D(p[3]) * 10; 178a4e4127fSJung-uk Kim freq *= i * 1000; 179a4e4127fSJung-uk Kim } else { 180a4e4127fSJung-uk Kim freq = C2D(p[0]) * 1000; 181a4e4127fSJung-uk Kim freq += C2D(p[1]) * 100; 182a4e4127fSJung-uk Kim freq += C2D(p[2]) * 10; 183a4e4127fSJung-uk Kim freq += C2D(p[3]); 184a4e4127fSJung-uk Kim freq *= i * 1000000; 185a4e4127fSJung-uk Kim } 186a4e4127fSJung-uk Kim #undef C2D 187a4e4127fSJung-uk Kim tsc_freq = freq; 188a4e4127fSJung-uk Kim } 189a4e4127fSJung-uk Kim } 190a4e4127fSJung-uk Kim } 191dd7d207dSJung-uk Kim 192a4e4127fSJung-uk Kim static void 193a4e4127fSJung-uk Kim probe_tsc_freq(void) 194a4e4127fSJung-uk Kim { 195155094d7SJung-uk Kim u_int regs[4]; 196a4e4127fSJung-uk Kim uint64_t tsc1, tsc2; 197dd7d207dSJung-uk Kim 1985da5812bSJung-uk Kim if (cpu_high >= 6) { 1995da5812bSJung-uk Kim do_cpuid(6, regs); 2005da5812bSJung-uk Kim if ((regs[2] & CPUID_PERF_STAT) != 0) { 2015da5812bSJung-uk Kim /* 2025da5812bSJung-uk Kim * XXX Some emulators expose host CPUID without actual 2035da5812bSJung-uk Kim * support for these MSRs. We must test whether they 2045da5812bSJung-uk Kim * really work. 2055da5812bSJung-uk Kim */ 2065da5812bSJung-uk Kim wrmsr(MSR_MPERF, 0); 2075da5812bSJung-uk Kim wrmsr(MSR_APERF, 0); 2085da5812bSJung-uk Kim DELAY(10); 2095da5812bSJung-uk Kim if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0) 2105da5812bSJung-uk Kim tsc_perf_stat = 1; 2115da5812bSJung-uk Kim } 2125da5812bSJung-uk Kim } 2135da5812bSJung-uk Kim 21401e1933dSJohn Baldwin if (vm_guest == VM_GUEST_VMWARE) { 21501e1933dSJohn Baldwin tsc_freq_vmware(); 2165da5812bSJung-uk Kim return; 21701e1933dSJohn Baldwin } 2185da5812bSJung-uk Kim 219dd7d207dSJung-uk Kim switch (cpu_vendor_id) { 220dd7d207dSJung-uk Kim case CPU_VENDOR_AMD: 221a106a27cSJung-uk Kim if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 222a106a27cSJung-uk Kim (vm_guest == VM_GUEST_NO && 223a106a27cSJung-uk Kim CPUID_TO_FAMILY(cpu_id) >= 0x10)) 224dd7d207dSJung-uk Kim tsc_is_invariant = 1; 225814124c3SKonstantin Belousov if (cpu_feature & CPUID_SSE2) { 226814124c3SKonstantin Belousov tsc_timecounter.tc_get_timecount = 227814124c3SKonstantin Belousov tsc_get_timecount_mfence; 228814124c3SKonstantin Belousov } 229dd7d207dSJung-uk Kim break; 230dd7d207dSJung-uk Kim case CPU_VENDOR_INTEL: 231a106a27cSJung-uk Kim if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 232a106a27cSJung-uk Kim (vm_guest == VM_GUEST_NO && 233a106a27cSJung-uk Kim ((CPUID_TO_FAMILY(cpu_id) == 0x6 && 234dd7d207dSJung-uk Kim CPUID_TO_MODEL(cpu_id) >= 0xe) || 235dd7d207dSJung-uk Kim (CPUID_TO_FAMILY(cpu_id) == 0xf && 236a106a27cSJung-uk Kim CPUID_TO_MODEL(cpu_id) >= 0x3)))) 237dd7d207dSJung-uk Kim tsc_is_invariant = 1; 238814124c3SKonstantin Belousov if (cpu_feature & CPUID_SSE2) { 239814124c3SKonstantin Belousov tsc_timecounter.tc_get_timecount = 240814124c3SKonstantin Belousov tsc_get_timecount_lfence; 241814124c3SKonstantin Belousov } 242dd7d207dSJung-uk Kim break; 243dd7d207dSJung-uk Kim case CPU_VENDOR_CENTAUR: 244a106a27cSJung-uk Kim if (vm_guest == VM_GUEST_NO && 245a106a27cSJung-uk Kim CPUID_TO_FAMILY(cpu_id) == 0x6 && 246dd7d207dSJung-uk Kim CPUID_TO_MODEL(cpu_id) >= 0xf && 247dd7d207dSJung-uk Kim (rdmsr(0x1203) & 0x100000000ULL) == 0) 248dd7d207dSJung-uk Kim tsc_is_invariant = 1; 249814124c3SKonstantin Belousov if (cpu_feature & CPUID_SSE2) { 250814124c3SKonstantin Belousov tsc_timecounter.tc_get_timecount = 251814124c3SKonstantin Belousov tsc_get_timecount_lfence; 252814124c3SKonstantin Belousov } 253dd7d207dSJung-uk Kim break; 254dd7d207dSJung-uk Kim } 255dd7d207dSJung-uk Kim 256a4e4127fSJung-uk Kim if (tsc_skip_calibration) { 257a4e4127fSJung-uk Kim if (cpu_vendor_id == CPU_VENDOR_INTEL) 258a4e4127fSJung-uk Kim tsc_freq_intel(); 259a4e4127fSJung-uk Kim return; 260a4e4127fSJung-uk Kim } 261a4e4127fSJung-uk Kim 262a4e4127fSJung-uk Kim if (bootverbose) 263a4e4127fSJung-uk Kim printf("Calibrating TSC clock ... "); 264a4e4127fSJung-uk Kim tsc1 = rdtsc(); 265a4e4127fSJung-uk Kim DELAY(1000000); 266a4e4127fSJung-uk Kim tsc2 = rdtsc(); 267a4e4127fSJung-uk Kim tsc_freq = tsc2 - tsc1; 268a4e4127fSJung-uk Kim if (bootverbose) 269a4e4127fSJung-uk Kim printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq); 270a4e4127fSJung-uk Kim } 271a4e4127fSJung-uk Kim 272a4e4127fSJung-uk Kim void 273a4e4127fSJung-uk Kim init_TSC(void) 274a4e4127fSJung-uk Kim { 275a4e4127fSJung-uk Kim 276a4e4127fSJung-uk Kim if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) 277a4e4127fSJung-uk Kim return; 278a4e4127fSJung-uk Kim 279fe760cfaSJohn Baldwin #ifdef __i386__ 280fe760cfaSJohn Baldwin /* The TSC is known to be broken on certain CPUs. */ 281fe760cfaSJohn Baldwin switch (cpu_vendor_id) { 282fe760cfaSJohn Baldwin case CPU_VENDOR_AMD: 283fe760cfaSJohn Baldwin switch (cpu_id & 0xFF0) { 284fe760cfaSJohn Baldwin case 0x500: 285fe760cfaSJohn Baldwin /* K5 Model 0 */ 286fe760cfaSJohn Baldwin return; 287fe760cfaSJohn Baldwin } 288fe760cfaSJohn Baldwin break; 289fe760cfaSJohn Baldwin case CPU_VENDOR_CENTAUR: 290fe760cfaSJohn Baldwin switch (cpu_id & 0xff0) { 291fe760cfaSJohn Baldwin case 0x540: 292fe760cfaSJohn Baldwin /* 293fe760cfaSJohn Baldwin * http://www.centtech.com/c6_data_sheet.pdf 294fe760cfaSJohn Baldwin * 295fe760cfaSJohn Baldwin * I-12 RDTSC may return incoherent values in EDX:EAX 296fe760cfaSJohn Baldwin * I-13 RDTSC hangs when certain event counters are used 297fe760cfaSJohn Baldwin */ 298fe760cfaSJohn Baldwin return; 299fe760cfaSJohn Baldwin } 300fe760cfaSJohn Baldwin break; 301fe760cfaSJohn Baldwin case CPU_VENDOR_NSC: 302fe760cfaSJohn Baldwin switch (cpu_id & 0xff0) { 303fe760cfaSJohn Baldwin case 0x540: 304fe760cfaSJohn Baldwin if ((cpu_id & CPUID_STEPPING) == 0) 305fe760cfaSJohn Baldwin return; 306fe760cfaSJohn Baldwin break; 307fe760cfaSJohn Baldwin } 308fe760cfaSJohn Baldwin break; 309fe760cfaSJohn Baldwin } 310fe760cfaSJohn Baldwin #endif 311fe760cfaSJohn Baldwin 312a4e4127fSJung-uk Kim probe_tsc_freq(); 313a4e4127fSJung-uk Kim 314dd7d207dSJung-uk Kim /* 315dd7d207dSJung-uk Kim * Inform CPU accounting about our boot-time clock rate. This will 316dd7d207dSJung-uk Kim * be updated if someone loads a cpufreq driver after boot that 317dd7d207dSJung-uk Kim * discovers a new max frequency. 318dd7d207dSJung-uk Kim */ 319a4e4127fSJung-uk Kim if (tsc_freq != 0) 3205ac44f72SJung-uk Kim set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant); 321dd7d207dSJung-uk Kim 322dd7d207dSJung-uk Kim if (tsc_is_invariant) 323dd7d207dSJung-uk Kim return; 324dd7d207dSJung-uk Kim 325dd7d207dSJung-uk Kim /* Register to find out about changes in CPU frequency. */ 326dd7d207dSJung-uk Kim tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change, 327dd7d207dSJung-uk Kim tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST); 328dd7d207dSJung-uk Kim tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 329dd7d207dSJung-uk Kim tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST); 330dd7d207dSJung-uk Kim tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed, 331dd7d207dSJung-uk Kim tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY); 332dd7d207dSJung-uk Kim } 333dd7d207dSJung-uk Kim 33465e7d70bSJung-uk Kim #ifdef SMP 33565e7d70bSJung-uk Kim 336814124c3SKonstantin Belousov /* 337814124c3SKonstantin Belousov * RDTSC is not a serializing instruction, and does not drain 338814124c3SKonstantin Belousov * instruction stream, so we need to drain the stream before executing 339814124c3SKonstantin Belousov * it. It could be fixed by use of RDTSCP, except the instruction is 340814124c3SKonstantin Belousov * not available everywhere. 341814124c3SKonstantin Belousov * 342814124c3SKonstantin Belousov * Use CPUID for draining in the boot-time SMP constistency test. The 343814124c3SKonstantin Belousov * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel 344814124c3SKonstantin Belousov * and VIA) when SSE2 is present, and nothing on older machines which 345814124c3SKonstantin Belousov * also do not issue RDTSC prematurely. There, testing for SSE2 and 346e1a18e46SKonstantin Belousov * vendor is too cumbersome, and we learn about TSC presence from CPUID. 347814124c3SKonstantin Belousov * 348814124c3SKonstantin Belousov * Do not use do_cpuid(), since we do not need CPUID results, which 349814124c3SKonstantin Belousov * have to be written into memory with do_cpuid(). 350814124c3SKonstantin Belousov */ 35165e7d70bSJung-uk Kim #define TSC_READ(x) \ 35265e7d70bSJung-uk Kim static void \ 35365e7d70bSJung-uk Kim tsc_read_##x(void *arg) \ 35465e7d70bSJung-uk Kim { \ 3557bfcb3bbSJim Harris uint64_t *tsc = arg; \ 35665e7d70bSJung-uk Kim u_int cpu = PCPU_GET(cpuid); \ 35765e7d70bSJung-uk Kim \ 358814124c3SKonstantin Belousov __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx"); \ 3597bfcb3bbSJim Harris tsc[cpu * 3 + x] = rdtsc(); \ 36065e7d70bSJung-uk Kim } 36165e7d70bSJung-uk Kim TSC_READ(0) 36265e7d70bSJung-uk Kim TSC_READ(1) 36365e7d70bSJung-uk Kim TSC_READ(2) 36465e7d70bSJung-uk Kim #undef TSC_READ 36565e7d70bSJung-uk Kim 36665e7d70bSJung-uk Kim #define N 1000 36765e7d70bSJung-uk Kim 36865e7d70bSJung-uk Kim static void 36965e7d70bSJung-uk Kim comp_smp_tsc(void *arg) 37065e7d70bSJung-uk Kim { 3717bfcb3bbSJim Harris uint64_t *tsc; 3727bfcb3bbSJim Harris int64_t d1, d2; 37365e7d70bSJung-uk Kim u_int cpu = PCPU_GET(cpuid); 37465e7d70bSJung-uk Kim u_int i, j, size; 37565e7d70bSJung-uk Kim 37665e7d70bSJung-uk Kim size = (mp_maxid + 1) * 3; 37765e7d70bSJung-uk Kim for (i = 0, tsc = arg; i < N; i++, tsc += size) 37865e7d70bSJung-uk Kim CPU_FOREACH(j) { 37965e7d70bSJung-uk Kim if (j == cpu) 38065e7d70bSJung-uk Kim continue; 38165e7d70bSJung-uk Kim d1 = tsc[cpu * 3 + 1] - tsc[j * 3]; 38265e7d70bSJung-uk Kim d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1]; 38365e7d70bSJung-uk Kim if (d1 <= 0 || d2 <= 0) { 38465e7d70bSJung-uk Kim smp_tsc = 0; 38565e7d70bSJung-uk Kim return; 38665e7d70bSJung-uk Kim } 38765e7d70bSJung-uk Kim } 38865e7d70bSJung-uk Kim } 38965e7d70bSJung-uk Kim 390b2c63698SAlexander Motin static void 391b2c63698SAlexander Motin adj_smp_tsc(void *arg) 392b2c63698SAlexander Motin { 393b2c63698SAlexander Motin uint64_t *tsc; 394b2c63698SAlexander Motin int64_t d, min, max; 395b2c63698SAlexander Motin u_int cpu = PCPU_GET(cpuid); 396b2c63698SAlexander Motin u_int first, i, size; 397b2c63698SAlexander Motin 398b2c63698SAlexander Motin first = CPU_FIRST(); 399b2c63698SAlexander Motin if (cpu == first) 400b2c63698SAlexander Motin return; 401b2c63698SAlexander Motin min = INT64_MIN; 402b2c63698SAlexander Motin max = INT64_MAX; 403b2c63698SAlexander Motin size = (mp_maxid + 1) * 3; 404b2c63698SAlexander Motin for (i = 0, tsc = arg; i < N; i++, tsc += size) { 405b2c63698SAlexander Motin d = tsc[first * 3] - tsc[cpu * 3 + 1]; 406b2c63698SAlexander Motin if (d > min) 407b2c63698SAlexander Motin min = d; 408b2c63698SAlexander Motin d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2]; 409b2c63698SAlexander Motin if (d > min) 410b2c63698SAlexander Motin min = d; 411b2c63698SAlexander Motin d = tsc[first * 3 + 1] - tsc[cpu * 3]; 412b2c63698SAlexander Motin if (d < max) 413b2c63698SAlexander Motin max = d; 414b2c63698SAlexander Motin d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1]; 415b2c63698SAlexander Motin if (d < max) 416b2c63698SAlexander Motin max = d; 417b2c63698SAlexander Motin } 418b2c63698SAlexander Motin if (min > max) 419b2c63698SAlexander Motin return; 420b2c63698SAlexander Motin d = min / 2 + max / 2; 421b2c63698SAlexander Motin __asm __volatile ( 422b2c63698SAlexander Motin "movl $0x10, %%ecx\n\t" 423b2c63698SAlexander Motin "rdmsr\n\t" 424b2c63698SAlexander Motin "addl %%edi, %%eax\n\t" 425b2c63698SAlexander Motin "adcl %%esi, %%edx\n\t" 426b2c63698SAlexander Motin "wrmsr\n" 427b2c63698SAlexander Motin : /* No output */ 428b2c63698SAlexander Motin : "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32)) 429b2c63698SAlexander Motin : "ax", "cx", "dx", "cc" 430b2c63698SAlexander Motin ); 431b2c63698SAlexander Motin } 432b2c63698SAlexander Motin 43365e7d70bSJung-uk Kim static int 434e7f1427dSKonstantin Belousov test_tsc(void) 43565e7d70bSJung-uk Kim { 4367bfcb3bbSJim Harris uint64_t *data, *tsc; 437b2c63698SAlexander Motin u_int i, size, adj; 43865e7d70bSJung-uk Kim 439e7f1427dSKonstantin Belousov if ((!smp_tsc && !tsc_is_invariant) || vm_guest) 44065e7d70bSJung-uk Kim return (-100); 44165e7d70bSJung-uk Kim size = (mp_maxid + 1) * 3; 44265e7d70bSJung-uk Kim data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK); 443b2c63698SAlexander Motin adj = 0; 444b2c63698SAlexander Motin retry: 44565e7d70bSJung-uk Kim for (i = 0, tsc = data; i < N; i++, tsc += size) 44665e7d70bSJung-uk Kim smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc); 44765e7d70bSJung-uk Kim smp_tsc = 1; /* XXX */ 44867d955aaSPatrick Kelsey smp_rendezvous(smp_no_rendezvous_barrier, comp_smp_tsc, 44967d955aaSPatrick Kelsey smp_no_rendezvous_barrier, data); 450b2c63698SAlexander Motin if (!smp_tsc && adj < smp_tsc_adjust) { 451b2c63698SAlexander Motin adj++; 45267d955aaSPatrick Kelsey smp_rendezvous(smp_no_rendezvous_barrier, adj_smp_tsc, 45367d955aaSPatrick Kelsey smp_no_rendezvous_barrier, data); 454b2c63698SAlexander Motin goto retry; 455b2c63698SAlexander Motin } 45665e7d70bSJung-uk Kim free(data, M_TEMP); 45765e7d70bSJung-uk Kim if (bootverbose) 458b2c63698SAlexander Motin printf("SMP: %sed TSC synchronization test%s\n", 459b2c63698SAlexander Motin smp_tsc ? "pass" : "fail", 460b2c63698SAlexander Motin adj > 0 ? " after adjustment" : ""); 46126e6537aSJung-uk Kim if (smp_tsc && tsc_is_invariant) { 46226e6537aSJung-uk Kim switch (cpu_vendor_id) { 46326e6537aSJung-uk Kim case CPU_VENDOR_AMD: 46426e6537aSJung-uk Kim /* 46526e6537aSJung-uk Kim * Starting with Family 15h processors, TSC clock 46626e6537aSJung-uk Kim * source is in the north bridge. Check whether 46726e6537aSJung-uk Kim * we have a single-socket/multi-core platform. 46826e6537aSJung-uk Kim * XXX Need more work for complex cases. 46926e6537aSJung-uk Kim */ 47026e6537aSJung-uk Kim if (CPUID_TO_FAMILY(cpu_id) < 0x15 || 47126e6537aSJung-uk Kim (amd_feature2 & AMDID2_CMP) == 0 || 47226e6537aSJung-uk Kim smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1) 47326e6537aSJung-uk Kim break; 47426e6537aSJung-uk Kim return (1000); 47526e6537aSJung-uk Kim case CPU_VENDOR_INTEL: 47626e6537aSJung-uk Kim /* 47726e6537aSJung-uk Kim * XXX Assume Intel platforms have synchronized TSCs. 47826e6537aSJung-uk Kim */ 47926e6537aSJung-uk Kim return (1000); 48026e6537aSJung-uk Kim } 48126e6537aSJung-uk Kim return (800); 48226e6537aSJung-uk Kim } 48326e6537aSJung-uk Kim return (-100); 48465e7d70bSJung-uk Kim } 48565e7d70bSJung-uk Kim 48665e7d70bSJung-uk Kim #undef N 48765e7d70bSJung-uk Kim 488e7f1427dSKonstantin Belousov #else 489e7f1427dSKonstantin Belousov 490e7f1427dSKonstantin Belousov /* 491e7f1427dSKonstantin Belousov * The function is not called, it is provided to avoid linking failure 492e7f1427dSKonstantin Belousov * on uniprocessor kernel. 493e7f1427dSKonstantin Belousov */ 494e7f1427dSKonstantin Belousov static int 495e7f1427dSKonstantin Belousov test_tsc(void) 496e7f1427dSKonstantin Belousov { 497e7f1427dSKonstantin Belousov 498e7f1427dSKonstantin Belousov return (0); 499e7f1427dSKonstantin Belousov } 500e7f1427dSKonstantin Belousov 50165e7d70bSJung-uk Kim #endif /* SMP */ 50265e7d70bSJung-uk Kim 50365e7d70bSJung-uk Kim static void 504dd7d207dSJung-uk Kim init_TSC_tc(void) 505dd7d207dSJung-uk Kim { 50695f2f098SJung-uk Kim uint64_t max_freq; 50795f2f098SJung-uk Kim int shift; 508dd7d207dSJung-uk Kim 50938b8542cSJung-uk Kim if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) 510dd7d207dSJung-uk Kim return; 511dd7d207dSJung-uk Kim 512dd7d207dSJung-uk Kim /* 51395f2f098SJung-uk Kim * Limit timecounter frequency to fit in an int and prevent it from 51495f2f098SJung-uk Kim * overflowing too fast. 51595f2f098SJung-uk Kim */ 51695f2f098SJung-uk Kim max_freq = UINT_MAX; 51795f2f098SJung-uk Kim 51895f2f098SJung-uk Kim /* 519dd7d207dSJung-uk Kim * We can not use the TSC if we support APM. Precise timekeeping 520dd7d207dSJung-uk Kim * on an APM'ed machine is at best a fools pursuit, since 521dd7d207dSJung-uk Kim * any and all of the time spent in various SMM code can't 522dd7d207dSJung-uk Kim * be reliably accounted for. Reading the RTC is your only 523dd7d207dSJung-uk Kim * source of reliable time info. The i8254 loses too, of course, 524dd7d207dSJung-uk Kim * but we need to have some kind of time... 525dd7d207dSJung-uk Kim * We don't know at this point whether APM is going to be used 526dd7d207dSJung-uk Kim * or not, nor when it might be activated. Play it safe. 527dd7d207dSJung-uk Kim */ 528dd7d207dSJung-uk Kim if (power_pm_get_type() == POWER_PM_TYPE_APM) { 529dd7d207dSJung-uk Kim tsc_timecounter.tc_quality = -1000; 530dd7d207dSJung-uk Kim if (bootverbose) 531dd7d207dSJung-uk Kim printf("TSC timecounter disabled: APM enabled.\n"); 53265e7d70bSJung-uk Kim goto init; 533dd7d207dSJung-uk Kim } 534dd7d207dSJung-uk Kim 535a49399a9SJung-uk Kim /* 53692597e06SJohn Baldwin * Intel CPUs without a C-state invariant TSC can stop the TSC 537d1411416SJohn Baldwin * in either C2 or C3. Disable use of C2 and C3 while using 538d1411416SJohn Baldwin * the TSC as the timecounter. The timecounter can be changed 539d1411416SJohn Baldwin * to enable C2 and C3. 540d1411416SJohn Baldwin * 541d1411416SJohn Baldwin * Note that the TSC is used as the cputicker for computing 542d1411416SJohn Baldwin * thread runtime regardless of the timecounter setting, so 543d1411416SJohn Baldwin * using an alternate timecounter and enabling C2 or C3 can 544d1411416SJohn Baldwin * result incorrect runtimes for kernel idle threads (but not 545d1411416SJohn Baldwin * for any non-idle threads). 546a49399a9SJung-uk Kim */ 5478cd59625SKonstantin Belousov if (cpu_vendor_id == CPU_VENDOR_INTEL && 548a49399a9SJung-uk Kim (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) { 54992597e06SJohn Baldwin tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP; 550a49399a9SJung-uk Kim if (bootverbose) 551d1411416SJohn Baldwin printf("TSC timecounter disables C2 and C3.\n"); 552a49399a9SJung-uk Kim } 553a49399a9SJung-uk Kim 554dd7d207dSJung-uk Kim /* 555e7f1427dSKonstantin Belousov * We can not use the TSC in SMP mode unless the TSCs on all CPUs 556e7f1427dSKonstantin Belousov * are synchronized. If the user is sure that the system has 557e7f1427dSKonstantin Belousov * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a 558e7f1427dSKonstantin Belousov * non-zero value. The TSC seems unreliable in virtualized SMP 5595cf8ac1bSMike Silbersack * environments, so it is set to a negative quality in those cases. 560dd7d207dSJung-uk Kim */ 561e7f1427dSKonstantin Belousov if (mp_ncpus > 1) 562e7f1427dSKonstantin Belousov tsc_timecounter.tc_quality = test_tsc(); 563e7f1427dSKonstantin Belousov else if (tsc_is_invariant) 56426e6537aSJung-uk Kim tsc_timecounter.tc_quality = 1000; 565e7f1427dSKonstantin Belousov max_freq >>= tsc_shift; 56626e6537aSJung-uk Kim 56765e7d70bSJung-uk Kim init: 568e7f1427dSKonstantin Belousov for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++) 56995f2f098SJung-uk Kim ; 570e7f1427dSKonstantin Belousov if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) { 571814124c3SKonstantin Belousov if (cpu_vendor_id == CPU_VENDOR_AMD) { 572e7f1427dSKonstantin Belousov tsc_timecounter.tc_get_timecount = shift > 0 ? 573e7f1427dSKonstantin Belousov tsc_get_timecount_low_mfence : 574e7f1427dSKonstantin Belousov tsc_get_timecount_mfence; 575814124c3SKonstantin Belousov } else { 576e7f1427dSKonstantin Belousov tsc_timecounter.tc_get_timecount = shift > 0 ? 577e7f1427dSKonstantin Belousov tsc_get_timecount_low_lfence : 578e7f1427dSKonstantin Belousov tsc_get_timecount_lfence; 579814124c3SKonstantin Belousov } 580e7f1427dSKonstantin Belousov } else { 581e7f1427dSKonstantin Belousov tsc_timecounter.tc_get_timecount = shift > 0 ? 582e7f1427dSKonstantin Belousov tsc_get_timecount_low : tsc_get_timecount; 583e7f1427dSKonstantin Belousov } 584e7f1427dSKonstantin Belousov if (shift > 0) { 58595f2f098SJung-uk Kim tsc_timecounter.tc_name = "TSC-low"; 58695f2f098SJung-uk Kim if (bootverbose) 587bc8e4ad2SJung-uk Kim printf("TSC timecounter discards lower %d bit(s)\n", 58895f2f098SJung-uk Kim shift); 58995f2f098SJung-uk Kim } 590bc34c87eSJung-uk Kim if (tsc_freq != 0) { 59195f2f098SJung-uk Kim tsc_timecounter.tc_frequency = tsc_freq >> shift; 59295f2f098SJung-uk Kim tsc_timecounter.tc_priv = (void *)(intptr_t)shift; 593dd7d207dSJung-uk Kim tc_init(&tsc_timecounter); 594dd7d207dSJung-uk Kim } 595dd7d207dSJung-uk Kim } 59665e7d70bSJung-uk Kim SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL); 597dd7d207dSJung-uk Kim 598dd7d207dSJung-uk Kim /* 599dd7d207dSJung-uk Kim * When cpufreq levels change, find out about the (new) max frequency. We 600dd7d207dSJung-uk Kim * use this to update CPU accounting in case it got a lower estimate at boot. 601dd7d207dSJung-uk Kim */ 602dd7d207dSJung-uk Kim static void 603dd7d207dSJung-uk Kim tsc_levels_changed(void *arg, int unit) 604dd7d207dSJung-uk Kim { 605dd7d207dSJung-uk Kim device_t cf_dev; 606dd7d207dSJung-uk Kim struct cf_level *levels; 607dd7d207dSJung-uk Kim int count, error; 608dd7d207dSJung-uk Kim uint64_t max_freq; 609dd7d207dSJung-uk Kim 610dd7d207dSJung-uk Kim /* Only use values from the first CPU, assuming all are equal. */ 611dd7d207dSJung-uk Kim if (unit != 0) 612dd7d207dSJung-uk Kim return; 613dd7d207dSJung-uk Kim 614dd7d207dSJung-uk Kim /* Find the appropriate cpufreq device instance. */ 615dd7d207dSJung-uk Kim cf_dev = devclass_get_device(devclass_find("cpufreq"), unit); 616dd7d207dSJung-uk Kim if (cf_dev == NULL) { 617dd7d207dSJung-uk Kim printf("tsc_levels_changed() called but no cpufreq device?\n"); 618dd7d207dSJung-uk Kim return; 619dd7d207dSJung-uk Kim } 620dd7d207dSJung-uk Kim 621dd7d207dSJung-uk Kim /* Get settings from the device and find the max frequency. */ 622dd7d207dSJung-uk Kim count = 64; 623dd7d207dSJung-uk Kim levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT); 624dd7d207dSJung-uk Kim if (levels == NULL) 625dd7d207dSJung-uk Kim return; 626dd7d207dSJung-uk Kim error = CPUFREQ_LEVELS(cf_dev, levels, &count); 627dd7d207dSJung-uk Kim if (error == 0 && count != 0) { 628dd7d207dSJung-uk Kim max_freq = (uint64_t)levels[0].total_set.freq * 1000000; 629dd7d207dSJung-uk Kim set_cputicker(rdtsc, max_freq, 1); 630dd7d207dSJung-uk Kim } else 631dd7d207dSJung-uk Kim printf("tsc_levels_changed: no max freq found\n"); 632dd7d207dSJung-uk Kim free(levels, M_TEMP); 633dd7d207dSJung-uk Kim } 634dd7d207dSJung-uk Kim 635dd7d207dSJung-uk Kim /* 636dd7d207dSJung-uk Kim * If the TSC timecounter is in use, veto the pending change. It may be 637dd7d207dSJung-uk Kim * possible in the future to handle a dynamically-changing timecounter rate. 638dd7d207dSJung-uk Kim */ 639dd7d207dSJung-uk Kim static void 640dd7d207dSJung-uk Kim tsc_freq_changing(void *arg, const struct cf_level *level, int *status) 641dd7d207dSJung-uk Kim { 642dd7d207dSJung-uk Kim 643dd7d207dSJung-uk Kim if (*status != 0 || timecounter != &tsc_timecounter) 644dd7d207dSJung-uk Kim return; 645dd7d207dSJung-uk Kim 646dd7d207dSJung-uk Kim printf("timecounter TSC must not be in use when " 647dd7d207dSJung-uk Kim "changing frequencies; change denied\n"); 648dd7d207dSJung-uk Kim *status = EBUSY; 649dd7d207dSJung-uk Kim } 650dd7d207dSJung-uk Kim 651dd7d207dSJung-uk Kim /* Update TSC freq with the value indicated by the caller. */ 652dd7d207dSJung-uk Kim static void 653dd7d207dSJung-uk Kim tsc_freq_changed(void *arg, const struct cf_level *level, int status) 654dd7d207dSJung-uk Kim { 6553453537fSJung-uk Kim uint64_t freq; 656dd7d207dSJung-uk Kim 657dd7d207dSJung-uk Kim /* If there was an error during the transition, don't do anything. */ 65879422085SJung-uk Kim if (tsc_disabled || status != 0) 659dd7d207dSJung-uk Kim return; 660dd7d207dSJung-uk Kim 661dd7d207dSJung-uk Kim /* Total setting for this level gives the new frequency in MHz. */ 6623453537fSJung-uk Kim freq = (uint64_t)level->total_set.freq * 1000000; 6633453537fSJung-uk Kim atomic_store_rel_64(&tsc_freq, freq); 66495f2f098SJung-uk Kim tsc_timecounter.tc_frequency = 66595f2f098SJung-uk Kim freq >> (int)(intptr_t)tsc_timecounter.tc_priv; 666dd7d207dSJung-uk Kim } 667dd7d207dSJung-uk Kim 668dd7d207dSJung-uk Kim static int 669dd7d207dSJung-uk Kim sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 670dd7d207dSJung-uk Kim { 671dd7d207dSJung-uk Kim int error; 672dd7d207dSJung-uk Kim uint64_t freq; 673dd7d207dSJung-uk Kim 6743453537fSJung-uk Kim freq = atomic_load_acq_64(&tsc_freq); 6753453537fSJung-uk Kim if (freq == 0) 676dd7d207dSJung-uk Kim return (EOPNOTSUPP); 677cbc134adSMatthew D Fleming error = sysctl_handle_64(oidp, &freq, 0, req); 6787ebbcb21SJung-uk Kim if (error == 0 && req->newptr != NULL) { 6793453537fSJung-uk Kim atomic_store_rel_64(&tsc_freq, freq); 680bc8e4ad2SJung-uk Kim atomic_store_rel_64(&tsc_timecounter.tc_frequency, 681bc8e4ad2SJung-uk Kim freq >> (int)(intptr_t)tsc_timecounter.tc_priv); 6827ebbcb21SJung-uk Kim } 683dd7d207dSJung-uk Kim return (error); 684dd7d207dSJung-uk Kim } 685dd7d207dSJung-uk Kim 686cbc134adSMatthew D Fleming SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_U64 | CTLFLAG_RW, 6875331d61dSJung-uk Kim 0, 0, sysctl_machdep_tsc_freq, "QU", "Time Stamp Counter frequency"); 688dd7d207dSJung-uk Kim 689727c7b2dSJung-uk Kim static u_int 69095f2f098SJung-uk Kim tsc_get_timecount(struct timecounter *tc __unused) 691dd7d207dSJung-uk Kim { 692727c7b2dSJung-uk Kim 693727c7b2dSJung-uk Kim return (rdtsc32()); 694dd7d207dSJung-uk Kim } 69595f2f098SJung-uk Kim 696814124c3SKonstantin Belousov static inline u_int 697bc8e4ad2SJung-uk Kim tsc_get_timecount_low(struct timecounter *tc) 69895f2f098SJung-uk Kim { 6995df88f46SJung-uk Kim uint32_t rv; 70095f2f098SJung-uk Kim 7015df88f46SJung-uk Kim __asm __volatile("rdtsc; shrd %%cl, %%edx, %0" 7025df88f46SJung-uk Kim : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx"); 7035df88f46SJung-uk Kim return (rv); 70495f2f098SJung-uk Kim } 705aea81038SKonstantin Belousov 706814124c3SKonstantin Belousov static u_int 707814124c3SKonstantin Belousov tsc_get_timecount_lfence(struct timecounter *tc __unused) 708814124c3SKonstantin Belousov { 709814124c3SKonstantin Belousov 710814124c3SKonstantin Belousov lfence(); 711814124c3SKonstantin Belousov return (rdtsc32()); 712814124c3SKonstantin Belousov } 713814124c3SKonstantin Belousov 714814124c3SKonstantin Belousov static u_int 715814124c3SKonstantin Belousov tsc_get_timecount_low_lfence(struct timecounter *tc) 716814124c3SKonstantin Belousov { 717814124c3SKonstantin Belousov 718814124c3SKonstantin Belousov lfence(); 719814124c3SKonstantin Belousov return (tsc_get_timecount_low(tc)); 720814124c3SKonstantin Belousov } 721814124c3SKonstantin Belousov 722814124c3SKonstantin Belousov static u_int 723814124c3SKonstantin Belousov tsc_get_timecount_mfence(struct timecounter *tc __unused) 724814124c3SKonstantin Belousov { 725814124c3SKonstantin Belousov 726814124c3SKonstantin Belousov mfence(); 727814124c3SKonstantin Belousov return (rdtsc32()); 728814124c3SKonstantin Belousov } 729814124c3SKonstantin Belousov 730814124c3SKonstantin Belousov static u_int 731814124c3SKonstantin Belousov tsc_get_timecount_low_mfence(struct timecounter *tc) 732814124c3SKonstantin Belousov { 733814124c3SKonstantin Belousov 734814124c3SKonstantin Belousov mfence(); 735814124c3SKonstantin Belousov return (tsc_get_timecount_low(tc)); 736814124c3SKonstantin Belousov } 737814124c3SKonstantin Belousov 73816808549SKonstantin Belousov static uint32_t 73916808549SKonstantin Belousov x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc) 740aea81038SKonstantin Belousov { 741aea81038SKonstantin Belousov 74216808549SKonstantin Belousov vdso_th->th_algo = VDSO_TH_ALGO_X86_TSC; 743d1b1b600SNeel Natu vdso_th->th_x86_shift = (int)(intptr_t)tc->tc_priv; 74416808549SKonstantin Belousov vdso_th->th_x86_hpet_idx = 0xffffffff; 745aea81038SKonstantin Belousov bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 74616808549SKonstantin Belousov return (1); 747aea81038SKonstantin Belousov } 748aea81038SKonstantin Belousov 749aea81038SKonstantin Belousov #ifdef COMPAT_FREEBSD32 75016808549SKonstantin Belousov static uint32_t 75116808549SKonstantin Belousov x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 752d1b1b600SNeel Natu struct timecounter *tc) 753aea81038SKonstantin Belousov { 754aea81038SKonstantin Belousov 75516808549SKonstantin Belousov vdso_th32->th_algo = VDSO_TH_ALGO_X86_TSC; 756d1b1b600SNeel Natu vdso_th32->th_x86_shift = (int)(intptr_t)tc->tc_priv; 75716808549SKonstantin Belousov vdso_th32->th_x86_hpet_idx = 0xffffffff; 758aea81038SKonstantin Belousov bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 75916808549SKonstantin Belousov return (1); 760aea81038SKonstantin Belousov } 761aea81038SKonstantin Belousov #endif 762