1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: MediaTek mmsys controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The MediaTek mmsys system controller provides clock control, routing control,
14  and miscellaneous control in mmsys partition.
15
16properties:
17  $nodename:
18    pattern: "^syscon@[0-9a-f]+$"
19
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2701-mmsys
25              - mediatek,mt2712-mmsys
26              - mediatek,mt6765-mmsys
27              - mediatek,mt6779-mmsys
28              - mediatek,mt6795-mmsys
29              - mediatek,mt6797-mmsys
30              - mediatek,mt8167-mmsys
31              - mediatek,mt8173-mmsys
32              - mediatek,mt8183-mmsys
33              - mediatek,mt8186-mmsys
34              - mediatek,mt8192-mmsys
35              - mediatek,mt8365-mmsys
36          - const: syscon
37
38      - description: vdosys0 and vdosys1 are 2 display HW pipelines,
39                     so mt8195 binding should be deprecated.
40        deprecated: true
41        items:
42          - const: mediatek,mt8195-mmsys
43          - const: syscon
44
45      - items:
46          - const: mediatek,mt7623-mmsys
47          - const: mediatek,mt2701-mmsys
48          - const: syscon
49
50      - items:
51          - const: mediatek,mt8195-vdosys0
52          - const: mediatek,mt8195-mmsys
53          - const: syscon
54
55  reg:
56    maxItems: 1
57
58  power-domains:
59    description:
60      A phandle and PM domain specifier as defined by bindings
61      of the power controller specified by phandle. See
62      Documentation/devicetree/bindings/power/power-domain.yaml for details.
63
64  mboxes:
65    description:
66      Using mailbox to communicate with GCE, it should have this
67      property and list of phandle, mailbox specifiers. See
68      Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
69      for details.
70    $ref: /schemas/types.yaml#/definitions/phandle-array
71
72  mediatek,gce-client-reg:
73    description:
74      The register of client driver can be configured by gce with 4 arguments
75      defined in this property, such as phandle of gce, subsys id,
76      register offset and size.
77      Each subsys id is mapping to a base address of display function blocks
78      register which is defined in the gce header
79      include/dt-bindings/gce/<chip>-gce.h.
80    $ref: /schemas/types.yaml#/definitions/phandle-array
81    maxItems: 1
82
83  "#clock-cells":
84    const: 1
85
86  '#reset-cells':
87    const: 1
88
89required:
90  - compatible
91  - reg
92  - "#clock-cells"
93
94additionalProperties: false
95
96examples:
97  - |
98    #include <dt-bindings/power/mt8173-power.h>
99    #include <dt-bindings/gce/mt8173-gce.h>
100
101    mmsys: syscon@14000000 {
102        compatible = "mediatek,mt8173-mmsys", "syscon";
103        reg = <0x14000000 0x1000>;
104        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
105        #clock-cells = <1>;
106        #reset-cells = <1>;
107        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
108                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
109        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
110    };
111