1=========================== 2 drm/i915 Intel GFX Driver 3=========================== 4 5The drm/i915 driver supports all (with the exception of some very early 6models) integrated GFX chipsets with both Intel display and rendering 7blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8those have basic support through the gma500 drm driver. 9 10Core Driver Infrastructure 11========================== 12 13This section covers core driver infrastructure used by both the display 14and the GEM parts of the driver. 15 16Runtime Power Management 17------------------------ 18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28Interrupt Handling 29------------------ 30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_runtime_pm_disable_interrupts 39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_runtime_pm_enable_interrupts 42 43Intel GVT-g Guest Support(vGPU) 44------------------------------- 45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52Intel GVT-g Host Support(vGPU device model) 53------------------------------------------- 54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61Workarounds 62----------- 63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67Display Hardware Handling 68========================= 69 70This section covers everything related to the display hardware including 71the mode setting infrastructure, plane, sprite and cursor handling and 72display, output probing and related topics. 73 74Mode Setting Infrastructure 75--------------------------- 76 77The i915 driver is thus far the only DRM driver which doesn't use the 78common DRM helper code to implement mode setting sequences. Thus it has 79its own tailor-made infrastructure for executing a display configuration 80change. 81 82Frontbuffer Tracking 83-------------------- 84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94Display FIFO Underrun Reporting 95------------------------------- 96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103Plane Configuration 104------------------- 105 106This section covers plane configuration and composition with the primary 107plane, sprites, cursors and overlays. This includes the infrastructure 108to do atomic vsync'ed updates of all this state and also tightly coupled 109topics like watermark setup and computation, framebuffer compression and 110panel self refresh. 111 112Atomic Plane Helpers 113-------------------- 114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 116 :doc: atomic plane helpers 117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 119 :internal: 120 121Asynchronous Page Flip 122---------------------- 123 124.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c 125 :doc: asynchronous flip implementation 126 127Output Probing 128-------------- 129 130This section covers output probing and related infrastructure like the 131hotplug interrupt storm detection and mitigation code. Note that the 132i915 driver still uses most of the common DRM helper code for output 133probing, so those sections fully apply. 134 135Hotplug 136------- 137 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 139 :doc: Hotplug 140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 142 :internal: 143 144High Definition Audio 145--------------------- 146 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 148 :doc: High Definition Audio over HDMI and Display Port 149 150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 151 :internal: 152 153.. kernel-doc:: include/drm/i915_component.h 154 :internal: 155 156Intel HDMI LPE Audio Support 157---------------------------- 158 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 160 :doc: LPE Audio integration for HDMI or DP playback 161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 163 :internal: 164 165Panel Self Refresh PSR (PSR/SRD) 166-------------------------------- 167 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 169 :doc: Panel Self Refresh (PSR/SRD) 170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 172 :internal: 173 174Frame Buffer Compression (FBC) 175------------------------------ 176 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 178 :doc: Frame Buffer Compression (FBC) 179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 181 :internal: 182 183Display Refresh Rate Switching (DRRS) 184------------------------------------- 185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 187 :doc: Display Refresh Rate Switching (DRRS) 188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 190 :internal: 191 192DPIO 193---- 194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 196 :doc: DPIO 197 198DMC Firmware Support 199-------------------- 200 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 202 :doc: DMC Firmware Support 203 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 205 :internal: 206 207DMC wakelock support 208-------------------- 209 210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c 211 :doc: DMC wakelock support 212 213.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c 214 :internal: 215 216Video BIOS Table (VBT) 217---------------------- 218 219.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 220 :doc: Video BIOS Table (VBT) 221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 223 :internal: 224 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 226 :internal: 227 228Display clocks 229-------------- 230 231.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 232 :doc: CDCLK / RAWCLK 233 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 235 :internal: 236 237Display PLLs 238------------ 239 240.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 241 :doc: Display PLLs 242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 244 :internal: 245 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 247 :internal: 248 249Display State Buffer 250-------------------- 251 252.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 253 :doc: DSB 254 255.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 256 :internal: 257 258GT Programming 259============== 260 261Multicast/Replicated (MCR) Registers 262------------------------------------ 263 264.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 265 :doc: GT Multicast/Replicated (MCR) Register Support 266 267.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 268 :internal: 269 270Memory Management and Command Submission 271======================================== 272 273This sections covers all things related to the GEM implementation in the 274i915 driver. 275 276Intel GPU Basics 277---------------- 278 279An Intel GPU has multiple engines. There are several engine types: 280 281- Render Command Streamer (RCS). An engine for rendering 3D and 282 performing compute. 283- Blitting Command Streamer (BCS). An engine for performing blitting and/or 284 copying operations. 285- Video Command Streamer. An engine used for video encoding and decoding. Also 286 sometimes called 'BSD' in hardware documentation. 287- Video Enhancement Command Streamer (VECS). An engine for video enhancement. 288 Also sometimes called 'VEBOX' in hardware documentation. 289- Compute Command Streamer (CCS). An engine that has access to the media and 290 GPGPU pipelines, but not the 3D pipeline. 291- Graphics Security Controller (GSCCS). A dedicated engine for internal 292 communication with GSC controller on security related tasks like 293 High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), 294 and HuC firmware authentication. 295 296The Intel GPU family is a family of integrated GPU's using Unified 297Memory Access. For having the GPU "do work", user space will feed the 298GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 299or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 300instruct the GPU to perform work (for example rendering) and that work 301needs memory from which to read and memory to which to write. All memory 302is encapsulated within GEM buffer objects (usually created with the ioctl 303`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 304to create will also list all GEM buffer objects that the batchbuffer reads 305and/or writes. For implementation details of memory management see 306`GEM BO Management Implementation Details`_. 307 308The i915 driver allows user space to create a context via the ioctl 309`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 310integer. Such a context should be viewed by user-space as -loosely- 311analogous to the idea of a CPU process of an operating system. The i915 312driver guarantees that commands issued to a fixed context are to be 313executed so that writes of a previously issued command are seen by 314reads of following commands. Actions issued between different contexts 315(even if from the same file descriptor) are NOT given that guarantee 316and the only way to synchronize across contexts (even from the same 317file descriptor) is through the use of fences. At least as far back as 318Gen4, also have that a context carries with it a GPU HW context; 319the HW context is essentially (most of at least) the state of a GPU. 320In addition to the ordering guarantees, the kernel will restore GPU 321state via HW context when commands are issued to a context, this saves 322user space the need to restore (most of at least) the GPU state at the 323start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 324work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 325to identify what context to use with the command. 326 327The GPU has its own memory management and address space. The kernel 328driver maintains the memory translation table for the GPU. For older 329GPUs (i.e. those before Gen8), there is a single global such translation 330table, a global Graphics Translation Table (GTT). For newer generation 331GPUs each context has its own translation table, called Per-Process 332Graphics Translation Table (PPGTT). Of important note, is that although 333PPGTT is named per-process it is actually per context. When user space 334submits a batchbuffer, the kernel walks the list of GEM buffer objects 335used by the batchbuffer and guarantees that not only is the memory of 336each such GEM buffer object resident but it is also present in the 337(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 338then it is given an address. Two consequences of this are: the kernel 339needs to edit the batchbuffer submitted to write the correct value of 340the GPU address when a GEM BO is assigned a GPU address and the kernel 341might evict a different GEM BO from the (PP)GTT to make address room 342for another GEM BO. Consequently, the ioctls submitting a batchbuffer 343for execution also include a list of all locations within buffers that 344refer to GPU-addresses so that the kernel can edit the buffer correctly. 345This process is dubbed relocation. 346 347Locking Guidelines 348------------------ 349 350.. note:: 351 This is a description of how the locking should be after 352 refactoring is done. Does not necessarily reflect what the locking 353 looks like while WIP. 354 355#. All locking rules and interface contracts with cross-driver interfaces 356 (dma-buf, dma_fence) need to be followed. 357 358#. No struct_mutex anywhere in the code 359 360#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 361 is to be hoisted at highest level and passed down within i915_gem_ctx 362 in the call chain 363 364#. While holding lru/memory manager (buddy, drm_mm, whatever) locks 365 system memory allocations are not allowed 366 367 * Enforce this by priming lockdep (with fs_reclaim). If we 368 allocate memory while holding these looks we get a rehash 369 of the shrinker vs. struct_mutex saga, and that would be 370 real bad. 371 372#. Do not nest different lru/memory manager locks within each other. 373 Take them in turn to update memory allocations, relying on the object’s 374 dma_resv ww_mutex to serialize against other operations. 375 376#. The suggestion for lru/memory managers locks is that they are small 377 enough to be spinlocks. 378 379#. All features need to come with exhaustive kernel selftests and/or 380 IGT tests when appropriate 381 382#. All LMEM uAPI paths need to be fully restartable (_interruptible() 383 for all locks/waits/sleeps) 384 385 * Error handling validation through signal injection. 386 Still the best strategy we have for validating GEM uAPI 387 corner cases. 388 Must be excessively used in the IGT, and we need to check 389 that we really have full path coverage of all error cases. 390 391 * -EDEADLK handling with ww_mutex 392 393GEM BO Management Implementation Details 394---------------------------------------- 395 396.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 397 :doc: Virtual Memory Address 398 399Buffer Object Eviction 400---------------------- 401 402This section documents the interface functions for evicting buffer 403objects to make space available in the virtual gpu address spaces. Note 404that this is mostly orthogonal to shrinking buffer objects caches, which 405has the goal to make main memory (shared with the gpu through the 406unified memory architecture) available. 407 408.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 409 :internal: 410 411Buffer Object Memory Shrinking 412------------------------------ 413 414This section documents the interface function for shrinking memory usage 415of buffer object caches. Shrinking is used to make main memory 416available. Note that this is mostly orthogonal to evicting buffer 417objects, which has the goal to make space in gpu virtual address spaces. 418 419.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 420 :internal: 421 422Batchbuffer Parsing 423------------------- 424 425.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 426 :doc: batch buffer command parser 427 428.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 429 :internal: 430 431User Batchbuffer Execution 432-------------------------- 433 434.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h 435 436.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 437 :doc: User command execution 438 439Scheduling 440---------- 441.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h 442 :functions: i915_sched_engine 443 444Logical Rings, Logical Ring Contexts and Execlists 445-------------------------------------------------- 446 447.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c 448 :doc: Logical Rings, Logical Ring Contexts and Execlists 449 450Global GTT views 451---------------- 452 453.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 454 :doc: Global GTT views 455 456.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 457 :internal: 458 459GTT Fences and Swizzling 460------------------------ 461 462.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 463 :internal: 464 465Global GTT Fence Handling 466~~~~~~~~~~~~~~~~~~~~~~~~~ 467 468.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 469 :doc: fence register handling 470 471Hardware Tiling and Swizzling Details 472~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 473 474.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 475 :doc: tiling swizzling details 476 477Object Tiling IOCTLs 478-------------------- 479 480.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 481 :internal: 482 483.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 484 :doc: buffer object tiling 485 486Protected Objects 487----------------- 488 489.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c 490 :doc: PXP 491 492.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h 493 494Microcontrollers 495================ 496 497Starting from gen9, three microcontrollers are available on the HW: the 498graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 499display microcontroller (DMC). The driver is responsible for loading the 500firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 501to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 502 503WOPCM 504----- 505 506WOPCM Layout 507~~~~~~~~~~~~ 508 509.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c 510 :doc: WOPCM Layout 511 512GuC 513--- 514 515.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 516 :doc: GuC 517 518.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h 519 520GuC Firmware Layout 521~~~~~~~~~~~~~~~~~~~ 522 523.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 524 :doc: Firmware Layout 525 526GuC Memory Management 527~~~~~~~~~~~~~~~~~~~~~ 528 529.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 530 :doc: GuC Memory Management 531.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 532 :functions: intel_guc_allocate_vma 533 534 535GuC-specific firmware loader 536~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 537 538.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 539 :internal: 540 541GuC-based command submission 542~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 543 544.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 545 :doc: GuC-based command submission 546 547GuC ABI 548~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 549 550.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 551.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 552.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 553.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 554.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 555 556HuC 557--- 558.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 559 :doc: HuC 560.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 561 :functions: intel_huc_auth 562 563HuC Memory Management 564~~~~~~~~~~~~~~~~~~~~~ 565 566.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 567 :doc: HuC Memory Management 568 569HuC Firmware Layout 570~~~~~~~~~~~~~~~~~~~ 571The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 572 573DMC 574--- 575See `DMC Firmware Support`_ 576 577Tracing 578======= 579 580This sections covers all things related to the tracepoints implemented 581in the i915 driver. 582 583i915_ppgtt_create and i915_ppgtt_release 584---------------------------------------- 585 586.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 587 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 588 589i915_context_create and i915_context_free 590----------------------------------------- 591 592.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 593 :doc: i915_context_create and i915_context_free tracepoints 594 595Perf 596==== 597 598Overview 599-------- 600.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 601 :doc: i915 Perf Overview 602 603Comparison with Core Perf 604------------------------- 605.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 606 :doc: i915 Perf History and Comparison with Core Perf 607 608i915 Driver Entry Points 609------------------------ 610 611This section covers the entrypoints exported outside of i915_perf.c to 612integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 613 614.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 615 :functions: i915_perf_init 616.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 617 :functions: i915_perf_fini 618.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 619 :functions: i915_perf_register 620.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 621 :functions: i915_perf_unregister 622.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 623 :functions: i915_perf_open_ioctl 624.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 625 :functions: i915_perf_release 626.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 627 :functions: i915_perf_add_config_ioctl 628.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 629 :functions: i915_perf_remove_config_ioctl 630 631i915 Perf Stream 632---------------- 633 634This section covers the stream-semantics-agnostic structures and functions 635for representing an i915 perf stream FD and associated file operations. 636 637.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 638 :functions: i915_perf_stream 639.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 640 :functions: i915_perf_stream_ops 641 642.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 643 :functions: read_properties_unlocked 644.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 645 :functions: i915_perf_open_ioctl_locked 646.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 647 :functions: i915_perf_destroy_locked 648.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 649 :functions: i915_perf_read 650.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 651 :functions: i915_perf_ioctl 652.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 653 :functions: i915_perf_enable_locked 654.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 655 :functions: i915_perf_disable_locked 656.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 657 :functions: i915_perf_poll 658.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 659 :functions: i915_perf_poll_locked 660 661i915 Perf Observation Architecture Stream 662----------------------------------------- 663 664.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 665 :functions: i915_oa_ops 666 667.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 668 :functions: i915_oa_stream_init 669.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 670 :functions: i915_oa_read 671.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 672 :functions: i915_oa_stream_enable 673.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 674 :functions: i915_oa_stream_disable 675.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 676 :functions: i915_oa_wait_unlocked 677.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 678 :functions: i915_oa_poll_wait 679 680Other i915 Perf Internals 681------------------------- 682 683This section simply includes all other currently documented i915 perf internals, 684in no particular order, but may include some more minor utilities or platform 685specific details than found in the more high-level sections. 686 687.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 688 :internal: 689 :no-identifiers: 690 i915_perf_init 691 i915_perf_fini 692 i915_perf_register 693 i915_perf_unregister 694 i915_perf_open_ioctl 695 i915_perf_release 696 i915_perf_add_config_ioctl 697 i915_perf_remove_config_ioctl 698 read_properties_unlocked 699 i915_perf_open_ioctl_locked 700 i915_perf_destroy_locked 701 i915_perf_read i915_perf_ioctl 702 i915_perf_enable_locked 703 i915_perf_disable_locked 704 i915_perf_poll i915_perf_poll_locked 705 i915_oa_stream_init i915_oa_read 706 i915_oa_stream_enable 707 i915_oa_stream_disable 708 i915_oa_wait_unlocked 709 i915_oa_poll_wait 710 711Style 712===== 713 714The drm/i915 driver codebase has some style rules in addition to (and, in some 715cases, deviating from) the kernel coding style. 716 717Register macro definition style 718------------------------------- 719 720The style guide for ``i915_reg.h``. 721 722.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 723 :doc: The i915 register macro definition style guide 724 725.. _i915-usage-stats: 726 727i915 DRM client usage stats implementation 728========================================== 729 730The drm/i915 driver implements the DRM client usage stats specification as 731documented in :ref:`drm-client-usage-stats`. 732 733Example of the output showing the implemented key value pairs and entirety of 734the currently possible format options: 735 736:: 737 738 pos: 0 739 flags: 0100002 740 mnt_id: 21 741 drm-driver: i915 742 drm-pdev: 0000:00:02.0 743 drm-client-id: 7 744 drm-engine-render: 9288864723 ns 745 drm-engine-copy: 2035071108 ns 746 drm-engine-video: 0 ns 747 drm-engine-capacity-video: 2 748 drm-engine-video-enhance: 0 ns 749 750Possible `drm-engine-` key names are: `render`, `copy`, `video` and 751`video-enhance`. 752