1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14
15 #include <linux/bits.h>
16
17 #define CIF_SIE 0 /* CPU needs SIE exit cleanup */
18 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
19 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */
20 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */
21 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
22
23 #define _CIF_SIE BIT(CIF_SIE)
24 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
25 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
26 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
27 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
28
29 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
30
31 #ifndef __ASSEMBLY__
32
33 #include <linux/cpumask.h>
34 #include <linux/linkage.h>
35 #include <linux/irqflags.h>
36 #include <asm/fpu-types.h>
37 #include <asm/cpu.h>
38 #include <asm/page.h>
39 #include <asm/ptrace.h>
40 #include <asm/setup.h>
41 #include <asm/runtime_instr.h>
42 #include <asm/irqflags.h>
43 #include <asm/alternative.h>
44
45 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
46
set_cpu_flag(int flag)47 static __always_inline void set_cpu_flag(int flag)
48 {
49 S390_lowcore.cpu_flags |= (1UL << flag);
50 }
51
clear_cpu_flag(int flag)52 static __always_inline void clear_cpu_flag(int flag)
53 {
54 S390_lowcore.cpu_flags &= ~(1UL << flag);
55 }
56
test_cpu_flag(int flag)57 static __always_inline bool test_cpu_flag(int flag)
58 {
59 return S390_lowcore.cpu_flags & (1UL << flag);
60 }
61
test_and_set_cpu_flag(int flag)62 static __always_inline bool test_and_set_cpu_flag(int flag)
63 {
64 if (test_cpu_flag(flag))
65 return true;
66 set_cpu_flag(flag);
67 return false;
68 }
69
test_and_clear_cpu_flag(int flag)70 static __always_inline bool test_and_clear_cpu_flag(int flag)
71 {
72 if (!test_cpu_flag(flag))
73 return false;
74 clear_cpu_flag(flag);
75 return true;
76 }
77
78 /*
79 * Test CIF flag of another CPU. The caller needs to ensure that
80 * CPU hotplug can not happen, e.g. by disabling preemption.
81 */
test_cpu_flag_of(int flag,int cpu)82 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
83 {
84 struct lowcore *lc = lowcore_ptr[cpu];
85
86 return lc->cpu_flags & (1UL << flag);
87 }
88
89 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
90
get_cpu_id(struct cpuid * ptr)91 static inline void get_cpu_id(struct cpuid *ptr)
92 {
93 asm volatile("stidp %0" : "=Q" (*ptr));
94 }
95
get_cpu_timer(void)96 static __always_inline unsigned long get_cpu_timer(void)
97 {
98 unsigned long timer;
99
100 asm volatile("stpt %[timer]" : [timer] "=Q" (timer));
101 return timer;
102 }
103
104 void s390_adjust_jiffies(void);
105 void s390_update_cpu_mhz(void);
106 void cpu_detect_mhz_feature(void);
107
108 extern const struct seq_operations cpuinfo_op;
109 extern void execve_tail(void);
110 unsigned long vdso_text_size(void);
111 unsigned long vdso_size(void);
112
113 /*
114 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
115 */
116
117 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \
118 _REGION3_SIZE : TASK_SIZE_MAX)
119 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
120 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
121 #define TASK_SIZE_MAX (-PAGE_SIZE)
122
123 #define VDSO_BASE (STACK_TOP + PAGE_SIZE)
124 #define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
125 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
126 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
127
128 #define HAVE_ARCH_PICK_MMAP_LAYOUT
129
130 #define __stackleak_poison __stackleak_poison
__stackleak_poison(unsigned long erase_low,unsigned long erase_high,unsigned long poison)131 static __always_inline void __stackleak_poison(unsigned long erase_low,
132 unsigned long erase_high,
133 unsigned long poison)
134 {
135 unsigned long tmp, count;
136
137 count = erase_high - erase_low;
138 if (!count)
139 return;
140 asm volatile(
141 " cghi %[count],8\n"
142 " je 2f\n"
143 " aghi %[count],-(8+1)\n"
144 " srlg %[tmp],%[count],8\n"
145 " ltgr %[tmp],%[tmp]\n"
146 " jz 1f\n"
147 "0: stg %[poison],0(%[addr])\n"
148 " mvc 8(256-8,%[addr]),0(%[addr])\n"
149 " la %[addr],256(%[addr])\n"
150 " brctg %[tmp],0b\n"
151 "1: stg %[poison],0(%[addr])\n"
152 " larl %[tmp],3f\n"
153 " ex %[count],0(%[tmp])\n"
154 " j 4f\n"
155 "2: stg %[poison],0(%[addr])\n"
156 " j 4f\n"
157 "3: mvc 8(1,%[addr]),0(%[addr])\n"
158 "4:\n"
159 : [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp)
160 : [poison] "d" (poison)
161 : "memory", "cc"
162 );
163 }
164
165 /*
166 * Thread structure
167 */
168 struct thread_struct {
169 unsigned int acrs[NUM_ACRS];
170 unsigned long ksp; /* kernel stack pointer */
171 unsigned long user_timer; /* task cputime in user space */
172 unsigned long guest_timer; /* task cputime in kvm guest */
173 unsigned long system_timer; /* task cputime in kernel space */
174 unsigned long hardirq_timer; /* task cputime in hardirq context */
175 unsigned long softirq_timer; /* task cputime in softirq context */
176 const sys_call_ptr_t *sys_call_table; /* system call table address */
177 unsigned long gmap_addr; /* address of last gmap fault. */
178 unsigned int gmap_write_flag; /* gmap fault write indication */
179 unsigned int gmap_int_code; /* int code of last gmap fault */
180 unsigned int gmap_pfault; /* signal of a pending guest pfault */
181 int ufpu_flags; /* user fpu flags */
182 int kfpu_flags; /* kernel fpu flags */
183
184 /* Per-thread information related to debugging */
185 struct per_regs per_user; /* User specified PER registers */
186 struct per_event per_event; /* Cause of the last PER trap */
187 unsigned long per_flags; /* Flags to control debug behavior */
188 unsigned int system_call; /* system call number in signal */
189 unsigned long last_break; /* last breaking-event-address. */
190 /* pfault_wait is used to block the process on a pfault event */
191 unsigned long pfault_wait;
192 struct list_head list;
193 /* cpu runtime instrumentation */
194 struct runtime_instr_cb *ri_cb;
195 struct gs_cb *gs_cb; /* Current guarded storage cb */
196 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
197 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
198 struct fpu ufpu; /* User FP and VX register save area */
199 struct fpu kfpu; /* Kernel FP and VX register save area */
200 };
201
202 /* Flag to disable transactions. */
203 #define PER_FLAG_NO_TE 1UL
204 /* Flag to enable random transaction aborts. */
205 #define PER_FLAG_TE_ABORT_RAND 2UL
206 /* Flag to specify random transaction abort mode:
207 * - abort each transaction at a random instruction before TEND if set.
208 * - abort random transactions at a random instruction if cleared.
209 */
210 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
211
212 typedef struct thread_struct thread_struct;
213
214 #define ARCH_MIN_TASKALIGN 8
215
216 #define INIT_THREAD { \
217 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
218 .last_break = 1, \
219 }
220
221 /*
222 * Do necessary setup to start up a new thread.
223 */
224 #define start_thread(regs, new_psw, new_stackp) do { \
225 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
226 regs->psw.addr = new_psw; \
227 regs->gprs[15] = new_stackp; \
228 execve_tail(); \
229 } while (0)
230
231 #define start_thread31(regs, new_psw, new_stackp) do { \
232 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
233 regs->psw.addr = new_psw; \
234 regs->gprs[15] = new_stackp; \
235 execve_tail(); \
236 } while (0)
237
238 struct task_struct;
239 struct mm_struct;
240 struct seq_file;
241 struct pt_regs;
242
243 void show_registers(struct pt_regs *regs);
244 void show_cacheinfo(struct seq_file *m);
245
246 /* Free guarded storage control block */
247 void guarded_storage_release(struct task_struct *tsk);
248 void gs_load_bc_cb(struct pt_regs *regs);
249
250 unsigned long __get_wchan(struct task_struct *p);
251 #define task_pt_regs(tsk) ((struct pt_regs *) \
252 (task_stack_page(tsk) + THREAD_SIZE) - 1)
253 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
254 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
255
256 /* Has task runtime instrumentation enabled ? */
257 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
258
259 /* avoid using global register due to gcc bug in versions < 8.4 */
260 #define current_stack_pointer (__current_stack_pointer())
261
__current_stack_pointer(void)262 static __always_inline unsigned long __current_stack_pointer(void)
263 {
264 unsigned long sp;
265
266 asm volatile("lgr %0,15" : "=d" (sp));
267 return sp;
268 }
269
on_thread_stack(void)270 static __always_inline bool on_thread_stack(void)
271 {
272 unsigned long ksp = S390_lowcore.kernel_stack;
273
274 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
275 }
276
stap(void)277 static __always_inline unsigned short stap(void)
278 {
279 unsigned short cpu_address;
280
281 asm volatile("stap %0" : "=Q" (cpu_address));
282 return cpu_address;
283 }
284
285 #define cpu_relax() barrier()
286
287 #define ECAG_CACHE_ATTRIBUTE 0
288 #define ECAG_CPU_ATTRIBUTE 1
289
__ecag(unsigned int asi,unsigned char parm)290 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
291 {
292 unsigned long val;
293
294 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
295 return val;
296 }
297
psw_set_key(unsigned int key)298 static inline void psw_set_key(unsigned int key)
299 {
300 asm volatile("spka 0(%0)" : : "d" (key));
301 }
302
303 /*
304 * Set PSW to specified value.
305 */
__load_psw(psw_t psw)306 static inline void __load_psw(psw_t psw)
307 {
308 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
309 }
310
311 /*
312 * Set PSW mask to specified value, while leaving the
313 * PSW addr pointing to the next instruction.
314 */
__load_psw_mask(unsigned long mask)315 static __always_inline void __load_psw_mask(unsigned long mask)
316 {
317 psw_t psw __uninitialized;
318 unsigned long addr;
319
320 psw.mask = mask;
321
322 asm volatile(
323 " larl %0,1f\n"
324 " stg %0,%1\n"
325 " lpswe %2\n"
326 "1:"
327 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
328 }
329
330 /*
331 * Extract current PSW mask
332 */
__extract_psw(void)333 static inline unsigned long __extract_psw(void)
334 {
335 unsigned int reg1, reg2;
336
337 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
338 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
339 }
340
__local_mcck_save(void)341 static inline unsigned long __local_mcck_save(void)
342 {
343 unsigned long mask = __extract_psw();
344
345 __load_psw_mask(mask & ~PSW_MASK_MCHECK);
346 return mask & PSW_MASK_MCHECK;
347 }
348
349 #define local_mcck_save(mflags) \
350 do { \
351 typecheck(unsigned long, mflags); \
352 mflags = __local_mcck_save(); \
353 } while (0)
354
local_mcck_restore(unsigned long mflags)355 static inline void local_mcck_restore(unsigned long mflags)
356 {
357 unsigned long mask = __extract_psw();
358
359 mask &= ~PSW_MASK_MCHECK;
360 __load_psw_mask(mask | mflags);
361 }
362
local_mcck_disable(void)363 static inline void local_mcck_disable(void)
364 {
365 __local_mcck_save();
366 }
367
local_mcck_enable(void)368 static inline void local_mcck_enable(void)
369 {
370 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
371 }
372
373 /*
374 * Rewind PSW instruction address by specified number of bytes.
375 */
__rewind_psw(psw_t psw,unsigned long ilc)376 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
377 {
378 unsigned long mask;
379
380 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
381 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
382 (1UL << 24) - 1;
383 return (psw.addr - ilc) & mask;
384 }
385
386 /*
387 * Function to drop a processor into disabled wait state
388 */
disabled_wait(void)389 static __always_inline void __noreturn disabled_wait(void)
390 {
391 psw_t psw;
392
393 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
394 psw.addr = _THIS_IP_;
395 __load_psw(psw);
396 while (1);
397 }
398
399 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
400
regs_irqs_disabled(struct pt_regs * regs)401 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
402 {
403 return arch_irqs_disabled_flags(regs->psw.mask);
404 }
405
bpon(void)406 static __always_inline void bpon(void)
407 {
408 asm volatile(ALTERNATIVE("nop", ".insn rrf,0xb2e80000,0,0,13,0", 82));
409 }
410
411 #endif /* __ASSEMBLY__ */
412
413 #endif /* __ASM_S390_PROCESSOR_H */
414