1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "kfd_events.h"
24 #include "kfd_debug.h"
25 #include "soc15_int.h"
26 #include "kfd_device_queue_manager.h"
27
28 /*
29 * GFX10 SQ Interrupts
30 *
31 * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit
32 * packet to the Interrupt Handler:
33 * Auto - Generated by the SQG (various cmd overflows, timestamps etc)
34 * Wave - Generated by S_SENDMSG through a shader program
35 * Error - HW generated errors (Illegal instructions, Memviols, EDC etc)
36 *
37 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
38 * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such:
39 *
40 * - context_id1[7:6]
41 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
42 *
43 * - context_id0[24]
44 * PRIV bit indicates that Wave S_SEND or error occurred within trap
45 *
46 * - context_id0[22:0]
47 * 23-bit data with the following layout per encoding type:
48 * Auto - only context_id0[8:0] is used, which reports various interrupts
49 * generated by SQG. The rest is 0.
50 * Wave - user data sent from m0 via S_SENDMSG
51 * Error - Error type (context_id0[22:19]), Error Details (rest of bits)
52 *
53 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave
54 * S_SENDMSG and Errors. These are 0 for Auto.
55 */
56
57 enum SQ_INTERRUPT_WORD_ENCODING {
58 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
59 SQ_INTERRUPT_WORD_ENCODING_INST,
60 SQ_INTERRUPT_WORD_ENCODING_ERROR,
61 };
62
63 enum SQ_INTERRUPT_ERROR_TYPE {
64 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
65 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST,
66 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL,
67 SQ_INTERRUPT_ERROR_TYPE_EDC_FED,
68 };
69
70 /* SQ_INTERRUPT_WORD_AUTO_CTXID */
71 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE__SHIFT 0
72 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT__SHIFT 1
73 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF0_FULL__SHIFT 2
74 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF1_FULL__SHIFT 3
75 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR__SHIFT 7
76 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__SE_ID__SHIFT 4
77 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING__SHIFT 6
78
79 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_MASK 0x00000001
80 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT_MASK 0x00000002
81 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF0_FULL_MASK 0x00000004
82 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF1_FULL_MASK 0x00000008
83 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR_MASK 0x00000080
84 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__SE_ID_MASK 0x030
85 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING_MASK 0x0c0
86
87 /* SQ_INTERRUPT_WORD_WAVE_CTXID */
88 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA__SHIFT 0
89 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SA_ID__SHIFT 23
90 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV__SHIFT 24
91 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID__SHIFT 25
92 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SIMD_ID__SHIFT 30
93 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID__SHIFT 0
94 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__SE_ID__SHIFT 4
95 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING__SHIFT 6
96
97 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA_MASK 0x000007fffff
98 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SA_ID_MASK 0x0000800000
99 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK 0x00001000000
100 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID_MASK 0x0003e000000
101 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SIMD_ID_MASK 0x000c0000000
102 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID_MASK 0x00f
103 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__SE_ID_MASK 0x030
104 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING_MASK 0x0c0
105
106 #define KFD_CTXID0__ERR_TYPE_MASK 0x780000
107 #define KFD_CTXID0__ERR_TYPE__SHIFT 19
108
109 /* GFX10 SQ interrupt ENC type bit (context_id1[7:6]) for wave s_sendmsg */
110 #define KFD_CONTEXT_ID1_ENC_TYPE_WAVE_MASK 0x40
111 /* GFX10 SQ interrupt PRIV bit (context_id0[24]) for s_sendmsg inside trap */
112 #define KFD_CONTEXT_ID0_PRIV_MASK 0x1000000
113 /*
114 * The debugger will send user data(m0) with PRIV=1 to indicate it requires
115 * notification from the KFD with the following queue id (DOORBELL_ID) and
116 * trap code (TRAP_CODE).
117 */
118 #define KFD_CONTEXT_ID0_DEBUG_DOORBELL_MASK 0x0003ff
119 #define KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_SHIFT 10
120 #define KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_MASK 0x07fc00
121 #define KFD_DEBUG_DOORBELL_ID(ctxid0) ((ctxid0) & \
122 KFD_CONTEXT_ID0_DEBUG_DOORBELL_MASK)
123 #define KFD_DEBUG_TRAP_CODE(ctxid0) (((ctxid0) & \
124 KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_MASK) \
125 >> KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_SHIFT)
126 #define KFD_DEBUG_CP_BAD_OP_ECODE_MASK 0x3fffc00
127 #define KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT 10
128 #define KFD_DEBUG_CP_BAD_OP_ECODE(ctxid0) (((ctxid0) & \
129 KFD_DEBUG_CP_BAD_OP_ECODE_MASK) \
130 >> KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT)
131
event_interrupt_poison_consumption(struct kfd_node * dev,uint16_t pasid,uint16_t client_id)132 static void event_interrupt_poison_consumption(struct kfd_node *dev,
133 uint16_t pasid, uint16_t client_id)
134 {
135 enum amdgpu_ras_block block = 0;
136 int old_poison, ret = -EINVAL;
137 uint32_t reset = 0;
138 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
139
140 if (!p)
141 return;
142
143 /* all queues of a process will be unmapped in one time */
144 old_poison = atomic_cmpxchg(&p->poison, 0, 1);
145 kfd_unref_process(p);
146 if (old_poison)
147 return;
148
149 switch (client_id) {
150 case SOC15_IH_CLIENTID_SE0SH:
151 case SOC15_IH_CLIENTID_SE1SH:
152 case SOC15_IH_CLIENTID_SE2SH:
153 case SOC15_IH_CLIENTID_SE3SH:
154 case SOC15_IH_CLIENTID_UTCL2:
155 ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
156 block = AMDGPU_RAS_BLOCK__GFX;
157 if (ret)
158 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
159 break;
160 case SOC15_IH_CLIENTID_SDMA0:
161 case SOC15_IH_CLIENTID_SDMA1:
162 case SOC15_IH_CLIENTID_SDMA2:
163 case SOC15_IH_CLIENTID_SDMA3:
164 case SOC15_IH_CLIENTID_SDMA4:
165 block = AMDGPU_RAS_BLOCK__SDMA;
166 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
167 break;
168 default:
169 break;
170 }
171
172 kfd_signal_poison_consumed_event(dev, pasid);
173
174 /* resetting queue passes, do page retirement without gpu reset
175 * resetting queue fails, fallback to gpu reset solution
176 */
177 if (!ret)
178 dev_warn(dev->adev->dev,
179 "RAS poison consumption, unmap queue flow succeeded: client id %d\n",
180 client_id);
181 else
182 dev_warn(dev->adev->dev,
183 "RAS poison consumption, fall back to gpu reset flow: client id %d\n",
184 client_id);
185
186 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, reset);
187 }
188
event_interrupt_isr_v10(struct kfd_node * dev,const uint32_t * ih_ring_entry,uint32_t * patched_ihre,bool * patched_flag)189 static bool event_interrupt_isr_v10(struct kfd_node *dev,
190 const uint32_t *ih_ring_entry,
191 uint32_t *patched_ihre,
192 bool *patched_flag)
193 {
194 uint16_t source_id, client_id, pasid, vmid;
195 const uint32_t *data = ih_ring_entry;
196
197 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
198 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
199
200 /* Only handle interrupts from KFD VMIDs */
201 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
202 if (!KFD_IRQ_IS_FENCE(client_id, source_id) &&
203 (vmid < dev->vm_info.first_vmid_kfd ||
204 vmid > dev->vm_info.last_vmid_kfd))
205 return false;
206
207 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
208
209 /* Only handle clients we care about */
210 if (client_id != SOC15_IH_CLIENTID_GRBM_CP &&
211 client_id != SOC15_IH_CLIENTID_SDMA0 &&
212 client_id != SOC15_IH_CLIENTID_SDMA1 &&
213 client_id != SOC15_IH_CLIENTID_SDMA2 &&
214 client_id != SOC15_IH_CLIENTID_SDMA3 &&
215 client_id != SOC15_IH_CLIENTID_SDMA4 &&
216 client_id != SOC15_IH_CLIENTID_SDMA5 &&
217 client_id != SOC15_IH_CLIENTID_SDMA6 &&
218 client_id != SOC15_IH_CLIENTID_SDMA7 &&
219 client_id != SOC15_IH_CLIENTID_VMC &&
220 client_id != SOC15_IH_CLIENTID_VMC1 &&
221 client_id != SOC15_IH_CLIENTID_UTCL2 &&
222 client_id != SOC15_IH_CLIENTID_SE0SH &&
223 client_id != SOC15_IH_CLIENTID_SE1SH &&
224 client_id != SOC15_IH_CLIENTID_SE2SH &&
225 client_id != SOC15_IH_CLIENTID_SE3SH)
226 return false;
227
228 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
229 client_id, source_id, vmid, pasid);
230 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",
231 data[0], data[1], data[2], data[3],
232 data[4], data[5], data[6], data[7]);
233
234 /* If there is no valid PASID, it's likely a bug */
235 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))
236 return 0;
237
238 /* Interrupt types we care about: various signals and faults.
239 * They will be forwarded to a work queue (see below).
240 */
241 return source_id == SOC15_INTSRC_CP_END_OF_PIPE ||
242 source_id == SOC15_INTSRC_SDMA_TRAP ||
243 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG ||
244 source_id == SOC15_INTSRC_CP_BAD_OPCODE ||
245 client_id == SOC15_IH_CLIENTID_VMC ||
246 client_id == SOC15_IH_CLIENTID_VMC1 ||
247 client_id == SOC15_IH_CLIENTID_UTCL2 ||
248 KFD_IRQ_IS_FENCE(client_id, source_id);
249 }
250
event_interrupt_wq_v10(struct kfd_node * dev,const uint32_t * ih_ring_entry)251 static void event_interrupt_wq_v10(struct kfd_node *dev,
252 const uint32_t *ih_ring_entry)
253 {
254 uint16_t source_id, client_id, pasid, vmid;
255 uint32_t context_id0, context_id1;
256 uint32_t encoding, sq_intr_err_type;
257
258 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
259 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
260 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
261 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
262 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
263 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
264
265 if (client_id == SOC15_IH_CLIENTID_GRBM_CP ||
266 client_id == SOC15_IH_CLIENTID_SE0SH ||
267 client_id == SOC15_IH_CLIENTID_SE1SH ||
268 client_id == SOC15_IH_CLIENTID_SE2SH ||
269 client_id == SOC15_IH_CLIENTID_SE3SH) {
270 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
271 kfd_signal_event_interrupt(pasid, context_id0, 32);
272 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
273 encoding = REG_GET_FIELD(context_id1,
274 SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING);
275 switch (encoding) {
276 case SQ_INTERRUPT_WORD_ENCODING_AUTO:
277 pr_debug_ratelimited(
278 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf0_full %d, ttrac_buf1_full %d, ttrace_utc_err %d\n",
279 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_AUTO_CTXID1,
280 SE_ID),
281 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
282 THREAD_TRACE),
283 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
284 WLT),
285 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
286 THREAD_TRACE_BUF0_FULL),
287 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
288 THREAD_TRACE_BUF1_FULL),
289 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
290 THREAD_TRACE_UTC_ERROR));
291 break;
292 case SQ_INTERRUPT_WORD_ENCODING_INST:
293 pr_debug_ratelimited("sq_intr: inst, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",
294 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
295 SE_ID),
296 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
297 DATA),
298 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
299 SA_ID),
300 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
301 PRIV),
302 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
303 WAVE_ID),
304 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
305 SIMD_ID),
306 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
307 WGP_ID));
308 if (context_id0 & SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK) {
309 if (kfd_set_dbg_ev_from_interrupt(dev, pasid,
310 KFD_DEBUG_DOORBELL_ID(context_id0),
311 KFD_DEBUG_TRAP_CODE(context_id0),
312 NULL, 0))
313 return;
314 }
315 break;
316 case SQ_INTERRUPT_WORD_ENCODING_ERROR:
317 sq_intr_err_type = REG_GET_FIELD(context_id0, KFD_CTXID0,
318 ERR_TYPE);
319 pr_warn_ratelimited("sq_intr: error, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d, err_type %d\n",
320 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
321 SE_ID),
322 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
323 DATA),
324 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
325 SA_ID),
326 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
327 PRIV),
328 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
329 WAVE_ID),
330 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
331 SIMD_ID),
332 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
333 WGP_ID),
334 sq_intr_err_type);
335 if (sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
336 sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
337 event_interrupt_poison_consumption(dev, pasid, source_id);
338 return;
339 }
340 break;
341 default:
342 break;
343 }
344 kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23);
345 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &&
346 KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) {
347 kfd_set_dbg_ev_from_interrupt(dev, pasid,
348 KFD_DEBUG_DOORBELL_ID(context_id0),
349 KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),
350 NULL,
351 0);
352 }
353 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 ||
354 client_id == SOC15_IH_CLIENTID_SDMA1 ||
355 client_id == SOC15_IH_CLIENTID_SDMA2 ||
356 client_id == SOC15_IH_CLIENTID_SDMA3 ||
357 (client_id == SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid &&
358 KFD_GC_VERSION(dev) == IP_VERSION(10, 3, 0)) ||
359 client_id == SOC15_IH_CLIENTID_SDMA4 ||
360 client_id == SOC15_IH_CLIENTID_SDMA5 ||
361 client_id == SOC15_IH_CLIENTID_SDMA6 ||
362 client_id == SOC15_IH_CLIENTID_SDMA7) {
363 if (source_id == SOC15_INTSRC_SDMA_TRAP) {
364 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
365 } else if (source_id == SOC15_INTSRC_SDMA_ECC) {
366 event_interrupt_poison_consumption(dev, pasid, source_id);
367 return;
368 }
369 } else if (client_id == SOC15_IH_CLIENTID_VMC ||
370 client_id == SOC15_IH_CLIENTID_VMC1 ||
371 client_id == SOC15_IH_CLIENTID_UTCL2) {
372 struct kfd_vm_fault_info info = {0};
373 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);
374 uint32_t node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry);
375 uint32_t vmid_type = SOC15_VMID_TYPE_FROM_IH_ENTRY(ih_ring_entry);
376 int hub_inst = 0;
377 struct kfd_hsa_memory_exception_data exception_data;
378
379 /* gfxhub */
380 if (!vmid_type && dev->adev->gfx.funcs->ih_node_to_logical_xcc) {
381 hub_inst = dev->adev->gfx.funcs->ih_node_to_logical_xcc(dev->adev,
382 node_id);
383 if (hub_inst < 0)
384 hub_inst = 0;
385 }
386
387 /* mmhub */
388 if (vmid_type && client_id == SOC15_IH_CLIENTID_VMC)
389 hub_inst = node_id / 4;
390
391 if (amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev,
392 hub_inst, vmid_type)) {
393 event_interrupt_poison_consumption(dev, pasid, client_id);
394 return;
395 }
396
397 info.vmid = vmid;
398 info.mc_id = client_id;
399 info.page_addr = ih_ring_entry[4] |
400 (uint64_t)(ih_ring_entry[5] & 0xf) << 32;
401 info.prot_valid = ring_id & 0x08;
402 info.prot_read = ring_id & 0x10;
403 info.prot_write = ring_id & 0x20;
404
405 memset(&exception_data, 0, sizeof(exception_data));
406 exception_data.gpu_id = dev->id;
407 exception_data.va = (info.page_addr) << PAGE_SHIFT;
408 exception_data.failure.NotPresent = info.prot_valid ? 1 : 0;
409 exception_data.failure.NoExecute = info.prot_exec ? 1 : 0;
410 exception_data.failure.ReadOnly = info.prot_write ? 1 : 0;
411 exception_data.failure.imprecise = 0;
412
413 kfd_set_dbg_ev_from_interrupt(dev,
414 pasid,
415 -1,
416 KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION),
417 &exception_data,
418 sizeof(exception_data));
419 } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) {
420 kfd_process_close_interrupt_drain(pasid);
421 }
422 }
423
424 const struct kfd_event_interrupt_class event_interrupt_class_v10 = {
425 .interrupt_isr = event_interrupt_isr_v10,
426 .interrupt_wq = event_interrupt_wq_v10,
427 };
428