1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_REGS_H_ 7 #define _XE_GT_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset 13 * for the media GT. xe_mmio and xe_gt_mcr functions will automatically 14 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. 15 */ 16 #define MEDIA_GT_GSI_OFFSET 0x380000 17 #define MEDIA_GT_GSI_LENGTH 0x40000 18 19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) 21 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 22 #define MTL_CC_MASK REG_GENMASK(12, 9) 23 24 /* RPM unit config (Gen8+) */ 25 #define RPM_CONFIG0 XE_REG(0xd00) 26 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 27 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 28 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 29 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 30 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 31 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 32 33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4) 34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4) 35 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84) 36 37 #define GMD_ID XE_REG(0xd8c) 38 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 39 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 40 #define GMD_ID_REVID REG_GENMASK(5, 0) 41 42 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) 43 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) 44 45 #define MCFG_MCR_SELECTOR XE_REG(0xfd0) 46 #define MTL_MCR_SELECTOR XE_REG(0xfd4) 47 #define SF_MCR_SELECTOR XE_REG(0xfd8) 48 #define MCR_SELECTOR XE_REG(0xfdc) 49 #define GAM_MCR_SELECTOR XE_REG(0xfe0) 50 #define MCR_MULTICAST REG_BIT(31) 51 #define MCR_SLICE_MASK REG_GENMASK(30, 27) 52 #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) 53 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) 54 #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) 55 #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 56 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 57 58 #define PS_INVOCATION_COUNT XE_REG(0x2348) 59 60 #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) 61 #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4) 62 #define CCS_AUX_INV XE_REG(0x4208) 63 64 #define VD0_AUX_INV XE_REG(0x4218) 65 #define VE0_AUX_INV XE_REG(0x4238) 66 67 #define VE1_AUX_INV XE_REG(0x42b8) 68 #define AUX_INV REG_BIT(0) 69 70 #define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4) 71 #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) 72 73 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) 74 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) 75 76 #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) 77 #define TBIMR_FAST_CLIP REG_BIT(5) 78 79 #define FF_MODE XE_REG_MCR(0x6210) 80 #define DIS_TE_AUTOSTRIP REG_BIT(31) 81 #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16) 82 #define DIS_MESH_AUTOSTRIP REG_BIT(15) 83 84 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED) 85 #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9) 86 #define DIS_AUTOSTRIP REG_BIT(6) 87 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 88 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 89 90 #define FF_MODE2 XE_REG(0x6604) 91 #define XEHP_FF_MODE2 XE_REG_MCR(0x6604) 92 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 93 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 94 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 95 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 96 97 #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) 98 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 99 100 #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010) 101 102 #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) 103 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 104 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 105 106 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) 107 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 108 109 #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) 110 #define FLSH_IGNORES_PSD REG_BIT(10) 111 #define FD_END_COLLECT REG_BIT(5) 112 113 #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) 114 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 115 116 #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED) 117 #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED) 118 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 119 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 120 #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 121 #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 122 123 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 124 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 125 126 #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED) 127 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 128 129 #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED) 130 #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13) 131 132 #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED) 133 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 134 135 #define SQCNT1 XE_REG_MCR(0x8718) 136 #define XELPMP_SQCNT1 XE_REG(0x8718) 137 #define ENFORCE_RAR REG_BIT(23) 138 139 #define XEHP_SQCM XE_REG_MCR(0x8724) 140 #define EN_32B_ACCESS REG_BIT(30) 141 142 #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) 143 #define XE2_FLAT_CCS_ENABLE REG_BIT(0) 144 145 #define GSCPSMI_BASE XE_REG(0x880c) 146 147 /* Fuse readout registers for GT */ 148 #define XEHP_FUSE4 XE_REG(0x9114) 149 #define CCS_EN_MASK REG_GENMASK(19, 16) 150 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 151 152 #define MIRROR_FUSE3 XE_REG(0x9118) 153 #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) 154 #define L3BANK_PAIR_COUNT 4 155 #define L3BANK_MASK REG_GENMASK(3, 0) 156 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 157 #define MAX_MSLICES 4 158 #define MEML3_EN_MASK REG_GENMASK(3, 0) 159 160 #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 161 #define XELP_EU_MASK REG_GENMASK(7, 0) 162 #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) 163 164 #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) 165 #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 166 #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 167 168 #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) 169 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) 170 #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) 171 #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) 172 #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) 173 174 #define GDRST XE_REG(0x941c) 175 #define GRDOM_GUC REG_BIT(3) 176 #define GRDOM_FULL REG_BIT(0) 177 178 #define MISCCPCTL XE_REG(0x9424) 179 #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 180 181 #define UNSLCGCTL9430 XE_REG(0x9430) 182 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 183 184 #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434) 185 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 186 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 187 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 188 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 189 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 190 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 191 192 #define UNSLCGCTL9440 XE_REG(0x9440) 193 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 194 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 195 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 196 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 197 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 198 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 199 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 200 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 201 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 202 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 203 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 204 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 205 206 #define UNSLCGCTL9444 XE_REG(0x9444) 207 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 208 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 209 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 210 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 211 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 212 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 213 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 214 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 215 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 216 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 217 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 218 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 219 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 220 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 221 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 222 #define LTCDD_CLKGATE_DIS REG_BIT(10) 223 224 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4) 225 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 226 #define L3_CLKGATE_DIS REG_BIT(16) 227 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 228 #define MSCUNIT_CLKGATE_DIS REG_BIT(10) 229 #define RCCUNIT_CLKGATE_DIS REG_BIT(7) 230 #define SARBUNIT_CLKGATE_DIS REG_BIT(5) 231 #define SBEUNIT_CLKGATE_DIS REG_BIT(4) 232 233 #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4) 234 #define VSUNIT_CLKGATE2_DIS REG_BIT(19) 235 236 #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524) 237 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 238 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 239 240 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528) 241 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 242 243 #define SSMCGCTL9530 XE_REG_MCR(0x9530) 244 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 245 246 #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550) 247 #define DFR_DISABLE REG_BIT(9) 248 249 #define RPNSWREQ XE_REG(0xa008) 250 #define REQ_RATIO_MASK REG_GENMASK(31, 23) 251 252 #define RP_CONTROL XE_REG(0xa024) 253 #define RPSWCTL_MASK REG_GENMASK(10, 9) 254 #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) 255 #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) 256 #define RC_CONTROL XE_REG(0xa090) 257 #define RC_CTL_HW_ENABLE REG_BIT(31) 258 #define RC_CTL_TO_MODE REG_BIT(28) 259 #define RC_CTL_RC6_ENABLE REG_BIT(18) 260 #define RC_STATE XE_REG(0xa094) 261 #define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) 262 263 #define PMINTRMSK XE_REG(0xa168) 264 #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) 265 #define ARAT_EXPIRED_INTRMSK REG_BIT(9) 266 267 #define FORCEWAKE_GT XE_REG(0xa188) 268 269 #define PG_ENABLE XE_REG(0xa210) 270 271 #define CTC_MODE XE_REG(0xa26c) 272 #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 273 #define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0) 274 275 #define FORCEWAKE_RENDER XE_REG(0xa278) 276 #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) 277 #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) 278 #define FORCEWAKE_GSC XE_REG(0xa618) 279 280 #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) 281 #define XEHPC_OVRLSCCC REG_BIT(0) 282 283 /* L3 Cache Control */ 284 #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) 285 #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) 286 #define LNCFCMOCS_REG_COUNT 32 287 288 #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) 289 #define XEHP_LNESPARE REG_BIT(19) 290 291 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) 292 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 293 294 #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188) 295 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 296 297 #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) 298 299 #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) 300 301 #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) 302 #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) 303 #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) 304 #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34) 305 #define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34) 306 #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38) 307 #define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38) 308 #define FORCE_MISS_FTLB REG_BIT(3) 309 310 #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c) 311 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 312 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 313 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 314 315 #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54) 316 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 317 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 318 319 #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) 320 #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) 321 322 #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED) 323 #define ENABLE_SMALLPL REG_BIT(15) 324 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 325 #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 326 #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 327 328 #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) 329 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 330 331 #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) 332 #define DISABLE_ECC REG_BIT(5) 333 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 334 335 #define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED) 336 #define DISABLE_GRF_CLEAR REG_BIT(13) 337 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 338 #define DISABLE_TDL_PUSH REG_BIT(9) 339 #define DIS_PICK_2ND_EU REG_BIT(7) 340 #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 341 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 342 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 343 344 #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) 345 #define DIS_FIX_EOT1_FLUSH REG_BIT(9) 346 347 #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) 348 #define UGM_BACKUP_MODE REG_BIT(13) 349 #define MDQ_ARBITRATION_MODE REG_BIT(12) 350 #define EARLY_EOT_DIS REG_BIT(1) 351 352 #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED) 353 #define DISABLE_READ_SUPPRESSION REG_BIT(15) 354 #define DISABLE_EARLY_READ REG_BIT(14) 355 #define ENABLE_LARGE_GRF_MODE REG_BIT(12) 356 #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 357 #define DISABLE_DOP_GATING REG_BIT(0) 358 359 #define RT_CTRL XE_REG_MCR(0xe530) 360 #define DIS_NULL_QUERY REG_BIT(10) 361 362 #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) 363 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 364 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 365 366 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) 367 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 368 #define TGM_WRITE_EOM_FORCE REG_BIT(17) 369 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 370 #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) 371 372 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) 373 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) 374 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 375 #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32) 376 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 377 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 378 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 379 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 380 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 381 382 #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) 383 #define COMP_CKN_IN REG_GENMASK(30, 29) 384 385 #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED) 386 #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 387 #define RCU_MODE_CCS_ENABLE REG_BIT(0) 388 389 /* 390 * Total of 4 cslices, where each cslice is in the form: 391 * [0-3] CCS ID 392 * [4-6] RSVD 393 * [7] Disabled 394 */ 395 #define CCS_MODE XE_REG(0x14804) 396 #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ 397 #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ 398 #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) 399 #define CCS_MODE_CSLICE(cslice, ccs) \ 400 ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH)) 401 402 #define FORCEWAKE_ACK_GT XE_REG(0x130044) 403 #define FORCEWAKE_KERNEL BIT(0) 404 #define FORCEWAKE_USER BIT(1) 405 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 406 407 #define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) 408 #define MTL_MEDIA_MC6 XE_REG(0x138048) 409 410 #define GT_CORE_STATUS XE_REG(0x138060) 411 #define RCN_MASK REG_GENMASK(2, 0) 412 #define GT_C0 0 413 #define GT_C6 3 414 415 #define GT_GFX_RC6_LOCKED XE_REG(0x138104) 416 #define GT_GFX_RC6 XE_REG(0x138108) 417 418 #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) 419 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 420 #define PROCHOT_MASK REG_BIT(0) 421 #define THERMAL_LIMIT_MASK REG_BIT(1) 422 #define RATL_MASK REG_BIT(5) 423 #define VR_THERMALERT_MASK REG_BIT(6) 424 #define VR_TDC_MASK REG_BIT(7) 425 #define POWER_LIMIT_4_MASK REG_BIT(8) 426 #define POWER_LIMIT_1_MASK REG_BIT(10) 427 #define POWER_LIMIT_2_MASK REG_BIT(11) 428 429 #define GT_PERF_STATUS XE_REG(0x1381b4) 430 #define VOLTAGE_MASK REG_GENMASK(10, 0) 431 432 #define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4)) 433 434 #define RENDER_COPY_INTR_ENABLE XE_REG(0x190030) 435 #define VCS_VECS_INTR_ENABLE XE_REG(0x190034) 436 #define GUC_SG_INTR_ENABLE XE_REG(0x190038) 437 #define ENGINE1_MASK REG_GENMASK(31, 16) 438 #define ENGINE0_MASK REG_GENMASK(15, 0) 439 #define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c) 440 #define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044) 441 #define CCS_RSVD_INTR_ENABLE XE_REG(0x190048) 442 443 #define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4)) 444 #define INTR_DATA_VALID REG_BIT(31) 445 #define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x) 446 #define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x) 447 #define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x) 448 #define OTHER_GUC_INSTANCE 0 449 #define OTHER_GSC_INSTANCE 6 450 451 #define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4)) 452 #define RCS0_RSVD_INTR_MASK XE_REG(0x190090) 453 #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0) 454 #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8) 455 #define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac) 456 #define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0) 457 #define GUC_SG_INTR_MASK XE_REG(0x1900e8) 458 #define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec) 459 #define GUNIT_GSC_INTR_MASK XE_REG(0x1900f4) 460 #define CCS0_CCS1_INTR_MASK XE_REG(0x190100) 461 #define CCS2_CCS3_INTR_MASK XE_REG(0x190104) 462 #define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110) 463 #define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114) 464 #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118) 465 #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c) 466 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) 467 #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) 468 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) 469 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 470 #define GT_RENDER_USER_INTERRUPT REG_BIT(0) 471 472 #define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004) 473 #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008) 474 #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068) 475 #define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c) 476 #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080) 477 478 #endif 479