1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_STATUS_EN_MSK BIT(10)
48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
55
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
61
62 #define CHIPID_AD7124_4 0x0
63 #define CHIPID_AD7124_8 0x1
64
65 /* AD7124_CHANNEL_X */
66 #define AD7124_CHANNEL_EN_MSK BIT(15)
67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
74
75 /* AD7124_CONFIG_X */
76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
84
85 /* AD7124_FILTER_X */
86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
90
91 #define AD7124_SINC3_FILTER 2
92 #define AD7124_SINC4_FILTER 0
93
94 #define AD7124_CONF_ADDR_OFFSET 20
95 #define AD7124_MAX_CONFIGS 8
96 #define AD7124_MAX_CHANNELS 16
97
98 enum ad7124_ids {
99 ID_AD7124_4,
100 ID_AD7124_8,
101 };
102
103 enum ad7124_ref_sel {
104 AD7124_REFIN1,
105 AD7124_REFIN2,
106 AD7124_INT_REF,
107 AD7124_AVDD_REF,
108 };
109
110 enum ad7124_power_mode {
111 AD7124_LOW_POWER,
112 AD7124_MID_POWER,
113 AD7124_FULL_POWER,
114 };
115
116 static const unsigned int ad7124_gain[8] = {
117 1, 2, 4, 8, 16, 32, 64, 128
118 };
119
120 static const unsigned int ad7124_reg_size[] = {
121 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
122 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
123 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
124 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
125 3, 3, 3, 3, 3
126 };
127
128 static const int ad7124_master_clk_freq_hz[3] = {
129 [AD7124_LOW_POWER] = 76800,
130 [AD7124_MID_POWER] = 153600,
131 [AD7124_FULL_POWER] = 614400,
132 };
133
134 static const char * const ad7124_ref_names[] = {
135 [AD7124_REFIN1] = "refin1",
136 [AD7124_REFIN2] = "refin2",
137 [AD7124_INT_REF] = "int",
138 [AD7124_AVDD_REF] = "avdd",
139 };
140
141 struct ad7124_chip_info {
142 const char *name;
143 unsigned int chip_id;
144 unsigned int num_inputs;
145 };
146
147 struct ad7124_channel_config {
148 bool live;
149 unsigned int cfg_slot;
150 enum ad7124_ref_sel refsel;
151 bool bipolar;
152 bool buf_positive;
153 bool buf_negative;
154 unsigned int vref_mv;
155 unsigned int pga_bits;
156 unsigned int odr;
157 unsigned int odr_sel_bits;
158 unsigned int filter_type;
159 };
160
161 struct ad7124_channel {
162 unsigned int nr;
163 struct ad7124_channel_config cfg;
164 unsigned int ain;
165 unsigned int slot;
166 };
167
168 struct ad7124_state {
169 const struct ad7124_chip_info *chip_info;
170 struct ad_sigma_delta sd;
171 struct ad7124_channel *channels;
172 struct regulator *vref[4];
173 struct clk *mclk;
174 unsigned int adc_control;
175 unsigned int num_channels;
176 struct mutex cfgs_lock; /* lock for configs access */
177 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
178 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
179 };
180
181 static const struct iio_chan_spec ad7124_channel_template = {
182 .type = IIO_VOLTAGE,
183 .indexed = 1,
184 .differential = 1,
185 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
186 BIT(IIO_CHAN_INFO_SCALE) |
187 BIT(IIO_CHAN_INFO_OFFSET) |
188 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
189 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
190 .scan_type = {
191 .sign = 'u',
192 .realbits = 24,
193 .storagebits = 32,
194 .endianness = IIO_BE,
195 },
196 };
197
198 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
199 [ID_AD7124_4] = {
200 .name = "ad7124-4",
201 .chip_id = CHIPID_AD7124_4,
202 .num_inputs = 8,
203 },
204 [ID_AD7124_8] = {
205 .name = "ad7124-8",
206 .chip_id = CHIPID_AD7124_8,
207 .num_inputs = 16,
208 },
209 };
210
ad7124_find_closest_match(const int * array,unsigned int size,int val)211 static int ad7124_find_closest_match(const int *array,
212 unsigned int size, int val)
213 {
214 int i, idx;
215 unsigned int diff_new, diff_old;
216
217 diff_old = U32_MAX;
218 idx = 0;
219
220 for (i = 0; i < size; i++) {
221 diff_new = abs(val - array[i]);
222 if (diff_new < diff_old) {
223 diff_old = diff_new;
224 idx = i;
225 }
226 }
227
228 return idx;
229 }
230
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)231 static int ad7124_spi_write_mask(struct ad7124_state *st,
232 unsigned int addr,
233 unsigned long mask,
234 unsigned int val,
235 unsigned int bytes)
236 {
237 unsigned int readval;
238 int ret;
239
240 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
241 if (ret < 0)
242 return ret;
243
244 readval &= ~mask;
245 readval |= val;
246
247 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
248 }
249
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)250 static int ad7124_set_mode(struct ad_sigma_delta *sd,
251 enum ad_sigma_delta_mode mode)
252 {
253 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
254
255 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
256 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
257
258 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
259 }
260
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)261 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
262 {
263 unsigned int fclk, odr_sel_bits;
264
265 fclk = clk_get_rate(st->mclk);
266 /*
267 * FS[10:0] = fCLK / (fADC x 32) where:
268 * fADC is the output data rate
269 * fCLK is the master clock frequency
270 * FS[10:0] are the bits in the filter register
271 * FS[10:0] can have a value from 1 to 2047
272 */
273 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
274 if (odr_sel_bits < 1)
275 odr_sel_bits = 1;
276 else if (odr_sel_bits > 2047)
277 odr_sel_bits = 2047;
278
279 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
280 st->channels[channel].cfg.live = false;
281
282 /* fADC = fCLK / (FS[10:0] x 32) */
283 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
284 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
285 }
286
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)287 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
288 unsigned int channel)
289 {
290 unsigned int fadc;
291
292 fadc = st->channels[channel].cfg.odr;
293
294 switch (st->channels[channel].cfg.filter_type) {
295 case AD7124_SINC3_FILTER:
296 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
297 case AD7124_SINC4_FILTER:
298 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
299 default:
300 return -EINVAL;
301 }
302 }
303
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)304 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
305 unsigned int freq)
306 {
307 unsigned int sinc4_3db_odr;
308 unsigned int sinc3_3db_odr;
309 unsigned int new_filter;
310 unsigned int new_odr;
311
312 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
313 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
314
315 if (sinc4_3db_odr > sinc3_3db_odr) {
316 new_filter = AD7124_SINC3_FILTER;
317 new_odr = sinc4_3db_odr;
318 } else {
319 new_filter = AD7124_SINC4_FILTER;
320 new_odr = sinc3_3db_odr;
321 }
322
323 if (new_odr != st->channels[channel].cfg.odr)
324 st->channels[channel].cfg.live = false;
325
326 st->channels[channel].cfg.filter_type = new_filter;
327 st->channels[channel].cfg.odr = new_odr;
328 }
329
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)330 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
331 struct ad7124_channel_config *cfg)
332 {
333 struct ad7124_channel_config *cfg_aux;
334 ptrdiff_t cmp_size;
335 int i;
336
337 cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
338 for (i = 0; i < st->num_channels; i++) {
339 cfg_aux = &st->channels[i].cfg;
340
341 if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
342 return cfg_aux;
343 }
344
345 return NULL;
346 }
347
ad7124_find_free_config_slot(struct ad7124_state * st)348 static int ad7124_find_free_config_slot(struct ad7124_state *st)
349 {
350 unsigned int free_cfg_slot;
351
352 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
353 if (free_cfg_slot == AD7124_MAX_CONFIGS)
354 return -1;
355
356 return free_cfg_slot;
357 }
358
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)359 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
360 {
361 unsigned int refsel = cfg->refsel;
362
363 switch (refsel) {
364 case AD7124_REFIN1:
365 case AD7124_REFIN2:
366 case AD7124_AVDD_REF:
367 if (IS_ERR(st->vref[refsel])) {
368 dev_err(&st->sd.spi->dev,
369 "Error, trying to use external voltage reference without a %s regulator.\n",
370 ad7124_ref_names[refsel]);
371 return PTR_ERR(st->vref[refsel]);
372 }
373 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
374 /* Conversion from uV to mV */
375 cfg->vref_mv /= 1000;
376 return 0;
377 case AD7124_INT_REF:
378 cfg->vref_mv = 2500;
379 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
380 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
381 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
382 2, st->adc_control);
383 default:
384 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
385 return -EINVAL;
386 }
387 }
388
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)389 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
390 unsigned int cfg_slot)
391 {
392 unsigned int tmp;
393 unsigned int val;
394 int ret;
395
396 cfg->cfg_slot = cfg_slot;
397
398 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
399 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
400 AD7124_CONFIG_IN_BUFF(tmp);
401 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
402 if (ret < 0)
403 return ret;
404
405 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
406 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
407 tmp, 3);
408 if (ret < 0)
409 return ret;
410
411 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
412 AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
413 if (ret < 0)
414 return ret;
415
416 return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
417 AD7124_CONFIG_PGA(cfg->pga_bits), 2);
418 }
419
ad7124_pop_config(struct ad7124_state * st)420 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
421 {
422 struct ad7124_channel_config *lru_cfg;
423 struct ad7124_channel_config *cfg;
424 int ret;
425 int i;
426
427 /*
428 * Pop least recently used config from the fifo
429 * in order to make room for the new one
430 */
431 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
432 if (ret <= 0)
433 return NULL;
434
435 lru_cfg->live = false;
436
437 /* mark slot as free */
438 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
439
440 /* invalidate all other configs that pointed to this one */
441 for (i = 0; i < st->num_channels; i++) {
442 cfg = &st->channels[i].cfg;
443
444 if (cfg->cfg_slot == lru_cfg->cfg_slot)
445 cfg->live = false;
446 }
447
448 return lru_cfg;
449 }
450
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)451 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
452 {
453 struct ad7124_channel_config *lru_cfg;
454 int free_cfg_slot;
455
456 free_cfg_slot = ad7124_find_free_config_slot(st);
457 if (free_cfg_slot >= 0) {
458 /* push the new config in configs queue */
459 kfifo_put(&st->live_cfgs_fifo, cfg);
460 } else {
461 /* pop one config to make room for the new one */
462 lru_cfg = ad7124_pop_config(st);
463 if (!lru_cfg)
464 return -EINVAL;
465
466 /* push the new config in configs queue */
467 free_cfg_slot = lru_cfg->cfg_slot;
468 kfifo_put(&st->live_cfgs_fifo, cfg);
469 }
470
471 /* mark slot as used */
472 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
473
474 return ad7124_write_config(st, cfg, free_cfg_slot);
475 }
476
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)477 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
478 {
479 ch->cfg.live = true;
480 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
481 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
482 }
483
ad7124_prepare_read(struct ad7124_state * st,int address)484 static int ad7124_prepare_read(struct ad7124_state *st, int address)
485 {
486 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
487 struct ad7124_channel_config *live_cfg;
488
489 /*
490 * Before doing any reads assign the channel a configuration.
491 * Check if channel's config is on the device
492 */
493 if (!cfg->live) {
494 /* check if config matches another one */
495 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
496 if (!live_cfg)
497 ad7124_push_config(st, cfg);
498 else
499 cfg->cfg_slot = live_cfg->cfg_slot;
500 }
501
502 /* point channel to the config slot and enable */
503 return ad7124_enable_channel(st, &st->channels[address]);
504 }
505
__ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)506 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
507 {
508 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
509
510 return ad7124_prepare_read(st, channel);
511 }
512
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)513 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
514 {
515 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
516 int ret;
517
518 mutex_lock(&st->cfgs_lock);
519 ret = __ad7124_set_channel(sd, channel);
520 mutex_unlock(&st->cfgs_lock);
521
522 return ret;
523 }
524
ad7124_append_status(struct ad_sigma_delta * sd,bool append)525 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
526 {
527 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
528 unsigned int adc_control = st->adc_control;
529 int ret;
530
531 adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
532 adc_control |= AD7124_ADC_STATUS_EN(append);
533
534 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
535 if (ret < 0)
536 return ret;
537
538 st->adc_control = adc_control;
539
540 return 0;
541 }
542
ad7124_disable_all(struct ad_sigma_delta * sd)543 static int ad7124_disable_all(struct ad_sigma_delta *sd)
544 {
545 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
546 int ret;
547 int i;
548
549 for (i = 0; i < st->num_channels; i++) {
550 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2);
551 if (ret < 0)
552 return ret;
553 }
554
555 return 0;
556 }
557
558 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
559 .set_channel = ad7124_set_channel,
560 .append_status = ad7124_append_status,
561 .disable_all = ad7124_disable_all,
562 .set_mode = ad7124_set_mode,
563 .has_registers = true,
564 .addr_shift = 0,
565 .read_mask = BIT(6),
566 .status_ch_mask = GENMASK(3, 0),
567 .data_reg = AD7124_DATA,
568 .num_slots = 8,
569 .irq_flags = IRQF_TRIGGER_FALLING,
570 };
571
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)572 static int ad7124_read_raw(struct iio_dev *indio_dev,
573 struct iio_chan_spec const *chan,
574 int *val, int *val2, long info)
575 {
576 struct ad7124_state *st = iio_priv(indio_dev);
577 int idx, ret;
578
579 switch (info) {
580 case IIO_CHAN_INFO_RAW:
581 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
582 if (ret < 0)
583 return ret;
584
585 /* After the conversion is performed, disable the channel */
586 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
587 st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
588 if (ret < 0)
589 return ret;
590
591 return IIO_VAL_INT;
592 case IIO_CHAN_INFO_SCALE:
593 mutex_lock(&st->cfgs_lock);
594
595 idx = st->channels[chan->address].cfg.pga_bits;
596 *val = st->channels[chan->address].cfg.vref_mv;
597 if (st->channels[chan->address].cfg.bipolar)
598 *val2 = chan->scan_type.realbits - 1 + idx;
599 else
600 *val2 = chan->scan_type.realbits + idx;
601
602 mutex_unlock(&st->cfgs_lock);
603 return IIO_VAL_FRACTIONAL_LOG2;
604 case IIO_CHAN_INFO_OFFSET:
605 mutex_lock(&st->cfgs_lock);
606 if (st->channels[chan->address].cfg.bipolar)
607 *val = -(1 << (chan->scan_type.realbits - 1));
608 else
609 *val = 0;
610
611 mutex_unlock(&st->cfgs_lock);
612 return IIO_VAL_INT;
613 case IIO_CHAN_INFO_SAMP_FREQ:
614 mutex_lock(&st->cfgs_lock);
615 *val = st->channels[chan->address].cfg.odr;
616 mutex_unlock(&st->cfgs_lock);
617
618 return IIO_VAL_INT;
619 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
620 mutex_lock(&st->cfgs_lock);
621 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
622 mutex_unlock(&st->cfgs_lock);
623
624 return IIO_VAL_INT;
625 default:
626 return -EINVAL;
627 }
628 }
629
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)630 static int ad7124_write_raw(struct iio_dev *indio_dev,
631 struct iio_chan_spec const *chan,
632 int val, int val2, long info)
633 {
634 struct ad7124_state *st = iio_priv(indio_dev);
635 unsigned int res, gain, full_scale, vref;
636 int ret = 0;
637
638 mutex_lock(&st->cfgs_lock);
639
640 switch (info) {
641 case IIO_CHAN_INFO_SAMP_FREQ:
642 if (val2 != 0) {
643 ret = -EINVAL;
644 break;
645 }
646
647 ad7124_set_channel_odr(st, chan->address, val);
648 break;
649 case IIO_CHAN_INFO_SCALE:
650 if (val != 0) {
651 ret = -EINVAL;
652 break;
653 }
654
655 if (st->channels[chan->address].cfg.bipolar)
656 full_scale = 1 << (chan->scan_type.realbits - 1);
657 else
658 full_scale = 1 << chan->scan_type.realbits;
659
660 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
661 res = DIV_ROUND_CLOSEST(vref, full_scale);
662 gain = DIV_ROUND_CLOSEST(res, val2);
663 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
664
665 if (st->channels[chan->address].cfg.pga_bits != res)
666 st->channels[chan->address].cfg.live = false;
667
668 st->channels[chan->address].cfg.pga_bits = res;
669 break;
670 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
671 if (val2 != 0) {
672 ret = -EINVAL;
673 break;
674 }
675
676 ad7124_set_3db_filter_freq(st, chan->address, val);
677 break;
678 default:
679 ret = -EINVAL;
680 }
681
682 mutex_unlock(&st->cfgs_lock);
683 return ret;
684 }
685
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)686 static int ad7124_reg_access(struct iio_dev *indio_dev,
687 unsigned int reg,
688 unsigned int writeval,
689 unsigned int *readval)
690 {
691 struct ad7124_state *st = iio_priv(indio_dev);
692 int ret;
693
694 if (reg >= ARRAY_SIZE(ad7124_reg_size))
695 return -EINVAL;
696
697 if (readval)
698 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
699 readval);
700 else
701 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
702 writeval);
703
704 return ret;
705 }
706
707 static IIO_CONST_ATTR(in_voltage_scale_available,
708 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
709
710 static struct attribute *ad7124_attributes[] = {
711 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
712 NULL,
713 };
714
715 static const struct attribute_group ad7124_attrs_group = {
716 .attrs = ad7124_attributes,
717 };
718
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)719 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
720 const unsigned long *scan_mask)
721 {
722 struct ad7124_state *st = iio_priv(indio_dev);
723 bool bit_set;
724 int ret;
725 int i;
726
727 mutex_lock(&st->cfgs_lock);
728 for (i = 0; i < st->num_channels; i++) {
729 bit_set = test_bit(i, scan_mask);
730 if (bit_set)
731 ret = __ad7124_set_channel(&st->sd, i);
732 else
733 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
734 0, 2);
735 if (ret < 0) {
736 mutex_unlock(&st->cfgs_lock);
737
738 return ret;
739 }
740 }
741
742 mutex_unlock(&st->cfgs_lock);
743
744 return 0;
745 }
746
747 static const struct iio_info ad7124_info = {
748 .read_raw = ad7124_read_raw,
749 .write_raw = ad7124_write_raw,
750 .debugfs_reg_access = &ad7124_reg_access,
751 .validate_trigger = ad_sd_validate_trigger,
752 .update_scan_mode = ad7124_update_scan_mode,
753 .attrs = &ad7124_attrs_group,
754 };
755
ad7124_soft_reset(struct ad7124_state * st)756 static int ad7124_soft_reset(struct ad7124_state *st)
757 {
758 unsigned int readval, timeout;
759 int ret;
760
761 ret = ad_sd_reset(&st->sd, 64);
762 if (ret < 0)
763 return ret;
764
765 timeout = 100;
766 do {
767 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
768 if (ret < 0)
769 return ret;
770
771 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
772 return 0;
773
774 /* The AD7124 requires typically 2ms to power up and settle */
775 usleep_range(100, 2000);
776 } while (--timeout);
777
778 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
779
780 return -EIO;
781 }
782
ad7124_check_chip_id(struct ad7124_state * st)783 static int ad7124_check_chip_id(struct ad7124_state *st)
784 {
785 unsigned int readval, chip_id, silicon_rev;
786 int ret;
787
788 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
789 if (ret < 0)
790 return ret;
791
792 chip_id = AD7124_DEVICE_ID_GET(readval);
793 silicon_rev = AD7124_SILICON_REV_GET(readval);
794
795 if (chip_id != st->chip_info->chip_id) {
796 dev_err(&st->sd.spi->dev,
797 "Chip ID mismatch: expected %u, got %u\n",
798 st->chip_info->chip_id, chip_id);
799 return -ENODEV;
800 }
801
802 if (silicon_rev == 0) {
803 dev_err(&st->sd.spi->dev,
804 "Silicon revision empty. Chip may not be present\n");
805 return -ENODEV;
806 }
807
808 return 0;
809 }
810
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)811 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
812 struct device *dev)
813 {
814 struct ad7124_state *st = iio_priv(indio_dev);
815 struct ad7124_channel_config *cfg;
816 struct ad7124_channel *channels;
817 struct iio_chan_spec *chan;
818 unsigned int ain[2], channel = 0, tmp;
819 int ret;
820
821 st->num_channels = device_get_child_node_count(dev);
822 if (!st->num_channels)
823 return dev_err_probe(dev, -ENODEV, "no channel children\n");
824
825 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
826 sizeof(*chan), GFP_KERNEL);
827 if (!chan)
828 return -ENOMEM;
829
830 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
831 GFP_KERNEL);
832 if (!channels)
833 return -ENOMEM;
834
835 indio_dev->channels = chan;
836 indio_dev->num_channels = st->num_channels;
837 st->channels = channels;
838
839 device_for_each_child_node_scoped(dev, child) {
840 cfg = &st->channels[channel].cfg;
841
842 ret = fwnode_property_read_u32(child, "reg", &channel);
843 if (ret)
844 return ret;
845
846 if (channel >= indio_dev->num_channels)
847 return dev_err_probe(dev, -EINVAL,
848 "Channel index >= number of channels\n");
849
850 ret = fwnode_property_read_u32_array(child, "diff-channels",
851 ain, 2);
852 if (ret)
853 return ret;
854
855 st->channels[channel].nr = channel;
856 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
857 AD7124_CHANNEL_AINM(ain[1]);
858
859 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
860
861 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
862 if (ret)
863 cfg->refsel = AD7124_INT_REF;
864 else
865 cfg->refsel = tmp;
866
867 cfg->buf_positive =
868 fwnode_property_read_bool(child, "adi,buffered-positive");
869 cfg->buf_negative =
870 fwnode_property_read_bool(child, "adi,buffered-negative");
871
872 chan[channel] = ad7124_channel_template;
873 chan[channel].address = channel;
874 chan[channel].scan_index = channel;
875 chan[channel].channel = ain[0];
876 chan[channel].channel2 = ain[1];
877 }
878
879 return 0;
880 }
881
ad7124_setup(struct ad7124_state * st)882 static int ad7124_setup(struct ad7124_state *st)
883 {
884 unsigned int fclk, power_mode;
885 int i, ret;
886
887 fclk = clk_get_rate(st->mclk);
888 if (!fclk)
889 return -EINVAL;
890
891 /* The power mode changes the master clock frequency */
892 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
893 ARRAY_SIZE(ad7124_master_clk_freq_hz),
894 fclk);
895 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
896 ret = clk_set_rate(st->mclk, fclk);
897 if (ret)
898 return ret;
899 }
900
901 /* Set the power mode */
902 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
903 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
904 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
905 if (ret < 0)
906 return ret;
907
908 mutex_init(&st->cfgs_lock);
909 INIT_KFIFO(st->live_cfgs_fifo);
910 for (i = 0; i < st->num_channels; i++) {
911
912 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
913 if (ret < 0)
914 return ret;
915
916 /*
917 * 9.38 SPS is the minimum output data rate supported
918 * regardless of the selected power mode. Round it up to 10 and
919 * set all channels to this default value.
920 */
921 ad7124_set_channel_odr(st, i, 10);
922 }
923
924 return ret;
925 }
926
ad7124_reg_disable(void * r)927 static void ad7124_reg_disable(void *r)
928 {
929 regulator_disable(r);
930 }
931
ad7124_probe(struct spi_device * spi)932 static int ad7124_probe(struct spi_device *spi)
933 {
934 const struct ad7124_chip_info *info;
935 struct ad7124_state *st;
936 struct iio_dev *indio_dev;
937 int i, ret;
938
939 info = spi_get_device_match_data(spi);
940 if (!info)
941 return -ENODEV;
942
943 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
944 if (!indio_dev)
945 return -ENOMEM;
946
947 st = iio_priv(indio_dev);
948
949 st->chip_info = info;
950
951 indio_dev->name = st->chip_info->name;
952 indio_dev->modes = INDIO_DIRECT_MODE;
953 indio_dev->info = &ad7124_info;
954
955 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
956 if (ret < 0)
957 return ret;
958
959 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
960 if (ret < 0)
961 return ret;
962
963 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
964 if (i == AD7124_INT_REF)
965 continue;
966
967 st->vref[i] = devm_regulator_get_optional(&spi->dev,
968 ad7124_ref_names[i]);
969 if (PTR_ERR(st->vref[i]) == -ENODEV)
970 continue;
971 else if (IS_ERR(st->vref[i]))
972 return PTR_ERR(st->vref[i]);
973
974 ret = regulator_enable(st->vref[i]);
975 if (ret)
976 return ret;
977
978 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
979 st->vref[i]);
980 if (ret)
981 return ret;
982 }
983
984 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
985 if (IS_ERR(st->mclk))
986 return PTR_ERR(st->mclk);
987
988 ret = ad7124_soft_reset(st);
989 if (ret < 0)
990 return ret;
991
992 ret = ad7124_check_chip_id(st);
993 if (ret)
994 return ret;
995
996 ret = ad7124_setup(st);
997 if (ret < 0)
998 return ret;
999
1000 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1001 if (ret < 0)
1002 return ret;
1003
1004 return devm_iio_device_register(&spi->dev, indio_dev);
1005
1006 }
1007
1008 static const struct of_device_id ad7124_of_match[] = {
1009 { .compatible = "adi,ad7124-4",
1010 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1011 { .compatible = "adi,ad7124-8",
1012 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1013 { },
1014 };
1015 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1016
1017 static const struct spi_device_id ad71124_ids[] = {
1018 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1019 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1020 {}
1021 };
1022 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1023
1024 static struct spi_driver ad71124_driver = {
1025 .driver = {
1026 .name = "ad7124",
1027 .of_match_table = ad7124_of_match,
1028 },
1029 .probe = ad7124_probe,
1030 .id_table = ad71124_ids,
1031 };
1032 module_spi_driver(ad71124_driver);
1033
1034 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1035 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1036 MODULE_LICENSE("GPL");
1037 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1038