1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/irq/irq-nvic.c
4 *
5 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
6 * Copyright (C) 2013 Pengutronix
7 *
8 * Support for the Nested Vectored Interrupt Controller found on the
9 * ARMv7-M CPUs (Cortex-M3/M4)
10 */
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqdomain.h>
23
24 #include <asm/v7m.h>
25 #include <asm/exception.h>
26
27 #define NVIC_ISER 0x000
28 #define NVIC_ICER 0x080
29 #define NVIC_IPR 0x400
30
31 #define NVIC_MAX_BANKS 16
32 /*
33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
34 * 16 irqs.
35 */
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
37
38 static struct irq_domain *nvic_irq_domain;
39
nvic_handle_irq(struct pt_regs * regs)40 static void __irq_entry nvic_handle_irq(struct pt_regs *regs)
41 {
42 unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR);
43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16;
44
45 generic_handle_domain_irq(nvic_irq_domain, hwirq);
46 }
47
nvic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)48 static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
49 unsigned int nr_irqs, void *arg)
50 {
51 int i, ret;
52 irq_hw_number_t hwirq;
53 unsigned int type = IRQ_TYPE_NONE;
54 struct irq_fwspec *fwspec = arg;
55
56 ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
57 if (ret)
58 return ret;
59
60 for (i = 0; i < nr_irqs; i++)
61 irq_map_generic_chip(domain, virq + i, hwirq + i);
62
63 return 0;
64 }
65
66 static const struct irq_domain_ops nvic_irq_domain_ops = {
67 .translate = irq_domain_translate_onecell,
68 .alloc = nvic_irq_domain_alloc,
69 .free = irq_domain_free_irqs_top,
70 };
71
nvic_of_init(struct device_node * node,struct device_node * parent)72 static int __init nvic_of_init(struct device_node *node,
73 struct device_node *parent)
74 {
75 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
76 unsigned int irqs, i, ret, numbanks;
77 void __iomem *nvic_base;
78
79 numbanks = (readl_relaxed(V7M_SCS_ICTR) &
80 V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
81
82 nvic_base = of_iomap(node, 0);
83 if (!nvic_base) {
84 pr_warn("unable to map nvic registers\n");
85 return -ENOMEM;
86 }
87
88 irqs = numbanks * 32;
89 if (irqs > NVIC_MAX_IRQ)
90 irqs = NVIC_MAX_IRQ;
91
92 nvic_irq_domain =
93 irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
94
95 if (!nvic_irq_domain) {
96 pr_warn("Failed to allocate irq domain\n");
97 iounmap(nvic_base);
98 return -ENOMEM;
99 }
100
101 ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
102 "nvic_irq", handle_fasteoi_irq,
103 clr, 0, IRQ_GC_INIT_MASK_CACHE);
104 if (ret) {
105 pr_warn("Failed to allocate irq chips\n");
106 irq_domain_remove(nvic_irq_domain);
107 iounmap(nvic_base);
108 return ret;
109 }
110
111 for (i = 0; i < numbanks; ++i) {
112 struct irq_chip_generic *gc;
113
114 gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
115 gc->reg_base = nvic_base + 4 * i;
116 gc->chip_types[0].regs.enable = NVIC_ISER;
117 gc->chip_types[0].regs.disable = NVIC_ICER;
118 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
119 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
120 /* This is a no-op as end of interrupt is signaled by the
121 * exception return sequence.
122 */
123 gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
124
125 /* disable interrupts */
126 writel_relaxed(~0, gc->reg_base + NVIC_ICER);
127 }
128
129 /* Set priority on all interrupts */
130 for (i = 0; i < irqs; i += 4)
131 writel_relaxed(0, nvic_base + NVIC_IPR + i);
132
133 set_handle_irq(nvic_handle_irq);
134 return 0;
135 }
136 IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
137