1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices ADV7511 HDMI Transmitter Device Driver
4 *
5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 */
7
8 /*
9 * This file is named adv7511-v4l2.c so it doesn't conflict with the Analog
10 * Device ADV7511 (config fragment CONFIG_DRM_I2C_ADV7511).
11 */
12
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/delay.h>
19 #include <linux/videodev2.h>
20 #include <linux/workqueue.h>
21 #include <linux/hdmi.h>
22 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-dv-timings.h>
27 #include <media/i2c/adv7511.h>
28 #include <media/cec.h>
29
30 static int debug;
31 module_param(debug, int, 0644);
32 MODULE_PARM_DESC(debug, "debug level (0-2)");
33
34 MODULE_DESCRIPTION("Analog Devices ADV7511 HDMI Transmitter Device Driver");
35 MODULE_AUTHOR("Hans Verkuil");
36 MODULE_LICENSE("GPL v2");
37
38 #define MASK_ADV7511_EDID_RDY_INT 0x04
39 #define MASK_ADV7511_MSEN_INT 0x40
40 #define MASK_ADV7511_HPD_INT 0x80
41
42 #define MASK_ADV7511_HPD_DETECT 0x40
43 #define MASK_ADV7511_MSEN_DETECT 0x20
44 #define MASK_ADV7511_EDID_RDY 0x10
45
46 #define EDID_MAX_RETRIES (8)
47 #define EDID_DELAY 250
48 #define EDID_MAX_SEGM 8
49
50 #define ADV7511_MAX_WIDTH 1920
51 #define ADV7511_MAX_HEIGHT 1200
52 #define ADV7511_MIN_PIXELCLOCK 20000000
53 #define ADV7511_MAX_PIXELCLOCK 225000000
54
55 #define ADV7511_MAX_ADDRS (3)
56
57 /*
58 **********************************************************************
59 *
60 * Arrays with configuration parameters for the ADV7511
61 *
62 **********************************************************************
63 */
64
65 struct i2c_reg_value {
66 unsigned char reg;
67 unsigned char value;
68 };
69
70 struct adv7511_state_edid {
71 /* total number of blocks */
72 u32 blocks;
73 /* Number of segments read */
74 u32 segments;
75 u8 data[EDID_MAX_SEGM * 256];
76 /* Number of EDID read retries left */
77 unsigned read_retries;
78 bool complete;
79 };
80
81 struct adv7511_state {
82 struct adv7511_platform_data pdata;
83 struct v4l2_subdev sd;
84 struct media_pad pad;
85 struct v4l2_ctrl_handler hdl;
86 int chip_revision;
87 u8 i2c_edid_addr;
88 u8 i2c_pktmem_addr;
89 u8 i2c_cec_addr;
90
91 struct i2c_client *i2c_cec;
92 struct cec_adapter *cec_adap;
93 u8 cec_addr[ADV7511_MAX_ADDRS];
94 u8 cec_valid_addrs;
95 bool cec_enabled_adap;
96
97 /* Is the adv7511 powered on? */
98 bool power_on;
99 /* Did we receive hotplug and rx-sense signals? */
100 bool have_monitor;
101 bool enabled_irq;
102 /* timings from s_dv_timings */
103 struct v4l2_dv_timings dv_timings;
104 u32 fmt_code;
105 u32 colorspace;
106 u32 ycbcr_enc;
107 u32 quantization;
108 u32 xfer_func;
109 u32 content_type;
110 /* controls */
111 struct v4l2_ctrl *hdmi_mode_ctrl;
112 struct v4l2_ctrl *hotplug_ctrl;
113 struct v4l2_ctrl *rx_sense_ctrl;
114 struct v4l2_ctrl *have_edid0_ctrl;
115 struct v4l2_ctrl *rgb_quantization_range_ctrl;
116 struct v4l2_ctrl *content_type_ctrl;
117 struct i2c_client *i2c_edid;
118 struct i2c_client *i2c_pktmem;
119 struct adv7511_state_edid edid;
120 /* Running counter of the number of detected EDIDs (for debugging) */
121 unsigned edid_detect_counter;
122 struct workqueue_struct *work_queue;
123 struct delayed_work edid_handler; /* work entry */
124 };
125
126 static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd);
127 static bool adv7511_check_edid_status(struct v4l2_subdev *sd);
128 static void adv7511_setup(struct v4l2_subdev *sd);
129 static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
130 static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
131
132
133 static const struct v4l2_dv_timings_cap adv7511_timings_cap = {
134 .type = V4L2_DV_BT_656_1120,
135 /* keep this initialization for compatibility with GCC < 4.4.6 */
136 .reserved = { 0 },
137 V4L2_INIT_BT_TIMINGS(640, ADV7511_MAX_WIDTH, 350, ADV7511_MAX_HEIGHT,
138 ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK,
139 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
140 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
141 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
142 V4L2_DV_BT_CAP_CUSTOM)
143 };
144
get_adv7511_state(struct v4l2_subdev * sd)145 static inline struct adv7511_state *get_adv7511_state(struct v4l2_subdev *sd)
146 {
147 return container_of(sd, struct adv7511_state, sd);
148 }
149
to_sd(struct v4l2_ctrl * ctrl)150 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
151 {
152 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd;
153 }
154
155 /* ------------------------ I2C ----------------------------------------------- */
156
adv_smbus_read_byte_data_check(struct i2c_client * client,u8 command,bool check)157 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
158 u8 command, bool check)
159 {
160 union i2c_smbus_data data;
161
162 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
163 I2C_SMBUS_READ, command,
164 I2C_SMBUS_BYTE_DATA, &data))
165 return data.byte;
166 if (check)
167 v4l_err(client, "error reading %02x, %02x\n",
168 client->addr, command);
169 return -1;
170 }
171
adv_smbus_read_byte_data(struct i2c_client * client,u8 command)172 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
173 {
174 int i;
175 for (i = 0; i < 3; i++) {
176 int ret = adv_smbus_read_byte_data_check(client, command, true);
177 if (ret >= 0) {
178 if (i)
179 v4l_err(client, "read ok after %d retries\n", i);
180 return ret;
181 }
182 }
183 v4l_err(client, "read failed\n");
184 return -1;
185 }
186
adv7511_rd(struct v4l2_subdev * sd,u8 reg)187 static int adv7511_rd(struct v4l2_subdev *sd, u8 reg)
188 {
189 struct i2c_client *client = v4l2_get_subdevdata(sd);
190
191 return adv_smbus_read_byte_data(client, reg);
192 }
193
adv7511_wr(struct v4l2_subdev * sd,u8 reg,u8 val)194 static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
195 {
196 struct i2c_client *client = v4l2_get_subdevdata(sd);
197 int ret;
198 int i;
199
200 for (i = 0; i < 3; i++) {
201 ret = i2c_smbus_write_byte_data(client, reg, val);
202 if (ret == 0)
203 return 0;
204 }
205 v4l2_err(sd, "%s: i2c write error\n", __func__);
206 return ret;
207 }
208
209 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
210 and then the value-mask (to be OR-ed). */
adv7511_wr_and_or(struct v4l2_subdev * sd,u8 reg,u8 clr_mask,u8 val_mask)211 static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask)
212 {
213 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask);
214 }
215
adv7511_edid_rd(struct v4l2_subdev * sd,uint16_t len,uint8_t * buf)216 static int adv7511_edid_rd(struct v4l2_subdev *sd, uint16_t len, uint8_t *buf)
217 {
218 struct adv7511_state *state = get_adv7511_state(sd);
219 int i;
220
221 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
222
223 for (i = 0; i < len; i += I2C_SMBUS_BLOCK_MAX) {
224 s32 ret;
225
226 ret = i2c_smbus_read_i2c_block_data(state->i2c_edid, i,
227 I2C_SMBUS_BLOCK_MAX, buf + i);
228 if (ret < 0) {
229 v4l2_err(sd, "%s: i2c read error\n", __func__);
230 return ret;
231 }
232 }
233
234 return 0;
235 }
236
adv7511_cec_read(struct v4l2_subdev * sd,u8 reg)237 static inline int adv7511_cec_read(struct v4l2_subdev *sd, u8 reg)
238 {
239 struct adv7511_state *state = get_adv7511_state(sd);
240
241 return i2c_smbus_read_byte_data(state->i2c_cec, reg);
242 }
243
adv7511_cec_write(struct v4l2_subdev * sd,u8 reg,u8 val)244 static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
245 {
246 struct adv7511_state *state = get_adv7511_state(sd);
247 int ret;
248 int i;
249
250 for (i = 0; i < 3; i++) {
251 ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val);
252 if (ret == 0)
253 return 0;
254 }
255 v4l2_err(sd, "%s: I2C Write Problem\n", __func__);
256 return ret;
257 }
258
adv7511_cec_write_and_or(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)259 static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask,
260 u8 val)
261 {
262 return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val);
263 }
264
adv7511_pktmem_rd(struct v4l2_subdev * sd,u8 reg)265 static int adv7511_pktmem_rd(struct v4l2_subdev *sd, u8 reg)
266 {
267 struct adv7511_state *state = get_adv7511_state(sd);
268
269 return adv_smbus_read_byte_data(state->i2c_pktmem, reg);
270 }
271
adv7511_have_hotplug(struct v4l2_subdev * sd)272 static inline bool adv7511_have_hotplug(struct v4l2_subdev *sd)
273 {
274 return adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT;
275 }
276
adv7511_have_rx_sense(struct v4l2_subdev * sd)277 static inline bool adv7511_have_rx_sense(struct v4l2_subdev *sd)
278 {
279 return adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT;
280 }
281
adv7511_csc_conversion_mode(struct v4l2_subdev * sd,u8 mode)282 static void adv7511_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
283 {
284 adv7511_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
285 }
286
adv7511_csc_coeff(struct v4l2_subdev * sd,u16 A1,u16 A2,u16 A3,u16 A4,u16 B1,u16 B2,u16 B3,u16 B4,u16 C1,u16 C2,u16 C3,u16 C4)287 static void adv7511_csc_coeff(struct v4l2_subdev *sd,
288 u16 A1, u16 A2, u16 A3, u16 A4,
289 u16 B1, u16 B2, u16 B3, u16 B4,
290 u16 C1, u16 C2, u16 C3, u16 C4)
291 {
292 /* A */
293 adv7511_wr_and_or(sd, 0x18, 0xe0, A1>>8);
294 adv7511_wr(sd, 0x19, A1);
295 adv7511_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
296 adv7511_wr(sd, 0x1B, A2);
297 adv7511_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
298 adv7511_wr(sd, 0x1d, A3);
299 adv7511_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
300 adv7511_wr(sd, 0x1f, A4);
301
302 /* B */
303 adv7511_wr_and_or(sd, 0x20, 0xe0, B1>>8);
304 adv7511_wr(sd, 0x21, B1);
305 adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8);
306 adv7511_wr(sd, 0x23, B2);
307 adv7511_wr_and_or(sd, 0x24, 0xe0, B3>>8);
308 adv7511_wr(sd, 0x25, B3);
309 adv7511_wr_and_or(sd, 0x26, 0xe0, B4>>8);
310 adv7511_wr(sd, 0x27, B4);
311
312 /* C */
313 adv7511_wr_and_or(sd, 0x28, 0xe0, C1>>8);
314 adv7511_wr(sd, 0x29, C1);
315 adv7511_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
316 adv7511_wr(sd, 0x2B, C2);
317 adv7511_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
318 adv7511_wr(sd, 0x2D, C3);
319 adv7511_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
320 adv7511_wr(sd, 0x2F, C4);
321 }
322
adv7511_csc_rgb_full2limit(struct v4l2_subdev * sd,bool enable)323 static void adv7511_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
324 {
325 if (enable) {
326 u8 csc_mode = 0;
327 adv7511_csc_conversion_mode(sd, csc_mode);
328 adv7511_csc_coeff(sd,
329 4096-564, 0, 0, 256,
330 0, 4096-564, 0, 256,
331 0, 0, 4096-564, 256);
332 /* enable CSC */
333 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x80);
334 /* AVI infoframe: Limited range RGB (16-235) */
335 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x04);
336 } else {
337 /* disable CSC */
338 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
339 /* AVI infoframe: Full range RGB (0-255) */
340 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x08);
341 }
342 }
343
adv7511_set_rgb_quantization_mode(struct v4l2_subdev * sd,struct v4l2_ctrl * ctrl)344 static void adv7511_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
345 {
346 struct adv7511_state *state = get_adv7511_state(sd);
347
348 /* Only makes sense for RGB formats */
349 if (state->fmt_code != MEDIA_BUS_FMT_RGB888_1X24) {
350 /* so just keep quantization */
351 adv7511_csc_rgb_full2limit(sd, false);
352 return;
353 }
354
355 switch (ctrl->val) {
356 case V4L2_DV_RGB_RANGE_AUTO:
357 /* automatic */
358 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
359 /* CE format, RGB limited range (16-235) */
360 adv7511_csc_rgb_full2limit(sd, true);
361 } else {
362 /* not CE format, RGB full range (0-255) */
363 adv7511_csc_rgb_full2limit(sd, false);
364 }
365 break;
366 case V4L2_DV_RGB_RANGE_LIMITED:
367 /* RGB limited range (16-235) */
368 adv7511_csc_rgb_full2limit(sd, true);
369 break;
370 case V4L2_DV_RGB_RANGE_FULL:
371 /* RGB full range (0-255) */
372 adv7511_csc_rgb_full2limit(sd, false);
373 break;
374 }
375 }
376
377 /* ------------------------------ CTRL OPS ------------------------------ */
378
adv7511_s_ctrl(struct v4l2_ctrl * ctrl)379 static int adv7511_s_ctrl(struct v4l2_ctrl *ctrl)
380 {
381 struct v4l2_subdev *sd = to_sd(ctrl);
382 struct adv7511_state *state = get_adv7511_state(sd);
383
384 v4l2_dbg(1, debug, sd, "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
385
386 if (state->hdmi_mode_ctrl == ctrl) {
387 /* Set HDMI or DVI-D */
388 adv7511_wr_and_or(sd, 0xaf, 0xfd, ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
389 return 0;
390 }
391 if (state->rgb_quantization_range_ctrl == ctrl) {
392 adv7511_set_rgb_quantization_mode(sd, ctrl);
393 return 0;
394 }
395 if (state->content_type_ctrl == ctrl) {
396 u8 itc, cn;
397
398 state->content_type = ctrl->val;
399 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
400 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
401 adv7511_wr_and_or(sd, 0x57, 0x7f, itc << 7);
402 adv7511_wr_and_or(sd, 0x59, 0xcf, cn << 4);
403 return 0;
404 }
405
406 return -EINVAL;
407 }
408
409 static const struct v4l2_ctrl_ops adv7511_ctrl_ops = {
410 .s_ctrl = adv7511_s_ctrl,
411 };
412
413 /* ---------------------------- CORE OPS ------------------------------------------- */
414
415 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv7511_inv_register(struct v4l2_subdev * sd)416 static void adv7511_inv_register(struct v4l2_subdev *sd)
417 {
418 struct adv7511_state *state = get_adv7511_state(sd);
419
420 v4l2_info(sd, "0x000-0x0ff: Main Map\n");
421 if (state->i2c_cec)
422 v4l2_info(sd, "0x100-0x1ff: CEC Map\n");
423 }
424
adv7511_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)425 static int adv7511_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
426 {
427 struct adv7511_state *state = get_adv7511_state(sd);
428
429 reg->size = 1;
430 switch (reg->reg >> 8) {
431 case 0:
432 reg->val = adv7511_rd(sd, reg->reg & 0xff);
433 break;
434 case 1:
435 if (state->i2c_cec) {
436 reg->val = adv7511_cec_read(sd, reg->reg & 0xff);
437 break;
438 }
439 fallthrough;
440 default:
441 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
442 adv7511_inv_register(sd);
443 break;
444 }
445 return 0;
446 }
447
adv7511_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)448 static int adv7511_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
449 {
450 struct adv7511_state *state = get_adv7511_state(sd);
451
452 switch (reg->reg >> 8) {
453 case 0:
454 adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff);
455 break;
456 case 1:
457 if (state->i2c_cec) {
458 adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
459 break;
460 }
461 fallthrough;
462 default:
463 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
464 adv7511_inv_register(sd);
465 break;
466 }
467 return 0;
468 }
469 #endif
470
471 struct adv7511_cfg_read_infoframe {
472 const char *desc;
473 u8 present_reg;
474 u8 present_mask;
475 u8 header[3];
476 u16 payload_addr;
477 };
478
hdmi_infoframe_checksum(u8 * ptr,size_t size)479 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size)
480 {
481 u8 csum = 0;
482 size_t i;
483
484 /* compute checksum */
485 for (i = 0; i < size; i++)
486 csum += ptr[i];
487
488 return 256 - csum;
489 }
490
log_infoframe(struct v4l2_subdev * sd,const struct adv7511_cfg_read_infoframe * cri)491 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7511_cfg_read_infoframe *cri)
492 {
493 struct i2c_client *client = v4l2_get_subdevdata(sd);
494 struct device *dev = &client->dev;
495 union hdmi_infoframe frame;
496 u8 buffer[32];
497 u8 len;
498 int i;
499
500 if (!(adv7511_rd(sd, cri->present_reg) & cri->present_mask)) {
501 v4l2_info(sd, "%s infoframe not transmitted\n", cri->desc);
502 return;
503 }
504
505 memcpy(buffer, cri->header, sizeof(cri->header));
506
507 len = buffer[2];
508
509 if (len + 4 > sizeof(buffer)) {
510 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
511 return;
512 }
513
514 if (cri->payload_addr >= 0x100) {
515 for (i = 0; i < len; i++)
516 buffer[i + 4] = adv7511_pktmem_rd(sd, cri->payload_addr + i - 0x100);
517 } else {
518 for (i = 0; i < len; i++)
519 buffer[i + 4] = adv7511_rd(sd, cri->payload_addr + i);
520 }
521 buffer[3] = 0;
522 buffer[3] = hdmi_infoframe_checksum(buffer, len + 4);
523
524 if (hdmi_infoframe_unpack(&frame, buffer, len + 4) < 0) {
525 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
526 return;
527 }
528
529 hdmi_infoframe_log(KERN_INFO, dev, &frame);
530 }
531
adv7511_log_infoframes(struct v4l2_subdev * sd)532 static void adv7511_log_infoframes(struct v4l2_subdev *sd)
533 {
534 static const struct adv7511_cfg_read_infoframe cri[] = {
535 { "AVI", 0x44, 0x10, { 0x82, 2, 13 }, 0x55 },
536 { "Audio", 0x44, 0x08, { 0x84, 1, 10 }, 0x73 },
537 { "SDP", 0x40, 0x40, { 0x83, 1, 25 }, 0x103 },
538 };
539 int i;
540
541 for (i = 0; i < ARRAY_SIZE(cri); i++)
542 log_infoframe(sd, &cri[i]);
543 }
544
adv7511_log_status(struct v4l2_subdev * sd)545 static int adv7511_log_status(struct v4l2_subdev *sd)
546 {
547 struct adv7511_state *state = get_adv7511_state(sd);
548 struct adv7511_state_edid *edid = &state->edid;
549 int i;
550
551 static const char * const states[] = {
552 "in reset",
553 "reading EDID",
554 "idle",
555 "initializing HDCP",
556 "HDCP enabled",
557 "initializing HDCP repeater",
558 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
559 };
560 static const char * const errors[] = {
561 "no error",
562 "bad receiver BKSV",
563 "Ri mismatch",
564 "Pj mismatch",
565 "i2c error",
566 "timed out",
567 "max repeater cascade exceeded",
568 "hash check failed",
569 "too many devices",
570 "9", "A", "B", "C", "D", "E", "F"
571 };
572
573 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
574 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
575 (adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT) ? "detected" : "no",
576 (adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT) ? "detected" : "no",
577 edid->segments ? "found" : "no",
578 edid->blocks);
579 v4l2_info(sd, "%s output %s\n",
580 (adv7511_rd(sd, 0xaf) & 0x02) ?
581 "HDMI" : "DVI-D",
582 (adv7511_rd(sd, 0xa1) & 0x3c) ?
583 "disabled" : "enabled");
584 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
585 states[adv7511_rd(sd, 0xc8) & 0xf],
586 errors[adv7511_rd(sd, 0xc8) >> 4], state->edid_detect_counter,
587 adv7511_rd(sd, 0x94), adv7511_rd(sd, 0x96));
588 v4l2_info(sd, "RGB quantization: %s range\n", adv7511_rd(sd, 0x18) & 0x80 ? "limited" : "full");
589 if (adv7511_rd(sd, 0xaf) & 0x02) {
590 /* HDMI only */
591 u8 manual_cts = adv7511_rd(sd, 0x0a) & 0x80;
592 u32 N = (adv7511_rd(sd, 0x01) & 0xf) << 16 |
593 adv7511_rd(sd, 0x02) << 8 |
594 adv7511_rd(sd, 0x03);
595 u8 vic_detect = adv7511_rd(sd, 0x3e) >> 2;
596 u8 vic_sent = adv7511_rd(sd, 0x3d) & 0x3f;
597 u32 CTS;
598
599 if (manual_cts)
600 CTS = (adv7511_rd(sd, 0x07) & 0xf) << 16 |
601 adv7511_rd(sd, 0x08) << 8 |
602 adv7511_rd(sd, 0x09);
603 else
604 CTS = (adv7511_rd(sd, 0x04) & 0xf) << 16 |
605 adv7511_rd(sd, 0x05) << 8 |
606 adv7511_rd(sd, 0x06);
607 v4l2_info(sd, "CTS %s mode: N %d, CTS %d\n",
608 manual_cts ? "manual" : "automatic", N, CTS);
609 v4l2_info(sd, "VIC: detected %d, sent %d\n",
610 vic_detect, vic_sent);
611 adv7511_log_infoframes(sd);
612 }
613 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
614 v4l2_print_dv_timings(sd->name, "timings: ",
615 &state->dv_timings, false);
616 else
617 v4l2_info(sd, "no timings set\n");
618 v4l2_info(sd, "i2c edid addr: 0x%x\n", state->i2c_edid_addr);
619
620 if (state->i2c_cec == NULL)
621 return 0;
622
623 v4l2_info(sd, "i2c cec addr: 0x%x\n", state->i2c_cec_addr);
624
625 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
626 "enabled" : "disabled");
627 if (state->cec_enabled_adap) {
628 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
629 bool is_valid = state->cec_valid_addrs & (1 << i);
630
631 if (is_valid)
632 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
633 state->cec_addr[i]);
634 }
635 }
636 v4l2_info(sd, "i2c pktmem addr: 0x%x\n", state->i2c_pktmem_addr);
637 return 0;
638 }
639
640 /* Power up/down adv7511 */
adv7511_s_power(struct v4l2_subdev * sd,int on)641 static int adv7511_s_power(struct v4l2_subdev *sd, int on)
642 {
643 struct adv7511_state *state = get_adv7511_state(sd);
644 const int retries = 20;
645 int i;
646
647 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
648
649 state->power_on = on;
650
651 if (!on) {
652 /* Power down */
653 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
654 return true;
655 }
656
657 /* Power up */
658 /* The adv7511 does not always come up immediately.
659 Retry multiple times. */
660 for (i = 0; i < retries; i++) {
661 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x0);
662 if ((adv7511_rd(sd, 0x41) & 0x40) == 0)
663 break;
664 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
665 msleep(10);
666 }
667 if (i == retries) {
668 v4l2_dbg(1, debug, sd, "%s: failed to powerup the adv7511!\n", __func__);
669 adv7511_s_power(sd, 0);
670 return false;
671 }
672 if (i > 1)
673 v4l2_dbg(1, debug, sd, "%s: needed %d retries to powerup the adv7511\n", __func__, i);
674
675 /* Reserved registers that must be set */
676 adv7511_wr(sd, 0x98, 0x03);
677 adv7511_wr_and_or(sd, 0x9a, 0xfe, 0x70);
678 adv7511_wr(sd, 0x9c, 0x30);
679 adv7511_wr_and_or(sd, 0x9d, 0xfc, 0x01);
680 adv7511_wr(sd, 0xa2, 0xa4);
681 adv7511_wr(sd, 0xa3, 0xa4);
682 adv7511_wr(sd, 0xe0, 0xd0);
683 adv7511_wr(sd, 0xf9, 0x00);
684
685 adv7511_wr(sd, 0x43, state->i2c_edid_addr);
686 adv7511_wr(sd, 0x45, state->i2c_pktmem_addr);
687
688 /* Set number of attempts to read the EDID */
689 adv7511_wr(sd, 0xc9, 0xf);
690 return true;
691 }
692
693 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
adv7511_cec_adap_enable(struct cec_adapter * adap,bool enable)694 static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
695 {
696 struct adv7511_state *state = cec_get_drvdata(adap);
697 struct v4l2_subdev *sd = &state->sd;
698
699 if (state->i2c_cec == NULL)
700 return -EIO;
701
702 if (!state->cec_enabled_adap && enable) {
703 /* power up cec section */
704 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x01);
705 /* legacy mode and clear all rx buffers */
706 adv7511_cec_write(sd, 0x4a, 0x00);
707 adv7511_cec_write(sd, 0x4a, 0x07);
708 adv7511_cec_write_and_or(sd, 0x11, 0xfe, 0); /* initially disable tx */
709 /* enabled irqs: */
710 /* tx: ready */
711 /* tx: arbitration lost */
712 /* tx: retry timeout */
713 /* rx: ready 1 */
714 if (state->enabled_irq)
715 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x39);
716 } else if (state->cec_enabled_adap && !enable) {
717 if (state->enabled_irq)
718 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x00);
719 /* disable address mask 1-3 */
720 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0x00);
721 /* power down cec section */
722 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x00);
723 state->cec_valid_addrs = 0;
724 }
725 state->cec_enabled_adap = enable;
726 return 0;
727 }
728
adv7511_cec_adap_log_addr(struct cec_adapter * adap,u8 addr)729 static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
730 {
731 struct adv7511_state *state = cec_get_drvdata(adap);
732 struct v4l2_subdev *sd = &state->sd;
733 unsigned int i, free_idx = ADV7511_MAX_ADDRS;
734
735 if (!state->cec_enabled_adap)
736 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
737
738 if (addr == CEC_LOG_ADDR_INVALID) {
739 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0);
740 state->cec_valid_addrs = 0;
741 return 0;
742 }
743
744 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
745 bool is_valid = state->cec_valid_addrs & (1 << i);
746
747 if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
748 free_idx = i;
749 if (is_valid && state->cec_addr[i] == addr)
750 return 0;
751 }
752 if (i == ADV7511_MAX_ADDRS) {
753 i = free_idx;
754 if (i == ADV7511_MAX_ADDRS)
755 return -ENXIO;
756 }
757 state->cec_addr[i] = addr;
758 state->cec_valid_addrs |= 1 << i;
759
760 switch (i) {
761 case 0:
762 /* enable address mask 0 */
763 adv7511_cec_write_and_or(sd, 0x4b, 0xef, 0x10);
764 /* set address for mask 0 */
765 adv7511_cec_write_and_or(sd, 0x4c, 0xf0, addr);
766 break;
767 case 1:
768 /* enable address mask 1 */
769 adv7511_cec_write_and_or(sd, 0x4b, 0xdf, 0x20);
770 /* set address for mask 1 */
771 adv7511_cec_write_and_or(sd, 0x4c, 0x0f, addr << 4);
772 break;
773 case 2:
774 /* enable address mask 2 */
775 adv7511_cec_write_and_or(sd, 0x4b, 0xbf, 0x40);
776 /* set address for mask 1 */
777 adv7511_cec_write_and_or(sd, 0x4d, 0xf0, addr);
778 break;
779 }
780 return 0;
781 }
782
adv7511_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)783 static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
784 u32 signal_free_time, struct cec_msg *msg)
785 {
786 struct adv7511_state *state = cec_get_drvdata(adap);
787 struct v4l2_subdev *sd = &state->sd;
788 u8 len = msg->len;
789 unsigned int i;
790
791 v4l2_dbg(1, debug, sd, "%s: len %d\n", __func__, len);
792
793 if (len > 16) {
794 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
795 return -EINVAL;
796 }
797
798 /*
799 * The number of retries is the number of attempts - 1, but retry
800 * at least once. It's not clear if a value of 0 is allowed, so
801 * let's do at least one retry.
802 */
803 adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4);
804
805 /* clear cec tx irq status */
806 adv7511_wr(sd, 0x97, 0x38);
807
808 /* write data */
809 for (i = 0; i < len; i++)
810 adv7511_cec_write(sd, i, msg->msg[i]);
811
812 /* set length (data + header) */
813 adv7511_cec_write(sd, 0x10, len);
814 /* start transmit, enable tx */
815 adv7511_cec_write(sd, 0x11, 0x01);
816 return 0;
817 }
818
adv_cec_tx_raw_status(struct v4l2_subdev * sd,u8 tx_raw_status)819 static void adv_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
820 {
821 struct adv7511_state *state = get_adv7511_state(sd);
822
823 if ((adv7511_cec_read(sd, 0x11) & 0x01) == 0) {
824 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
825 return;
826 }
827
828 if (tx_raw_status & 0x10) {
829 v4l2_dbg(1, debug, sd,
830 "%s: tx raw: arbitration lost\n", __func__);
831 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
832 1, 0, 0, 0);
833 return;
834 }
835 if (tx_raw_status & 0x08) {
836 u8 status;
837 u8 nack_cnt;
838 u8 low_drive_cnt;
839
840 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
841 /*
842 * We set this status bit since this hardware performs
843 * retransmissions.
844 */
845 status = CEC_TX_STATUS_MAX_RETRIES;
846 nack_cnt = adv7511_cec_read(sd, 0x14) & 0xf;
847 if (nack_cnt)
848 status |= CEC_TX_STATUS_NACK;
849 low_drive_cnt = adv7511_cec_read(sd, 0x14) >> 4;
850 if (low_drive_cnt)
851 status |= CEC_TX_STATUS_LOW_DRIVE;
852 cec_transmit_done(state->cec_adap, status,
853 0, nack_cnt, low_drive_cnt, 0);
854 return;
855 }
856 if (tx_raw_status & 0x20) {
857 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
858 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
859 return;
860 }
861 }
862
863 static const struct cec_adap_ops adv7511_cec_adap_ops = {
864 .adap_enable = adv7511_cec_adap_enable,
865 .adap_log_addr = adv7511_cec_adap_log_addr,
866 .adap_transmit = adv7511_cec_adap_transmit,
867 };
868 #endif
869
870 /* Enable interrupts */
adv7511_set_isr(struct v4l2_subdev * sd,bool enable)871 static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable)
872 {
873 struct adv7511_state *state = get_adv7511_state(sd);
874 u8 irqs = MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT;
875 u8 irqs_rd;
876 int retries = 100;
877
878 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? "enable" : "disable");
879
880 if (state->enabled_irq == enable)
881 return;
882 state->enabled_irq = enable;
883
884 /* The datasheet says that the EDID ready interrupt should be
885 disabled if there is no hotplug. */
886 if (!enable)
887 irqs = 0;
888 else if (adv7511_have_hotplug(sd))
889 irqs |= MASK_ADV7511_EDID_RDY_INT;
890
891 /*
892 * This i2c write can fail (approx. 1 in 1000 writes). But it
893 * is essential that this register is correct, so retry it
894 * multiple times.
895 *
896 * Note that the i2c write does not report an error, but the readback
897 * clearly shows the wrong value.
898 */
899 do {
900 adv7511_wr(sd, 0x94, irqs);
901 irqs_rd = adv7511_rd(sd, 0x94);
902 } while (retries-- && irqs_rd != irqs);
903
904 if (irqs_rd != irqs)
905 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
906
907 adv7511_wr_and_or(sd, 0x95, 0xc0,
908 (state->cec_enabled_adap && enable) ? 0x39 : 0x00);
909 }
910
911 /* Interrupt handler */
adv7511_isr(struct v4l2_subdev * sd,u32 status,bool * handled)912 static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
913 {
914 u8 irq_status;
915 u8 cec_irq;
916
917 /* disable interrupts to prevent a race condition */
918 adv7511_set_isr(sd, false);
919 irq_status = adv7511_rd(sd, 0x96);
920 cec_irq = adv7511_rd(sd, 0x97);
921 /* clear detected interrupts */
922 adv7511_wr(sd, 0x96, irq_status);
923 adv7511_wr(sd, 0x97, cec_irq);
924
925 v4l2_dbg(1, debug, sd, "%s: irq 0x%x, cec-irq 0x%x\n", __func__,
926 irq_status, cec_irq);
927
928 if (irq_status & (MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT))
929 adv7511_check_monitor_present_status(sd);
930 if (irq_status & MASK_ADV7511_EDID_RDY_INT)
931 adv7511_check_edid_status(sd);
932
933 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
934 if (cec_irq & 0x38)
935 adv_cec_tx_raw_status(sd, cec_irq);
936
937 if (cec_irq & 1) {
938 struct adv7511_state *state = get_adv7511_state(sd);
939 struct cec_msg msg;
940
941 msg.len = adv7511_cec_read(sd, 0x25) & 0x1f;
942
943 v4l2_dbg(1, debug, sd, "%s: cec msg len %d\n", __func__,
944 msg.len);
945
946 if (msg.len > CEC_MAX_MSG_SIZE)
947 msg.len = CEC_MAX_MSG_SIZE;
948
949 if (msg.len) {
950 u8 i;
951
952 for (i = 0; i < msg.len; i++)
953 msg.msg[i] = adv7511_cec_read(sd, i + 0x15);
954
955 adv7511_cec_write(sd, 0x4a, 0); /* toggle to re-enable rx 1 */
956 adv7511_cec_write(sd, 0x4a, 1);
957 cec_received_msg(state->cec_adap, &msg);
958 }
959 }
960 #endif
961
962 /* enable interrupts */
963 adv7511_set_isr(sd, true);
964
965 if (handled)
966 *handled = true;
967 return 0;
968 }
969
970 static const struct v4l2_subdev_core_ops adv7511_core_ops = {
971 .log_status = adv7511_log_status,
972 #ifdef CONFIG_VIDEO_ADV_DEBUG
973 .g_register = adv7511_g_register,
974 .s_register = adv7511_s_register,
975 #endif
976 .s_power = adv7511_s_power,
977 .interrupt_service_routine = adv7511_isr,
978 };
979
980 /* ------------------------------ VIDEO OPS ------------------------------ */
981
982 /* Enable/disable adv7511 output */
adv7511_s_stream(struct v4l2_subdev * sd,int enable)983 static int adv7511_s_stream(struct v4l2_subdev *sd, int enable)
984 {
985 struct adv7511_state *state = get_adv7511_state(sd);
986
987 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
988 adv7511_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
989 if (enable) {
990 adv7511_check_monitor_present_status(sd);
991 } else {
992 adv7511_s_power(sd, 0);
993 state->have_monitor = false;
994 }
995 return 0;
996 }
997
adv7511_s_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)998 static int adv7511_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
999 struct v4l2_dv_timings *timings)
1000 {
1001 struct adv7511_state *state = get_adv7511_state(sd);
1002 struct v4l2_bt_timings *bt = &timings->bt;
1003 u32 fps;
1004
1005 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1006
1007 if (pad != 0)
1008 return -EINVAL;
1009
1010 /* quick sanity check */
1011 if (!v4l2_valid_dv_timings(timings, &adv7511_timings_cap, NULL, NULL))
1012 return -EINVAL;
1013
1014 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1015 if the format is one of the CEA or DMT timings. */
1016 v4l2_find_dv_timings_cap(timings, &adv7511_timings_cap, 0, NULL, NULL);
1017
1018 /* save timings */
1019 state->dv_timings = *timings;
1020
1021 /* set h/vsync polarities */
1022 adv7511_wr_and_or(sd, 0x17, 0x9f,
1023 ((bt->polarities & V4L2_DV_VSYNC_POS_POL) ? 0 : 0x40) |
1024 ((bt->polarities & V4L2_DV_HSYNC_POS_POL) ? 0 : 0x20));
1025
1026 fps = (u32)bt->pixelclock / (V4L2_DV_BT_FRAME_WIDTH(bt) * V4L2_DV_BT_FRAME_HEIGHT(bt));
1027 switch (fps) {
1028 case 24:
1029 adv7511_wr_and_or(sd, 0xfb, 0xf9, 1 << 1);
1030 break;
1031 case 25:
1032 adv7511_wr_and_or(sd, 0xfb, 0xf9, 2 << 1);
1033 break;
1034 case 30:
1035 adv7511_wr_and_or(sd, 0xfb, 0xf9, 3 << 1);
1036 break;
1037 default:
1038 adv7511_wr_and_or(sd, 0xfb, 0xf9, 0);
1039 break;
1040 }
1041
1042 /* update quantization range based on new dv_timings */
1043 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1044
1045 return 0;
1046 }
1047
adv7511_g_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)1048 static int adv7511_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1049 struct v4l2_dv_timings *timings)
1050 {
1051 struct adv7511_state *state = get_adv7511_state(sd);
1052
1053 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1054
1055 if (pad != 0)
1056 return -EINVAL;
1057
1058 if (!timings)
1059 return -EINVAL;
1060
1061 *timings = state->dv_timings;
1062
1063 return 0;
1064 }
1065
adv7511_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1066 static int adv7511_enum_dv_timings(struct v4l2_subdev *sd,
1067 struct v4l2_enum_dv_timings *timings)
1068 {
1069 if (timings->pad != 0)
1070 return -EINVAL;
1071
1072 return v4l2_enum_dv_timings_cap(timings, &adv7511_timings_cap, NULL, NULL);
1073 }
1074
adv7511_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1075 static int adv7511_dv_timings_cap(struct v4l2_subdev *sd,
1076 struct v4l2_dv_timings_cap *cap)
1077 {
1078 if (cap->pad != 0)
1079 return -EINVAL;
1080
1081 *cap = adv7511_timings_cap;
1082 return 0;
1083 }
1084
1085 static const struct v4l2_subdev_video_ops adv7511_video_ops = {
1086 .s_stream = adv7511_s_stream,
1087 };
1088
1089 /* ------------------------------ AUDIO OPS ------------------------------ */
adv7511_s_audio_stream(struct v4l2_subdev * sd,int enable)1090 static int adv7511_s_audio_stream(struct v4l2_subdev *sd, int enable)
1091 {
1092 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1093
1094 if (enable)
1095 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x80);
1096 else
1097 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x40);
1098
1099 return 0;
1100 }
1101
adv7511_s_clock_freq(struct v4l2_subdev * sd,u32 freq)1102 static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1103 {
1104 u32 N;
1105
1106 switch (freq) {
1107 case 32000: N = 4096; break;
1108 case 44100: N = 6272; break;
1109 case 48000: N = 6144; break;
1110 case 88200: N = 12544; break;
1111 case 96000: N = 12288; break;
1112 case 176400: N = 25088; break;
1113 case 192000: N = 24576; break;
1114 default:
1115 return -EINVAL;
1116 }
1117
1118 /* Set N (used with CTS to regenerate the audio clock) */
1119 adv7511_wr(sd, 0x01, (N >> 16) & 0xf);
1120 adv7511_wr(sd, 0x02, (N >> 8) & 0xff);
1121 adv7511_wr(sd, 0x03, N & 0xff);
1122
1123 return 0;
1124 }
1125
adv7511_s_i2s_clock_freq(struct v4l2_subdev * sd,u32 freq)1126 static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1127 {
1128 u32 i2s_sf;
1129
1130 switch (freq) {
1131 case 32000: i2s_sf = 0x30; break;
1132 case 44100: i2s_sf = 0x00; break;
1133 case 48000: i2s_sf = 0x20; break;
1134 case 88200: i2s_sf = 0x80; break;
1135 case 96000: i2s_sf = 0xa0; break;
1136 case 176400: i2s_sf = 0xc0; break;
1137 case 192000: i2s_sf = 0xe0; break;
1138 default:
1139 return -EINVAL;
1140 }
1141
1142 /* Set sampling frequency for I2S audio to 48 kHz */
1143 adv7511_wr_and_or(sd, 0x15, 0xf, i2s_sf);
1144
1145 return 0;
1146 }
1147
adv7511_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)1148 static int adv7511_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
1149 {
1150 /* Only 2 channels in use for application */
1151 adv7511_wr_and_or(sd, 0x73, 0xf8, 0x1);
1152 /* Speaker mapping */
1153 adv7511_wr(sd, 0x76, 0x00);
1154
1155 /* 16 bit audio word length */
1156 adv7511_wr_and_or(sd, 0x14, 0xf0, 0x02);
1157
1158 return 0;
1159 }
1160
1161 static const struct v4l2_subdev_audio_ops adv7511_audio_ops = {
1162 .s_stream = adv7511_s_audio_stream,
1163 .s_clock_freq = adv7511_s_clock_freq,
1164 .s_i2s_clock_freq = adv7511_s_i2s_clock_freq,
1165 .s_routing = adv7511_s_routing,
1166 };
1167
1168 /* ---------------------------- PAD OPS ------------------------------------- */
1169
adv7511_get_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)1170 static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1171 {
1172 struct adv7511_state *state = get_adv7511_state(sd);
1173
1174 memset(edid->reserved, 0, sizeof(edid->reserved));
1175
1176 if (edid->pad != 0)
1177 return -EINVAL;
1178
1179 if (edid->start_block == 0 && edid->blocks == 0) {
1180 edid->blocks = state->edid.blocks;
1181 return 0;
1182 }
1183
1184 if (state->edid.blocks == 0)
1185 return -ENODATA;
1186
1187 if (edid->start_block >= state->edid.blocks)
1188 return -EINVAL;
1189
1190 if (edid->start_block + edid->blocks > state->edid.blocks)
1191 edid->blocks = state->edid.blocks - edid->start_block;
1192
1193 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
1194 128 * edid->blocks);
1195
1196 return 0;
1197 }
1198
adv7511_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1199 static int adv7511_enum_mbus_code(struct v4l2_subdev *sd,
1200 struct v4l2_subdev_state *sd_state,
1201 struct v4l2_subdev_mbus_code_enum *code)
1202 {
1203 if (code->pad != 0)
1204 return -EINVAL;
1205
1206 switch (code->index) {
1207 case 0:
1208 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1209 break;
1210 case 1:
1211 code->code = MEDIA_BUS_FMT_YUYV8_1X16;
1212 break;
1213 case 2:
1214 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1215 break;
1216 default:
1217 return -EINVAL;
1218 }
1219 return 0;
1220 }
1221
adv7511_fill_format(struct adv7511_state * state,struct v4l2_mbus_framefmt * format)1222 static void adv7511_fill_format(struct adv7511_state *state,
1223 struct v4l2_mbus_framefmt *format)
1224 {
1225 format->width = state->dv_timings.bt.width;
1226 format->height = state->dv_timings.bt.height;
1227 format->field = V4L2_FIELD_NONE;
1228 }
1229
adv7511_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1230 static int adv7511_get_fmt(struct v4l2_subdev *sd,
1231 struct v4l2_subdev_state *sd_state,
1232 struct v4l2_subdev_format *format)
1233 {
1234 struct adv7511_state *state = get_adv7511_state(sd);
1235
1236 if (format->pad != 0)
1237 return -EINVAL;
1238
1239 memset(&format->format, 0, sizeof(format->format));
1240 adv7511_fill_format(state, &format->format);
1241
1242 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1243 struct v4l2_mbus_framefmt *fmt;
1244
1245 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1246 format->format.code = fmt->code;
1247 format->format.colorspace = fmt->colorspace;
1248 format->format.ycbcr_enc = fmt->ycbcr_enc;
1249 format->format.quantization = fmt->quantization;
1250 format->format.xfer_func = fmt->xfer_func;
1251 } else {
1252 format->format.code = state->fmt_code;
1253 format->format.colorspace = state->colorspace;
1254 format->format.ycbcr_enc = state->ycbcr_enc;
1255 format->format.quantization = state->quantization;
1256 format->format.xfer_func = state->xfer_func;
1257 }
1258
1259 return 0;
1260 }
1261
adv7511_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1262 static int adv7511_set_fmt(struct v4l2_subdev *sd,
1263 struct v4l2_subdev_state *sd_state,
1264 struct v4l2_subdev_format *format)
1265 {
1266 struct adv7511_state *state = get_adv7511_state(sd);
1267 /*
1268 * Bitfield namings come the CEA-861-F standard, table 8 "Auxiliary
1269 * Video Information (AVI) InfoFrame Format"
1270 *
1271 * c = Colorimetry
1272 * ec = Extended Colorimetry
1273 * y = RGB or YCbCr
1274 * q = RGB Quantization Range
1275 * yq = YCC Quantization Range
1276 */
1277 u8 c = HDMI_COLORIMETRY_NONE;
1278 u8 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1279 u8 y = HDMI_COLORSPACE_RGB;
1280 u8 q = HDMI_QUANTIZATION_RANGE_DEFAULT;
1281 u8 yq = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1282 u8 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1283 u8 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
1284
1285 if (format->pad != 0)
1286 return -EINVAL;
1287 switch (format->format.code) {
1288 case MEDIA_BUS_FMT_UYVY8_1X16:
1289 case MEDIA_BUS_FMT_YUYV8_1X16:
1290 case MEDIA_BUS_FMT_RGB888_1X24:
1291 break;
1292 default:
1293 return -EINVAL;
1294 }
1295
1296 adv7511_fill_format(state, &format->format);
1297 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1298 struct v4l2_mbus_framefmt *fmt;
1299
1300 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1301 fmt->code = format->format.code;
1302 fmt->colorspace = format->format.colorspace;
1303 fmt->ycbcr_enc = format->format.ycbcr_enc;
1304 fmt->quantization = format->format.quantization;
1305 fmt->xfer_func = format->format.xfer_func;
1306 return 0;
1307 }
1308
1309 switch (format->format.code) {
1310 case MEDIA_BUS_FMT_UYVY8_1X16:
1311 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1312 adv7511_wr_and_or(sd, 0x16, 0x03, 0xb8);
1313 y = HDMI_COLORSPACE_YUV422;
1314 break;
1315 case MEDIA_BUS_FMT_YUYV8_1X16:
1316 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1317 adv7511_wr_and_or(sd, 0x16, 0x03, 0xbc);
1318 y = HDMI_COLORSPACE_YUV422;
1319 break;
1320 case MEDIA_BUS_FMT_RGB888_1X24:
1321 default:
1322 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x00);
1323 adv7511_wr_and_or(sd, 0x16, 0x03, 0x00);
1324 break;
1325 }
1326 state->fmt_code = format->format.code;
1327 state->colorspace = format->format.colorspace;
1328 state->ycbcr_enc = format->format.ycbcr_enc;
1329 state->quantization = format->format.quantization;
1330 state->xfer_func = format->format.xfer_func;
1331
1332 switch (format->format.colorspace) {
1333 case V4L2_COLORSPACE_OPRGB:
1334 c = HDMI_COLORIMETRY_EXTENDED;
1335 ec = y ? HDMI_EXTENDED_COLORIMETRY_OPYCC_601 :
1336 HDMI_EXTENDED_COLORIMETRY_OPRGB;
1337 break;
1338 case V4L2_COLORSPACE_SMPTE170M:
1339 c = y ? HDMI_COLORIMETRY_ITU_601 : HDMI_COLORIMETRY_NONE;
1340 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV601) {
1341 c = HDMI_COLORIMETRY_EXTENDED;
1342 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1343 }
1344 break;
1345 case V4L2_COLORSPACE_REC709:
1346 c = y ? HDMI_COLORIMETRY_ITU_709 : HDMI_COLORIMETRY_NONE;
1347 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV709) {
1348 c = HDMI_COLORIMETRY_EXTENDED;
1349 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1350 }
1351 break;
1352 case V4L2_COLORSPACE_SRGB:
1353 c = y ? HDMI_COLORIMETRY_EXTENDED : HDMI_COLORIMETRY_NONE;
1354 ec = y ? HDMI_EXTENDED_COLORIMETRY_S_YCC_601 :
1355 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1356 break;
1357 case V4L2_COLORSPACE_BT2020:
1358 c = HDMI_COLORIMETRY_EXTENDED;
1359 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_BT2020_CONST_LUM)
1360 ec = 5; /* Not yet available in hdmi.h */
1361 else
1362 ec = 6; /* Not yet available in hdmi.h */
1363 break;
1364 default:
1365 break;
1366 }
1367
1368 /*
1369 * CEA-861-F says that for RGB formats the YCC range must match the
1370 * RGB range, although sources should ignore the YCC range.
1371 *
1372 * The RGB quantization range shouldn't be non-zero if the EDID doesn't
1373 * have the Q bit set in the Video Capabilities Data Block, however this
1374 * isn't checked at the moment. The assumption is that the application
1375 * knows the EDID and can detect this.
1376 *
1377 * The same is true for the YCC quantization range: non-standard YCC
1378 * quantization ranges should only be sent if the EDID has the YQ bit
1379 * set in the Video Capabilities Data Block.
1380 */
1381 switch (format->format.quantization) {
1382 case V4L2_QUANTIZATION_FULL_RANGE:
1383 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1384 HDMI_QUANTIZATION_RANGE_FULL;
1385 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_FULL;
1386 break;
1387 case V4L2_QUANTIZATION_LIM_RANGE:
1388 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1389 HDMI_QUANTIZATION_RANGE_LIMITED;
1390 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1391 break;
1392 }
1393
1394 adv7511_wr_and_or(sd, 0x4a, 0xbf, 0);
1395 adv7511_wr_and_or(sd, 0x55, 0x9f, y << 5);
1396 adv7511_wr_and_or(sd, 0x56, 0x3f, c << 6);
1397 adv7511_wr_and_or(sd, 0x57, 0x83, (ec << 4) | (q << 2) | (itc << 7));
1398 adv7511_wr_and_or(sd, 0x59, 0x0f, (yq << 6) | (cn << 4));
1399 adv7511_wr_and_or(sd, 0x4a, 0xff, 1);
1400 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1401
1402 return 0;
1403 }
1404
1405 static const struct v4l2_subdev_pad_ops adv7511_pad_ops = {
1406 .get_edid = adv7511_get_edid,
1407 .enum_mbus_code = adv7511_enum_mbus_code,
1408 .get_fmt = adv7511_get_fmt,
1409 .set_fmt = adv7511_set_fmt,
1410 .s_dv_timings = adv7511_s_dv_timings,
1411 .g_dv_timings = adv7511_g_dv_timings,
1412 .enum_dv_timings = adv7511_enum_dv_timings,
1413 .dv_timings_cap = adv7511_dv_timings_cap,
1414 };
1415
1416 /* --------------------- SUBDEV OPS --------------------------------------- */
1417
1418 static const struct v4l2_subdev_ops adv7511_ops = {
1419 .core = &adv7511_core_ops,
1420 .pad = &adv7511_pad_ops,
1421 .video = &adv7511_video_ops,
1422 .audio = &adv7511_audio_ops,
1423 };
1424
1425 /* ----------------------------------------------------------------------- */
adv7511_dbg_dump_edid(int lvl,int debug,struct v4l2_subdev * sd,int segment,u8 * buf)1426 static void adv7511_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd, int segment, u8 *buf)
1427 {
1428 if (debug >= lvl) {
1429 int i, j;
1430 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
1431 for (i = 0; i < 256; i += 16) {
1432 u8 b[128];
1433 u8 *bp = b;
1434 if (i == 128)
1435 v4l2_dbg(lvl, debug, sd, "\n");
1436 for (j = i; j < i + 16; j++) {
1437 sprintf(bp, "0x%02x, ", buf[j]);
1438 bp += 6;
1439 }
1440 bp[0] = '\0';
1441 v4l2_dbg(lvl, debug, sd, "%s\n", b);
1442 }
1443 }
1444 }
1445
adv7511_notify_no_edid(struct v4l2_subdev * sd)1446 static void adv7511_notify_no_edid(struct v4l2_subdev *sd)
1447 {
1448 struct adv7511_state *state = get_adv7511_state(sd);
1449 struct adv7511_edid_detect ed;
1450
1451 /* We failed to read the EDID, so send an event for this. */
1452 ed.present = false;
1453 ed.segment = adv7511_rd(sd, 0xc4);
1454 ed.phys_addr = CEC_PHYS_ADDR_INVALID;
1455 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
1456 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1457 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x0);
1458 }
1459
adv7511_edid_handler(struct work_struct * work)1460 static void adv7511_edid_handler(struct work_struct *work)
1461 {
1462 struct delayed_work *dwork = to_delayed_work(work);
1463 struct adv7511_state *state = container_of(dwork, struct adv7511_state, edid_handler);
1464 struct v4l2_subdev *sd = &state->sd;
1465
1466 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1467
1468 if (adv7511_check_edid_status(sd)) {
1469 /* Return if we received the EDID. */
1470 return;
1471 }
1472
1473 if (adv7511_have_hotplug(sd)) {
1474 /* We must retry reading the EDID several times, it is possible
1475 * that initially the EDID couldn't be read due to i2c errors
1476 * (DVI connectors are particularly prone to this problem). */
1477 if (state->edid.read_retries) {
1478 state->edid.read_retries--;
1479 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
1480 state->have_monitor = false;
1481 adv7511_s_power(sd, false);
1482 adv7511_s_power(sd, true);
1483 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1484 return;
1485 }
1486 }
1487
1488 /* We failed to read the EDID, so send an event for this. */
1489 adv7511_notify_no_edid(sd);
1490 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
1491 }
1492
adv7511_audio_setup(struct v4l2_subdev * sd)1493 static void adv7511_audio_setup(struct v4l2_subdev *sd)
1494 {
1495 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1496
1497 adv7511_s_i2s_clock_freq(sd, 48000);
1498 adv7511_s_clock_freq(sd, 48000);
1499 adv7511_s_routing(sd, 0, 0, 0);
1500 }
1501
1502 /* Configure hdmi transmitter. */
adv7511_setup(struct v4l2_subdev * sd)1503 static void adv7511_setup(struct v4l2_subdev *sd)
1504 {
1505 struct adv7511_state *state = get_adv7511_state(sd);
1506 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1507
1508 /* Input format: RGB 4:4:4 */
1509 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x0);
1510 /* Output format: RGB 4:4:4 */
1511 adv7511_wr_and_or(sd, 0x16, 0x7f, 0x0);
1512 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion, Aspect ratio: 16:9 */
1513 adv7511_wr_and_or(sd, 0x17, 0xf9, 0x06);
1514 /* Disable pixel repetition */
1515 adv7511_wr_and_or(sd, 0x3b, 0x9f, 0x0);
1516 /* Disable CSC */
1517 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
1518 /* Output format: RGB 4:4:4, Active Format Information is valid,
1519 * underscanned */
1520 adv7511_wr_and_or(sd, 0x55, 0x9c, 0x12);
1521 /* AVI Info frame packet enable, Audio Info frame disable */
1522 adv7511_wr_and_or(sd, 0x44, 0xe7, 0x10);
1523 /* Colorimetry, Active format aspect ratio: same as picure. */
1524 adv7511_wr(sd, 0x56, 0xa8);
1525 /* No encryption */
1526 adv7511_wr_and_or(sd, 0xaf, 0xed, 0x0);
1527
1528 /* Positive clk edge capture for input video clock */
1529 adv7511_wr_and_or(sd, 0xba, 0x1f, 0x60);
1530
1531 adv7511_audio_setup(sd);
1532
1533 v4l2_ctrl_handler_setup(&state->hdl);
1534 }
1535
adv7511_notify_monitor_detect(struct v4l2_subdev * sd)1536 static void adv7511_notify_monitor_detect(struct v4l2_subdev *sd)
1537 {
1538 struct adv7511_monitor_detect mdt;
1539 struct adv7511_state *state = get_adv7511_state(sd);
1540
1541 mdt.present = state->have_monitor;
1542 v4l2_subdev_notify(sd, ADV7511_MONITOR_DETECT, (void *)&mdt);
1543 }
1544
adv7511_check_monitor_present_status(struct v4l2_subdev * sd)1545 static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd)
1546 {
1547 struct adv7511_state *state = get_adv7511_state(sd);
1548 /* read hotplug and rx-sense state */
1549 u8 status = adv7511_rd(sd, 0x42);
1550
1551 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1552 __func__,
1553 status,
1554 status & MASK_ADV7511_HPD_DETECT ? ", hotplug" : "",
1555 status & MASK_ADV7511_MSEN_DETECT ? ", rx-sense" : "");
1556
1557 /* update read only ctrls */
1558 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, adv7511_have_hotplug(sd) ? 0x1 : 0x0);
1559 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, adv7511_have_rx_sense(sd) ? 0x1 : 0x0);
1560
1561 if ((status & MASK_ADV7511_HPD_DETECT) && ((status & MASK_ADV7511_MSEN_DETECT) || state->edid.segments)) {
1562 v4l2_dbg(1, debug, sd, "%s: hotplug and (rx-sense or edid)\n", __func__);
1563 if (!state->have_monitor) {
1564 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1565 state->have_monitor = true;
1566 adv7511_set_isr(sd, true);
1567 if (!adv7511_s_power(sd, true)) {
1568 v4l2_dbg(1, debug, sd, "%s: monitor detected, powerup failed\n", __func__);
1569 return;
1570 }
1571 adv7511_setup(sd);
1572 adv7511_notify_monitor_detect(sd);
1573 state->edid.read_retries = EDID_MAX_RETRIES;
1574 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1575 }
1576 } else if (status & MASK_ADV7511_HPD_DETECT) {
1577 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1578 state->edid.read_retries = EDID_MAX_RETRIES;
1579 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1580 } else if (!(status & MASK_ADV7511_HPD_DETECT)) {
1581 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1582 if (state->have_monitor) {
1583 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1584 state->have_monitor = false;
1585 adv7511_notify_monitor_detect(sd);
1586 }
1587 adv7511_s_power(sd, false);
1588 memset(&state->edid, 0, sizeof(struct adv7511_state_edid));
1589 adv7511_notify_no_edid(sd);
1590 }
1591 }
1592
edid_block_verify_crc(u8 * edid_block)1593 static bool edid_block_verify_crc(u8 *edid_block)
1594 {
1595 u8 sum = 0;
1596 int i;
1597
1598 for (i = 0; i < 128; i++)
1599 sum += edid_block[i];
1600 return sum == 0;
1601 }
1602
edid_verify_crc(struct v4l2_subdev * sd,u32 segment)1603 static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
1604 {
1605 struct adv7511_state *state = get_adv7511_state(sd);
1606 u32 blocks = state->edid.blocks;
1607 u8 *data = state->edid.data;
1608
1609 if (!edid_block_verify_crc(&data[segment * 256]))
1610 return false;
1611 if ((segment + 1) * 2 <= blocks)
1612 return edid_block_verify_crc(&data[segment * 256 + 128]);
1613 return true;
1614 }
1615
edid_verify_header(struct v4l2_subdev * sd,u32 segment)1616 static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1617 {
1618 static const u8 hdmi_header[] = {
1619 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1620 };
1621 struct adv7511_state *state = get_adv7511_state(sd);
1622 u8 *data = state->edid.data;
1623
1624 if (segment != 0)
1625 return true;
1626 return !memcmp(data, hdmi_header, sizeof(hdmi_header));
1627 }
1628
adv7511_check_edid_status(struct v4l2_subdev * sd)1629 static bool adv7511_check_edid_status(struct v4l2_subdev *sd)
1630 {
1631 struct adv7511_state *state = get_adv7511_state(sd);
1632 u8 edidRdy = adv7511_rd(sd, 0xc5);
1633
1634 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1635 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1636
1637 if (state->edid.complete)
1638 return true;
1639
1640 if (edidRdy & MASK_ADV7511_EDID_RDY) {
1641 int segment = adv7511_rd(sd, 0xc4);
1642 struct adv7511_edid_detect ed;
1643 int err;
1644
1645 if (segment >= EDID_MAX_SEGM) {
1646 v4l2_err(sd, "edid segment number too big\n");
1647 return false;
1648 }
1649 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1650 err = adv7511_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1651 if (!err) {
1652 adv7511_dbg_dump_edid(2, debug, sd, segment, &state->edid.data[segment * 256]);
1653 if (segment == 0) {
1654 state->edid.blocks = state->edid.data[0x7e] + 1;
1655 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1656 __func__, state->edid.blocks);
1657 }
1658 }
1659
1660 if (err || !edid_verify_crc(sd, segment) || !edid_verify_header(sd, segment)) {
1661 /* Couldn't read EDID or EDID is invalid. Force retry! */
1662 if (!err)
1663 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
1664 state->have_monitor = false;
1665 adv7511_s_power(sd, false);
1666 adv7511_s_power(sd, true);
1667 return false;
1668 }
1669 /* one more segment read ok */
1670 state->edid.segments = segment + 1;
1671 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x1);
1672 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1673 /* Request next EDID segment */
1674 v4l2_dbg(1, debug, sd, "%s: request segment %d\n", __func__, state->edid.segments);
1675 adv7511_wr(sd, 0xc9, 0xf);
1676 adv7511_wr(sd, 0xc4, state->edid.segments);
1677 state->edid.read_retries = EDID_MAX_RETRIES;
1678 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1679 return false;
1680 }
1681
1682 v4l2_dbg(1, debug, sd, "%s: edid complete with %d segment(s)\n", __func__, state->edid.segments);
1683 state->edid.complete = true;
1684 ed.phys_addr = cec_get_edid_phys_addr(state->edid.data,
1685 state->edid.segments * 256,
1686 NULL);
1687 /* report when we have all segments
1688 but report only for segment 0
1689 */
1690 ed.present = true;
1691 ed.segment = 0;
1692 state->edid_detect_counter++;
1693 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
1694 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1695 return ed.present;
1696 }
1697
1698 return false;
1699 }
1700
adv7511_registered(struct v4l2_subdev * sd)1701 static int adv7511_registered(struct v4l2_subdev *sd)
1702 {
1703 struct adv7511_state *state = get_adv7511_state(sd);
1704 struct i2c_client *client = v4l2_get_subdevdata(sd);
1705 int err;
1706
1707 err = cec_register_adapter(state->cec_adap, &client->dev);
1708 if (err)
1709 cec_delete_adapter(state->cec_adap);
1710 return err;
1711 }
1712
adv7511_unregistered(struct v4l2_subdev * sd)1713 static void adv7511_unregistered(struct v4l2_subdev *sd)
1714 {
1715 struct adv7511_state *state = get_adv7511_state(sd);
1716
1717 cec_unregister_adapter(state->cec_adap);
1718 }
1719
1720 static const struct v4l2_subdev_internal_ops adv7511_int_ops = {
1721 .registered = adv7511_registered,
1722 .unregistered = adv7511_unregistered,
1723 };
1724
1725 /* ----------------------------------------------------------------------- */
1726 /* Setup ADV7511 */
adv7511_init_setup(struct v4l2_subdev * sd)1727 static void adv7511_init_setup(struct v4l2_subdev *sd)
1728 {
1729 struct adv7511_state *state = get_adv7511_state(sd);
1730 struct adv7511_state_edid *edid = &state->edid;
1731 u32 cec_clk = state->pdata.cec_clk;
1732 u8 ratio;
1733
1734 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1735
1736 /* clear all interrupts */
1737 adv7511_wr(sd, 0x96, 0xff);
1738 adv7511_wr(sd, 0x97, 0xff);
1739 /*
1740 * Stop HPD from resetting a lot of registers.
1741 * It might leave the chip in a partly un-initialized state,
1742 * in particular with regards to hotplug bounces.
1743 */
1744 adv7511_wr_and_or(sd, 0xd6, 0x3f, 0xc0);
1745 memset(edid, 0, sizeof(struct adv7511_state_edid));
1746 state->have_monitor = false;
1747 adv7511_set_isr(sd, false);
1748 adv7511_s_stream(sd, false);
1749 adv7511_s_audio_stream(sd, false);
1750
1751 if (state->i2c_cec == NULL)
1752 return;
1753
1754 v4l2_dbg(1, debug, sd, "%s: cec_clk %d\n", __func__, cec_clk);
1755
1756 /* cec soft reset */
1757 adv7511_cec_write(sd, 0x50, 0x01);
1758 adv7511_cec_write(sd, 0x50, 0x00);
1759
1760 /* legacy mode */
1761 adv7511_cec_write(sd, 0x4a, 0x00);
1762 adv7511_cec_write(sd, 0x4a, 0x07);
1763
1764 if (cec_clk % 750000 != 0)
1765 v4l2_err(sd, "%s: cec_clk %d, not multiple of 750 Khz\n",
1766 __func__, cec_clk);
1767
1768 ratio = (cec_clk / 750000) - 1;
1769 adv7511_cec_write(sd, 0x4e, ratio << 2);
1770 }
1771
adv7511_probe(struct i2c_client * client)1772 static int adv7511_probe(struct i2c_client *client)
1773 {
1774 struct adv7511_state *state;
1775 struct adv7511_platform_data *pdata = client->dev.platform_data;
1776 struct v4l2_ctrl_handler *hdl;
1777 struct v4l2_subdev *sd;
1778 u8 chip_id[2];
1779 int err = -EIO;
1780
1781 /* Check if the adapter supports the needed features */
1782 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1783 return -EIO;
1784
1785 state = devm_kzalloc(&client->dev, sizeof(struct adv7511_state), GFP_KERNEL);
1786 if (!state)
1787 return -ENOMEM;
1788
1789 /* Platform data */
1790 if (!pdata) {
1791 v4l_err(client, "No platform data!\n");
1792 return -ENODEV;
1793 }
1794 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1795 state->fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1796 state->colorspace = V4L2_COLORSPACE_SRGB;
1797
1798 sd = &state->sd;
1799
1800 v4l2_dbg(1, debug, sd, "detecting adv7511 client on address 0x%x\n",
1801 client->addr << 1);
1802
1803 v4l2_i2c_subdev_init(sd, client, &adv7511_ops);
1804 sd->internal_ops = &adv7511_int_ops;
1805
1806 hdl = &state->hdl;
1807 v4l2_ctrl_handler_init(hdl, 10);
1808 /* add in ascending ID order */
1809 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1810 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1811 0, V4L2_DV_TX_MODE_DVI_D);
1812 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1813 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1814 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1815 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1816 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1817 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1818 state->rgb_quantization_range_ctrl =
1819 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1820 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1821 0, V4L2_DV_RGB_RANGE_AUTO);
1822 state->content_type_ctrl =
1823 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1824 V4L2_CID_DV_TX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
1825 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
1826 sd->ctrl_handler = hdl;
1827 if (hdl->error) {
1828 err = hdl->error;
1829 goto err_hdl;
1830 }
1831 state->pad.flags = MEDIA_PAD_FL_SINK;
1832 sd->entity.function = MEDIA_ENT_F_DV_ENCODER;
1833 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1834 if (err)
1835 goto err_hdl;
1836
1837 /* EDID and CEC i2c addr */
1838 state->i2c_edid_addr = state->pdata.i2c_edid << 1;
1839 state->i2c_cec_addr = state->pdata.i2c_cec << 1;
1840 state->i2c_pktmem_addr = state->pdata.i2c_pktmem << 1;
1841
1842 state->chip_revision = adv7511_rd(sd, 0x0);
1843 chip_id[0] = adv7511_rd(sd, 0xf5);
1844 chip_id[1] = adv7511_rd(sd, 0xf6);
1845 if (chip_id[0] != 0x75 || chip_id[1] != 0x11) {
1846 v4l2_err(sd, "chip_id != 0x7511, read 0x%02x%02x\n", chip_id[0],
1847 chip_id[1]);
1848 err = -EIO;
1849 goto err_entity;
1850 }
1851
1852 state->i2c_edid = i2c_new_dummy_device(client->adapter,
1853 state->i2c_edid_addr >> 1);
1854 if (IS_ERR(state->i2c_edid)) {
1855 v4l2_err(sd, "failed to register edid i2c client\n");
1856 err = PTR_ERR(state->i2c_edid);
1857 goto err_entity;
1858 }
1859
1860 adv7511_wr(sd, 0xe1, state->i2c_cec_addr);
1861 if (state->pdata.cec_clk < 3000000 ||
1862 state->pdata.cec_clk > 100000000) {
1863 v4l2_err(sd, "%s: cec_clk %u outside range, disabling cec\n",
1864 __func__, state->pdata.cec_clk);
1865 state->pdata.cec_clk = 0;
1866 }
1867
1868 if (state->pdata.cec_clk) {
1869 state->i2c_cec = i2c_new_dummy_device(client->adapter,
1870 state->i2c_cec_addr >> 1);
1871 if (IS_ERR(state->i2c_cec)) {
1872 v4l2_err(sd, "failed to register cec i2c client\n");
1873 err = PTR_ERR(state->i2c_cec);
1874 goto err_unreg_edid;
1875 }
1876 adv7511_wr(sd, 0xe2, 0x00); /* power up cec section */
1877 } else {
1878 adv7511_wr(sd, 0xe2, 0x01); /* power down cec section */
1879 }
1880
1881 state->i2c_pktmem = i2c_new_dummy_device(client->adapter, state->i2c_pktmem_addr >> 1);
1882 if (IS_ERR(state->i2c_pktmem)) {
1883 v4l2_err(sd, "failed to register pktmem i2c client\n");
1884 err = PTR_ERR(state->i2c_pktmem);
1885 goto err_unreg_cec;
1886 }
1887
1888 state->work_queue = create_singlethread_workqueue(sd->name);
1889 if (state->work_queue == NULL) {
1890 v4l2_err(sd, "could not create workqueue\n");
1891 err = -ENOMEM;
1892 goto err_unreg_pktmem;
1893 }
1894
1895 INIT_DELAYED_WORK(&state->edid_handler, adv7511_edid_handler);
1896
1897 adv7511_init_setup(sd);
1898
1899 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
1900 state->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
1901 state, dev_name(&client->dev), CEC_CAP_DEFAULTS,
1902 ADV7511_MAX_ADDRS);
1903 err = PTR_ERR_OR_ZERO(state->cec_adap);
1904 if (err) {
1905 destroy_workqueue(state->work_queue);
1906 goto err_unreg_pktmem;
1907 }
1908 #endif
1909
1910 adv7511_set_isr(sd, true);
1911 adv7511_check_monitor_present_status(sd);
1912
1913 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1914 client->addr << 1, client->adapter->name);
1915 return 0;
1916
1917 err_unreg_pktmem:
1918 i2c_unregister_device(state->i2c_pktmem);
1919 err_unreg_cec:
1920 i2c_unregister_device(state->i2c_cec);
1921 err_unreg_edid:
1922 i2c_unregister_device(state->i2c_edid);
1923 err_entity:
1924 media_entity_cleanup(&sd->entity);
1925 err_hdl:
1926 v4l2_ctrl_handler_free(&state->hdl);
1927 return err;
1928 }
1929
1930 /* ----------------------------------------------------------------------- */
1931
adv7511_remove(struct i2c_client * client)1932 static void adv7511_remove(struct i2c_client *client)
1933 {
1934 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1935 struct adv7511_state *state = get_adv7511_state(sd);
1936
1937 state->chip_revision = -1;
1938
1939 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1940 client->addr << 1, client->adapter->name);
1941
1942 adv7511_set_isr(sd, false);
1943 adv7511_init_setup(sd);
1944 cancel_delayed_work_sync(&state->edid_handler);
1945 i2c_unregister_device(state->i2c_edid);
1946 i2c_unregister_device(state->i2c_cec);
1947 i2c_unregister_device(state->i2c_pktmem);
1948 destroy_workqueue(state->work_queue);
1949 v4l2_device_unregister_subdev(sd);
1950 media_entity_cleanup(&sd->entity);
1951 v4l2_ctrl_handler_free(sd->ctrl_handler);
1952 }
1953
1954 /* ----------------------------------------------------------------------- */
1955
1956 static const struct i2c_device_id adv7511_id[] = {
1957 { "adv7511-v4l2", 0 },
1958 { }
1959 };
1960 MODULE_DEVICE_TABLE(i2c, adv7511_id);
1961
1962 static struct i2c_driver adv7511_driver = {
1963 .driver = {
1964 .name = "adv7511-v4l2",
1965 },
1966 .probe = adv7511_probe,
1967 .remove = adv7511_remove,
1968 .id_table = adv7511_id,
1969 };
1970
1971 module_i2c_driver(adv7511_driver);
1972