1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Mediatek IR Receiver Controller
4 *
5 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/io.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset.h>
15 #include <media/rc-core.h>
16
17 #define MTK_IR_DEV KBUILD_MODNAME
18
19 /* Register to enable PWM and IR */
20 #define MTK_CONFIG_HIGH_REG 0x0c
21
22 /* Bit to enable IR pulse width detection */
23 #define MTK_PWM_EN BIT(13)
24
25 /*
26 * Register to setting ok count whose unit based on hardware sampling period
27 * indicating IR receiving completion and then making IRQ fires
28 */
29 #define MTK_OK_COUNT_MASK (GENMASK(22, 16))
30 #define MTK_OK_COUNT(x) ((x) << 16)
31
32 /* Bit to enable IR hardware function */
33 #define MTK_IR_EN BIT(0)
34
35 /* Bit to restart IR receiving */
36 #define MTK_IRCLR BIT(0)
37
38 /* Fields containing pulse width data */
39 #define MTK_WIDTH_MASK (GENMASK(7, 0))
40
41 /* IR threshold */
42 #define MTK_IRTHD 0x14
43 #define MTK_DG_CNT_MASK (GENMASK(12, 8))
44 #define MTK_DG_CNT(x) ((x) << 8)
45
46 /* Bit to enable interrupt */
47 #define MTK_IRINT_EN BIT(0)
48
49 /* Bit to clear interrupt status */
50 #define MTK_IRINT_CLR BIT(0)
51
52 /* Maximum count of samples */
53 #define MTK_MAX_SAMPLES 0xff
54 /* Indicate the end of IR message */
55 #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
56 /* Number of registers to record the pulse width */
57 #define MTK_CHKDATA_SZ 17
58 /* Sample period in us */
59 #define MTK_IR_SAMPLE 46
60
61 enum mtk_fields {
62 /* Register to setting software sampling period */
63 MTK_CHK_PERIOD,
64 /* Register to setting hardware sampling period */
65 MTK_HW_PERIOD,
66 };
67
68 enum mtk_regs {
69 /* Register to clear state of state machine */
70 MTK_IRCLR_REG,
71 /* Register containing pulse width data */
72 MTK_CHKDATA_REG,
73 /* Register to enable IR interrupt */
74 MTK_IRINT_EN_REG,
75 /* Register to ack IR interrupt */
76 MTK_IRINT_CLR_REG
77 };
78
79 static const u32 mt7623_regs[] = {
80 [MTK_IRCLR_REG] = 0x20,
81 [MTK_CHKDATA_REG] = 0x88,
82 [MTK_IRINT_EN_REG] = 0xcc,
83 [MTK_IRINT_CLR_REG] = 0xd0,
84 };
85
86 static const u32 mt7622_regs[] = {
87 [MTK_IRCLR_REG] = 0x18,
88 [MTK_CHKDATA_REG] = 0x30,
89 [MTK_IRINT_EN_REG] = 0x1c,
90 [MTK_IRINT_CLR_REG] = 0x20,
91 };
92
93 struct mtk_field_type {
94 u32 reg;
95 u8 offset;
96 u32 mask;
97 };
98
99 /*
100 * struct mtk_ir_data - This is the structure holding all differences among
101 various hardwares
102 * @regs: The pointer to the array holding registers offset
103 * @fields: The pointer to the array holding fields location
104 * @div: The internal divisor for the based reference clock
105 * @ok_count: The count indicating the completion of IR data
106 * receiving when count is reached
107 * @hw_period: The value indicating the hardware sampling period
108 */
109 struct mtk_ir_data {
110 const u32 *regs;
111 const struct mtk_field_type *fields;
112 u8 div;
113 u8 ok_count;
114 u32 hw_period;
115 };
116
117 static const struct mtk_field_type mt7623_fields[] = {
118 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
119 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
120 };
121
122 static const struct mtk_field_type mt7622_fields[] = {
123 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
124 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
125 };
126
127 /*
128 * struct mtk_ir - This is the main datasructure for holding the state
129 * of the driver
130 * @dev: The device pointer
131 * @rc: The rc instrance
132 * @base: The mapped register i/o base
133 * @irq: The IRQ that we are using
134 * @clk: The clock that IR internal is using
135 * @bus: The clock that software decoder is using
136 * @data: Holding specific data for vaious platform
137 */
138 struct mtk_ir {
139 struct device *dev;
140 struct rc_dev *rc;
141 void __iomem *base;
142 int irq;
143 struct clk *clk;
144 struct clk *bus;
145 const struct mtk_ir_data *data;
146 };
147
mtk_chkdata_reg(struct mtk_ir * ir,u32 i)148 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
149 {
150 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
151 }
152
mtk_chk_period(struct mtk_ir * ir)153 static inline u32 mtk_chk_period(struct mtk_ir *ir)
154 {
155 u32 val;
156
157 /*
158 * Period for software decoder used in the
159 * unit of raw software sampling
160 */
161 val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus),
162 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE);
163
164 dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
165 clk_get_rate(ir->bus) / ir->data->div);
166 dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
167
168 return val;
169 }
170
mtk_w32_mask(struct mtk_ir * ir,u32 val,u32 mask,unsigned int reg)171 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
172 {
173 u32 tmp;
174
175 tmp = __raw_readl(ir->base + reg);
176 tmp = (tmp & ~mask) | val;
177 __raw_writel(tmp, ir->base + reg);
178 }
179
mtk_w32(struct mtk_ir * ir,u32 val,unsigned int reg)180 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
181 {
182 __raw_writel(val, ir->base + reg);
183 }
184
mtk_r32(struct mtk_ir * ir,unsigned int reg)185 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
186 {
187 return __raw_readl(ir->base + reg);
188 }
189
mtk_irq_disable(struct mtk_ir * ir,u32 mask)190 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
191 {
192 u32 val;
193
194 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
195 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
196 }
197
mtk_irq_enable(struct mtk_ir * ir,u32 mask)198 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
199 {
200 u32 val;
201
202 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
203 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
204 }
205
mtk_ir_irq(int irqno,void * dev_id)206 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
207 {
208 struct ir_raw_event rawir = {};
209 struct mtk_ir *ir = dev_id;
210 u32 i, j, val;
211 u8 wid;
212
213 /*
214 * Each pulse and space is encoded as a single byte, each byte
215 * alternating between pulse and space. If a pulse or space is longer
216 * than can be encoded in a single byte, it is encoded as the maximum
217 * value 0xff.
218 *
219 * If a space is longer than ok_count (about 23ms), the value is
220 * encoded as zero, and all following bytes are zero. Any IR that
221 * follows will be presented in the next interrupt.
222 *
223 * If there are more than 68 (=MTK_CHKDATA_SZ * 4) pulses and spaces,
224 * then the only the first 68 will be presented; the rest is lost.
225 */
226
227 /* Handle all pulse and space IR controller captures */
228 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
229 val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
230 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
231
232 for (j = 0 ; j < 4 ; j++) {
233 wid = val & MTK_WIDTH_MASK;
234 val >>= 8;
235 rawir.pulse = !rawir.pulse;
236 rawir.duration = wid * (MTK_IR_SAMPLE + 1);
237 ir_raw_event_store_with_filter(ir->rc, &rawir);
238 }
239 }
240
241 /*
242 * The maximum number of edges the IR controller can
243 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
244 * is over the limit, the last incomplete IR message would
245 * be appended trailing space and still would be sent into
246 * ir-rc-raw to decode. That helps it is possible that it
247 * has enough information to decode a scancode even if the
248 * trailing end of the message is missing.
249 */
250 if (!MTK_IR_END(wid, rawir.pulse)) {
251 rawir.pulse = false;
252 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
253 ir_raw_event_store_with_filter(ir->rc, &rawir);
254 }
255
256 ir_raw_event_handle(ir->rc);
257
258 /*
259 * Restart controller for the next receive that would
260 * clear up all CHKDATA registers
261 */
262 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
263
264 /* Clear interrupt status */
265 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
266 ir->data->regs[MTK_IRINT_CLR_REG]);
267
268 return IRQ_HANDLED;
269 }
270
271 static const struct mtk_ir_data mt7623_data = {
272 .regs = mt7623_regs,
273 .fields = mt7623_fields,
274 .ok_count = 3,
275 .hw_period = 0xff,
276 .div = 4,
277 };
278
279 static const struct mtk_ir_data mt7622_data = {
280 .regs = mt7622_regs,
281 .fields = mt7622_fields,
282 .ok_count = 3,
283 .hw_period = 0xffff,
284 .div = 32,
285 };
286
287 static const struct of_device_id mtk_ir_match[] = {
288 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
289 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
290 {},
291 };
292 MODULE_DEVICE_TABLE(of, mtk_ir_match);
293
mtk_ir_probe(struct platform_device * pdev)294 static int mtk_ir_probe(struct platform_device *pdev)
295 {
296 struct device *dev = &pdev->dev;
297 struct device_node *dn = dev->of_node;
298 struct mtk_ir *ir;
299 u32 val;
300 int ret = 0;
301 const char *map_name;
302
303 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
304 if (!ir)
305 return -ENOMEM;
306
307 ir->dev = dev;
308 ir->data = of_device_get_match_data(dev);
309
310 ir->clk = devm_clk_get(dev, "clk");
311 if (IS_ERR(ir->clk)) {
312 dev_err(dev, "failed to get a ir clock.\n");
313 return PTR_ERR(ir->clk);
314 }
315
316 ir->bus = devm_clk_get(dev, "bus");
317 if (IS_ERR(ir->bus)) {
318 /*
319 * For compatibility with older device trees try unnamed
320 * ir->bus uses the same clock as ir->clock.
321 */
322 ir->bus = ir->clk;
323 }
324
325 ir->base = devm_platform_ioremap_resource(pdev, 0);
326 if (IS_ERR(ir->base))
327 return PTR_ERR(ir->base);
328
329 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
330 if (!ir->rc) {
331 dev_err(dev, "failed to allocate device\n");
332 return -ENOMEM;
333 }
334
335 ir->rc->priv = ir;
336 ir->rc->device_name = MTK_IR_DEV;
337 ir->rc->input_phys = MTK_IR_DEV "/input0";
338 ir->rc->input_id.bustype = BUS_HOST;
339 ir->rc->input_id.vendor = 0x0001;
340 ir->rc->input_id.product = 0x0001;
341 ir->rc->input_id.version = 0x0001;
342 map_name = of_get_property(dn, "linux,rc-map-name", NULL);
343 ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
344 ir->rc->dev.parent = dev;
345 ir->rc->driver_name = MTK_IR_DEV;
346 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
347 ir->rc->rx_resolution = MTK_IR_SAMPLE;
348 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
349
350 ret = devm_rc_register_device(dev, ir->rc);
351 if (ret) {
352 dev_err(dev, "failed to register rc device\n");
353 return ret;
354 }
355
356 platform_set_drvdata(pdev, ir);
357
358 ir->irq = platform_get_irq(pdev, 0);
359 if (ir->irq < 0)
360 return -ENODEV;
361
362 if (clk_prepare_enable(ir->clk)) {
363 dev_err(dev, "try to enable ir_clk failed\n");
364 return -EINVAL;
365 }
366
367 if (clk_prepare_enable(ir->bus)) {
368 dev_err(dev, "try to enable ir_clk failed\n");
369 ret = -EINVAL;
370 goto exit_clkdisable_clk;
371 }
372
373 /*
374 * Enable interrupt after proper hardware
375 * setup and IRQ handler registration
376 */
377 mtk_irq_disable(ir, MTK_IRINT_EN);
378
379 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
380 if (ret) {
381 dev_err(dev, "failed request irq\n");
382 goto exit_clkdisable_bus;
383 }
384
385 /*
386 * Setup software sample period as the reference of software decoder
387 */
388 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
389 ir->data->fields[MTK_CHK_PERIOD].mask;
390 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
391 ir->data->fields[MTK_CHK_PERIOD].reg);
392
393 /*
394 * Setup hardware sampling period used to setup the proper timeout for
395 * indicating end of IR receiving completion
396 */
397 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
398 ir->data->fields[MTK_HW_PERIOD].mask;
399 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
400 ir->data->fields[MTK_HW_PERIOD].reg);
401
402 /* Set de-glitch counter */
403 mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
404
405 /* Enable IR and PWM */
406 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG) & ~MTK_OK_COUNT_MASK;
407 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
408 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
409
410 mtk_irq_enable(ir, MTK_IRINT_EN);
411
412 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
413 MTK_IR_SAMPLE);
414
415 return 0;
416
417 exit_clkdisable_bus:
418 clk_disable_unprepare(ir->bus);
419 exit_clkdisable_clk:
420 clk_disable_unprepare(ir->clk);
421
422 return ret;
423 }
424
mtk_ir_remove(struct platform_device * pdev)425 static void mtk_ir_remove(struct platform_device *pdev)
426 {
427 struct mtk_ir *ir = platform_get_drvdata(pdev);
428
429 /*
430 * Avoid contention between remove handler and
431 * IRQ handler so that disabling IR interrupt and
432 * waiting for pending IRQ handler to complete
433 */
434 mtk_irq_disable(ir, MTK_IRINT_EN);
435 synchronize_irq(ir->irq);
436
437 clk_disable_unprepare(ir->bus);
438 clk_disable_unprepare(ir->clk);
439 }
440
441 static struct platform_driver mtk_ir_driver = {
442 .probe = mtk_ir_probe,
443 .remove_new = mtk_ir_remove,
444 .driver = {
445 .name = MTK_IR_DEV,
446 .of_match_table = mtk_ir_match,
447 },
448 };
449
450 module_platform_driver(mtk_ir_driver);
451
452 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
453 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
454 MODULE_LICENSE("GPL");
455