1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H
8 #define __LINUX_MTD_SPI_NOR_INTERNAL_H
9
10 #include "sfdp.h"
11
12 #define SPI_NOR_MAX_ID_LEN 6
13 /*
14 * 256 bytes is a sane default for most older flashes. Newer flashes will
15 * have the page size defined within their SFDP tables.
16 */
17 #define SPI_NOR_DEFAULT_PAGE_SIZE 256
18 #define SPI_NOR_DEFAULT_N_BANKS 1
19 #define SPI_NOR_DEFAULT_SECTOR_SIZE SZ_64K
20
21 /* Standard SPI NOR flash operations. */
22 #define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \
23 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \
24 SPI_MEM_OP_ADDR(naddr, 0, 0), \
25 SPI_MEM_OP_DUMMY(ndummy, 0), \
26 SPI_MEM_OP_DATA_IN(len, buf, 0))
27
28 #define SPI_NOR_WREN_OP \
29 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), \
30 SPI_MEM_OP_NO_ADDR, \
31 SPI_MEM_OP_NO_DUMMY, \
32 SPI_MEM_OP_NO_DATA)
33
34 #define SPI_NOR_WRDI_OP \
35 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), \
36 SPI_MEM_OP_NO_ADDR, \
37 SPI_MEM_OP_NO_DUMMY, \
38 SPI_MEM_OP_NO_DATA)
39
40 #define SPI_NOR_RDSR_OP(buf) \
41 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \
42 SPI_MEM_OP_NO_ADDR, \
43 SPI_MEM_OP_NO_DUMMY, \
44 SPI_MEM_OP_DATA_IN(1, buf, 0))
45
46 #define SPI_NOR_WRSR_OP(buf, len) \
47 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \
48 SPI_MEM_OP_NO_ADDR, \
49 SPI_MEM_OP_NO_DUMMY, \
50 SPI_MEM_OP_DATA_OUT(len, buf, 0))
51
52 #define SPI_NOR_RDSR2_OP(buf) \
53 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \
54 SPI_MEM_OP_NO_ADDR, \
55 SPI_MEM_OP_NO_DUMMY, \
56 SPI_MEM_OP_DATA_OUT(1, buf, 0))
57
58 #define SPI_NOR_WRSR2_OP(buf) \
59 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \
60 SPI_MEM_OP_NO_ADDR, \
61 SPI_MEM_OP_NO_DUMMY, \
62 SPI_MEM_OP_DATA_OUT(1, buf, 0))
63
64 #define SPI_NOR_RDCR_OP(buf) \
65 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \
66 SPI_MEM_OP_NO_ADDR, \
67 SPI_MEM_OP_NO_DUMMY, \
68 SPI_MEM_OP_DATA_IN(1, buf, 0))
69
70 #define SPI_NOR_EN4B_EX4B_OP(enable) \
71 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \
72 SPI_MEM_OP_NO_ADDR, \
73 SPI_MEM_OP_NO_DUMMY, \
74 SPI_MEM_OP_NO_DATA)
75
76 #define SPI_NOR_BRWR_OP(buf) \
77 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), \
78 SPI_MEM_OP_NO_ADDR, \
79 SPI_MEM_OP_NO_DUMMY, \
80 SPI_MEM_OP_DATA_OUT(1, buf, 0))
81
82 #define SPI_NOR_GBULK_OP \
83 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), \
84 SPI_MEM_OP_NO_ADDR, \
85 SPI_MEM_OP_NO_DUMMY, \
86 SPI_MEM_OP_NO_DATA)
87
88 #define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice) \
89 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
90 SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0), \
91 SPI_MEM_OP_NO_DUMMY, \
92 SPI_MEM_OP_NO_DATA)
93
94 #define SPI_NOR_SECTOR_ERASE_OP(opcode, addr_nbytes, addr) \
95 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
96 SPI_MEM_OP_ADDR(addr_nbytes, addr, 0), \
97 SPI_MEM_OP_NO_DUMMY, \
98 SPI_MEM_OP_NO_DATA)
99
100 #define SPI_NOR_READ_OP(opcode) \
101 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
102 SPI_MEM_OP_ADDR(3, 0, 0), \
103 SPI_MEM_OP_DUMMY(1, 0), \
104 SPI_MEM_OP_DATA_IN(2, NULL, 0))
105
106 #define SPI_NOR_PP_OP(opcode) \
107 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
108 SPI_MEM_OP_ADDR(3, 0, 0), \
109 SPI_MEM_OP_NO_DUMMY, \
110 SPI_MEM_OP_DATA_OUT(2, NULL, 0))
111
112 #define SPINOR_SRSTEN_OP \
113 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), \
114 SPI_MEM_OP_NO_DUMMY, \
115 SPI_MEM_OP_NO_ADDR, \
116 SPI_MEM_OP_NO_DATA)
117
118 #define SPINOR_SRST_OP \
119 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), \
120 SPI_MEM_OP_NO_DUMMY, \
121 SPI_MEM_OP_NO_ADDR, \
122 SPI_MEM_OP_NO_DATA)
123
124 /* Keep these in sync with the list in debugfs.c */
125 enum spi_nor_option_flags {
126 SNOR_F_HAS_SR_TB = BIT(0),
127 SNOR_F_NO_OP_CHIP_ERASE = BIT(1),
128 SNOR_F_BROKEN_RESET = BIT(2),
129 SNOR_F_4B_OPCODES = BIT(3),
130 SNOR_F_HAS_4BAIT = BIT(4),
131 SNOR_F_HAS_LOCK = BIT(5),
132 SNOR_F_HAS_16BIT_SR = BIT(6),
133 SNOR_F_NO_READ_CR = BIT(7),
134 SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
135 SNOR_F_HAS_4BIT_BP = BIT(9),
136 SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
137 SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
138 SNOR_F_SOFT_RESET = BIT(12),
139 SNOR_F_SWP_IS_VOLATILE = BIT(13),
140 SNOR_F_RWW = BIT(14),
141 SNOR_F_ECC = BIT(15),
142 SNOR_F_NO_WP = BIT(16),
143 };
144
145 struct spi_nor_read_command {
146 u8 num_mode_clocks;
147 u8 num_wait_states;
148 u8 opcode;
149 enum spi_nor_protocol proto;
150 };
151
152 struct spi_nor_pp_command {
153 u8 opcode;
154 enum spi_nor_protocol proto;
155 };
156
157 enum spi_nor_read_command_index {
158 SNOR_CMD_READ,
159 SNOR_CMD_READ_FAST,
160 SNOR_CMD_READ_1_1_1_DTR,
161
162 /* Dual SPI */
163 SNOR_CMD_READ_1_1_2,
164 SNOR_CMD_READ_1_2_2,
165 SNOR_CMD_READ_2_2_2,
166 SNOR_CMD_READ_1_2_2_DTR,
167
168 /* Quad SPI */
169 SNOR_CMD_READ_1_1_4,
170 SNOR_CMD_READ_1_4_4,
171 SNOR_CMD_READ_4_4_4,
172 SNOR_CMD_READ_1_4_4_DTR,
173
174 /* Octal SPI */
175 SNOR_CMD_READ_1_1_8,
176 SNOR_CMD_READ_1_8_8,
177 SNOR_CMD_READ_8_8_8,
178 SNOR_CMD_READ_1_8_8_DTR,
179 SNOR_CMD_READ_8_8_8_DTR,
180
181 SNOR_CMD_READ_MAX
182 };
183
184 enum spi_nor_pp_command_index {
185 SNOR_CMD_PP,
186
187 /* Quad SPI */
188 SNOR_CMD_PP_1_1_4,
189 SNOR_CMD_PP_1_4_4,
190 SNOR_CMD_PP_4_4_4,
191
192 /* Octal SPI */
193 SNOR_CMD_PP_1_1_8,
194 SNOR_CMD_PP_1_8_8,
195 SNOR_CMD_PP_8_8_8,
196 SNOR_CMD_PP_8_8_8_DTR,
197
198 SNOR_CMD_PP_MAX
199 };
200
201 /**
202 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
203 * @size: the size of the sector/block erased by the erase type.
204 * JEDEC JESD216B imposes erase sizes to be a power of 2.
205 * @size_shift: @size is a power of 2, the shift is stored in
206 * @size_shift.
207 * @size_mask: the size mask based on @size_shift.
208 * @opcode: the SPI command op code to erase the sector/block.
209 * @idx: Erase Type index as sorted in the Basic Flash Parameter
210 * Table. It will be used to synchronize the supported
211 * Erase Types with the ones identified in the SFDP
212 * optional tables.
213 */
214 struct spi_nor_erase_type {
215 u32 size;
216 u32 size_shift;
217 u32 size_mask;
218 u8 opcode;
219 u8 idx;
220 };
221
222 /**
223 * struct spi_nor_erase_command - Used for non-uniform erases
224 * The structure is used to describe a list of erase commands to be executed
225 * once we validate that the erase can be performed. The elements in the list
226 * are run-length encoded.
227 * @list: for inclusion into the list of erase commands.
228 * @count: how many times the same erase command should be
229 * consecutively used.
230 * @size: the size of the sector/block erased by the command.
231 * @opcode: the SPI command op code to erase the sector/block.
232 */
233 struct spi_nor_erase_command {
234 struct list_head list;
235 u32 count;
236 u32 size;
237 u8 opcode;
238 };
239
240 /**
241 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
242 * @offset: the offset in the data array of erase region start.
243 * @size: the size of the region in bytes.
244 * @erase_mask: bitmask to indicate all the supported erase commands
245 * inside this region. The erase types are sorted in
246 * ascending order with the smallest Erase Type size being
247 * at BIT(0).
248 * @overlaid: determine if this region is overlaid.
249 */
250 struct spi_nor_erase_region {
251 u64 offset;
252 u64 size;
253 u8 erase_mask;
254 bool overlaid;
255 };
256
257 #define SNOR_ERASE_TYPE_MAX 4
258
259 /**
260 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
261 * @regions: array of erase regions. The regions are consecutive in
262 * address space. Walking through the regions is done
263 * incrementally.
264 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
265 * sector size (legacy implementation).
266 * @erase_type: an array of erase types shared by all the regions.
267 * The erase types are sorted in ascending order, with the
268 * smallest Erase Type size being the first member in the
269 * erase_type array.
270 * @n_regions: number of erase regions.
271 */
272 struct spi_nor_erase_map {
273 struct spi_nor_erase_region *regions;
274 struct spi_nor_erase_region uniform_region;
275 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
276 unsigned int n_regions;
277 };
278
279 /**
280 * struct spi_nor_locking_ops - SPI NOR locking methods
281 * @lock: lock a region of the SPI NOR.
282 * @unlock: unlock a region of the SPI NOR.
283 * @is_locked: check if a region of the SPI NOR is completely locked
284 */
285 struct spi_nor_locking_ops {
286 int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len);
287 int (*unlock)(struct spi_nor *nor, loff_t ofs, u64 len);
288 int (*is_locked)(struct spi_nor *nor, loff_t ofs, u64 len);
289 };
290
291 /**
292 * struct spi_nor_otp_organization - Structure to describe the SPI NOR OTP regions
293 * @len: size of one OTP region in bytes.
294 * @base: start address of the OTP area.
295 * @offset: offset between consecutive OTP regions if there are more
296 * than one.
297 * @n_regions: number of individual OTP regions.
298 */
299 struct spi_nor_otp_organization {
300 size_t len;
301 loff_t base;
302 loff_t offset;
303 unsigned int n_regions;
304 };
305
306 /**
307 * struct spi_nor_otp_ops - SPI NOR OTP methods
308 * @read: read from the SPI NOR OTP area.
309 * @write: write to the SPI NOR OTP area.
310 * @lock: lock an OTP region.
311 * @erase: erase an OTP region.
312 * @is_locked: check if an OTP region of the SPI NOR is locked.
313 */
314 struct spi_nor_otp_ops {
315 int (*read)(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf);
316 int (*write)(struct spi_nor *nor, loff_t addr, size_t len,
317 const u8 *buf);
318 int (*lock)(struct spi_nor *nor, unsigned int region);
319 int (*erase)(struct spi_nor *nor, loff_t addr);
320 int (*is_locked)(struct spi_nor *nor, unsigned int region);
321 };
322
323 /**
324 * struct spi_nor_otp - SPI NOR OTP grouping structure
325 * @org: OTP region organization
326 * @ops: OTP access ops
327 */
328 struct spi_nor_otp {
329 const struct spi_nor_otp_organization *org;
330 const struct spi_nor_otp_ops *ops;
331 };
332
333 /**
334 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
335 * Includes legacy flash parameters and settings that can be overwritten
336 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
337 * Serial Flash Discoverable Parameters (SFDP) tables.
338 *
339 * @bank_size: the flash memory bank density in bytes.
340 * @size: the total flash memory density in bytes.
341 * @writesize Minimal writable flash unit size. Defaults to 1. Set to
342 * ECC unit size for ECC-ed flashes.
343 * @page_size: the page size of the SPI NOR flash memory.
344 * @addr_nbytes: number of address bytes to send.
345 * @addr_mode_nbytes: number of address bytes of current address mode. Useful
346 * when the flash operates with 4B opcodes but needs the
347 * internal address mode for opcodes that don't have a 4B
348 * opcode correspondent.
349 * @rdsr_dummy: dummy cycles needed for Read Status Register command
350 * in octal DTR mode.
351 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
352 * command in octal DTR mode.
353 * @n_banks: number of banks.
354 * @n_dice: number of dice in the flash memory.
355 * @die_erase_opcode: die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.
356 * @vreg_offset: volatile register offset for each die.
357 * @hwcaps: describes the read and page program hardware
358 * capabilities.
359 * @reads: read capabilities ordered by priority: the higher index
360 * in the array, the higher priority.
361 * @page_programs: page program capabilities ordered by priority: the
362 * higher index in the array, the higher priority.
363 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
364 * Table.
365 * @otp: SPI NOR OTP info.
366 * @set_octal_dtr: enables or disables SPI NOR octal DTR mode.
367 * @quad_enable: enables SPI NOR quad mode.
368 * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
369 * @convert_addr: converts an absolute address into something the flash
370 * will understand. Particularly useful when pagesize is
371 * not a power-of-2.
372 * @setup: (optional) configures the SPI NOR memory. Useful for
373 * SPI NOR flashes that have peculiarities to the SPI NOR
374 * standard e.g. different opcodes, specific address
375 * calculation, page size, etc.
376 * @ready: (optional) flashes might use a different mechanism
377 * than reading the status register to indicate they
378 * are ready for a new command
379 * @locking_ops: SPI NOR locking methods.
380 * @priv: flash's private data.
381 */
382 struct spi_nor_flash_parameter {
383 u64 bank_size;
384 u64 size;
385 u32 writesize;
386 u32 page_size;
387 u8 addr_nbytes;
388 u8 addr_mode_nbytes;
389 u8 rdsr_dummy;
390 u8 rdsr_addr_nbytes;
391 u8 n_banks;
392 u8 n_dice;
393 u8 die_erase_opcode;
394 u32 *vreg_offset;
395
396 struct spi_nor_hwcaps hwcaps;
397 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
398 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
399
400 struct spi_nor_erase_map erase_map;
401 struct spi_nor_otp otp;
402
403 int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
404 int (*quad_enable)(struct spi_nor *nor);
405 int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
406 u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
407 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
408 int (*ready)(struct spi_nor *nor);
409
410 const struct spi_nor_locking_ops *locking_ops;
411 void *priv;
412 };
413
414 /**
415 * struct spi_nor_fixups - SPI NOR fixup hooks
416 * @default_init: called after default flash parameters init. Used to tweak
417 * flash parameters when information provided by the flash_info
418 * table is incomplete or wrong.
419 * @post_bfpt: called after the BFPT table has been parsed
420 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
421 * that do not support RDSFDP). Typically used to tweak various
422 * parameters that could not be extracted by other means (i.e.
423 * when information provided by the SFDP/flash_info tables are
424 * incomplete or wrong).
425 * @late_init: used to initialize flash parameters that are not declared in the
426 * JESD216 SFDP standard, or where SFDP tables not defined at all.
427 * Will replace the default_init() hook.
428 *
429 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
430 * table is broken or not available.
431 */
432 struct spi_nor_fixups {
433 void (*default_init)(struct spi_nor *nor);
434 int (*post_bfpt)(struct spi_nor *nor,
435 const struct sfdp_parameter_header *bfpt_header,
436 const struct sfdp_bfpt *bfpt);
437 int (*post_sfdp)(struct spi_nor *nor);
438 int (*late_init)(struct spi_nor *nor);
439 };
440
441 /**
442 * struct spi_nor_id - SPI NOR flash ID.
443 *
444 * @bytes: the bytes returned by the flash when issuing command 9F. Typically,
445 * the first byte is the manufacturer ID code (see JEP106) and the next
446 * two bytes are a flash part specific ID.
447 * @len: the number of bytes of ID.
448 */
449 struct spi_nor_id {
450 const u8 *bytes;
451 u8 len;
452 };
453
454 /**
455 * struct flash_info - SPI NOR flash_info entry.
456 * @id: pointer to struct spi_nor_id or NULL, which means "no ID" (mostly
457 * older chips).
458 * @name: (obsolete) the name of the flash. Do not set it for new additions.
459 * @size: the size of the flash in bytes.
460 * @sector_size: (optional) the size listed here is what works with
461 * SPINOR_OP_SE, which isn't necessarily called a "sector" by
462 * the vendor. Defaults to 64k.
463 * @n_banks: (optional) the number of banks. Defaults to 1.
464 * @page_size: (optional) the flash's page size. Defaults to 256.
465 * @addr_nbytes: number of address bytes to send.
466 *
467 * @flags: flags that indicate support that is not defined by the
468 * JESD216 standard in its SFDP tables. Flag meanings:
469 * SPI_NOR_HAS_LOCK: flash supports lock/unlock via SR
470 * SPI_NOR_HAS_TB: flash SR has Top/Bottom (TB) protect bit. Must be
471 * used with SPI_NOR_HAS_LOCK.
472 * SPI_NOR_TB_SR_BIT6: Top/Bottom (TB) is bit 6 of status register.
473 * Must be used with SPI_NOR_HAS_TB.
474 * SPI_NOR_4BIT_BP: flash SR has 4 bit fields (BP0-3) for block
475 * protection.
476 * SPI_NOR_BP3_SR_BIT6: BP3 is bit 6 of status register. Must be used with
477 * SPI_NOR_4BIT_BP.
478 * SPI_NOR_SWP_IS_VOLATILE: flash has volatile software write protection bits.
479 * Usually these will power-up in a write-protected
480 * state.
481 * SPI_NOR_NO_ERASE: no erase command needed.
482 * SPI_NOR_NO_FR: can't do fastread.
483 * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
484 * SPI_NOR_RWW: flash supports reads while write.
485 *
486 * @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
487 * Used when SFDP tables are not defined in the flash. These
488 * flags are used together with the SPI_NOR_SKIP_SFDP flag.
489 * SPI_NOR_SKIP_SFDP: skip parsing of SFDP tables.
490 * SECT_4K: SPINOR_OP_BE_4K works uniformly.
491 * SPI_NOR_DUAL_READ: flash supports Dual Read.
492 * SPI_NOR_QUAD_READ: flash supports Quad Read.
493 * SPI_NOR_OCTAL_READ: flash supports Octal Read.
494 * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
495 * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
496 *
497 * @fixup_flags: flags that indicate support that can be discovered via SFDP
498 * ideally, but can not be discovered for this particular flash
499 * because the SFDP table that indicates this support is not
500 * defined by the flash. In case the table for this support is
501 * defined but has wrong values, one should instead use a
502 * post_sfdp() hook to set the SNOR_F equivalent flag.
503 *
504 * SPI_NOR_4B_OPCODES: use dedicated 4byte address op codes to support
505 * memory size above 128Mib.
506 * SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode
507 * via a volatile bit.
508 * @mfr_flags: manufacturer private flags. Used in the manufacturer fixup
509 * hooks to differentiate support between flashes of the same
510 * manufacturer.
511 * @otp_org: flash's OTP organization.
512 * @fixups: part specific fixup hooks.
513 */
514 struct flash_info {
515 char *name;
516 const struct spi_nor_id *id;
517 size_t size;
518 unsigned sector_size;
519 u16 page_size;
520 u8 n_banks;
521 u8 addr_nbytes;
522
523 u16 flags;
524 #define SPI_NOR_HAS_LOCK BIT(0)
525 #define SPI_NOR_HAS_TB BIT(1)
526 #define SPI_NOR_TB_SR_BIT6 BIT(2)
527 #define SPI_NOR_4BIT_BP BIT(3)
528 #define SPI_NOR_BP3_SR_BIT6 BIT(4)
529 #define SPI_NOR_SWP_IS_VOLATILE BIT(5)
530 #define SPI_NOR_NO_ERASE BIT(6)
531 #define SPI_NOR_NO_FR BIT(7)
532 #define SPI_NOR_QUAD_PP BIT(8)
533 #define SPI_NOR_RWW BIT(9)
534
535 u8 no_sfdp_flags;
536 #define SPI_NOR_SKIP_SFDP BIT(0)
537 #define SECT_4K BIT(1)
538 #define SPI_NOR_DUAL_READ BIT(3)
539 #define SPI_NOR_QUAD_READ BIT(4)
540 #define SPI_NOR_OCTAL_READ BIT(5)
541 #define SPI_NOR_OCTAL_DTR_READ BIT(6)
542 #define SPI_NOR_OCTAL_DTR_PP BIT(7)
543
544 u8 fixup_flags;
545 #define SPI_NOR_4B_OPCODES BIT(0)
546 #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1)
547
548 u8 mfr_flags;
549
550 const struct spi_nor_otp_organization *otp;
551 const struct spi_nor_fixups *fixups;
552 };
553
554 #define SNOR_ID(...) \
555 (&(const struct spi_nor_id){ \
556 .bytes = (const u8[]){ __VA_ARGS__ }, \
557 .len = sizeof((u8[]){ __VA_ARGS__ }), \
558 })
559
560 #define SNOR_OTP(_len, _n_regions, _base, _offset) \
561 (&(const struct spi_nor_otp_organization){ \
562 .len = (_len), \
563 .base = (_base), \
564 .offset = (_offset), \
565 .n_regions = (_n_regions), \
566 })
567
568 /**
569 * struct spi_nor_manufacturer - SPI NOR manufacturer object
570 * @name: manufacturer name
571 * @parts: array of parts supported by this manufacturer
572 * @nparts: number of entries in the parts array
573 * @fixups: hooks called at various points in time during spi_nor_scan()
574 */
575 struct spi_nor_manufacturer {
576 const char *name;
577 const struct flash_info *parts;
578 unsigned int nparts;
579 const struct spi_nor_fixups *fixups;
580 };
581
582 /**
583 * struct sfdp - SFDP data
584 * @num_dwords: number of entries in the dwords array
585 * @dwords: array of double words of the SFDP data
586 */
587 struct sfdp {
588 size_t num_dwords;
589 u32 *dwords;
590 };
591
592 /* Manufacturer drivers. */
593 extern const struct spi_nor_manufacturer spi_nor_atmel;
594 extern const struct spi_nor_manufacturer spi_nor_eon;
595 extern const struct spi_nor_manufacturer spi_nor_esmt;
596 extern const struct spi_nor_manufacturer spi_nor_everspin;
597 extern const struct spi_nor_manufacturer spi_nor_gigadevice;
598 extern const struct spi_nor_manufacturer spi_nor_intel;
599 extern const struct spi_nor_manufacturer spi_nor_issi;
600 extern const struct spi_nor_manufacturer spi_nor_macronix;
601 extern const struct spi_nor_manufacturer spi_nor_micron;
602 extern const struct spi_nor_manufacturer spi_nor_st;
603 extern const struct spi_nor_manufacturer spi_nor_spansion;
604 extern const struct spi_nor_manufacturer spi_nor_sst;
605 extern const struct spi_nor_manufacturer spi_nor_winbond;
606 extern const struct spi_nor_manufacturer spi_nor_xilinx;
607 extern const struct spi_nor_manufacturer spi_nor_xmc;
608
609 extern const struct attribute_group *spi_nor_sysfs_groups[];
610
611 void spi_nor_spimem_setup_op(const struct spi_nor *nor,
612 struct spi_mem_op *op,
613 const enum spi_nor_protocol proto);
614 int spi_nor_write_enable(struct spi_nor *nor);
615 int spi_nor_write_disable(struct spi_nor *nor);
616 int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable);
617 int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor,
618 bool enable);
619 int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable);
620 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
621 int spi_nor_wait_till_ready(struct spi_nor *nor);
622 int spi_nor_global_block_unlock(struct spi_nor *nor);
623 int spi_nor_prep_and_lock(struct spi_nor *nor);
624 void spi_nor_unlock_and_unprep(struct spi_nor *nor);
625 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
626 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
627 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
628 int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
629 enum spi_nor_protocol reg_proto);
630 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
631 int spi_nor_sr_ready(struct spi_nor *nor);
632 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
633 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
634 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
635 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
636
637 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
638 u8 *buf);
639 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
640 const u8 *buf);
641 int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
642 enum spi_nor_protocol proto);
643 int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
644 enum spi_nor_protocol proto);
645 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr);
646
647 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf);
648 int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
649 const u8 *buf);
650 int spi_nor_otp_erase_secr(struct spi_nor *nor, loff_t addr);
651 int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region);
652 int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region);
653
654 int spi_nor_hwcaps_read2cmd(u32 hwcaps);
655 int spi_nor_hwcaps_pp2cmd(u32 hwcaps);
656 u8 spi_nor_convert_3to4_read(u8 opcode);
657 void spi_nor_set_read_settings(struct spi_nor_read_command *read,
658 u8 num_mode_clocks,
659 u8 num_wait_states,
660 u8 opcode,
661 enum spi_nor_protocol proto);
662 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
663 enum spi_nor_protocol proto);
664
665 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
666 u8 opcode);
667 void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase);
668 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
669 u8 erase_mask, u64 flash_size);
670
671 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
672 const struct sfdp_parameter_header *bfpt_header,
673 const struct sfdp_bfpt *bfpt);
674
675 void spi_nor_init_default_locking_ops(struct spi_nor *nor);
676 void spi_nor_try_unlock_all(struct spi_nor *nor);
677 void spi_nor_set_mtd_locking_ops(struct spi_nor *nor);
678 void spi_nor_set_mtd_otp_ops(struct spi_nor *nor);
679
680 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
681 u8 *buf, size_t len);
682 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
683 const u8 *buf, size_t len);
684
685 int spi_nor_check_sfdp_signature(struct spi_nor *nor);
686 int spi_nor_parse_sfdp(struct spi_nor *nor);
687
mtd_to_spi_nor(struct mtd_info * mtd)688 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
689 {
690 return container_of(mtd, struct spi_nor, mtd);
691 }
692
693 /**
694 * spi_nor_needs_sfdp() - returns true if SFDP parsing is used for this flash.
695 *
696 * Return: true if SFDP parsing is needed
697 */
spi_nor_needs_sfdp(const struct spi_nor * nor)698 static inline bool spi_nor_needs_sfdp(const struct spi_nor *nor)
699 {
700 /*
701 * The flash size is one property parsed by the SFDP. We use it as an
702 * indicator whether we need SFDP parsing for a particular flash. I.e.
703 * non-legacy flash entries in flash_info will have a size of zero iff
704 * SFDP should be used.
705 */
706 return !nor->info->size;
707 }
708
709 #ifdef CONFIG_DEBUG_FS
710 void spi_nor_debugfs_register(struct spi_nor *nor);
711 void spi_nor_debugfs_shutdown(void);
712 #else
spi_nor_debugfs_register(struct spi_nor * nor)713 static inline void spi_nor_debugfs_register(struct spi_nor *nor) {}
spi_nor_debugfs_shutdown(void)714 static inline void spi_nor_debugfs_shutdown(void) {}
715 #endif
716
717 #endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
718