1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
39 */
40
41 #include "e1000.h"
42
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status {
46 struct ich8_hsfsts {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56 } hsf_status;
57 u16 regval;
58 };
59
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
69 } hsf_ctrl;
70 u16 regval;
71 };
72
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc {
75 struct ich8_flracc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80 } hsf_flregacc;
81 u16 regval;
82 };
83
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range {
86 struct ich8_pr {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
93 } range;
94 u32 regval;
95 };
96
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
__er16flash(struct e1000_hw * hw,unsigned long reg)141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142 {
143 return readw(hw->flash_address + reg);
144 }
145
__er32flash(struct e1000_hw * hw,unsigned long reg)146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147 {
148 return readl(hw->flash_address + reg);
149 }
150
__ew16flash(struct e1000_hw * hw,unsigned long reg,u16 val)151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152 {
153 writew(val, hw->flash_address + reg);
154 }
155
__ew32flash(struct e1000_hw * hw,unsigned long reg,u32 val)156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157 {
158 writel(val, hw->flash_address + reg);
159 }
160
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166 /**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
e1000_phy_is_accessible_pchlan(struct e1000_hw * hw)176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177 {
178 u16 phy_reg = 0;
179 u32 phy_id = 0;
180 s32 ret_val = 0;
181 u16 retry_count;
182 u32 mac_reg = 0;
183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
201 goto out;
202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 goto out;
206 }
207
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
210 */
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
218
219 if (ret_val)
220 return false;
221 out:
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Switching PHY interface always returns MDI error
226 * so disable retry mechanism to avoid wasting time
227 */
228 e1000e_disable_phy_retry(hw);
229
230 /* Unforce SMBus mode in PHY */
231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
234
235 e1000e_enable_phy_retry(hw);
236
237 /* Unforce SMBus mode in MAC */
238 mac_reg = er32(CTRL_EXT);
239 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
240 ew32(CTRL_EXT, mac_reg);
241 }
242 }
243
244 return true;
245 }
246
247 /**
248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
249 * @hw: pointer to the HW structure
250 *
251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
252 * used to reset the PHY to a quiescent state when necessary.
253 **/
e1000_toggle_lanphypc_pch_lpt(struct e1000_hw * hw)254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
255 {
256 u32 mac_reg;
257
258 /* Set Phy Config Counter to 50msec */
259 mac_reg = er32(FEXTNVM3);
260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
262 ew32(FEXTNVM3, mac_reg);
263
264 /* Toggle LANPHYPC Value bit */
265 mac_reg = er32(CTRL);
266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
268 ew32(CTRL, mac_reg);
269 e1e_flush();
270 usleep_range(10, 20);
271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
272 ew32(CTRL, mac_reg);
273 e1e_flush();
274
275 if (hw->mac.type < e1000_pch_lpt) {
276 msleep(50);
277 } else {
278 u16 count = 20;
279
280 do {
281 usleep_range(5000, 6000);
282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
283
284 msleep(30);
285 }
286 }
287
288 /**
289 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
290 * @hw: pointer to the HW structure
291 *
292 * Workarounds/flow necessary for PHY initialization during driver load
293 * and resume paths.
294 **/
e1000_init_phy_workarounds_pchlan(struct e1000_hw * hw)295 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
296 {
297 struct e1000_adapter *adapter = hw->adapter;
298 u32 mac_reg, fwsm = er32(FWSM);
299 s32 ret_val;
300
301 /* Gate automatic PHY configuration by hardware on managed and
302 * non-managed 82579 and newer adapters.
303 */
304 e1000_gate_hw_phy_config_ich8lan(hw, true);
305
306 /* It is not possible to be certain of the current state of ULP
307 * so forcibly disable it.
308 */
309 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
310 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
311 if (ret_val)
312 e_warn("Failed to disable ULP\n");
313
314 ret_val = hw->phy.ops.acquire(hw);
315 if (ret_val) {
316 e_dbg("Failed to initialize PHY flow\n");
317 goto out;
318 }
319
320 /* There is no guarantee that the PHY is accessible at this time
321 * so disable retry mechanism to avoid wasting time
322 */
323 e1000e_disable_phy_retry(hw);
324
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326 * inaccessible and resetting the PHY is not blocked, toggle the
327 * LANPHYPC Value bit to force the interconnect to PCIe mode.
328 */
329 switch (hw->mac.type) {
330 case e1000_pch_lpt:
331 case e1000_pch_spt:
332 case e1000_pch_cnp:
333 case e1000_pch_tgp:
334 case e1000_pch_adp:
335 case e1000_pch_mtp:
336 case e1000_pch_lnp:
337 case e1000_pch_ptp:
338 case e1000_pch_nvp:
339 if (e1000_phy_is_accessible_pchlan(hw))
340 break;
341
342 /* Before toggling LANPHYPC, see if PHY is accessible by
343 * forcing MAC to SMBus mode first.
344 */
345 mac_reg = er32(CTRL_EXT);
346 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
347 ew32(CTRL_EXT, mac_reg);
348
349 /* Wait 50 milliseconds for MAC to finish any retries
350 * that it might be trying to perform from previous
351 * attempts to acknowledge any phy read requests.
352 */
353 msleep(50);
354
355 fallthrough;
356 case e1000_pch2lan:
357 if (e1000_phy_is_accessible_pchlan(hw))
358 break;
359
360 fallthrough;
361 case e1000_pchlan:
362 if ((hw->mac.type == e1000_pchlan) &&
363 (fwsm & E1000_ICH_FWSM_FW_VALID))
364 break;
365
366 if (hw->phy.ops.check_reset_block(hw)) {
367 e_dbg("Required LANPHYPC toggle blocked by ME\n");
368 ret_val = -E1000_ERR_PHY;
369 break;
370 }
371
372 /* Toggle LANPHYPC Value bit */
373 e1000_toggle_lanphypc_pch_lpt(hw);
374 if (hw->mac.type >= e1000_pch_lpt) {
375 if (e1000_phy_is_accessible_pchlan(hw))
376 break;
377
378 /* Toggling LANPHYPC brings the PHY out of SMBus mode
379 * so ensure that the MAC is also out of SMBus mode
380 */
381 mac_reg = er32(CTRL_EXT);
382 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
383 ew32(CTRL_EXT, mac_reg);
384
385 if (e1000_phy_is_accessible_pchlan(hw))
386 break;
387
388 ret_val = -E1000_ERR_PHY;
389 }
390 break;
391 default:
392 break;
393 }
394
395 e1000e_enable_phy_retry(hw);
396
397 hw->phy.ops.release(hw);
398 if (!ret_val) {
399
400 /* Check to see if able to reset PHY. Print error if not */
401 if (hw->phy.ops.check_reset_block(hw)) {
402 e_err("Reset blocked by ME\n");
403 goto out;
404 }
405
406 /* Reset the PHY before any access to it. Doing so, ensures
407 * that the PHY is in a known good state before we read/write
408 * PHY registers. The generic reset is sufficient here,
409 * because we haven't determined the PHY type yet.
410 */
411 ret_val = e1000e_phy_hw_reset_generic(hw);
412 if (ret_val)
413 goto out;
414
415 /* On a successful reset, possibly need to wait for the PHY
416 * to quiesce to an accessible state before returning control
417 * to the calling function. If the PHY does not quiesce, then
418 * return E1000E_BLK_PHY_RESET, as this is the condition that
419 * the PHY is in.
420 */
421 ret_val = hw->phy.ops.check_reset_block(hw);
422 if (ret_val)
423 e_err("ME blocked access to PHY after reset\n");
424 }
425
426 out:
427 /* Ungate automatic PHY configuration on non-managed 82579 */
428 if ((hw->mac.type == e1000_pch2lan) &&
429 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
430 usleep_range(10000, 11000);
431 e1000_gate_hw_phy_config_ich8lan(hw, false);
432 }
433
434 return ret_val;
435 }
436
437 /**
438 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
439 * @hw: pointer to the HW structure
440 *
441 * Initialize family-specific PHY parameters and function pointers.
442 **/
e1000_init_phy_params_pchlan(struct e1000_hw * hw)443 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
444 {
445 struct e1000_phy_info *phy = &hw->phy;
446 s32 ret_val;
447
448 phy->addr = 1;
449 phy->reset_delay_us = 100;
450
451 phy->ops.set_page = e1000_set_page_igp;
452 phy->ops.read_reg = e1000_read_phy_reg_hv;
453 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
454 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
455 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
456 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
457 phy->ops.write_reg = e1000_write_phy_reg_hv;
458 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
459 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
460 phy->ops.power_up = e1000_power_up_phy_copper;
461 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
462 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
463
464 phy->id = e1000_phy_unknown;
465
466 if (hw->mac.type == e1000_pch_mtp) {
467 phy->retry_count = 2;
468 e1000e_enable_phy_retry(hw);
469 }
470
471 ret_val = e1000_init_phy_workarounds_pchlan(hw);
472 if (ret_val)
473 return ret_val;
474
475 if (phy->id == e1000_phy_unknown)
476 switch (hw->mac.type) {
477 default:
478 ret_val = e1000e_get_phy_id(hw);
479 if (ret_val)
480 return ret_val;
481 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
482 break;
483 fallthrough;
484 case e1000_pch2lan:
485 case e1000_pch_lpt:
486 case e1000_pch_spt:
487 case e1000_pch_cnp:
488 case e1000_pch_tgp:
489 case e1000_pch_adp:
490 case e1000_pch_mtp:
491 case e1000_pch_lnp:
492 case e1000_pch_ptp:
493 case e1000_pch_nvp:
494 /* In case the PHY needs to be in mdio slow mode,
495 * set slow mode and try to get the PHY id again.
496 */
497 ret_val = e1000_set_mdio_slow_mode_hv(hw);
498 if (ret_val)
499 return ret_val;
500 ret_val = e1000e_get_phy_id(hw);
501 if (ret_val)
502 return ret_val;
503 break;
504 }
505 phy->type = e1000e_get_phy_type_from_id(phy->id);
506
507 switch (phy->type) {
508 case e1000_phy_82577:
509 case e1000_phy_82579:
510 case e1000_phy_i217:
511 phy->ops.check_polarity = e1000_check_polarity_82577;
512 phy->ops.force_speed_duplex =
513 e1000_phy_force_speed_duplex_82577;
514 phy->ops.get_cable_length = e1000_get_cable_length_82577;
515 phy->ops.get_info = e1000_get_phy_info_82577;
516 phy->ops.commit = e1000e_phy_sw_reset;
517 break;
518 case e1000_phy_82578:
519 phy->ops.check_polarity = e1000_check_polarity_m88;
520 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
521 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
522 phy->ops.get_info = e1000e_get_phy_info_m88;
523 break;
524 default:
525 ret_val = -E1000_ERR_PHY;
526 break;
527 }
528
529 return ret_val;
530 }
531
532 /**
533 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
534 * @hw: pointer to the HW structure
535 *
536 * Initialize family-specific PHY parameters and function pointers.
537 **/
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)538 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
539 {
540 struct e1000_phy_info *phy = &hw->phy;
541 s32 ret_val;
542 u16 i = 0;
543
544 phy->addr = 1;
545 phy->reset_delay_us = 100;
546
547 phy->ops.power_up = e1000_power_up_phy_copper;
548 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
549
550 /* We may need to do this twice - once for IGP and if that fails,
551 * we'll set BM func pointers and try again
552 */
553 ret_val = e1000e_determine_phy_address(hw);
554 if (ret_val) {
555 phy->ops.write_reg = e1000e_write_phy_reg_bm;
556 phy->ops.read_reg = e1000e_read_phy_reg_bm;
557 ret_val = e1000e_determine_phy_address(hw);
558 if (ret_val) {
559 e_dbg("Cannot determine PHY addr. Erroring out\n");
560 return ret_val;
561 }
562 }
563
564 phy->id = 0;
565 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
566 (i++ < 100)) {
567 usleep_range(1000, 1100);
568 ret_val = e1000e_get_phy_id(hw);
569 if (ret_val)
570 return ret_val;
571 }
572
573 /* Verify phy id */
574 switch (phy->id) {
575 case IGP03E1000_E_PHY_ID:
576 phy->type = e1000_phy_igp_3;
577 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
578 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
579 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
580 phy->ops.get_info = e1000e_get_phy_info_igp;
581 phy->ops.check_polarity = e1000_check_polarity_igp;
582 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
583 break;
584 case IFE_E_PHY_ID:
585 case IFE_PLUS_E_PHY_ID:
586 case IFE_C_E_PHY_ID:
587 phy->type = e1000_phy_ife;
588 phy->autoneg_mask = E1000_ALL_NOT_GIG;
589 phy->ops.get_info = e1000_get_phy_info_ife;
590 phy->ops.check_polarity = e1000_check_polarity_ife;
591 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
592 break;
593 case BME1000_E_PHY_ID:
594 phy->type = e1000_phy_bm;
595 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
596 phy->ops.read_reg = e1000e_read_phy_reg_bm;
597 phy->ops.write_reg = e1000e_write_phy_reg_bm;
598 phy->ops.commit = e1000e_phy_sw_reset;
599 phy->ops.get_info = e1000e_get_phy_info_m88;
600 phy->ops.check_polarity = e1000_check_polarity_m88;
601 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
602 break;
603 default:
604 return -E1000_ERR_PHY;
605 }
606
607 return 0;
608 }
609
610 /**
611 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
612 * @hw: pointer to the HW structure
613 *
614 * Initialize family-specific NVM parameters and function
615 * pointers.
616 **/
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)617 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
618 {
619 struct e1000_nvm_info *nvm = &hw->nvm;
620 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
621 u32 gfpreg, sector_base_addr, sector_end_addr;
622 u16 i;
623 u32 nvm_size;
624
625 nvm->type = e1000_nvm_flash_sw;
626
627 if (hw->mac.type >= e1000_pch_spt) {
628 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
629 * STRAP register. This is because in SPT the GbE Flash region
630 * is no longer accessed through the flash registers. Instead,
631 * the mechanism has changed, and the Flash region access
632 * registers are now implemented in GbE memory space.
633 */
634 nvm->flash_base_addr = 0;
635 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
636 * NVM_SIZE_MULTIPLIER;
637 nvm->flash_bank_size = nvm_size / 2;
638 /* Adjust to word count */
639 nvm->flash_bank_size /= sizeof(u16);
640 /* Set the base address for flash register access */
641 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
642 } else {
643 /* Can't read flash registers if register set isn't mapped. */
644 if (!hw->flash_address) {
645 e_dbg("ERROR: Flash registers not mapped\n");
646 return -E1000_ERR_CONFIG;
647 }
648
649 gfpreg = er32flash(ICH_FLASH_GFPREG);
650
651 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
652 * Add 1 to sector_end_addr since this sector is included in
653 * the overall size.
654 */
655 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
656 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
657
658 /* flash_base_addr is byte-aligned */
659 nvm->flash_base_addr = sector_base_addr
660 << FLASH_SECTOR_ADDR_SHIFT;
661
662 /* find total size of the NVM, then cut in half since the total
663 * size represents two separate NVM banks.
664 */
665 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
666 << FLASH_SECTOR_ADDR_SHIFT);
667 nvm->flash_bank_size /= 2;
668 /* Adjust to word count */
669 nvm->flash_bank_size /= sizeof(u16);
670 }
671
672 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
673
674 /* Clear shadow ram */
675 for (i = 0; i < nvm->word_size; i++) {
676 dev_spec->shadow_ram[i].modified = false;
677 dev_spec->shadow_ram[i].value = 0xFFFF;
678 }
679
680 return 0;
681 }
682
683 /**
684 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
685 * @hw: pointer to the HW structure
686 *
687 * Initialize family-specific MAC parameters and function
688 * pointers.
689 **/
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)690 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
691 {
692 struct e1000_mac_info *mac = &hw->mac;
693
694 /* Set media type function pointer */
695 hw->phy.media_type = e1000_media_type_copper;
696
697 /* Set mta register count */
698 mac->mta_reg_count = 32;
699 /* Set rar entry count */
700 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
701 if (mac->type == e1000_ich8lan)
702 mac->rar_entry_count--;
703 /* FWSM register */
704 mac->has_fwsm = true;
705 /* ARC subsystem not supported */
706 mac->arc_subsystem_valid = false;
707 /* Adaptive IFS supported */
708 mac->adaptive_ifs = true;
709
710 /* LED and other operations */
711 switch (mac->type) {
712 case e1000_ich8lan:
713 case e1000_ich9lan:
714 case e1000_ich10lan:
715 /* check management mode */
716 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
717 /* ID LED init */
718 mac->ops.id_led_init = e1000e_id_led_init_generic;
719 /* blink LED */
720 mac->ops.blink_led = e1000e_blink_led_generic;
721 /* setup LED */
722 mac->ops.setup_led = e1000e_setup_led_generic;
723 /* cleanup LED */
724 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
725 /* turn on/off LED */
726 mac->ops.led_on = e1000_led_on_ich8lan;
727 mac->ops.led_off = e1000_led_off_ich8lan;
728 break;
729 case e1000_pch2lan:
730 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
731 mac->ops.rar_set = e1000_rar_set_pch2lan;
732 fallthrough;
733 case e1000_pch_lpt:
734 case e1000_pch_spt:
735 case e1000_pch_cnp:
736 case e1000_pch_tgp:
737 case e1000_pch_adp:
738 case e1000_pch_mtp:
739 case e1000_pch_lnp:
740 case e1000_pch_ptp:
741 case e1000_pch_nvp:
742 case e1000_pchlan:
743 /* check management mode */
744 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
745 /* ID LED init */
746 mac->ops.id_led_init = e1000_id_led_init_pchlan;
747 /* setup LED */
748 mac->ops.setup_led = e1000_setup_led_pchlan;
749 /* cleanup LED */
750 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
751 /* turn on/off LED */
752 mac->ops.led_on = e1000_led_on_pchlan;
753 mac->ops.led_off = e1000_led_off_pchlan;
754 break;
755 default:
756 break;
757 }
758
759 if (mac->type >= e1000_pch_lpt) {
760 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
761 mac->ops.rar_set = e1000_rar_set_pch_lpt;
762 mac->ops.setup_physical_interface =
763 e1000_setup_copper_link_pch_lpt;
764 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
765 }
766
767 /* Enable PCS Lock-loss workaround for ICH8 */
768 if (mac->type == e1000_ich8lan)
769 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
770
771 return 0;
772 }
773
774 /**
775 * __e1000_access_emi_reg_locked - Read/write EMI register
776 * @hw: pointer to the HW structure
777 * @address: EMI address to program
778 * @data: pointer to value to read/write from/to the EMI address
779 * @read: boolean flag to indicate read or write
780 *
781 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
782 **/
__e1000_access_emi_reg_locked(struct e1000_hw * hw,u16 address,u16 * data,bool read)783 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
784 u16 *data, bool read)
785 {
786 s32 ret_val;
787
788 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
789 if (ret_val)
790 return ret_val;
791
792 if (read)
793 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
794 else
795 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
796
797 return ret_val;
798 }
799
800 /**
801 * e1000_read_emi_reg_locked - Read Extended Management Interface register
802 * @hw: pointer to the HW structure
803 * @addr: EMI address to program
804 * @data: value to be read from the EMI address
805 *
806 * Assumes the SW/FW/HW Semaphore is already acquired.
807 **/
e1000_read_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 * data)808 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
809 {
810 return __e1000_access_emi_reg_locked(hw, addr, data, true);
811 }
812
813 /**
814 * e1000_write_emi_reg_locked - Write Extended Management Interface register
815 * @hw: pointer to the HW structure
816 * @addr: EMI address to program
817 * @data: value to be written to the EMI address
818 *
819 * Assumes the SW/FW/HW Semaphore is already acquired.
820 **/
e1000_write_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 data)821 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
822 {
823 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
824 }
825
826 /**
827 * e1000_set_eee_pchlan - Enable/disable EEE support
828 * @hw: pointer to the HW structure
829 *
830 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
831 * the link and the EEE capabilities of the link partner. The LPI Control
832 * register bits will remain set only if/when link is up.
833 *
834 * EEE LPI must not be asserted earlier than one second after link is up.
835 * On 82579, EEE LPI should not be enabled until such time otherwise there
836 * can be link issues with some switches. Other devices can have EEE LPI
837 * enabled immediately upon link up since they have a timer in hardware which
838 * prevents LPI from being asserted too early.
839 **/
e1000_set_eee_pchlan(struct e1000_hw * hw)840 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
841 {
842 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
843 s32 ret_val;
844 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
845
846 switch (hw->phy.type) {
847 case e1000_phy_82579:
848 lpa = I82579_EEE_LP_ABILITY;
849 pcs_status = I82579_EEE_PCS_STATUS;
850 adv_addr = I82579_EEE_ADVERTISEMENT;
851 break;
852 case e1000_phy_i217:
853 lpa = I217_EEE_LP_ABILITY;
854 pcs_status = I217_EEE_PCS_STATUS;
855 adv_addr = I217_EEE_ADVERTISEMENT;
856 break;
857 default:
858 return 0;
859 }
860
861 ret_val = hw->phy.ops.acquire(hw);
862 if (ret_val)
863 return ret_val;
864
865 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
866 if (ret_val)
867 goto release;
868
869 /* Clear bits that enable EEE in various speeds */
870 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
871
872 /* Enable EEE if not disabled by user */
873 if (!dev_spec->eee_disable) {
874 /* Save off link partner's EEE ability */
875 ret_val = e1000_read_emi_reg_locked(hw, lpa,
876 &dev_spec->eee_lp_ability);
877 if (ret_val)
878 goto release;
879
880 /* Read EEE advertisement */
881 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
882 if (ret_val)
883 goto release;
884
885 /* Enable EEE only for speeds in which the link partner is
886 * EEE capable and for which we advertise EEE.
887 */
888 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
889 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
890
891 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
892 e1e_rphy_locked(hw, MII_LPA, &data);
893 if (data & LPA_100FULL)
894 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
895 else
896 /* EEE is not supported in 100Half, so ignore
897 * partner's EEE in 100 ability if full-duplex
898 * is not advertised.
899 */
900 dev_spec->eee_lp_ability &=
901 ~I82579_EEE_100_SUPPORTED;
902 }
903 }
904
905 if (hw->phy.type == e1000_phy_82579) {
906 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
907 &data);
908 if (ret_val)
909 goto release;
910
911 data &= ~I82579_LPI_100_PLL_SHUT;
912 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
913 data);
914 }
915
916 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
917 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
918 if (ret_val)
919 goto release;
920
921 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
922 release:
923 hw->phy.ops.release(hw);
924
925 return ret_val;
926 }
927
928 /**
929 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
930 * @hw: pointer to the HW structure
931 * @link: link up bool flag
932 *
933 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
934 * preventing further DMA write requests. Workaround the issue by disabling
935 * the de-assertion of the clock request when in 1Gpbs mode.
936 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
937 * speeds in order to avoid Tx hangs.
938 **/
e1000_k1_workaround_lpt_lp(struct e1000_hw * hw,bool link)939 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
940 {
941 u32 fextnvm6 = er32(FEXTNVM6);
942 u32 status = er32(STATUS);
943 s32 ret_val = 0;
944 u16 reg;
945
946 if (link && (status & E1000_STATUS_SPEED_1000)) {
947 ret_val = hw->phy.ops.acquire(hw);
948 if (ret_val)
949 return ret_val;
950
951 ret_val =
952 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
953 ®);
954 if (ret_val)
955 goto release;
956
957 ret_val =
958 e1000e_write_kmrn_reg_locked(hw,
959 E1000_KMRNCTRLSTA_K1_CONFIG,
960 reg &
961 ~E1000_KMRNCTRLSTA_K1_ENABLE);
962 if (ret_val)
963 goto release;
964
965 usleep_range(10, 20);
966
967 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
968
969 ret_val =
970 e1000e_write_kmrn_reg_locked(hw,
971 E1000_KMRNCTRLSTA_K1_CONFIG,
972 reg);
973 release:
974 hw->phy.ops.release(hw);
975 } else {
976 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
977 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
978
979 if ((hw->phy.revision > 5) || !link ||
980 ((status & E1000_STATUS_SPEED_100) &&
981 (status & E1000_STATUS_FD)))
982 goto update_fextnvm6;
983
984 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
985 if (ret_val)
986 return ret_val;
987
988 /* Clear link status transmit timeout */
989 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
990
991 if (status & E1000_STATUS_SPEED_100) {
992 /* Set inband Tx timeout to 5x10us for 100Half */
993 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
994
995 /* Do not extend the K1 entry latency for 100Half */
996 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
997 } else {
998 /* Set inband Tx timeout to 50x10us for 10Full/Half */
999 reg |= 50 <<
1000 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1001
1002 /* Extend the K1 entry latency for 10 Mbps */
1003 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1004 }
1005
1006 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
1007 if (ret_val)
1008 return ret_val;
1009
1010 update_fextnvm6:
1011 ew32(FEXTNVM6, fextnvm6);
1012 }
1013
1014 return ret_val;
1015 }
1016
1017 /**
1018 * e1000_platform_pm_pch_lpt - Set platform power management values
1019 * @hw: pointer to the HW structure
1020 * @link: bool indicating link status
1021 *
1022 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1023 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1024 * when link is up (which must not exceed the maximum latency supported
1025 * by the platform), otherwise specify there is no LTR requirement.
1026 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1027 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1028 * Capability register set, on this device LTR is set by writing the
1029 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1030 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1031 * message to the PMC.
1032 **/
e1000_platform_pm_pch_lpt(struct e1000_hw * hw,bool link)1033 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1034 {
1035 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1036 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1037 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1038 u32 lat_enc_d = 0; /* latency decoded */
1039 u16 lat_enc = 0; /* latency encoded */
1040
1041 if (link) {
1042 u16 speed, duplex, scale = 0;
1043 u16 max_snoop, max_nosnoop;
1044 u16 max_ltr_enc; /* max LTR latency encoded */
1045 u64 value;
1046 u32 rxa;
1047
1048 if (!hw->adapter->max_frame_size) {
1049 e_dbg("max_frame_size not set.\n");
1050 return -E1000_ERR_CONFIG;
1051 }
1052
1053 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1054 if (!speed) {
1055 e_dbg("Speed not set.\n");
1056 return -E1000_ERR_CONFIG;
1057 }
1058
1059 /* Rx Packet Buffer Allocation size (KB) */
1060 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1061
1062 /* Determine the maximum latency tolerated by the device.
1063 *
1064 * Per the PCIe spec, the tolerated latencies are encoded as
1065 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1066 * a 10-bit value (0-1023) to provide a range from 1 ns to
1067 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1068 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1069 */
1070 rxa *= 512;
1071 value = (rxa > hw->adapter->max_frame_size) ?
1072 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1073 0;
1074
1075 while (value > PCI_LTR_VALUE_MASK) {
1076 scale++;
1077 value = DIV_ROUND_UP(value, BIT(5));
1078 }
1079 if (scale > E1000_LTRV_SCALE_MAX) {
1080 e_dbg("Invalid LTR latency scale %d\n", scale);
1081 return -E1000_ERR_CONFIG;
1082 }
1083 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1084
1085 /* Determine the maximum latency tolerated by the platform */
1086 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1087 &max_snoop);
1088 pci_read_config_word(hw->adapter->pdev,
1089 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1090 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1091
1092 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1093 (1U << (E1000_LTRV_SCALE_FACTOR *
1094 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc)));
1095
1096 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1097 (1U << (E1000_LTRV_SCALE_FACTOR *
1098 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc)));
1099
1100 if (lat_enc_d > max_ltr_enc_d)
1101 lat_enc = max_ltr_enc;
1102 }
1103
1104 /* Set Snoop and No-Snoop latencies the same */
1105 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1106 ew32(LTRV, reg);
1107
1108 return 0;
1109 }
1110
1111 /**
1112 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1113 * @hw: pointer to the HW structure
1114 * @to_sx: boolean indicating a system power state transition to Sx
1115 *
1116 * When link is down, configure ULP mode to significantly reduce the power
1117 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1118 * ME firmware to start the ULP configuration. If not on an ME enabled
1119 * system, configure the ULP mode by software.
1120 */
e1000_enable_ulp_lpt_lp(struct e1000_hw * hw,bool to_sx)1121 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1122 {
1123 u32 mac_reg;
1124 s32 ret_val = 0;
1125 u16 phy_reg;
1126 u16 oem_reg = 0;
1127
1128 if ((hw->mac.type < e1000_pch_lpt) ||
1129 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1130 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1131 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1132 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1133 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1134 return 0;
1135
1136 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1137 /* Request ME configure ULP mode in the PHY */
1138 mac_reg = er32(H2ME);
1139 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1140 ew32(H2ME, mac_reg);
1141
1142 goto out;
1143 }
1144
1145 if (!to_sx) {
1146 int i = 0;
1147
1148 /* Poll up to 5 seconds for Cable Disconnected indication */
1149 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1150 /* Bail if link is re-acquired */
1151 if (er32(STATUS) & E1000_STATUS_LU)
1152 return -E1000_ERR_PHY;
1153
1154 if (i++ == 100)
1155 break;
1156
1157 msleep(50);
1158 }
1159 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1160 (er32(FEXT) &
1161 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1162 }
1163
1164 ret_val = hw->phy.ops.acquire(hw);
1165 if (ret_val)
1166 goto out;
1167
1168 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1169 * LPLU and disable Gig speed when entering ULP
1170 */
1171 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1172 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1173 &oem_reg);
1174 if (ret_val)
1175 goto release;
1176
1177 phy_reg = oem_reg;
1178 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1179
1180 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1181 phy_reg);
1182
1183 if (ret_val)
1184 goto release;
1185 }
1186
1187 /* Set Inband ULP Exit, Reset to SMBus mode and
1188 * Disable SMBus Release on PERST# in PHY
1189 */
1190 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1191 if (ret_val)
1192 goto release;
1193 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1195 if (to_sx) {
1196 if (er32(WUFC) & E1000_WUFC_LNKC)
1197 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1198 else
1199 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200
1201 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1203 } else {
1204 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1207 }
1208 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1209
1210 /* Set Disable SMBus Release on PERST# in MAC */
1211 mac_reg = er32(FEXTNVM7);
1212 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213 ew32(FEXTNVM7, mac_reg);
1214
1215 /* Commit ULP changes in PHY by starting auto ULP configuration */
1216 phy_reg |= I218_ULP_CONFIG1_START;
1217 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1218
1219 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1220 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1221 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1222 oem_reg);
1223 if (ret_val)
1224 goto release;
1225 }
1226
1227 release:
1228 /* Switching PHY interface always returns MDI error
1229 * so disable retry mechanism to avoid wasting time
1230 */
1231 e1000e_disable_phy_retry(hw);
1232
1233 /* Force SMBus mode in PHY */
1234 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1235 if (ret_val) {
1236 e1000e_enable_phy_retry(hw);
1237 hw->phy.ops.release(hw);
1238 goto out;
1239 }
1240 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1241 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1242
1243 e1000e_enable_phy_retry(hw);
1244
1245 /* Force SMBus mode in MAC */
1246 mac_reg = er32(CTRL_EXT);
1247 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1248 ew32(CTRL_EXT, mac_reg);
1249
1250 hw->phy.ops.release(hw);
1251 out:
1252 if (ret_val)
1253 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1254 else
1255 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1256
1257 return ret_val;
1258 }
1259
1260 /**
1261 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1262 * @hw: pointer to the HW structure
1263 * @force: boolean indicating whether or not to force disabling ULP
1264 *
1265 * Un-configure ULP mode when link is up, the system is transitioned from
1266 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1267 * system, poll for an indication from ME that ULP has been un-configured.
1268 * If not on an ME enabled system, un-configure the ULP mode by software.
1269 *
1270 * During nominal operation, this function is called when link is acquired
1271 * to disable ULP mode (force=false); otherwise, for example when unloading
1272 * the driver or during Sx->S0 transitions, this is called with force=true
1273 * to forcibly disable ULP.
1274 */
e1000_disable_ulp_lpt_lp(struct e1000_hw * hw,bool force)1275 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1276 {
1277 s32 ret_val = 0;
1278 u32 mac_reg;
1279 u16 phy_reg;
1280 int i = 0;
1281
1282 if ((hw->mac.type < e1000_pch_lpt) ||
1283 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1284 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1285 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1286 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1287 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1288 return 0;
1289
1290 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1291 struct e1000_adapter *adapter = hw->adapter;
1292 bool firmware_bug = false;
1293
1294 if (force) {
1295 /* Request ME un-configure ULP mode in the PHY */
1296 mac_reg = er32(H2ME);
1297 mac_reg &= ~E1000_H2ME_ULP;
1298 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1299 ew32(H2ME, mac_reg);
1300 }
1301
1302 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1303 * If this takes more than 1 second, show a warning indicating a
1304 * firmware bug
1305 */
1306 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1307 if (i++ == 250) {
1308 ret_val = -E1000_ERR_PHY;
1309 goto out;
1310 }
1311 if (i > 100 && !firmware_bug)
1312 firmware_bug = true;
1313
1314 usleep_range(10000, 11000);
1315 }
1316 if (firmware_bug)
1317 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1318 i * 10);
1319 else
1320 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1321 i * 10);
1322
1323 if (force) {
1324 mac_reg = er32(H2ME);
1325 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1326 ew32(H2ME, mac_reg);
1327 } else {
1328 /* Clear H2ME.ULP after ME ULP configuration */
1329 mac_reg = er32(H2ME);
1330 mac_reg &= ~E1000_H2ME_ULP;
1331 ew32(H2ME, mac_reg);
1332 }
1333
1334 goto out;
1335 }
1336
1337 ret_val = hw->phy.ops.acquire(hw);
1338 if (ret_val)
1339 goto out;
1340
1341 if (force)
1342 /* Toggle LANPHYPC Value bit */
1343 e1000_toggle_lanphypc_pch_lpt(hw);
1344
1345 /* Switching PHY interface always returns MDI error
1346 * so disable retry mechanism to avoid wasting time
1347 */
1348 e1000e_disable_phy_retry(hw);
1349
1350 /* Unforce SMBus mode in PHY */
1351 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1352 if (ret_val) {
1353 /* The MAC might be in PCIe mode, so temporarily force to
1354 * SMBus mode in order to access the PHY.
1355 */
1356 mac_reg = er32(CTRL_EXT);
1357 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1358 ew32(CTRL_EXT, mac_reg);
1359
1360 msleep(50);
1361
1362 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1363 &phy_reg);
1364 if (ret_val)
1365 goto release;
1366 }
1367 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1368 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1369
1370 e1000e_enable_phy_retry(hw);
1371
1372 /* Unforce SMBus mode in MAC */
1373 mac_reg = er32(CTRL_EXT);
1374 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1375 ew32(CTRL_EXT, mac_reg);
1376
1377 /* When ULP mode was previously entered, K1 was disabled by the
1378 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1379 */
1380 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1381 if (ret_val)
1382 goto release;
1383 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1384 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1385
1386 /* Clear ULP enabled configuration */
1387 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1388 if (ret_val)
1389 goto release;
1390 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1391 I218_ULP_CONFIG1_STICKY_ULP |
1392 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1393 I218_ULP_CONFIG1_WOL_HOST |
1394 I218_ULP_CONFIG1_INBAND_EXIT |
1395 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1396 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1397 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1398 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1399
1400 /* Commit ULP changes by starting auto ULP configuration */
1401 phy_reg |= I218_ULP_CONFIG1_START;
1402 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1403
1404 /* Clear Disable SMBus Release on PERST# in MAC */
1405 mac_reg = er32(FEXTNVM7);
1406 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1407 ew32(FEXTNVM7, mac_reg);
1408
1409 release:
1410 hw->phy.ops.release(hw);
1411 if (force) {
1412 e1000_phy_hw_reset(hw);
1413 msleep(50);
1414 }
1415 out:
1416 if (ret_val)
1417 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1418 else
1419 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1420
1421 return ret_val;
1422 }
1423
1424 /**
1425 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1426 * @hw: pointer to the HW structure
1427 *
1428 * Checks to see of the link status of the hardware has changed. If a
1429 * change in link status has been detected, then we read the PHY registers
1430 * to get the current speed/duplex if link exists.
1431 **/
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)1432 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1433 {
1434 struct e1000_mac_info *mac = &hw->mac;
1435 s32 ret_val, tipg_reg = 0;
1436 u16 emi_addr, emi_val = 0;
1437 bool link;
1438 u16 phy_reg;
1439
1440 /* We only want to go out to the PHY registers to see if Auto-Neg
1441 * has completed and/or if our link status has changed. The
1442 * get_link_status flag is set upon receiving a Link Status
1443 * Change or Rx Sequence Error interrupt.
1444 */
1445 if (!mac->get_link_status)
1446 return 0;
1447 mac->get_link_status = false;
1448
1449 /* First we want to see if the MII Status Register reports
1450 * link. If so, then we want to get the current speed/duplex
1451 * of the PHY.
1452 */
1453 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1454 if (ret_val)
1455 goto out;
1456
1457 if (hw->mac.type == e1000_pchlan) {
1458 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1459 if (ret_val)
1460 goto out;
1461 }
1462
1463 /* When connected at 10Mbps half-duplex, some parts are excessively
1464 * aggressive resulting in many collisions. To avoid this, increase
1465 * the IPG and reduce Rx latency in the PHY.
1466 */
1467 if ((hw->mac.type >= e1000_pch2lan) && link) {
1468 u16 speed, duplex;
1469
1470 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1471 tipg_reg = er32(TIPG);
1472 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1473
1474 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1475 tipg_reg |= 0xFF;
1476 /* Reduce Rx latency in analog PHY */
1477 emi_val = 0;
1478 } else if (hw->mac.type >= e1000_pch_spt &&
1479 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1480 tipg_reg |= 0xC;
1481 emi_val = 1;
1482 } else {
1483
1484 /* Roll back the default values */
1485 tipg_reg |= 0x08;
1486 emi_val = 1;
1487 }
1488
1489 ew32(TIPG, tipg_reg);
1490
1491 ret_val = hw->phy.ops.acquire(hw);
1492 if (ret_val)
1493 goto out;
1494
1495 if (hw->mac.type == e1000_pch2lan)
1496 emi_addr = I82579_RX_CONFIG;
1497 else
1498 emi_addr = I217_RX_CONFIG;
1499 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1500
1501 if (hw->mac.type >= e1000_pch_lpt) {
1502 u16 phy_reg;
1503
1504 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1505 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1506 if (speed == SPEED_100 || speed == SPEED_10)
1507 phy_reg |= 0x3E8;
1508 else
1509 phy_reg |= 0xFA;
1510 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1511
1512 if (speed == SPEED_1000) {
1513 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1514 &phy_reg);
1515
1516 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1517
1518 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1519 phy_reg);
1520 }
1521 }
1522 hw->phy.ops.release(hw);
1523
1524 if (ret_val)
1525 goto out;
1526
1527 if (hw->mac.type >= e1000_pch_spt) {
1528 u16 data;
1529 u16 ptr_gap;
1530
1531 if (speed == SPEED_1000) {
1532 ret_val = hw->phy.ops.acquire(hw);
1533 if (ret_val)
1534 goto out;
1535
1536 ret_val = e1e_rphy_locked(hw,
1537 PHY_REG(776, 20),
1538 &data);
1539 if (ret_val) {
1540 hw->phy.ops.release(hw);
1541 goto out;
1542 }
1543
1544 ptr_gap = (data & (0x3FF << 2)) >> 2;
1545 if (ptr_gap < 0x18) {
1546 data &= ~(0x3FF << 2);
1547 data |= (0x18 << 2);
1548 ret_val =
1549 e1e_wphy_locked(hw,
1550 PHY_REG(776, 20),
1551 data);
1552 }
1553 hw->phy.ops.release(hw);
1554 if (ret_val)
1555 goto out;
1556 } else {
1557 ret_val = hw->phy.ops.acquire(hw);
1558 if (ret_val)
1559 goto out;
1560
1561 ret_val = e1e_wphy_locked(hw,
1562 PHY_REG(776, 20),
1563 0xC023);
1564 hw->phy.ops.release(hw);
1565 if (ret_val)
1566 goto out;
1567
1568 }
1569 }
1570 }
1571
1572 /* I217 Packet Loss issue:
1573 * ensure that FEXTNVM4 Beacon Duration is set correctly
1574 * on power up.
1575 * Set the Beacon Duration for I217 to 8 usec
1576 */
1577 if (hw->mac.type >= e1000_pch_lpt) {
1578 u32 mac_reg;
1579
1580 mac_reg = er32(FEXTNVM4);
1581 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1582 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1583 ew32(FEXTNVM4, mac_reg);
1584 }
1585
1586 /* Work-around I218 hang issue */
1587 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1588 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1589 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1590 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1591 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1592 if (ret_val)
1593 goto out;
1594 }
1595 if (hw->mac.type >= e1000_pch_lpt) {
1596 /* Set platform power management values for
1597 * Latency Tolerance Reporting (LTR)
1598 */
1599 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1600 if (ret_val)
1601 goto out;
1602 }
1603
1604 /* Clear link partner's EEE ability */
1605 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1606
1607 if (hw->mac.type >= e1000_pch_lpt) {
1608 u32 fextnvm6 = er32(FEXTNVM6);
1609
1610 if (hw->mac.type == e1000_pch_spt) {
1611 /* FEXTNVM6 K1-off workaround - for SPT only */
1612 u32 pcieanacfg = er32(PCIEANACFG);
1613
1614 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1615 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1616 else
1617 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1618 }
1619
1620 ew32(FEXTNVM6, fextnvm6);
1621 }
1622
1623 if (!link)
1624 goto out;
1625
1626 switch (hw->mac.type) {
1627 case e1000_pch2lan:
1628 ret_val = e1000_k1_workaround_lv(hw);
1629 if (ret_val)
1630 return ret_val;
1631 fallthrough;
1632 case e1000_pchlan:
1633 if (hw->phy.type == e1000_phy_82578) {
1634 ret_val = e1000_link_stall_workaround_hv(hw);
1635 if (ret_val)
1636 return ret_val;
1637 }
1638
1639 /* Workaround for PCHx parts in half-duplex:
1640 * Set the number of preambles removed from the packet
1641 * when it is passed from the PHY to the MAC to prevent
1642 * the MAC from misinterpreting the packet type.
1643 */
1644 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1645 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1646
1647 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1648 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1649
1650 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1651 break;
1652 default:
1653 break;
1654 }
1655
1656 /* Check if there was DownShift, must be checked
1657 * immediately after link-up
1658 */
1659 e1000e_check_downshift(hw);
1660
1661 /* Enable/Disable EEE after link up */
1662 if (hw->phy.type > e1000_phy_82579) {
1663 ret_val = e1000_set_eee_pchlan(hw);
1664 if (ret_val)
1665 return ret_val;
1666 }
1667
1668 /* If we are forcing speed/duplex, then we simply return since
1669 * we have already determined whether we have link or not.
1670 */
1671 if (!mac->autoneg)
1672 return -E1000_ERR_CONFIG;
1673
1674 /* Auto-Neg is enabled. Auto Speed Detection takes care
1675 * of MAC speed/duplex configuration. So we only need to
1676 * configure Collision Distance in the MAC.
1677 */
1678 mac->ops.config_collision_dist(hw);
1679
1680 /* Configure Flow Control now that Auto-Neg has completed.
1681 * First, we need to restore the desired flow control
1682 * settings because we may have had to re-autoneg with a
1683 * different link partner.
1684 */
1685 ret_val = e1000e_config_fc_after_link_up(hw);
1686 if (ret_val)
1687 e_dbg("Error configuring flow control\n");
1688
1689 return ret_val;
1690
1691 out:
1692 mac->get_link_status = true;
1693 return ret_val;
1694 }
1695
e1000_get_variants_ich8lan(struct e1000_adapter * adapter)1696 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1697 {
1698 struct e1000_hw *hw = &adapter->hw;
1699 s32 rc;
1700
1701 rc = e1000_init_mac_params_ich8lan(hw);
1702 if (rc)
1703 return rc;
1704
1705 rc = e1000_init_nvm_params_ich8lan(hw);
1706 if (rc)
1707 return rc;
1708
1709 switch (hw->mac.type) {
1710 case e1000_ich8lan:
1711 case e1000_ich9lan:
1712 case e1000_ich10lan:
1713 rc = e1000_init_phy_params_ich8lan(hw);
1714 break;
1715 case e1000_pchlan:
1716 case e1000_pch2lan:
1717 case e1000_pch_lpt:
1718 case e1000_pch_spt:
1719 case e1000_pch_cnp:
1720 case e1000_pch_tgp:
1721 case e1000_pch_adp:
1722 case e1000_pch_mtp:
1723 case e1000_pch_lnp:
1724 case e1000_pch_ptp:
1725 case e1000_pch_nvp:
1726 rc = e1000_init_phy_params_pchlan(hw);
1727 break;
1728 default:
1729 break;
1730 }
1731 if (rc)
1732 return rc;
1733
1734 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1735 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1736 */
1737 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1738 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1739 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1740 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1741 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1742
1743 hw->mac.ops.blink_led = NULL;
1744 }
1745
1746 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1747 (adapter->hw.phy.type != e1000_phy_ife))
1748 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1749
1750 /* Enable workaround for 82579 w/ ME enabled */
1751 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1752 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1753 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1754
1755 return 0;
1756 }
1757
1758 static DEFINE_MUTEX(nvm_mutex);
1759
1760 /**
1761 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1762 * @hw: pointer to the HW structure
1763 *
1764 * Acquires the mutex for performing NVM operations.
1765 **/
e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused * hw)1766 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1767 {
1768 mutex_lock(&nvm_mutex);
1769
1770 return 0;
1771 }
1772
1773 /**
1774 * e1000_release_nvm_ich8lan - Release NVM mutex
1775 * @hw: pointer to the HW structure
1776 *
1777 * Releases the mutex used while performing NVM operations.
1778 **/
e1000_release_nvm_ich8lan(struct e1000_hw __always_unused * hw)1779 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1780 {
1781 mutex_unlock(&nvm_mutex);
1782 }
1783
1784 /**
1785 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1786 * @hw: pointer to the HW structure
1787 *
1788 * Acquires the software control flag for performing PHY and select
1789 * MAC CSR accesses.
1790 **/
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)1791 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1792 {
1793 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1794 s32 ret_val = 0;
1795
1796 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1797 &hw->adapter->state)) {
1798 e_dbg("contention for Phy access\n");
1799 return -E1000_ERR_PHY;
1800 }
1801
1802 while (timeout) {
1803 extcnf_ctrl = er32(EXTCNF_CTRL);
1804 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1805 break;
1806
1807 mdelay(1);
1808 timeout--;
1809 }
1810
1811 if (!timeout) {
1812 e_dbg("SW has already locked the resource.\n");
1813 ret_val = -E1000_ERR_CONFIG;
1814 goto out;
1815 }
1816
1817 timeout = SW_FLAG_TIMEOUT;
1818
1819 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1820 ew32(EXTCNF_CTRL, extcnf_ctrl);
1821
1822 while (timeout) {
1823 extcnf_ctrl = er32(EXTCNF_CTRL);
1824 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1825 break;
1826
1827 mdelay(1);
1828 timeout--;
1829 }
1830
1831 if (!timeout) {
1832 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1833 er32(FWSM), extcnf_ctrl);
1834 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1835 ew32(EXTCNF_CTRL, extcnf_ctrl);
1836 ret_val = -E1000_ERR_CONFIG;
1837 goto out;
1838 }
1839
1840 out:
1841 if (ret_val)
1842 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1843
1844 return ret_val;
1845 }
1846
1847 /**
1848 * e1000_release_swflag_ich8lan - Release software control flag
1849 * @hw: pointer to the HW structure
1850 *
1851 * Releases the software control flag for performing PHY and select
1852 * MAC CSR accesses.
1853 **/
e1000_release_swflag_ich8lan(struct e1000_hw * hw)1854 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1855 {
1856 u32 extcnf_ctrl;
1857
1858 extcnf_ctrl = er32(EXTCNF_CTRL);
1859
1860 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1861 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1862 ew32(EXTCNF_CTRL, extcnf_ctrl);
1863 } else {
1864 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1865 }
1866
1867 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1868 }
1869
1870 /**
1871 * e1000_check_mng_mode_ich8lan - Checks management mode
1872 * @hw: pointer to the HW structure
1873 *
1874 * This checks if the adapter has any manageability enabled.
1875 * This is a function pointer entry point only called by read/write
1876 * routines for the PHY and NVM parts.
1877 **/
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)1878 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1879 {
1880 u32 fwsm;
1881
1882 fwsm = er32(FWSM);
1883 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1884 ((fwsm & E1000_FWSM_MODE_MASK) ==
1885 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1886 }
1887
1888 /**
1889 * e1000_check_mng_mode_pchlan - Checks management mode
1890 * @hw: pointer to the HW structure
1891 *
1892 * This checks if the adapter has iAMT enabled.
1893 * This is a function pointer entry point only called by read/write
1894 * routines for the PHY and NVM parts.
1895 **/
e1000_check_mng_mode_pchlan(struct e1000_hw * hw)1896 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1897 {
1898 u32 fwsm;
1899
1900 fwsm = er32(FWSM);
1901 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1902 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1903 }
1904
1905 /**
1906 * e1000_rar_set_pch2lan - Set receive address register
1907 * @hw: pointer to the HW structure
1908 * @addr: pointer to the receive address
1909 * @index: receive address array register
1910 *
1911 * Sets the receive address array register at index to the address passed
1912 * in by addr. For 82579, RAR[0] is the base address register that is to
1913 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1914 * Use SHRA[0-3] in place of those reserved for ME.
1915 **/
e1000_rar_set_pch2lan(struct e1000_hw * hw,u8 * addr,u32 index)1916 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1917 {
1918 u32 rar_low, rar_high;
1919
1920 /* HW expects these in little endian so we reverse the byte order
1921 * from network order (big endian) to little endian
1922 */
1923 rar_low = ((u32)addr[0] |
1924 ((u32)addr[1] << 8) |
1925 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1926
1927 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1928
1929 /* If MAC address zero, no need to set the AV bit */
1930 if (rar_low || rar_high)
1931 rar_high |= E1000_RAH_AV;
1932
1933 if (index == 0) {
1934 ew32(RAL(index), rar_low);
1935 e1e_flush();
1936 ew32(RAH(index), rar_high);
1937 e1e_flush();
1938 return 0;
1939 }
1940
1941 /* RAR[1-6] are owned by manageability. Skip those and program the
1942 * next address into the SHRA register array.
1943 */
1944 if (index < (u32)(hw->mac.rar_entry_count)) {
1945 s32 ret_val;
1946
1947 ret_val = e1000_acquire_swflag_ich8lan(hw);
1948 if (ret_val)
1949 goto out;
1950
1951 ew32(SHRAL(index - 1), rar_low);
1952 e1e_flush();
1953 ew32(SHRAH(index - 1), rar_high);
1954 e1e_flush();
1955
1956 e1000_release_swflag_ich8lan(hw);
1957
1958 /* verify the register updates */
1959 if ((er32(SHRAL(index - 1)) == rar_low) &&
1960 (er32(SHRAH(index - 1)) == rar_high))
1961 return 0;
1962
1963 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1964 (index - 1), er32(FWSM));
1965 }
1966
1967 out:
1968 e_dbg("Failed to write receive address at index %d\n", index);
1969 return -E1000_ERR_CONFIG;
1970 }
1971
1972 /**
1973 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1974 * @hw: pointer to the HW structure
1975 *
1976 * Get the number of available receive registers that the Host can
1977 * program. SHRA[0-10] are the shared receive address registers
1978 * that are shared between the Host and manageability engine (ME).
1979 * ME can reserve any number of addresses and the host needs to be
1980 * able to tell how many available registers it has access to.
1981 **/
e1000_rar_get_count_pch_lpt(struct e1000_hw * hw)1982 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1983 {
1984 u32 wlock_mac;
1985 u32 num_entries;
1986
1987 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1988 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1989
1990 switch (wlock_mac) {
1991 case 0:
1992 /* All SHRA[0..10] and RAR[0] available */
1993 num_entries = hw->mac.rar_entry_count;
1994 break;
1995 case 1:
1996 /* Only RAR[0] available */
1997 num_entries = 1;
1998 break;
1999 default:
2000 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
2001 num_entries = wlock_mac + 1;
2002 break;
2003 }
2004
2005 return num_entries;
2006 }
2007
2008 /**
2009 * e1000_rar_set_pch_lpt - Set receive address registers
2010 * @hw: pointer to the HW structure
2011 * @addr: pointer to the receive address
2012 * @index: receive address array register
2013 *
2014 * Sets the receive address register array at index to the address passed
2015 * in by addr. For LPT, RAR[0] is the base address register that is to
2016 * contain the MAC address. SHRA[0-10] are the shared receive address
2017 * registers that are shared between the Host and manageability engine (ME).
2018 **/
e1000_rar_set_pch_lpt(struct e1000_hw * hw,u8 * addr,u32 index)2019 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2020 {
2021 u32 rar_low, rar_high;
2022 u32 wlock_mac;
2023
2024 /* HW expects these in little endian so we reverse the byte order
2025 * from network order (big endian) to little endian
2026 */
2027 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
2028 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
2029
2030 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
2031
2032 /* If MAC address zero, no need to set the AV bit */
2033 if (rar_low || rar_high)
2034 rar_high |= E1000_RAH_AV;
2035
2036 if (index == 0) {
2037 ew32(RAL(index), rar_low);
2038 e1e_flush();
2039 ew32(RAH(index), rar_high);
2040 e1e_flush();
2041 return 0;
2042 }
2043
2044 /* The manageability engine (ME) can lock certain SHRAR registers that
2045 * it is using - those registers are unavailable for use.
2046 */
2047 if (index < hw->mac.rar_entry_count) {
2048 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2049 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2050
2051 /* Check if all SHRAR registers are locked */
2052 if (wlock_mac == 1)
2053 goto out;
2054
2055 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2056 s32 ret_val;
2057
2058 ret_val = e1000_acquire_swflag_ich8lan(hw);
2059
2060 if (ret_val)
2061 goto out;
2062
2063 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2064 e1e_flush();
2065 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2066 e1e_flush();
2067
2068 e1000_release_swflag_ich8lan(hw);
2069
2070 /* verify the register updates */
2071 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2072 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2073 return 0;
2074 }
2075 }
2076
2077 out:
2078 e_dbg("Failed to write receive address at index %d\n", index);
2079 return -E1000_ERR_CONFIG;
2080 }
2081
2082 /**
2083 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2084 * @hw: pointer to the HW structure
2085 *
2086 * Checks if firmware is blocking the reset of the PHY.
2087 * This is a function pointer entry point only called by
2088 * reset routines.
2089 **/
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)2090 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2091 {
2092 bool blocked = false;
2093 int i = 0;
2094
2095 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2096 (i++ < 30))
2097 usleep_range(10000, 11000);
2098 return blocked ? E1000_BLK_PHY_RESET : 0;
2099 }
2100
2101 /**
2102 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2103 * @hw: pointer to the HW structure
2104 *
2105 * Assumes semaphore already acquired.
2106 *
2107 **/
e1000_write_smbus_addr(struct e1000_hw * hw)2108 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2109 {
2110 u16 phy_data;
2111 u32 strap = er32(STRAP);
2112 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap);
2113 s32 ret_val;
2114
2115 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2116
2117 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2118 if (ret_val)
2119 return ret_val;
2120
2121 phy_data &= ~HV_SMB_ADDR_MASK;
2122 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2123 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2124
2125 if (hw->phy.type == e1000_phy_i217) {
2126 /* Restore SMBus frequency */
2127 if (freq--) {
2128 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2129 phy_data |= (freq & BIT(0)) <<
2130 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2131 phy_data |= (freq & BIT(1)) <<
2132 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2133 } else {
2134 e_dbg("Unsupported SMB frequency in PHY\n");
2135 }
2136 }
2137
2138 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2139 }
2140
2141 /**
2142 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2143 * @hw: pointer to the HW structure
2144 *
2145 * SW should configure the LCD from the NVM extended configuration region
2146 * as a workaround for certain parts.
2147 **/
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)2148 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2149 {
2150 struct e1000_phy_info *phy = &hw->phy;
2151 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2152 s32 ret_val = 0;
2153 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2154
2155 /* Initialize the PHY from the NVM on ICH platforms. This
2156 * is needed due to an issue where the NVM configuration is
2157 * not properly autoloaded after power transitions.
2158 * Therefore, after each PHY reset, we will load the
2159 * configuration data out of the NVM manually.
2160 */
2161 switch (hw->mac.type) {
2162 case e1000_ich8lan:
2163 if (phy->type != e1000_phy_igp_3)
2164 return ret_val;
2165
2166 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2167 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2168 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2169 break;
2170 }
2171 fallthrough;
2172 case e1000_pchlan:
2173 case e1000_pch2lan:
2174 case e1000_pch_lpt:
2175 case e1000_pch_spt:
2176 case e1000_pch_cnp:
2177 case e1000_pch_tgp:
2178 case e1000_pch_adp:
2179 case e1000_pch_mtp:
2180 case e1000_pch_lnp:
2181 case e1000_pch_ptp:
2182 case e1000_pch_nvp:
2183 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2184 break;
2185 default:
2186 return ret_val;
2187 }
2188
2189 ret_val = hw->phy.ops.acquire(hw);
2190 if (ret_val)
2191 return ret_val;
2192
2193 data = er32(FEXTNVM);
2194 if (!(data & sw_cfg_mask))
2195 goto release;
2196
2197 /* Make sure HW does not configure LCD from PHY
2198 * extended configuration before SW configuration
2199 */
2200 data = er32(EXTCNF_CTRL);
2201 if ((hw->mac.type < e1000_pch2lan) &&
2202 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2203 goto release;
2204
2205 cnf_size = er32(EXTCNF_SIZE);
2206 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2207 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2208 if (!cnf_size)
2209 goto release;
2210
2211 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2212 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2213
2214 if (((hw->mac.type == e1000_pchlan) &&
2215 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2216 (hw->mac.type > e1000_pchlan)) {
2217 /* HW configures the SMBus address and LEDs when the
2218 * OEM and LCD Write Enable bits are set in the NVM.
2219 * When both NVM bits are cleared, SW will configure
2220 * them instead.
2221 */
2222 ret_val = e1000_write_smbus_addr(hw);
2223 if (ret_val)
2224 goto release;
2225
2226 data = er32(LEDCTL);
2227 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2228 (u16)data);
2229 if (ret_val)
2230 goto release;
2231 }
2232
2233 /* Configure LCD from extended configuration region. */
2234
2235 /* cnf_base_addr is in DWORD */
2236 word_addr = (u16)(cnf_base_addr << 1);
2237
2238 for (i = 0; i < cnf_size; i++) {
2239 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2240 if (ret_val)
2241 goto release;
2242
2243 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2244 1, ®_addr);
2245 if (ret_val)
2246 goto release;
2247
2248 /* Save off the PHY page for future writes. */
2249 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2250 phy_page = reg_data;
2251 continue;
2252 }
2253
2254 reg_addr &= PHY_REG_MASK;
2255 reg_addr |= phy_page;
2256
2257 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2258 if (ret_val)
2259 goto release;
2260 }
2261
2262 release:
2263 hw->phy.ops.release(hw);
2264 return ret_val;
2265 }
2266
2267 /**
2268 * e1000_k1_gig_workaround_hv - K1 Si workaround
2269 * @hw: pointer to the HW structure
2270 * @link: link up bool flag
2271 *
2272 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2273 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2274 * If link is down, the function will restore the default K1 setting located
2275 * in the NVM.
2276 **/
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)2277 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2278 {
2279 s32 ret_val = 0;
2280 u16 status_reg = 0;
2281 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2282
2283 if (hw->mac.type != e1000_pchlan)
2284 return 0;
2285
2286 /* Wrap the whole flow with the sw flag */
2287 ret_val = hw->phy.ops.acquire(hw);
2288 if (ret_val)
2289 return ret_val;
2290
2291 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2292 if (link) {
2293 if (hw->phy.type == e1000_phy_82578) {
2294 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2295 &status_reg);
2296 if (ret_val)
2297 goto release;
2298
2299 status_reg &= (BM_CS_STATUS_LINK_UP |
2300 BM_CS_STATUS_RESOLVED |
2301 BM_CS_STATUS_SPEED_MASK);
2302
2303 if (status_reg == (BM_CS_STATUS_LINK_UP |
2304 BM_CS_STATUS_RESOLVED |
2305 BM_CS_STATUS_SPEED_1000))
2306 k1_enable = false;
2307 }
2308
2309 if (hw->phy.type == e1000_phy_82577) {
2310 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2311 if (ret_val)
2312 goto release;
2313
2314 status_reg &= (HV_M_STATUS_LINK_UP |
2315 HV_M_STATUS_AUTONEG_COMPLETE |
2316 HV_M_STATUS_SPEED_MASK);
2317
2318 if (status_reg == (HV_M_STATUS_LINK_UP |
2319 HV_M_STATUS_AUTONEG_COMPLETE |
2320 HV_M_STATUS_SPEED_1000))
2321 k1_enable = false;
2322 }
2323
2324 /* Link stall fix for link up */
2325 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2326 if (ret_val)
2327 goto release;
2328
2329 } else {
2330 /* Link stall fix for link down */
2331 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2332 if (ret_val)
2333 goto release;
2334 }
2335
2336 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2337
2338 release:
2339 hw->phy.ops.release(hw);
2340
2341 return ret_val;
2342 }
2343
2344 /**
2345 * e1000_configure_k1_ich8lan - Configure K1 power state
2346 * @hw: pointer to the HW structure
2347 * @k1_enable: K1 state to configure
2348 *
2349 * Configure the K1 power state based on the provided parameter.
2350 * Assumes semaphore already acquired.
2351 *
2352 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2353 **/
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)2354 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2355 {
2356 s32 ret_val;
2357 u32 ctrl_reg = 0;
2358 u32 ctrl_ext = 0;
2359 u32 reg = 0;
2360 u16 kmrn_reg = 0;
2361
2362 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2363 &kmrn_reg);
2364 if (ret_val)
2365 return ret_val;
2366
2367 if (k1_enable)
2368 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2369 else
2370 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2371
2372 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2373 kmrn_reg);
2374 if (ret_val)
2375 return ret_val;
2376
2377 usleep_range(20, 40);
2378 ctrl_ext = er32(CTRL_EXT);
2379 ctrl_reg = er32(CTRL);
2380
2381 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2382 reg |= E1000_CTRL_FRCSPD;
2383 ew32(CTRL, reg);
2384
2385 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2386 e1e_flush();
2387 usleep_range(20, 40);
2388 ew32(CTRL, ctrl_reg);
2389 ew32(CTRL_EXT, ctrl_ext);
2390 e1e_flush();
2391 usleep_range(20, 40);
2392
2393 return 0;
2394 }
2395
2396 /**
2397 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2398 * @hw: pointer to the HW structure
2399 * @d0_state: boolean if entering d0 or d3 device state
2400 *
2401 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2402 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2403 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2404 **/
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)2405 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2406 {
2407 s32 ret_val = 0;
2408 u32 mac_reg;
2409 u16 oem_reg;
2410
2411 if (hw->mac.type < e1000_pchlan)
2412 return ret_val;
2413
2414 ret_val = hw->phy.ops.acquire(hw);
2415 if (ret_val)
2416 return ret_val;
2417
2418 if (hw->mac.type == e1000_pchlan) {
2419 mac_reg = er32(EXTCNF_CTRL);
2420 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2421 goto release;
2422 }
2423
2424 mac_reg = er32(FEXTNVM);
2425 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2426 goto release;
2427
2428 mac_reg = er32(PHY_CTRL);
2429
2430 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2431 if (ret_val)
2432 goto release;
2433
2434 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2435
2436 if (d0_state) {
2437 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2438 oem_reg |= HV_OEM_BITS_GBE_DIS;
2439
2440 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2441 oem_reg |= HV_OEM_BITS_LPLU;
2442 } else {
2443 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2444 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2445 oem_reg |= HV_OEM_BITS_GBE_DIS;
2446
2447 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2448 E1000_PHY_CTRL_NOND0A_LPLU))
2449 oem_reg |= HV_OEM_BITS_LPLU;
2450 }
2451
2452 /* Set Restart auto-neg to activate the bits */
2453 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2454 !hw->phy.ops.check_reset_block(hw))
2455 oem_reg |= HV_OEM_BITS_RESTART_AN;
2456
2457 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2458
2459 release:
2460 hw->phy.ops.release(hw);
2461
2462 return ret_val;
2463 }
2464
2465 /**
2466 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2467 * @hw: pointer to the HW structure
2468 **/
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw)2469 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2470 {
2471 s32 ret_val;
2472 u16 data;
2473
2474 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2475 if (ret_val)
2476 return ret_val;
2477
2478 data |= HV_KMRN_MDIO_SLOW;
2479
2480 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2481
2482 return ret_val;
2483 }
2484
2485 /**
2486 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2487 * @hw: pointer to the HW structure
2488 *
2489 * A series of PHY workarounds to be done after every PHY reset.
2490 **/
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)2491 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2492 {
2493 s32 ret_val = 0;
2494 u16 phy_data;
2495
2496 if (hw->mac.type != e1000_pchlan)
2497 return 0;
2498
2499 /* Set MDIO slow mode before any other MDIO access */
2500 if (hw->phy.type == e1000_phy_82577) {
2501 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2502 if (ret_val)
2503 return ret_val;
2504 }
2505
2506 if (((hw->phy.type == e1000_phy_82577) &&
2507 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2508 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2509 /* Disable generation of early preamble */
2510 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2511 if (ret_val)
2512 return ret_val;
2513
2514 /* Preamble tuning for SSC */
2515 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2516 if (ret_val)
2517 return ret_val;
2518 }
2519
2520 if (hw->phy.type == e1000_phy_82578) {
2521 /* Return registers to default by doing a soft reset then
2522 * writing 0x3140 to the control register.
2523 */
2524 if (hw->phy.revision < 2) {
2525 e1000e_phy_sw_reset(hw);
2526 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2527 if (ret_val)
2528 return ret_val;
2529 }
2530 }
2531
2532 /* Select page 0 */
2533 ret_val = hw->phy.ops.acquire(hw);
2534 if (ret_val)
2535 return ret_val;
2536
2537 hw->phy.addr = 1;
2538 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2539 hw->phy.ops.release(hw);
2540 if (ret_val)
2541 return ret_val;
2542
2543 /* Configure the K1 Si workaround during phy reset assuming there is
2544 * link so that it disables K1 if link is in 1Gbps.
2545 */
2546 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2547 if (ret_val)
2548 return ret_val;
2549
2550 /* Workaround for link disconnects on a busy hub in half duplex */
2551 ret_val = hw->phy.ops.acquire(hw);
2552 if (ret_val)
2553 return ret_val;
2554 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2555 if (ret_val)
2556 goto release;
2557 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2558 if (ret_val)
2559 goto release;
2560
2561 /* set MSE higher to enable link to stay up when noise is high */
2562 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2563 release:
2564 hw->phy.ops.release(hw);
2565
2566 return ret_val;
2567 }
2568
2569 /**
2570 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2571 * @hw: pointer to the HW structure
2572 **/
e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw * hw)2573 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2574 {
2575 u32 mac_reg;
2576 u16 i, phy_reg = 0;
2577 s32 ret_val;
2578
2579 ret_val = hw->phy.ops.acquire(hw);
2580 if (ret_val)
2581 return;
2582 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2583 if (ret_val)
2584 goto release;
2585
2586 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2587 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2588 mac_reg = er32(RAL(i));
2589 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2590 (u16)(mac_reg & 0xFFFF));
2591 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2592 (u16)((mac_reg >> 16) & 0xFFFF));
2593
2594 mac_reg = er32(RAH(i));
2595 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2596 (u16)(mac_reg & 0xFFFF));
2597 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2598 (u16)((mac_reg & E1000_RAH_AV) >> 16));
2599 }
2600
2601 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2602
2603 release:
2604 hw->phy.ops.release(hw);
2605 }
2606
2607 /**
2608 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2609 * with 82579 PHY
2610 * @hw: pointer to the HW structure
2611 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2612 **/
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw * hw,bool enable)2613 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2614 {
2615 s32 ret_val = 0;
2616 u16 phy_reg, data;
2617 u32 mac_reg;
2618 u16 i;
2619
2620 if (hw->mac.type < e1000_pch2lan)
2621 return 0;
2622
2623 /* disable Rx path while enabling/disabling workaround */
2624 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2625 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2626 if (ret_val)
2627 return ret_val;
2628
2629 if (enable) {
2630 /* Write Rx addresses (rar_entry_count for RAL/H, and
2631 * SHRAL/H) and initial CRC values to the MAC
2632 */
2633 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2634 u8 mac_addr[ETH_ALEN] = { 0 };
2635 u32 addr_high, addr_low;
2636
2637 addr_high = er32(RAH(i));
2638 if (!(addr_high & E1000_RAH_AV))
2639 continue;
2640 addr_low = er32(RAL(i));
2641 mac_addr[0] = (addr_low & 0xFF);
2642 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2643 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2644 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2645 mac_addr[4] = (addr_high & 0xFF);
2646 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2647
2648 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2649 }
2650
2651 /* Write Rx addresses to the PHY */
2652 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2653
2654 /* Enable jumbo frame workaround in the MAC */
2655 mac_reg = er32(FFLT_DBG);
2656 mac_reg &= ~BIT(14);
2657 mac_reg |= (7 << 15);
2658 ew32(FFLT_DBG, mac_reg);
2659
2660 mac_reg = er32(RCTL);
2661 mac_reg |= E1000_RCTL_SECRC;
2662 ew32(RCTL, mac_reg);
2663
2664 ret_val = e1000e_read_kmrn_reg(hw,
2665 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2666 &data);
2667 if (ret_val)
2668 return ret_val;
2669 ret_val = e1000e_write_kmrn_reg(hw,
2670 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2671 data | BIT(0));
2672 if (ret_val)
2673 return ret_val;
2674 ret_val = e1000e_read_kmrn_reg(hw,
2675 E1000_KMRNCTRLSTA_HD_CTRL,
2676 &data);
2677 if (ret_val)
2678 return ret_val;
2679 data &= ~(0xF << 8);
2680 data |= (0xB << 8);
2681 ret_val = e1000e_write_kmrn_reg(hw,
2682 E1000_KMRNCTRLSTA_HD_CTRL,
2683 data);
2684 if (ret_val)
2685 return ret_val;
2686
2687 /* Enable jumbo frame workaround in the PHY */
2688 e1e_rphy(hw, PHY_REG(769, 23), &data);
2689 data &= ~(0x7F << 5);
2690 data |= (0x37 << 5);
2691 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2692 if (ret_val)
2693 return ret_val;
2694 e1e_rphy(hw, PHY_REG(769, 16), &data);
2695 data &= ~BIT(13);
2696 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2697 if (ret_val)
2698 return ret_val;
2699 e1e_rphy(hw, PHY_REG(776, 20), &data);
2700 data &= ~(0x3FF << 2);
2701 data |= (E1000_TX_PTR_GAP << 2);
2702 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2703 if (ret_val)
2704 return ret_val;
2705 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2706 if (ret_val)
2707 return ret_val;
2708 e1e_rphy(hw, HV_PM_CTRL, &data);
2709 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2710 if (ret_val)
2711 return ret_val;
2712 } else {
2713 /* Write MAC register values back to h/w defaults */
2714 mac_reg = er32(FFLT_DBG);
2715 mac_reg &= ~(0xF << 14);
2716 ew32(FFLT_DBG, mac_reg);
2717
2718 mac_reg = er32(RCTL);
2719 mac_reg &= ~E1000_RCTL_SECRC;
2720 ew32(RCTL, mac_reg);
2721
2722 ret_val = e1000e_read_kmrn_reg(hw,
2723 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2724 &data);
2725 if (ret_val)
2726 return ret_val;
2727 ret_val = e1000e_write_kmrn_reg(hw,
2728 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2729 data & ~BIT(0));
2730 if (ret_val)
2731 return ret_val;
2732 ret_val = e1000e_read_kmrn_reg(hw,
2733 E1000_KMRNCTRLSTA_HD_CTRL,
2734 &data);
2735 if (ret_val)
2736 return ret_val;
2737 data &= ~(0xF << 8);
2738 data |= (0xB << 8);
2739 ret_val = e1000e_write_kmrn_reg(hw,
2740 E1000_KMRNCTRLSTA_HD_CTRL,
2741 data);
2742 if (ret_val)
2743 return ret_val;
2744
2745 /* Write PHY register values back to h/w defaults */
2746 e1e_rphy(hw, PHY_REG(769, 23), &data);
2747 data &= ~(0x7F << 5);
2748 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2749 if (ret_val)
2750 return ret_val;
2751 e1e_rphy(hw, PHY_REG(769, 16), &data);
2752 data |= BIT(13);
2753 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2754 if (ret_val)
2755 return ret_val;
2756 e1e_rphy(hw, PHY_REG(776, 20), &data);
2757 data &= ~(0x3FF << 2);
2758 data |= (0x8 << 2);
2759 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2760 if (ret_val)
2761 return ret_val;
2762 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2763 if (ret_val)
2764 return ret_val;
2765 e1e_rphy(hw, HV_PM_CTRL, &data);
2766 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2767 if (ret_val)
2768 return ret_val;
2769 }
2770
2771 /* re-enable Rx path after enabling/disabling workaround */
2772 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2773 }
2774
2775 /**
2776 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2777 * @hw: pointer to the HW structure
2778 *
2779 * A series of PHY workarounds to be done after every PHY reset.
2780 **/
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw * hw)2781 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2782 {
2783 s32 ret_val = 0;
2784
2785 if (hw->mac.type != e1000_pch2lan)
2786 return 0;
2787
2788 /* Set MDIO slow mode before any other MDIO access */
2789 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2790 if (ret_val)
2791 return ret_val;
2792
2793 ret_val = hw->phy.ops.acquire(hw);
2794 if (ret_val)
2795 return ret_val;
2796 /* set MSE higher to enable link to stay up when noise is high */
2797 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2798 if (ret_val)
2799 goto release;
2800 /* drop link after 5 times MSE threshold was reached */
2801 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2802 release:
2803 hw->phy.ops.release(hw);
2804
2805 return ret_val;
2806 }
2807
2808 /**
2809 * e1000_k1_workaround_lv - K1 Si workaround
2810 * @hw: pointer to the HW structure
2811 *
2812 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2813 * Disable K1 in 1000Mbps and 100Mbps
2814 **/
e1000_k1_workaround_lv(struct e1000_hw * hw)2815 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2816 {
2817 s32 ret_val = 0;
2818 u16 status_reg = 0;
2819
2820 if (hw->mac.type != e1000_pch2lan)
2821 return 0;
2822
2823 /* Set K1 beacon duration based on 10Mbs speed */
2824 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2825 if (ret_val)
2826 return ret_val;
2827
2828 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2829 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2830 if (status_reg &
2831 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2832 u16 pm_phy_reg;
2833
2834 /* LV 1G/100 Packet drop issue wa */
2835 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2836 if (ret_val)
2837 return ret_val;
2838 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2839 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2840 if (ret_val)
2841 return ret_val;
2842 } else {
2843 u32 mac_reg;
2844
2845 mac_reg = er32(FEXTNVM4);
2846 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2847 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2848 ew32(FEXTNVM4, mac_reg);
2849 }
2850 }
2851
2852 return ret_val;
2853 }
2854
2855 /**
2856 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2857 * @hw: pointer to the HW structure
2858 * @gate: boolean set to true to gate, false to ungate
2859 *
2860 * Gate/ungate the automatic PHY configuration via hardware; perform
2861 * the configuration via software instead.
2862 **/
e1000_gate_hw_phy_config_ich8lan(struct e1000_hw * hw,bool gate)2863 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2864 {
2865 u32 extcnf_ctrl;
2866
2867 if (hw->mac.type < e1000_pch2lan)
2868 return;
2869
2870 extcnf_ctrl = er32(EXTCNF_CTRL);
2871
2872 if (gate)
2873 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2874 else
2875 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2876
2877 ew32(EXTCNF_CTRL, extcnf_ctrl);
2878 }
2879
2880 /**
2881 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2882 * @hw: pointer to the HW structure
2883 *
2884 * Check the appropriate indication the MAC has finished configuring the
2885 * PHY after a software reset.
2886 **/
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)2887 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2888 {
2889 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2890
2891 /* Wait for basic configuration completes before proceeding */
2892 do {
2893 data = er32(STATUS);
2894 data &= E1000_STATUS_LAN_INIT_DONE;
2895 usleep_range(100, 200);
2896 } while ((!data) && --loop);
2897
2898 /* If basic configuration is incomplete before the above loop
2899 * count reaches 0, loading the configuration from NVM will
2900 * leave the PHY in a bad state possibly resulting in no link.
2901 */
2902 if (loop == 0)
2903 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2904
2905 /* Clear the Init Done bit for the next init event */
2906 data = er32(STATUS);
2907 data &= ~E1000_STATUS_LAN_INIT_DONE;
2908 ew32(STATUS, data);
2909 }
2910
2911 /**
2912 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2913 * @hw: pointer to the HW structure
2914 **/
e1000_post_phy_reset_ich8lan(struct e1000_hw * hw)2915 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2916 {
2917 s32 ret_val = 0;
2918 u16 reg;
2919
2920 if (hw->phy.ops.check_reset_block(hw))
2921 return 0;
2922
2923 /* Allow time for h/w to get to quiescent state after reset */
2924 usleep_range(10000, 11000);
2925
2926 /* Perform any necessary post-reset workarounds */
2927 switch (hw->mac.type) {
2928 case e1000_pchlan:
2929 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2930 if (ret_val)
2931 return ret_val;
2932 break;
2933 case e1000_pch2lan:
2934 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2935 if (ret_val)
2936 return ret_val;
2937 break;
2938 default:
2939 break;
2940 }
2941
2942 /* Clear the host wakeup bit after lcd reset */
2943 if (hw->mac.type >= e1000_pchlan) {
2944 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2945 reg &= ~BM_WUC_HOST_WU_BIT;
2946 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2947 }
2948
2949 /* Configure the LCD with the extended configuration region in NVM */
2950 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2951 if (ret_val)
2952 return ret_val;
2953
2954 /* Configure the LCD with the OEM bits in NVM */
2955 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2956
2957 if (hw->mac.type == e1000_pch2lan) {
2958 /* Ungate automatic PHY configuration on non-managed 82579 */
2959 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2960 usleep_range(10000, 11000);
2961 e1000_gate_hw_phy_config_ich8lan(hw, false);
2962 }
2963
2964 /* Set EEE LPI Update Timer to 200usec */
2965 ret_val = hw->phy.ops.acquire(hw);
2966 if (ret_val)
2967 return ret_val;
2968 ret_val = e1000_write_emi_reg_locked(hw,
2969 I82579_LPI_UPDATE_TIMER,
2970 0x1387);
2971 hw->phy.ops.release(hw);
2972 }
2973
2974 return ret_val;
2975 }
2976
2977 /**
2978 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2979 * @hw: pointer to the HW structure
2980 *
2981 * Resets the PHY
2982 * This is a function pointer entry point called by drivers
2983 * or other shared routines.
2984 **/
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)2985 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2986 {
2987 s32 ret_val = 0;
2988
2989 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2990 if ((hw->mac.type == e1000_pch2lan) &&
2991 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2992 e1000_gate_hw_phy_config_ich8lan(hw, true);
2993
2994 ret_val = e1000e_phy_hw_reset_generic(hw);
2995 if (ret_val)
2996 return ret_val;
2997
2998 return e1000_post_phy_reset_ich8lan(hw);
2999 }
3000
3001 /**
3002 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3003 * @hw: pointer to the HW structure
3004 * @active: true to enable LPLU, false to disable
3005 *
3006 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3007 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3008 * the phy speed. This function will manually set the LPLU bit and restart
3009 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3010 * since it configures the same bit.
3011 **/
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)3012 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3013 {
3014 s32 ret_val;
3015 u16 oem_reg;
3016
3017 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
3018 if (ret_val)
3019 return ret_val;
3020
3021 if (active)
3022 oem_reg |= HV_OEM_BITS_LPLU;
3023 else
3024 oem_reg &= ~HV_OEM_BITS_LPLU;
3025
3026 if (!hw->phy.ops.check_reset_block(hw))
3027 oem_reg |= HV_OEM_BITS_RESTART_AN;
3028
3029 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
3030 }
3031
3032 /**
3033 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3034 * @hw: pointer to the HW structure
3035 * @active: true to enable LPLU, false to disable
3036 *
3037 * Sets the LPLU D0 state according to the active flag. When
3038 * activating LPLU this function also disables smart speed
3039 * and vice versa. LPLU will not be activated unless the
3040 * device autonegotiation advertisement meets standards of
3041 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3042 * This is a function pointer entry point only called by
3043 * PHY setup routines.
3044 **/
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3045 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3046 {
3047 struct e1000_phy_info *phy = &hw->phy;
3048 u32 phy_ctrl;
3049 s32 ret_val = 0;
3050 u16 data;
3051
3052 if (phy->type == e1000_phy_ife)
3053 return 0;
3054
3055 phy_ctrl = er32(PHY_CTRL);
3056
3057 if (active) {
3058 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3059 ew32(PHY_CTRL, phy_ctrl);
3060
3061 if (phy->type != e1000_phy_igp_3)
3062 return 0;
3063
3064 /* Call gig speed drop workaround on LPLU before accessing
3065 * any PHY registers
3066 */
3067 if (hw->mac.type == e1000_ich8lan)
3068 e1000e_gig_downshift_workaround_ich8lan(hw);
3069
3070 /* When LPLU is enabled, we should disable SmartSpeed */
3071 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3072 if (ret_val)
3073 return ret_val;
3074 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3075 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3076 if (ret_val)
3077 return ret_val;
3078 } else {
3079 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3080 ew32(PHY_CTRL, phy_ctrl);
3081
3082 if (phy->type != e1000_phy_igp_3)
3083 return 0;
3084
3085 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3086 * during Dx states where the power conservation is most
3087 * important. During driver activity we should enable
3088 * SmartSpeed, so performance is maintained.
3089 */
3090 if (phy->smart_speed == e1000_smart_speed_on) {
3091 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3092 &data);
3093 if (ret_val)
3094 return ret_val;
3095
3096 data |= IGP01E1000_PSCFR_SMART_SPEED;
3097 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3098 data);
3099 if (ret_val)
3100 return ret_val;
3101 } else if (phy->smart_speed == e1000_smart_speed_off) {
3102 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3103 &data);
3104 if (ret_val)
3105 return ret_val;
3106
3107 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3108 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3109 data);
3110 if (ret_val)
3111 return ret_val;
3112 }
3113 }
3114
3115 return 0;
3116 }
3117
3118 /**
3119 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3120 * @hw: pointer to the HW structure
3121 * @active: true to enable LPLU, false to disable
3122 *
3123 * Sets the LPLU D3 state according to the active flag. When
3124 * activating LPLU this function also disables smart speed
3125 * and vice versa. LPLU will not be activated unless the
3126 * device autonegotiation advertisement meets standards of
3127 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3128 * This is a function pointer entry point only called by
3129 * PHY setup routines.
3130 **/
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3131 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3132 {
3133 struct e1000_phy_info *phy = &hw->phy;
3134 u32 phy_ctrl;
3135 s32 ret_val = 0;
3136 u16 data;
3137
3138 phy_ctrl = er32(PHY_CTRL);
3139
3140 if (!active) {
3141 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3142 ew32(PHY_CTRL, phy_ctrl);
3143
3144 if (phy->type != e1000_phy_igp_3)
3145 return 0;
3146
3147 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3148 * during Dx states where the power conservation is most
3149 * important. During driver activity we should enable
3150 * SmartSpeed, so performance is maintained.
3151 */
3152 if (phy->smart_speed == e1000_smart_speed_on) {
3153 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3154 &data);
3155 if (ret_val)
3156 return ret_val;
3157
3158 data |= IGP01E1000_PSCFR_SMART_SPEED;
3159 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3160 data);
3161 if (ret_val)
3162 return ret_val;
3163 } else if (phy->smart_speed == e1000_smart_speed_off) {
3164 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3165 &data);
3166 if (ret_val)
3167 return ret_val;
3168
3169 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3170 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3171 data);
3172 if (ret_val)
3173 return ret_val;
3174 }
3175 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3176 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3177 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3178 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3179 ew32(PHY_CTRL, phy_ctrl);
3180
3181 if (phy->type != e1000_phy_igp_3)
3182 return 0;
3183
3184 /* Call gig speed drop workaround on LPLU before accessing
3185 * any PHY registers
3186 */
3187 if (hw->mac.type == e1000_ich8lan)
3188 e1000e_gig_downshift_workaround_ich8lan(hw);
3189
3190 /* When LPLU is enabled, we should disable SmartSpeed */
3191 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3192 if (ret_val)
3193 return ret_val;
3194
3195 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3196 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3197 }
3198
3199 return ret_val;
3200 }
3201
3202 /**
3203 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3204 * @hw: pointer to the HW structure
3205 * @bank: pointer to the variable that returns the active bank
3206 *
3207 * Reads signature byte from the NVM using the flash access registers.
3208 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3209 **/
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)3210 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3211 {
3212 u32 eecd;
3213 struct e1000_nvm_info *nvm = &hw->nvm;
3214 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3215 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3216 u32 nvm_dword = 0;
3217 u8 sig_byte = 0;
3218 s32 ret_val;
3219
3220 switch (hw->mac.type) {
3221 case e1000_pch_spt:
3222 case e1000_pch_cnp:
3223 case e1000_pch_tgp:
3224 case e1000_pch_adp:
3225 case e1000_pch_mtp:
3226 case e1000_pch_lnp:
3227 case e1000_pch_ptp:
3228 case e1000_pch_nvp:
3229 bank1_offset = nvm->flash_bank_size;
3230 act_offset = E1000_ICH_NVM_SIG_WORD;
3231
3232 /* set bank to 0 in case flash read fails */
3233 *bank = 0;
3234
3235 /* Check bank 0 */
3236 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3237 &nvm_dword);
3238 if (ret_val)
3239 return ret_val;
3240 sig_byte = FIELD_GET(0xFF00, nvm_dword);
3241 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3242 E1000_ICH_NVM_SIG_VALUE) {
3243 *bank = 0;
3244 return 0;
3245 }
3246
3247 /* Check bank 1 */
3248 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3249 bank1_offset,
3250 &nvm_dword);
3251 if (ret_val)
3252 return ret_val;
3253 sig_byte = FIELD_GET(0xFF00, nvm_dword);
3254 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3255 E1000_ICH_NVM_SIG_VALUE) {
3256 *bank = 1;
3257 return 0;
3258 }
3259
3260 e_dbg("ERROR: No valid NVM bank present\n");
3261 return -E1000_ERR_NVM;
3262 case e1000_ich8lan:
3263 case e1000_ich9lan:
3264 eecd = er32(EECD);
3265 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3266 E1000_EECD_SEC1VAL_VALID_MASK) {
3267 if (eecd & E1000_EECD_SEC1VAL)
3268 *bank = 1;
3269 else
3270 *bank = 0;
3271
3272 return 0;
3273 }
3274 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3275 fallthrough;
3276 default:
3277 /* set bank to 0 in case flash read fails */
3278 *bank = 0;
3279
3280 /* Check bank 0 */
3281 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3282 &sig_byte);
3283 if (ret_val)
3284 return ret_val;
3285 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3286 E1000_ICH_NVM_SIG_VALUE) {
3287 *bank = 0;
3288 return 0;
3289 }
3290
3291 /* Check bank 1 */
3292 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3293 bank1_offset,
3294 &sig_byte);
3295 if (ret_val)
3296 return ret_val;
3297 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3298 E1000_ICH_NVM_SIG_VALUE) {
3299 *bank = 1;
3300 return 0;
3301 }
3302
3303 e_dbg("ERROR: No valid NVM bank present\n");
3304 return -E1000_ERR_NVM;
3305 }
3306 }
3307
3308 /**
3309 * e1000_read_nvm_spt - NVM access for SPT
3310 * @hw: pointer to the HW structure
3311 * @offset: The offset (in bytes) of the word(s) to read.
3312 * @words: Size of data to read in words.
3313 * @data: pointer to the word(s) to read at offset.
3314 *
3315 * Reads a word(s) from the NVM
3316 **/
e1000_read_nvm_spt(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3317 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3318 u16 *data)
3319 {
3320 struct e1000_nvm_info *nvm = &hw->nvm;
3321 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3322 u32 act_offset;
3323 s32 ret_val = 0;
3324 u32 bank = 0;
3325 u32 dword = 0;
3326 u16 offset_to_read;
3327 u16 i;
3328
3329 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3330 (words == 0)) {
3331 e_dbg("nvm parameter(s) out of bounds\n");
3332 ret_val = -E1000_ERR_NVM;
3333 goto out;
3334 }
3335
3336 nvm->ops.acquire(hw);
3337
3338 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3339 if (ret_val) {
3340 e_dbg("Could not detect valid bank, assuming bank 0\n");
3341 bank = 0;
3342 }
3343
3344 act_offset = (bank) ? nvm->flash_bank_size : 0;
3345 act_offset += offset;
3346
3347 ret_val = 0;
3348
3349 for (i = 0; i < words; i += 2) {
3350 if (words - i == 1) {
3351 if (dev_spec->shadow_ram[offset + i].modified) {
3352 data[i] =
3353 dev_spec->shadow_ram[offset + i].value;
3354 } else {
3355 offset_to_read = act_offset + i -
3356 ((act_offset + i) % 2);
3357 ret_val =
3358 e1000_read_flash_dword_ich8lan(hw,
3359 offset_to_read,
3360 &dword);
3361 if (ret_val)
3362 break;
3363 if ((act_offset + i) % 2 == 0)
3364 data[i] = (u16)(dword & 0xFFFF);
3365 else
3366 data[i] = (u16)((dword >> 16) & 0xFFFF);
3367 }
3368 } else {
3369 offset_to_read = act_offset + i;
3370 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3371 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3372 ret_val =
3373 e1000_read_flash_dword_ich8lan(hw,
3374 offset_to_read,
3375 &dword);
3376 if (ret_val)
3377 break;
3378 }
3379 if (dev_spec->shadow_ram[offset + i].modified)
3380 data[i] =
3381 dev_spec->shadow_ram[offset + i].value;
3382 else
3383 data[i] = (u16)(dword & 0xFFFF);
3384 if (dev_spec->shadow_ram[offset + i].modified)
3385 data[i + 1] =
3386 dev_spec->shadow_ram[offset + i + 1].value;
3387 else
3388 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3389 }
3390 }
3391
3392 nvm->ops.release(hw);
3393
3394 out:
3395 if (ret_val)
3396 e_dbg("NVM read error: %d\n", ret_val);
3397
3398 return ret_val;
3399 }
3400
3401 /**
3402 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3403 * @hw: pointer to the HW structure
3404 * @offset: The offset (in bytes) of the word(s) to read.
3405 * @words: Size of data to read in words
3406 * @data: Pointer to the word(s) to read at offset.
3407 *
3408 * Reads a word(s) from the NVM using the flash access registers.
3409 **/
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3410 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3411 u16 *data)
3412 {
3413 struct e1000_nvm_info *nvm = &hw->nvm;
3414 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3415 u32 act_offset;
3416 s32 ret_val = 0;
3417 u32 bank = 0;
3418 u16 i, word;
3419
3420 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3421 (words == 0)) {
3422 e_dbg("nvm parameter(s) out of bounds\n");
3423 ret_val = -E1000_ERR_NVM;
3424 goto out;
3425 }
3426
3427 nvm->ops.acquire(hw);
3428
3429 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3430 if (ret_val) {
3431 e_dbg("Could not detect valid bank, assuming bank 0\n");
3432 bank = 0;
3433 }
3434
3435 act_offset = (bank) ? nvm->flash_bank_size : 0;
3436 act_offset += offset;
3437
3438 ret_val = 0;
3439 for (i = 0; i < words; i++) {
3440 if (dev_spec->shadow_ram[offset + i].modified) {
3441 data[i] = dev_spec->shadow_ram[offset + i].value;
3442 } else {
3443 ret_val = e1000_read_flash_word_ich8lan(hw,
3444 act_offset + i,
3445 &word);
3446 if (ret_val)
3447 break;
3448 data[i] = word;
3449 }
3450 }
3451
3452 nvm->ops.release(hw);
3453
3454 out:
3455 if (ret_val)
3456 e_dbg("NVM read error: %d\n", ret_val);
3457
3458 return ret_val;
3459 }
3460
3461 /**
3462 * e1000_flash_cycle_init_ich8lan - Initialize flash
3463 * @hw: pointer to the HW structure
3464 *
3465 * This function does initial flash setup so that a new read/write/erase cycle
3466 * can be started.
3467 **/
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)3468 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3469 {
3470 union ich8_hws_flash_status hsfsts;
3471 s32 ret_val = -E1000_ERR_NVM;
3472
3473 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3474
3475 /* Check if the flash descriptor is valid */
3476 if (!hsfsts.hsf_status.fldesvalid) {
3477 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3478 return -E1000_ERR_NVM;
3479 }
3480
3481 /* Clear FCERR and DAEL in hw status by writing 1 */
3482 hsfsts.hsf_status.flcerr = 1;
3483 hsfsts.hsf_status.dael = 1;
3484 if (hw->mac.type >= e1000_pch_spt)
3485 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3486 else
3487 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3488
3489 /* Either we should have a hardware SPI cycle in progress
3490 * bit to check against, in order to start a new cycle or
3491 * FDONE bit should be changed in the hardware so that it
3492 * is 1 after hardware reset, which can then be used as an
3493 * indication whether a cycle is in progress or has been
3494 * completed.
3495 */
3496
3497 if (!hsfsts.hsf_status.flcinprog) {
3498 /* There is no cycle running at present,
3499 * so we can start a cycle.
3500 * Begin by setting Flash Cycle Done.
3501 */
3502 hsfsts.hsf_status.flcdone = 1;
3503 if (hw->mac.type >= e1000_pch_spt)
3504 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3505 else
3506 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3507 ret_val = 0;
3508 } else {
3509 s32 i;
3510
3511 /* Otherwise poll for sometime so the current
3512 * cycle has a chance to end before giving up.
3513 */
3514 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3515 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3516 if (!hsfsts.hsf_status.flcinprog) {
3517 ret_val = 0;
3518 break;
3519 }
3520 udelay(1);
3521 }
3522 if (!ret_val) {
3523 /* Successful in waiting for previous cycle to timeout,
3524 * now set the Flash Cycle Done.
3525 */
3526 hsfsts.hsf_status.flcdone = 1;
3527 if (hw->mac.type >= e1000_pch_spt)
3528 ew32flash(ICH_FLASH_HSFSTS,
3529 hsfsts.regval & 0xFFFF);
3530 else
3531 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3532 } else {
3533 e_dbg("Flash controller busy, cannot get access\n");
3534 }
3535 }
3536
3537 return ret_val;
3538 }
3539
3540 /**
3541 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3542 * @hw: pointer to the HW structure
3543 * @timeout: maximum time to wait for completion
3544 *
3545 * This function starts a flash cycle and waits for its completion.
3546 **/
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)3547 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3548 {
3549 union ich8_hws_flash_ctrl hsflctl;
3550 union ich8_hws_flash_status hsfsts;
3551 u32 i = 0;
3552
3553 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3554 if (hw->mac.type >= e1000_pch_spt)
3555 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3556 else
3557 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3558 hsflctl.hsf_ctrl.flcgo = 1;
3559
3560 if (hw->mac.type >= e1000_pch_spt)
3561 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3562 else
3563 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3564
3565 /* wait till FDONE bit is set to 1 */
3566 do {
3567 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3568 if (hsfsts.hsf_status.flcdone)
3569 break;
3570 udelay(1);
3571 } while (i++ < timeout);
3572
3573 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3574 return 0;
3575
3576 return -E1000_ERR_NVM;
3577 }
3578
3579 /**
3580 * e1000_read_flash_dword_ich8lan - Read dword from flash
3581 * @hw: pointer to the HW structure
3582 * @offset: offset to data location
3583 * @data: pointer to the location for storing the data
3584 *
3585 * Reads the flash dword at offset into data. Offset is converted
3586 * to bytes before read.
3587 **/
e1000_read_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3588 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3589 u32 *data)
3590 {
3591 /* Must convert word offset into bytes. */
3592 offset <<= 1;
3593 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3594 }
3595
3596 /**
3597 * e1000_read_flash_word_ich8lan - Read word from flash
3598 * @hw: pointer to the HW structure
3599 * @offset: offset to data location
3600 * @data: pointer to the location for storing the data
3601 *
3602 * Reads the flash word at offset into data. Offset is converted
3603 * to bytes before read.
3604 **/
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)3605 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3606 u16 *data)
3607 {
3608 /* Must convert offset into bytes. */
3609 offset <<= 1;
3610
3611 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3612 }
3613
3614 /**
3615 * e1000_read_flash_byte_ich8lan - Read byte from flash
3616 * @hw: pointer to the HW structure
3617 * @offset: The offset of the byte to read.
3618 * @data: Pointer to a byte to store the value read.
3619 *
3620 * Reads a single byte from the NVM using the flash access registers.
3621 **/
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)3622 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3623 u8 *data)
3624 {
3625 s32 ret_val;
3626 u16 word = 0;
3627
3628 /* In SPT, only 32 bits access is supported,
3629 * so this function should not be called.
3630 */
3631 if (hw->mac.type >= e1000_pch_spt)
3632 return -E1000_ERR_NVM;
3633 else
3634 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3635
3636 if (ret_val)
3637 return ret_val;
3638
3639 *data = (u8)word;
3640
3641 return 0;
3642 }
3643
3644 /**
3645 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3646 * @hw: pointer to the HW structure
3647 * @offset: The offset (in bytes) of the byte or word to read.
3648 * @size: Size of data to read, 1=byte 2=word
3649 * @data: Pointer to the word to store the value read.
3650 *
3651 * Reads a byte or word from the NVM using the flash access registers.
3652 **/
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)3653 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3654 u8 size, u16 *data)
3655 {
3656 union ich8_hws_flash_status hsfsts;
3657 union ich8_hws_flash_ctrl hsflctl;
3658 u32 flash_linear_addr;
3659 u32 flash_data = 0;
3660 s32 ret_val = -E1000_ERR_NVM;
3661 u8 count = 0;
3662
3663 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3664 return -E1000_ERR_NVM;
3665
3666 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3667 hw->nvm.flash_base_addr);
3668
3669 do {
3670 udelay(1);
3671 /* Steps */
3672 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3673 if (ret_val)
3674 break;
3675
3676 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3677 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3678 hsflctl.hsf_ctrl.fldbcount = size - 1;
3679 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3680 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3681
3682 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3683
3684 ret_val =
3685 e1000_flash_cycle_ich8lan(hw,
3686 ICH_FLASH_READ_COMMAND_TIMEOUT);
3687
3688 /* Check if FCERR is set to 1, if set to 1, clear it
3689 * and try the whole sequence a few more times, else
3690 * read in (shift in) the Flash Data0, the order is
3691 * least significant byte first msb to lsb
3692 */
3693 if (!ret_val) {
3694 flash_data = er32flash(ICH_FLASH_FDATA0);
3695 if (size == 1)
3696 *data = (u8)(flash_data & 0x000000FF);
3697 else if (size == 2)
3698 *data = (u16)(flash_data & 0x0000FFFF);
3699 break;
3700 } else {
3701 /* If we've gotten here, then things are probably
3702 * completely hosed, but if the error condition is
3703 * detected, it won't hurt to give it another try...
3704 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3705 */
3706 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3707 if (hsfsts.hsf_status.flcerr) {
3708 /* Repeat for some time before giving up. */
3709 continue;
3710 } else if (!hsfsts.hsf_status.flcdone) {
3711 e_dbg("Timeout error - flash cycle did not complete.\n");
3712 break;
3713 }
3714 }
3715 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3716
3717 return ret_val;
3718 }
3719
3720 /**
3721 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3722 * @hw: pointer to the HW structure
3723 * @offset: The offset (in bytes) of the dword to read.
3724 * @data: Pointer to the dword to store the value read.
3725 *
3726 * Reads a byte or word from the NVM using the flash access registers.
3727 **/
3728
e1000_read_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3729 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3730 u32 *data)
3731 {
3732 union ich8_hws_flash_status hsfsts;
3733 union ich8_hws_flash_ctrl hsflctl;
3734 u32 flash_linear_addr;
3735 s32 ret_val = -E1000_ERR_NVM;
3736 u8 count = 0;
3737
3738 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3739 return -E1000_ERR_NVM;
3740 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3741 hw->nvm.flash_base_addr);
3742
3743 do {
3744 udelay(1);
3745 /* Steps */
3746 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3747 if (ret_val)
3748 break;
3749 /* In SPT, This register is in Lan memory space, not flash.
3750 * Therefore, only 32 bit access is supported
3751 */
3752 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3753
3754 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3755 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3756 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3757 /* In SPT, This register is in Lan memory space, not flash.
3758 * Therefore, only 32 bit access is supported
3759 */
3760 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3761 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3762
3763 ret_val =
3764 e1000_flash_cycle_ich8lan(hw,
3765 ICH_FLASH_READ_COMMAND_TIMEOUT);
3766
3767 /* Check if FCERR is set to 1, if set to 1, clear it
3768 * and try the whole sequence a few more times, else
3769 * read in (shift in) the Flash Data0, the order is
3770 * least significant byte first msb to lsb
3771 */
3772 if (!ret_val) {
3773 *data = er32flash(ICH_FLASH_FDATA0);
3774 break;
3775 } else {
3776 /* If we've gotten here, then things are probably
3777 * completely hosed, but if the error condition is
3778 * detected, it won't hurt to give it another try...
3779 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3780 */
3781 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3782 if (hsfsts.hsf_status.flcerr) {
3783 /* Repeat for some time before giving up. */
3784 continue;
3785 } else if (!hsfsts.hsf_status.flcdone) {
3786 e_dbg("Timeout error - flash cycle did not complete.\n");
3787 break;
3788 }
3789 }
3790 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3791
3792 return ret_val;
3793 }
3794
3795 /**
3796 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3797 * @hw: pointer to the HW structure
3798 * @offset: The offset (in bytes) of the word(s) to write.
3799 * @words: Size of data to write in words
3800 * @data: Pointer to the word(s) to write at offset.
3801 *
3802 * Writes a byte or word to the NVM using the flash access registers.
3803 **/
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3804 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3805 u16 *data)
3806 {
3807 struct e1000_nvm_info *nvm = &hw->nvm;
3808 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3809 u16 i;
3810
3811 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3812 (words == 0)) {
3813 e_dbg("nvm parameter(s) out of bounds\n");
3814 return -E1000_ERR_NVM;
3815 }
3816
3817 nvm->ops.acquire(hw);
3818
3819 for (i = 0; i < words; i++) {
3820 dev_spec->shadow_ram[offset + i].modified = true;
3821 dev_spec->shadow_ram[offset + i].value = data[i];
3822 }
3823
3824 nvm->ops.release(hw);
3825
3826 return 0;
3827 }
3828
3829 /**
3830 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3831 * @hw: pointer to the HW structure
3832 *
3833 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3834 * which writes the checksum to the shadow ram. The changes in the shadow
3835 * ram are then committed to the EEPROM by processing each bank at a time
3836 * checking for the modified bit and writing only the pending changes.
3837 * After a successful commit, the shadow ram is cleared and is ready for
3838 * future writes.
3839 **/
e1000_update_nvm_checksum_spt(struct e1000_hw * hw)3840 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3841 {
3842 struct e1000_nvm_info *nvm = &hw->nvm;
3843 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3844 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3845 s32 ret_val;
3846 u32 dword = 0;
3847
3848 ret_val = e1000e_update_nvm_checksum_generic(hw);
3849 if (ret_val)
3850 goto out;
3851
3852 if (nvm->type != e1000_nvm_flash_sw)
3853 goto out;
3854
3855 nvm->ops.acquire(hw);
3856
3857 /* We're writing to the opposite bank so if we're on bank 1,
3858 * write to bank 0 etc. We also need to erase the segment that
3859 * is going to be written
3860 */
3861 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3862 if (ret_val) {
3863 e_dbg("Could not detect valid bank, assuming bank 0\n");
3864 bank = 0;
3865 }
3866
3867 if (bank == 0) {
3868 new_bank_offset = nvm->flash_bank_size;
3869 old_bank_offset = 0;
3870 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3871 if (ret_val)
3872 goto release;
3873 } else {
3874 old_bank_offset = nvm->flash_bank_size;
3875 new_bank_offset = 0;
3876 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3877 if (ret_val)
3878 goto release;
3879 }
3880 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3881 /* Determine whether to write the value stored
3882 * in the other NVM bank or a modified value stored
3883 * in the shadow RAM
3884 */
3885 ret_val = e1000_read_flash_dword_ich8lan(hw,
3886 i + old_bank_offset,
3887 &dword);
3888
3889 if (dev_spec->shadow_ram[i].modified) {
3890 dword &= 0xffff0000;
3891 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3892 }
3893 if (dev_spec->shadow_ram[i + 1].modified) {
3894 dword &= 0x0000ffff;
3895 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3896 << 16);
3897 }
3898 if (ret_val)
3899 break;
3900
3901 /* If the word is 0x13, then make sure the signature bits
3902 * (15:14) are 11b until the commit has completed.
3903 * This will allow us to write 10b which indicates the
3904 * signature is valid. We want to do this after the write
3905 * has completed so that we don't mark the segment valid
3906 * while the write is still in progress
3907 */
3908 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3909 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3910
3911 /* Convert offset to bytes. */
3912 act_offset = (i + new_bank_offset) << 1;
3913
3914 usleep_range(100, 200);
3915
3916 /* Write the data to the new bank. Offset in words */
3917 act_offset = i + new_bank_offset;
3918 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3919 dword);
3920 if (ret_val)
3921 break;
3922 }
3923
3924 /* Don't bother writing the segment valid bits if sector
3925 * programming failed.
3926 */
3927 if (ret_val) {
3928 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3929 e_dbg("Flash commit failed.\n");
3930 goto release;
3931 }
3932
3933 /* Finally validate the new segment by setting bit 15:14
3934 * to 10b in word 0x13 , this can be done without an
3935 * erase as well since these bits are 11 to start with
3936 * and we need to change bit 14 to 0b
3937 */
3938 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3939
3940 /*offset in words but we read dword */
3941 --act_offset;
3942 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3943
3944 if (ret_val)
3945 goto release;
3946
3947 dword &= 0xBFFFFFFF;
3948 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3949
3950 if (ret_val)
3951 goto release;
3952
3953 /* offset in words but we read dword */
3954 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3955 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3956
3957 if (ret_val)
3958 goto release;
3959
3960 dword &= 0x00FFFFFF;
3961 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3962
3963 if (ret_val)
3964 goto release;
3965
3966 /* Great! Everything worked, we can now clear the cached entries. */
3967 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3968 dev_spec->shadow_ram[i].modified = false;
3969 dev_spec->shadow_ram[i].value = 0xFFFF;
3970 }
3971
3972 release:
3973 nvm->ops.release(hw);
3974
3975 /* Reload the EEPROM, or else modifications will not appear
3976 * until after the next adapter reset.
3977 */
3978 if (!ret_val) {
3979 nvm->ops.reload(hw);
3980 usleep_range(10000, 11000);
3981 }
3982
3983 out:
3984 if (ret_val)
3985 e_dbg("NVM update error: %d\n", ret_val);
3986
3987 return ret_val;
3988 }
3989
3990 /**
3991 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3992 * @hw: pointer to the HW structure
3993 *
3994 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3995 * which writes the checksum to the shadow ram. The changes in the shadow
3996 * ram are then committed to the EEPROM by processing each bank at a time
3997 * checking for the modified bit and writing only the pending changes.
3998 * After a successful commit, the shadow ram is cleared and is ready for
3999 * future writes.
4000 **/
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)4001 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4002 {
4003 struct e1000_nvm_info *nvm = &hw->nvm;
4004 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4005 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4006 s32 ret_val;
4007 u16 data = 0;
4008
4009 ret_val = e1000e_update_nvm_checksum_generic(hw);
4010 if (ret_val)
4011 goto out;
4012
4013 if (nvm->type != e1000_nvm_flash_sw)
4014 goto out;
4015
4016 nvm->ops.acquire(hw);
4017
4018 /* We're writing to the opposite bank so if we're on bank 1,
4019 * write to bank 0 etc. We also need to erase the segment that
4020 * is going to be written
4021 */
4022 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4023 if (ret_val) {
4024 e_dbg("Could not detect valid bank, assuming bank 0\n");
4025 bank = 0;
4026 }
4027
4028 if (bank == 0) {
4029 new_bank_offset = nvm->flash_bank_size;
4030 old_bank_offset = 0;
4031 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4032 if (ret_val)
4033 goto release;
4034 } else {
4035 old_bank_offset = nvm->flash_bank_size;
4036 new_bank_offset = 0;
4037 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4038 if (ret_val)
4039 goto release;
4040 }
4041 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4042 if (dev_spec->shadow_ram[i].modified) {
4043 data = dev_spec->shadow_ram[i].value;
4044 } else {
4045 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4046 old_bank_offset,
4047 &data);
4048 if (ret_val)
4049 break;
4050 }
4051
4052 /* If the word is 0x13, then make sure the signature bits
4053 * (15:14) are 11b until the commit has completed.
4054 * This will allow us to write 10b which indicates the
4055 * signature is valid. We want to do this after the write
4056 * has completed so that we don't mark the segment valid
4057 * while the write is still in progress
4058 */
4059 if (i == E1000_ICH_NVM_SIG_WORD)
4060 data |= E1000_ICH_NVM_SIG_MASK;
4061
4062 /* Convert offset to bytes. */
4063 act_offset = (i + new_bank_offset) << 1;
4064
4065 usleep_range(100, 200);
4066 /* Write the bytes to the new bank. */
4067 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4068 act_offset,
4069 (u8)data);
4070 if (ret_val)
4071 break;
4072
4073 usleep_range(100, 200);
4074 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4075 act_offset + 1,
4076 (u8)(data >> 8));
4077 if (ret_val)
4078 break;
4079 }
4080
4081 /* Don't bother writing the segment valid bits if sector
4082 * programming failed.
4083 */
4084 if (ret_val) {
4085 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4086 e_dbg("Flash commit failed.\n");
4087 goto release;
4088 }
4089
4090 /* Finally validate the new segment by setting bit 15:14
4091 * to 10b in word 0x13 , this can be done without an
4092 * erase as well since these bits are 11 to start with
4093 * and we need to change bit 14 to 0b
4094 */
4095 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4096 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4097 if (ret_val)
4098 goto release;
4099
4100 data &= 0xBFFF;
4101 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4102 act_offset * 2 + 1,
4103 (u8)(data >> 8));
4104 if (ret_val)
4105 goto release;
4106
4107 /* And invalidate the previously valid segment by setting
4108 * its signature word (0x13) high_byte to 0b. This can be
4109 * done without an erase because flash erase sets all bits
4110 * to 1's. We can write 1's to 0's without an erase
4111 */
4112 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4113 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4114 if (ret_val)
4115 goto release;
4116
4117 /* Great! Everything worked, we can now clear the cached entries. */
4118 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4119 dev_spec->shadow_ram[i].modified = false;
4120 dev_spec->shadow_ram[i].value = 0xFFFF;
4121 }
4122
4123 release:
4124 nvm->ops.release(hw);
4125
4126 /* Reload the EEPROM, or else modifications will not appear
4127 * until after the next adapter reset.
4128 */
4129 if (!ret_val) {
4130 nvm->ops.reload(hw);
4131 usleep_range(10000, 11000);
4132 }
4133
4134 out:
4135 if (ret_val)
4136 e_dbg("NVM update error: %d\n", ret_val);
4137
4138 return ret_val;
4139 }
4140
4141 /**
4142 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4143 * @hw: pointer to the HW structure
4144 *
4145 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4146 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4147 * calculated, in which case we need to calculate the checksum and set bit 6.
4148 **/
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)4149 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4150 {
4151 s32 ret_val;
4152 u16 data;
4153 u16 word;
4154 u16 valid_csum_mask;
4155
4156 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4157 * the checksum needs to be fixed. This bit is an indication that
4158 * the NVM was prepared by OEM software and did not calculate
4159 * the checksum...a likely scenario.
4160 */
4161 switch (hw->mac.type) {
4162 case e1000_pch_lpt:
4163 case e1000_pch_spt:
4164 case e1000_pch_cnp:
4165 case e1000_pch_tgp:
4166 case e1000_pch_adp:
4167 case e1000_pch_mtp:
4168 case e1000_pch_lnp:
4169 case e1000_pch_ptp:
4170 case e1000_pch_nvp:
4171 word = NVM_COMPAT;
4172 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4173 break;
4174 default:
4175 word = NVM_FUTURE_INIT_WORD1;
4176 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4177 break;
4178 }
4179
4180 ret_val = e1000_read_nvm(hw, word, 1, &data);
4181 if (ret_val)
4182 return ret_val;
4183
4184 if (!(data & valid_csum_mask)) {
4185 e_dbg("NVM Checksum valid bit not set\n");
4186
4187 if (hw->mac.type < e1000_pch_tgp) {
4188 data |= valid_csum_mask;
4189 ret_val = e1000_write_nvm(hw, word, 1, &data);
4190 if (ret_val)
4191 return ret_val;
4192 ret_val = e1000e_update_nvm_checksum(hw);
4193 if (ret_val)
4194 return ret_val;
4195 }
4196 }
4197
4198 return e1000e_validate_nvm_checksum_generic(hw);
4199 }
4200
4201 /**
4202 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4203 * @hw: pointer to the HW structure
4204 *
4205 * To prevent malicious write/erase of the NVM, set it to be read-only
4206 * so that the hardware ignores all write/erase cycles of the NVM via
4207 * the flash control registers. The shadow-ram copy of the NVM will
4208 * still be updated, however any updates to this copy will not stick
4209 * across driver reloads.
4210 **/
e1000e_write_protect_nvm_ich8lan(struct e1000_hw * hw)4211 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4212 {
4213 struct e1000_nvm_info *nvm = &hw->nvm;
4214 union ich8_flash_protected_range pr0;
4215 union ich8_hws_flash_status hsfsts;
4216 u32 gfpreg;
4217
4218 nvm->ops.acquire(hw);
4219
4220 gfpreg = er32flash(ICH_FLASH_GFPREG);
4221
4222 /* Write-protect GbE Sector of NVM */
4223 pr0.regval = er32flash(ICH_FLASH_PR0);
4224 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4225 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4226 pr0.range.wpe = true;
4227 ew32flash(ICH_FLASH_PR0, pr0.regval);
4228
4229 /* Lock down a subset of GbE Flash Control Registers, e.g.
4230 * PR0 to prevent the write-protection from being lifted.
4231 * Once FLOCKDN is set, the registers protected by it cannot
4232 * be written until FLOCKDN is cleared by a hardware reset.
4233 */
4234 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4235 hsfsts.hsf_status.flockdn = true;
4236 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4237
4238 nvm->ops.release(hw);
4239 }
4240
4241 /**
4242 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4243 * @hw: pointer to the HW structure
4244 * @offset: The offset (in bytes) of the byte/word to read.
4245 * @size: Size of data to read, 1=byte 2=word
4246 * @data: The byte(s) to write to the NVM.
4247 *
4248 * Writes one/two bytes to the NVM using the flash access registers.
4249 **/
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)4250 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4251 u8 size, u16 data)
4252 {
4253 union ich8_hws_flash_status hsfsts;
4254 union ich8_hws_flash_ctrl hsflctl;
4255 u32 flash_linear_addr;
4256 u32 flash_data = 0;
4257 s32 ret_val;
4258 u8 count = 0;
4259
4260 if (hw->mac.type >= e1000_pch_spt) {
4261 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4262 return -E1000_ERR_NVM;
4263 } else {
4264 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4265 return -E1000_ERR_NVM;
4266 }
4267
4268 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4269 hw->nvm.flash_base_addr);
4270
4271 do {
4272 udelay(1);
4273 /* Steps */
4274 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4275 if (ret_val)
4276 break;
4277 /* In SPT, This register is in Lan memory space, not
4278 * flash. Therefore, only 32 bit access is supported
4279 */
4280 if (hw->mac.type >= e1000_pch_spt)
4281 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4282 else
4283 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4284
4285 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4286 hsflctl.hsf_ctrl.fldbcount = size - 1;
4287 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4288 /* In SPT, This register is in Lan memory space,
4289 * not flash. Therefore, only 32 bit access is
4290 * supported
4291 */
4292 if (hw->mac.type >= e1000_pch_spt)
4293 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4294 else
4295 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4296
4297 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4298
4299 if (size == 1)
4300 flash_data = (u32)data & 0x00FF;
4301 else
4302 flash_data = (u32)data;
4303
4304 ew32flash(ICH_FLASH_FDATA0, flash_data);
4305
4306 /* check if FCERR is set to 1 , if set to 1, clear it
4307 * and try the whole sequence a few more times else done
4308 */
4309 ret_val =
4310 e1000_flash_cycle_ich8lan(hw,
4311 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4312 if (!ret_val)
4313 break;
4314
4315 /* If we're here, then things are most likely
4316 * completely hosed, but if the error condition
4317 * is detected, it won't hurt to give it another
4318 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4319 */
4320 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4321 if (hsfsts.hsf_status.flcerr)
4322 /* Repeat for some time before giving up. */
4323 continue;
4324 if (!hsfsts.hsf_status.flcdone) {
4325 e_dbg("Timeout error - flash cycle did not complete.\n");
4326 break;
4327 }
4328 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4329
4330 return ret_val;
4331 }
4332
4333 /**
4334 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4335 * @hw: pointer to the HW structure
4336 * @offset: The offset (in bytes) of the dwords to read.
4337 * @data: The 4 bytes to write to the NVM.
4338 *
4339 * Writes one/two/four bytes to the NVM using the flash access registers.
4340 **/
e1000_write_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 data)4341 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4342 u32 data)
4343 {
4344 union ich8_hws_flash_status hsfsts;
4345 union ich8_hws_flash_ctrl hsflctl;
4346 u32 flash_linear_addr;
4347 s32 ret_val;
4348 u8 count = 0;
4349
4350 if (hw->mac.type >= e1000_pch_spt) {
4351 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4352 return -E1000_ERR_NVM;
4353 }
4354 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4355 hw->nvm.flash_base_addr);
4356 do {
4357 udelay(1);
4358 /* Steps */
4359 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4360 if (ret_val)
4361 break;
4362
4363 /* In SPT, This register is in Lan memory space, not
4364 * flash. Therefore, only 32 bit access is supported
4365 */
4366 if (hw->mac.type >= e1000_pch_spt)
4367 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4368 >> 16;
4369 else
4370 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4371
4372 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4373 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4374
4375 /* In SPT, This register is in Lan memory space,
4376 * not flash. Therefore, only 32 bit access is
4377 * supported
4378 */
4379 if (hw->mac.type >= e1000_pch_spt)
4380 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4381 else
4382 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4383
4384 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4385
4386 ew32flash(ICH_FLASH_FDATA0, data);
4387
4388 /* check if FCERR is set to 1 , if set to 1, clear it
4389 * and try the whole sequence a few more times else done
4390 */
4391 ret_val =
4392 e1000_flash_cycle_ich8lan(hw,
4393 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4394
4395 if (!ret_val)
4396 break;
4397
4398 /* If we're here, then things are most likely
4399 * completely hosed, but if the error condition
4400 * is detected, it won't hurt to give it another
4401 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4402 */
4403 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4404
4405 if (hsfsts.hsf_status.flcerr)
4406 /* Repeat for some time before giving up. */
4407 continue;
4408 if (!hsfsts.hsf_status.flcdone) {
4409 e_dbg("Timeout error - flash cycle did not complete.\n");
4410 break;
4411 }
4412 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4413
4414 return ret_val;
4415 }
4416
4417 /**
4418 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4419 * @hw: pointer to the HW structure
4420 * @offset: The index of the byte to read.
4421 * @data: The byte to write to the NVM.
4422 *
4423 * Writes a single byte to the NVM using the flash access registers.
4424 **/
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)4425 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4426 u8 data)
4427 {
4428 u16 word = (u16)data;
4429
4430 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4431 }
4432
4433 /**
4434 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4435 * @hw: pointer to the HW structure
4436 * @offset: The offset of the word to write.
4437 * @dword: The dword to write to the NVM.
4438 *
4439 * Writes a single dword to the NVM using the flash access registers.
4440 * Goes through a retry algorithm before giving up.
4441 **/
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 dword)4442 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4443 u32 offset, u32 dword)
4444 {
4445 s32 ret_val;
4446 u16 program_retries;
4447
4448 /* Must convert word offset into bytes. */
4449 offset <<= 1;
4450 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4451
4452 if (!ret_val)
4453 return ret_val;
4454 for (program_retries = 0; program_retries < 100; program_retries++) {
4455 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4456 usleep_range(100, 200);
4457 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4458 if (!ret_val)
4459 break;
4460 }
4461 if (program_retries == 100)
4462 return -E1000_ERR_NVM;
4463
4464 return 0;
4465 }
4466
4467 /**
4468 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4469 * @hw: pointer to the HW structure
4470 * @offset: The offset of the byte to write.
4471 * @byte: The byte to write to the NVM.
4472 *
4473 * Writes a single byte to the NVM using the flash access registers.
4474 * Goes through a retry algorithm before giving up.
4475 **/
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)4476 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4477 u32 offset, u8 byte)
4478 {
4479 s32 ret_val;
4480 u16 program_retries;
4481
4482 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4483 if (!ret_val)
4484 return ret_val;
4485
4486 for (program_retries = 0; program_retries < 100; program_retries++) {
4487 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4488 usleep_range(100, 200);
4489 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4490 if (!ret_val)
4491 break;
4492 }
4493 if (program_retries == 100)
4494 return -E1000_ERR_NVM;
4495
4496 return 0;
4497 }
4498
4499 /**
4500 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4501 * @hw: pointer to the HW structure
4502 * @bank: 0 for first bank, 1 for second bank, etc.
4503 *
4504 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4505 * bank N is 4096 * N + flash_reg_addr.
4506 **/
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)4507 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4508 {
4509 struct e1000_nvm_info *nvm = &hw->nvm;
4510 union ich8_hws_flash_status hsfsts;
4511 union ich8_hws_flash_ctrl hsflctl;
4512 u32 flash_linear_addr;
4513 /* bank size is in 16bit words - adjust to bytes */
4514 u32 flash_bank_size = nvm->flash_bank_size * 2;
4515 s32 ret_val;
4516 s32 count = 0;
4517 s32 j, iteration, sector_size;
4518
4519 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4520
4521 /* Determine HW Sector size: Read BERASE bits of hw flash status
4522 * register
4523 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4524 * consecutive sectors. The start index for the nth Hw sector
4525 * can be calculated as = bank * 4096 + n * 256
4526 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4527 * The start index for the nth Hw sector can be calculated
4528 * as = bank * 4096
4529 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4530 * (ich9 only, otherwise error condition)
4531 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4532 */
4533 switch (hsfsts.hsf_status.berasesz) {
4534 case 0:
4535 /* Hw sector size 256 */
4536 sector_size = ICH_FLASH_SEG_SIZE_256;
4537 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4538 break;
4539 case 1:
4540 sector_size = ICH_FLASH_SEG_SIZE_4K;
4541 iteration = 1;
4542 break;
4543 case 2:
4544 sector_size = ICH_FLASH_SEG_SIZE_8K;
4545 iteration = 1;
4546 break;
4547 case 3:
4548 sector_size = ICH_FLASH_SEG_SIZE_64K;
4549 iteration = 1;
4550 break;
4551 default:
4552 return -E1000_ERR_NVM;
4553 }
4554
4555 /* Start with the base address, then add the sector offset. */
4556 flash_linear_addr = hw->nvm.flash_base_addr;
4557 flash_linear_addr += (bank) ? flash_bank_size : 0;
4558
4559 for (j = 0; j < iteration; j++) {
4560 do {
4561 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4562
4563 /* Steps */
4564 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4565 if (ret_val)
4566 return ret_val;
4567
4568 /* Write a value 11 (block Erase) in Flash
4569 * Cycle field in hw flash control
4570 */
4571 if (hw->mac.type >= e1000_pch_spt)
4572 hsflctl.regval =
4573 er32flash(ICH_FLASH_HSFSTS) >> 16;
4574 else
4575 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4576
4577 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4578 if (hw->mac.type >= e1000_pch_spt)
4579 ew32flash(ICH_FLASH_HSFSTS,
4580 hsflctl.regval << 16);
4581 else
4582 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4583
4584 /* Write the last 24 bits of an index within the
4585 * block into Flash Linear address field in Flash
4586 * Address.
4587 */
4588 flash_linear_addr += (j * sector_size);
4589 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4590
4591 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4592 if (!ret_val)
4593 break;
4594
4595 /* Check if FCERR is set to 1. If 1,
4596 * clear it and try the whole sequence
4597 * a few more times else Done
4598 */
4599 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4600 if (hsfsts.hsf_status.flcerr)
4601 /* repeat for some time before giving up */
4602 continue;
4603 else if (!hsfsts.hsf_status.flcdone)
4604 return ret_val;
4605 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4606 }
4607
4608 return 0;
4609 }
4610
4611 /**
4612 * e1000_valid_led_default_ich8lan - Set the default LED settings
4613 * @hw: pointer to the HW structure
4614 * @data: Pointer to the LED settings
4615 *
4616 * Reads the LED default settings from the NVM to data. If the NVM LED
4617 * settings is all 0's or F's, set the LED default to a valid LED default
4618 * setting.
4619 **/
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)4620 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4621 {
4622 s32 ret_val;
4623
4624 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4625 if (ret_val) {
4626 e_dbg("NVM Read Error\n");
4627 return ret_val;
4628 }
4629
4630 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4631 *data = ID_LED_DEFAULT_ICH8LAN;
4632
4633 return 0;
4634 }
4635
4636 /**
4637 * e1000_id_led_init_pchlan - store LED configurations
4638 * @hw: pointer to the HW structure
4639 *
4640 * PCH does not control LEDs via the LEDCTL register, rather it uses
4641 * the PHY LED configuration register.
4642 *
4643 * PCH also does not have an "always on" or "always off" mode which
4644 * complicates the ID feature. Instead of using the "on" mode to indicate
4645 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4646 * use "link_up" mode. The LEDs will still ID on request if there is no
4647 * link based on logic in e1000_led_[on|off]_pchlan().
4648 **/
e1000_id_led_init_pchlan(struct e1000_hw * hw)4649 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4650 {
4651 struct e1000_mac_info *mac = &hw->mac;
4652 s32 ret_val;
4653 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4654 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4655 u16 data, i, temp, shift;
4656
4657 /* Get default ID LED modes */
4658 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4659 if (ret_val)
4660 return ret_val;
4661
4662 mac->ledctl_default = er32(LEDCTL);
4663 mac->ledctl_mode1 = mac->ledctl_default;
4664 mac->ledctl_mode2 = mac->ledctl_default;
4665
4666 for (i = 0; i < 4; i++) {
4667 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4668 shift = (i * 5);
4669 switch (temp) {
4670 case ID_LED_ON1_DEF2:
4671 case ID_LED_ON1_ON2:
4672 case ID_LED_ON1_OFF2:
4673 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4674 mac->ledctl_mode1 |= (ledctl_on << shift);
4675 break;
4676 case ID_LED_OFF1_DEF2:
4677 case ID_LED_OFF1_ON2:
4678 case ID_LED_OFF1_OFF2:
4679 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4680 mac->ledctl_mode1 |= (ledctl_off << shift);
4681 break;
4682 default:
4683 /* Do nothing */
4684 break;
4685 }
4686 switch (temp) {
4687 case ID_LED_DEF1_ON2:
4688 case ID_LED_ON1_ON2:
4689 case ID_LED_OFF1_ON2:
4690 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4691 mac->ledctl_mode2 |= (ledctl_on << shift);
4692 break;
4693 case ID_LED_DEF1_OFF2:
4694 case ID_LED_ON1_OFF2:
4695 case ID_LED_OFF1_OFF2:
4696 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4697 mac->ledctl_mode2 |= (ledctl_off << shift);
4698 break;
4699 default:
4700 /* Do nothing */
4701 break;
4702 }
4703 }
4704
4705 return 0;
4706 }
4707
4708 /**
4709 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4710 * @hw: pointer to the HW structure
4711 *
4712 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4713 * register, so the bus width is hard coded.
4714 **/
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)4715 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4716 {
4717 struct e1000_bus_info *bus = &hw->bus;
4718 s32 ret_val;
4719
4720 ret_val = e1000e_get_bus_info_pcie(hw);
4721
4722 /* ICH devices are "PCI Express"-ish. They have
4723 * a configuration space, but do not contain
4724 * PCI Express Capability registers, so bus width
4725 * must be hardcoded.
4726 */
4727 if (bus->width == e1000_bus_width_unknown)
4728 bus->width = e1000_bus_width_pcie_x1;
4729
4730 return ret_val;
4731 }
4732
4733 /**
4734 * e1000_reset_hw_ich8lan - Reset the hardware
4735 * @hw: pointer to the HW structure
4736 *
4737 * Does a full reset of the hardware which includes a reset of the PHY and
4738 * MAC.
4739 **/
e1000_reset_hw_ich8lan(struct e1000_hw * hw)4740 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4741 {
4742 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4743 u16 kum_cfg;
4744 u32 ctrl, reg;
4745 s32 ret_val;
4746
4747 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4748 * on the last TLP read/write transaction when MAC is reset.
4749 */
4750 ret_val = e1000e_disable_pcie_master(hw);
4751 if (ret_val)
4752 e_dbg("PCI-E Master disable polling has failed.\n");
4753
4754 e_dbg("Masking off all interrupts\n");
4755 ew32(IMC, 0xffffffff);
4756
4757 /* Disable the Transmit and Receive units. Then delay to allow
4758 * any pending transactions to complete before we hit the MAC
4759 * with the global reset.
4760 */
4761 ew32(RCTL, 0);
4762 ew32(TCTL, E1000_TCTL_PSP);
4763 e1e_flush();
4764
4765 usleep_range(10000, 11000);
4766
4767 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4768 if (hw->mac.type == e1000_ich8lan) {
4769 /* Set Tx and Rx buffer allocation to 8k apiece. */
4770 ew32(PBA, E1000_PBA_8K);
4771 /* Set Packet Buffer Size to 16k. */
4772 ew32(PBS, E1000_PBS_16K);
4773 }
4774
4775 if (hw->mac.type == e1000_pchlan) {
4776 /* Save the NVM K1 bit setting */
4777 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4778 if (ret_val)
4779 return ret_val;
4780
4781 if (kum_cfg & E1000_NVM_K1_ENABLE)
4782 dev_spec->nvm_k1_enabled = true;
4783 else
4784 dev_spec->nvm_k1_enabled = false;
4785 }
4786
4787 ctrl = er32(CTRL);
4788
4789 if (!hw->phy.ops.check_reset_block(hw)) {
4790 /* Full-chip reset requires MAC and PHY reset at the same
4791 * time to make sure the interface between MAC and the
4792 * external PHY is reset.
4793 */
4794 ctrl |= E1000_CTRL_PHY_RST;
4795
4796 /* Gate automatic PHY configuration by hardware on
4797 * non-managed 82579
4798 */
4799 if ((hw->mac.type == e1000_pch2lan) &&
4800 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4801 e1000_gate_hw_phy_config_ich8lan(hw, true);
4802 }
4803 ret_val = e1000_acquire_swflag_ich8lan(hw);
4804 e_dbg("Issuing a global reset to ich8lan\n");
4805 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4806 /* cannot issue a flush here because it hangs the hardware */
4807 msleep(20);
4808
4809 /* Set Phy Config Counter to 50msec */
4810 if (hw->mac.type == e1000_pch2lan) {
4811 reg = er32(FEXTNVM3);
4812 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4813 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4814 ew32(FEXTNVM3, reg);
4815 }
4816
4817 if (!ret_val)
4818 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4819
4820 if (ctrl & E1000_CTRL_PHY_RST) {
4821 ret_val = hw->phy.ops.get_cfg_done(hw);
4822 if (ret_val)
4823 return ret_val;
4824
4825 ret_val = e1000_post_phy_reset_ich8lan(hw);
4826 if (ret_val)
4827 return ret_val;
4828 }
4829
4830 /* For PCH, this write will make sure that any noise
4831 * will be detected as a CRC error and be dropped rather than show up
4832 * as a bad packet to the DMA engine.
4833 */
4834 if (hw->mac.type == e1000_pchlan)
4835 ew32(CRC_OFFSET, 0x65656565);
4836
4837 ew32(IMC, 0xffffffff);
4838 er32(ICR);
4839
4840 reg = er32(KABGTXD);
4841 reg |= E1000_KABGTXD_BGSQLBIAS;
4842 ew32(KABGTXD, reg);
4843
4844 return 0;
4845 }
4846
4847 /**
4848 * e1000_init_hw_ich8lan - Initialize the hardware
4849 * @hw: pointer to the HW structure
4850 *
4851 * Prepares the hardware for transmit and receive by doing the following:
4852 * - initialize hardware bits
4853 * - initialize LED identification
4854 * - setup receive address registers
4855 * - setup flow control
4856 * - setup transmit descriptors
4857 * - clear statistics
4858 **/
e1000_init_hw_ich8lan(struct e1000_hw * hw)4859 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4860 {
4861 struct e1000_mac_info *mac = &hw->mac;
4862 u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4863 s32 ret_val;
4864 u16 i;
4865
4866 e1000_initialize_hw_bits_ich8lan(hw);
4867
4868 /* Initialize identification LED */
4869 ret_val = mac->ops.id_led_init(hw);
4870 /* An error is not fatal and we should not stop init due to this */
4871 if (ret_val)
4872 e_dbg("Error initializing identification LED\n");
4873
4874 /* Setup the receive address. */
4875 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4876
4877 /* Zero out the Multicast HASH table */
4878 e_dbg("Zeroing the MTA\n");
4879 for (i = 0; i < mac->mta_reg_count; i++)
4880 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4881
4882 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4883 * the ME. Disable wakeup by clearing the host wakeup bit.
4884 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4885 */
4886 if (hw->phy.type == e1000_phy_82578) {
4887 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4888 i &= ~BM_WUC_HOST_WU_BIT;
4889 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4890 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4891 if (ret_val)
4892 return ret_val;
4893 }
4894
4895 /* Setup link and flow control */
4896 ret_val = mac->ops.setup_link(hw);
4897
4898 /* Set the transmit descriptor write-back policy for both queues */
4899 txdctl = er32(TXDCTL(0));
4900 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4901 E1000_TXDCTL_FULL_TX_DESC_WB);
4902 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4903 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4904 ew32(TXDCTL(0), txdctl);
4905 txdctl = er32(TXDCTL(1));
4906 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4907 E1000_TXDCTL_FULL_TX_DESC_WB);
4908 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4909 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4910 ew32(TXDCTL(1), txdctl);
4911
4912 /* ICH8 has opposite polarity of no_snoop bits.
4913 * By default, we should use snoop behavior.
4914 */
4915 if (mac->type == e1000_ich8lan)
4916 snoop = PCIE_ICH8_SNOOP_ALL;
4917 else
4918 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4919 e1000e_set_pcie_no_snoop(hw, snoop);
4920
4921 /* Enable workaround for packet loss issue on TGP PCH
4922 * Do not gate DMA clock from the modPHY block
4923 */
4924 if (mac->type >= e1000_pch_tgp) {
4925 fflt_dbg = er32(FFLT_DBG);
4926 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4927 ew32(FFLT_DBG, fflt_dbg);
4928 }
4929
4930 ctrl_ext = er32(CTRL_EXT);
4931 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4932 ew32(CTRL_EXT, ctrl_ext);
4933
4934 /* Clear all of the statistics registers (clear on read). It is
4935 * important that we do this after we have tried to establish link
4936 * because the symbol error count will increment wildly if there
4937 * is no link.
4938 */
4939 e1000_clear_hw_cntrs_ich8lan(hw);
4940
4941 return ret_val;
4942 }
4943
4944 /**
4945 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4946 * @hw: pointer to the HW structure
4947 *
4948 * Sets/Clears required hardware bits necessary for correctly setting up the
4949 * hardware for transmit and receive.
4950 **/
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)4951 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4952 {
4953 u32 reg;
4954
4955 /* Extended Device Control */
4956 reg = er32(CTRL_EXT);
4957 reg |= BIT(22);
4958 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4959 if (hw->mac.type >= e1000_pchlan)
4960 reg |= E1000_CTRL_EXT_PHYPDEN;
4961 ew32(CTRL_EXT, reg);
4962
4963 /* Transmit Descriptor Control 0 */
4964 reg = er32(TXDCTL(0));
4965 reg |= BIT(22);
4966 ew32(TXDCTL(0), reg);
4967
4968 /* Transmit Descriptor Control 1 */
4969 reg = er32(TXDCTL(1));
4970 reg |= BIT(22);
4971 ew32(TXDCTL(1), reg);
4972
4973 /* Transmit Arbitration Control 0 */
4974 reg = er32(TARC(0));
4975 if (hw->mac.type == e1000_ich8lan)
4976 reg |= BIT(28) | BIT(29);
4977 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4978 ew32(TARC(0), reg);
4979
4980 /* Transmit Arbitration Control 1 */
4981 reg = er32(TARC(1));
4982 if (er32(TCTL) & E1000_TCTL_MULR)
4983 reg &= ~BIT(28);
4984 else
4985 reg |= BIT(28);
4986 reg |= BIT(24) | BIT(26) | BIT(30);
4987 ew32(TARC(1), reg);
4988
4989 /* Device Status */
4990 if (hw->mac.type == e1000_ich8lan) {
4991 reg = er32(STATUS);
4992 reg &= ~BIT(31);
4993 ew32(STATUS, reg);
4994 }
4995
4996 /* work-around descriptor data corruption issue during nfs v2 udp
4997 * traffic, just disable the nfs filtering capability
4998 */
4999 reg = er32(RFCTL);
5000 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5001
5002 /* Disable IPv6 extension header parsing because some malformed
5003 * IPv6 headers can hang the Rx.
5004 */
5005 if (hw->mac.type == e1000_ich8lan)
5006 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5007 ew32(RFCTL, reg);
5008
5009 /* Enable ECC on Lynxpoint */
5010 if (hw->mac.type >= e1000_pch_lpt) {
5011 reg = er32(PBECCSTS);
5012 reg |= E1000_PBECCSTS_ECC_ENABLE;
5013 ew32(PBECCSTS, reg);
5014
5015 reg = er32(CTRL);
5016 reg |= E1000_CTRL_MEHE;
5017 ew32(CTRL, reg);
5018 }
5019 }
5020
5021 /**
5022 * e1000_setup_link_ich8lan - Setup flow control and link settings
5023 * @hw: pointer to the HW structure
5024 *
5025 * Determines which flow control settings to use, then configures flow
5026 * control. Calls the appropriate media-specific link configuration
5027 * function. Assuming the adapter has a valid link partner, a valid link
5028 * should be established. Assumes the hardware has previously been reset
5029 * and the transmitter and receiver are not enabled.
5030 **/
e1000_setup_link_ich8lan(struct e1000_hw * hw)5031 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5032 {
5033 s32 ret_val;
5034
5035 if (hw->phy.ops.check_reset_block(hw))
5036 return 0;
5037
5038 /* ICH parts do not have a word in the NVM to determine
5039 * the default flow control setting, so we explicitly
5040 * set it to full.
5041 */
5042 if (hw->fc.requested_mode == e1000_fc_default) {
5043 /* Workaround h/w hang when Tx flow control enabled */
5044 if (hw->mac.type == e1000_pchlan)
5045 hw->fc.requested_mode = e1000_fc_rx_pause;
5046 else
5047 hw->fc.requested_mode = e1000_fc_full;
5048 }
5049
5050 /* Save off the requested flow control mode for use later. Depending
5051 * on the link partner's capabilities, we may or may not use this mode.
5052 */
5053 hw->fc.current_mode = hw->fc.requested_mode;
5054
5055 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5056
5057 /* Continue to configure the copper link. */
5058 ret_val = hw->mac.ops.setup_physical_interface(hw);
5059 if (ret_val)
5060 return ret_val;
5061
5062 ew32(FCTTV, hw->fc.pause_time);
5063 if ((hw->phy.type == e1000_phy_82578) ||
5064 (hw->phy.type == e1000_phy_82579) ||
5065 (hw->phy.type == e1000_phy_i217) ||
5066 (hw->phy.type == e1000_phy_82577)) {
5067 ew32(FCRTV_PCH, hw->fc.refresh_time);
5068
5069 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5070 hw->fc.pause_time);
5071 if (ret_val)
5072 return ret_val;
5073 }
5074
5075 return e1000e_set_fc_watermarks(hw);
5076 }
5077
5078 /**
5079 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5080 * @hw: pointer to the HW structure
5081 *
5082 * Configures the kumeran interface to the PHY to wait the appropriate time
5083 * when polling the PHY, then call the generic setup_copper_link to finish
5084 * configuring the copper link.
5085 **/
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)5086 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5087 {
5088 u32 ctrl;
5089 s32 ret_val;
5090 u16 reg_data;
5091
5092 ctrl = er32(CTRL);
5093 ctrl |= E1000_CTRL_SLU;
5094 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5095 ew32(CTRL, ctrl);
5096
5097 /* Set the mac to wait the maximum time between each iteration
5098 * and increase the max iterations when polling the phy;
5099 * this fixes erroneous timeouts at 10Mbps.
5100 */
5101 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5102 if (ret_val)
5103 return ret_val;
5104 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5105 ®_data);
5106 if (ret_val)
5107 return ret_val;
5108 reg_data |= 0x3F;
5109 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5110 reg_data);
5111 if (ret_val)
5112 return ret_val;
5113
5114 switch (hw->phy.type) {
5115 case e1000_phy_igp_3:
5116 ret_val = e1000e_copper_link_setup_igp(hw);
5117 if (ret_val)
5118 return ret_val;
5119 break;
5120 case e1000_phy_bm:
5121 case e1000_phy_82578:
5122 ret_val = e1000e_copper_link_setup_m88(hw);
5123 if (ret_val)
5124 return ret_val;
5125 break;
5126 case e1000_phy_82577:
5127 case e1000_phy_82579:
5128 ret_val = e1000_copper_link_setup_82577(hw);
5129 if (ret_val)
5130 return ret_val;
5131 break;
5132 case e1000_phy_ife:
5133 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5134 if (ret_val)
5135 return ret_val;
5136
5137 reg_data &= ~IFE_PMC_AUTO_MDIX;
5138
5139 switch (hw->phy.mdix) {
5140 case 1:
5141 reg_data &= ~IFE_PMC_FORCE_MDIX;
5142 break;
5143 case 2:
5144 reg_data |= IFE_PMC_FORCE_MDIX;
5145 break;
5146 case 0:
5147 default:
5148 reg_data |= IFE_PMC_AUTO_MDIX;
5149 break;
5150 }
5151 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5152 if (ret_val)
5153 return ret_val;
5154 break;
5155 default:
5156 break;
5157 }
5158
5159 return e1000e_setup_copper_link(hw);
5160 }
5161
5162 /**
5163 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5164 * @hw: pointer to the HW structure
5165 *
5166 * Calls the PHY specific link setup function and then calls the
5167 * generic setup_copper_link to finish configuring the link for
5168 * Lynxpoint PCH devices
5169 **/
e1000_setup_copper_link_pch_lpt(struct e1000_hw * hw)5170 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5171 {
5172 u32 ctrl;
5173 s32 ret_val;
5174
5175 ctrl = er32(CTRL);
5176 ctrl |= E1000_CTRL_SLU;
5177 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5178 ew32(CTRL, ctrl);
5179
5180 ret_val = e1000_copper_link_setup_82577(hw);
5181 if (ret_val)
5182 return ret_val;
5183
5184 return e1000e_setup_copper_link(hw);
5185 }
5186
5187 /**
5188 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5189 * @hw: pointer to the HW structure
5190 * @speed: pointer to store current link speed
5191 * @duplex: pointer to store the current link duplex
5192 *
5193 * Calls the generic get_speed_and_duplex to retrieve the current link
5194 * information and then calls the Kumeran lock loss workaround for links at
5195 * gigabit speeds.
5196 **/
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)5197 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5198 u16 *duplex)
5199 {
5200 s32 ret_val;
5201
5202 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5203 if (ret_val)
5204 return ret_val;
5205
5206 if ((hw->mac.type == e1000_ich8lan) &&
5207 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5208 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5209 }
5210
5211 return ret_val;
5212 }
5213
5214 /**
5215 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5216 * @hw: pointer to the HW structure
5217 *
5218 * Work-around for 82566 Kumeran PCS lock loss:
5219 * On link status change (i.e. PCI reset, speed change) and link is up and
5220 * speed is gigabit-
5221 * 0) if workaround is optionally disabled do nothing
5222 * 1) wait 1ms for Kumeran link to come up
5223 * 2) check Kumeran Diagnostic register PCS lock loss bit
5224 * 3) if not set the link is locked (all is good), otherwise...
5225 * 4) reset the PHY
5226 * 5) repeat up to 10 times
5227 * Note: this is only called for IGP3 copper when speed is 1gb.
5228 **/
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)5229 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5230 {
5231 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5232 u32 phy_ctrl;
5233 s32 ret_val;
5234 u16 i, data;
5235 bool link;
5236
5237 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5238 return 0;
5239
5240 /* Make sure link is up before proceeding. If not just return.
5241 * Attempting this while link is negotiating fouled up link
5242 * stability
5243 */
5244 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5245 if (!link)
5246 return 0;
5247
5248 for (i = 0; i < 10; i++) {
5249 /* read once to clear */
5250 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5251 if (ret_val)
5252 return ret_val;
5253 /* and again to get new status */
5254 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5255 if (ret_val)
5256 return ret_val;
5257
5258 /* check for PCS lock */
5259 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5260 return 0;
5261
5262 /* Issue PHY reset */
5263 e1000_phy_hw_reset(hw);
5264 mdelay(5);
5265 }
5266 /* Disable GigE link negotiation */
5267 phy_ctrl = er32(PHY_CTRL);
5268 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5269 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5270 ew32(PHY_CTRL, phy_ctrl);
5271
5272 /* Call gig speed drop workaround on Gig disable before accessing
5273 * any PHY registers
5274 */
5275 e1000e_gig_downshift_workaround_ich8lan(hw);
5276
5277 /* unable to acquire PCS lock */
5278 return -E1000_ERR_PHY;
5279 }
5280
5281 /**
5282 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5283 * @hw: pointer to the HW structure
5284 * @state: boolean value used to set the current Kumeran workaround state
5285 *
5286 * If ICH8, set the current Kumeran workaround state (enabled - true
5287 * /disabled - false).
5288 **/
e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)5289 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5290 bool state)
5291 {
5292 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5293
5294 if (hw->mac.type != e1000_ich8lan) {
5295 e_dbg("Workaround applies to ICH8 only.\n");
5296 return;
5297 }
5298
5299 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5300 }
5301
5302 /**
5303 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5304 * @hw: pointer to the HW structure
5305 *
5306 * Workaround for 82566 power-down on D3 entry:
5307 * 1) disable gigabit link
5308 * 2) write VR power-down enable
5309 * 3) read it back
5310 * Continue if successful, else issue LCD reset and repeat
5311 **/
e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)5312 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5313 {
5314 u32 reg;
5315 u16 data;
5316 u8 retry = 0;
5317
5318 if (hw->phy.type != e1000_phy_igp_3)
5319 return;
5320
5321 /* Try the workaround twice (if needed) */
5322 do {
5323 /* Disable link */
5324 reg = er32(PHY_CTRL);
5325 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5326 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5327 ew32(PHY_CTRL, reg);
5328
5329 /* Call gig speed drop workaround on Gig disable before
5330 * accessing any PHY registers
5331 */
5332 if (hw->mac.type == e1000_ich8lan)
5333 e1000e_gig_downshift_workaround_ich8lan(hw);
5334
5335 /* Write VR power-down enable */
5336 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5337 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5338 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5339
5340 /* Read it back and test */
5341 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5342 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5343 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5344 break;
5345
5346 /* Issue PHY reset and repeat at most one more time */
5347 reg = er32(CTRL);
5348 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5349 retry++;
5350 } while (retry);
5351 }
5352
5353 /**
5354 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5355 * @hw: pointer to the HW structure
5356 *
5357 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5358 * LPLU, Gig disable, MDIC PHY reset):
5359 * 1) Set Kumeran Near-end loopback
5360 * 2) Clear Kumeran Near-end loopback
5361 * Should only be called for ICH8[m] devices with any 1G Phy.
5362 **/
e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)5363 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5364 {
5365 s32 ret_val;
5366 u16 reg_data;
5367
5368 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5369 return;
5370
5371 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5372 ®_data);
5373 if (ret_val)
5374 return;
5375 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5376 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5377 reg_data);
5378 if (ret_val)
5379 return;
5380 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5381 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5382 }
5383
5384 /**
5385 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5386 * @hw: pointer to the HW structure
5387 *
5388 * During S0 to Sx transition, it is possible the link remains at gig
5389 * instead of negotiating to a lower speed. Before going to Sx, set
5390 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5391 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5392 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5393 * needs to be written.
5394 * Parts that support (and are linked to a partner which support) EEE in
5395 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5396 * than 10Mbps w/o EEE.
5397 **/
e1000_suspend_workarounds_ich8lan(struct e1000_hw * hw)5398 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5399 {
5400 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5401 u32 phy_ctrl;
5402 s32 ret_val;
5403
5404 phy_ctrl = er32(PHY_CTRL);
5405 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5406
5407 if (hw->phy.type == e1000_phy_i217) {
5408 u16 phy_reg, device_id = hw->adapter->pdev->device;
5409
5410 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5411 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5412 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5413 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5414 (hw->mac.type >= e1000_pch_spt)) {
5415 u32 fextnvm6 = er32(FEXTNVM6);
5416
5417 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5418 }
5419
5420 ret_val = hw->phy.ops.acquire(hw);
5421 if (ret_val)
5422 goto out;
5423
5424 if (!dev_spec->eee_disable) {
5425 u16 eee_advert;
5426
5427 ret_val =
5428 e1000_read_emi_reg_locked(hw,
5429 I217_EEE_ADVERTISEMENT,
5430 &eee_advert);
5431 if (ret_val)
5432 goto release;
5433
5434 /* Disable LPLU if both link partners support 100BaseT
5435 * EEE and 100Full is advertised on both ends of the
5436 * link, and enable Auto Enable LPI since there will
5437 * be no driver to enable LPI while in Sx.
5438 */
5439 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5440 (dev_spec->eee_lp_ability &
5441 I82579_EEE_100_SUPPORTED) &&
5442 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5443 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5444 E1000_PHY_CTRL_NOND0A_LPLU);
5445
5446 /* Set Auto Enable LPI after link up */
5447 e1e_rphy_locked(hw,
5448 I217_LPI_GPIO_CTRL, &phy_reg);
5449 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5450 e1e_wphy_locked(hw,
5451 I217_LPI_GPIO_CTRL, phy_reg);
5452 }
5453 }
5454
5455 /* For i217 Intel Rapid Start Technology support,
5456 * when the system is going into Sx and no manageability engine
5457 * is present, the driver must configure proxy to reset only on
5458 * power good. LPI (Low Power Idle) state must also reset only
5459 * on power good, as well as the MTA (Multicast table array).
5460 * The SMBus release must also be disabled on LCD reset.
5461 */
5462 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5463 /* Enable proxy to reset only on power good. */
5464 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5465 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5466 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5467
5468 /* Set bit enable LPI (EEE) to reset only on
5469 * power good.
5470 */
5471 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5472 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5473 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5474
5475 /* Disable the SMB release on LCD reset. */
5476 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5477 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5478 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5479 }
5480
5481 /* Enable MTA to reset for Intel Rapid Start Technology
5482 * Support
5483 */
5484 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5485 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5486 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5487
5488 release:
5489 hw->phy.ops.release(hw);
5490 }
5491 out:
5492 ew32(PHY_CTRL, phy_ctrl);
5493
5494 if (hw->mac.type == e1000_ich8lan)
5495 e1000e_gig_downshift_workaround_ich8lan(hw);
5496
5497 if (hw->mac.type >= e1000_pchlan) {
5498 e1000_oem_bits_config_ich8lan(hw, false);
5499
5500 /* Reset PHY to activate OEM bits on 82577/8 */
5501 if (hw->mac.type == e1000_pchlan)
5502 e1000e_phy_hw_reset_generic(hw);
5503
5504 ret_val = hw->phy.ops.acquire(hw);
5505 if (ret_val)
5506 return;
5507 e1000_write_smbus_addr(hw);
5508 hw->phy.ops.release(hw);
5509 }
5510 }
5511
5512 /**
5513 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5514 * @hw: pointer to the HW structure
5515 *
5516 * During Sx to S0 transitions on non-managed devices or managed devices
5517 * on which PHY resets are not blocked, if the PHY registers cannot be
5518 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5519 * the PHY.
5520 * On i217, setup Intel Rapid Start Technology.
5521 **/
e1000_resume_workarounds_pchlan(struct e1000_hw * hw)5522 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5523 {
5524 s32 ret_val;
5525
5526 if (hw->mac.type < e1000_pch2lan)
5527 return;
5528
5529 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5530 if (ret_val) {
5531 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5532 return;
5533 }
5534
5535 /* For i217 Intel Rapid Start Technology support when the system
5536 * is transitioning from Sx and no manageability engine is present
5537 * configure SMBus to restore on reset, disable proxy, and enable
5538 * the reset on MTA (Multicast table array).
5539 */
5540 if (hw->phy.type == e1000_phy_i217) {
5541 u16 phy_reg;
5542
5543 ret_val = hw->phy.ops.acquire(hw);
5544 if (ret_val) {
5545 e_dbg("Failed to setup iRST\n");
5546 return;
5547 }
5548
5549 /* Clear Auto Enable LPI after link up */
5550 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5551 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5552 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5553
5554 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5555 /* Restore clear on SMB if no manageability engine
5556 * is present
5557 */
5558 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5559 if (ret_val)
5560 goto release;
5561 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5562 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5563
5564 /* Disable Proxy */
5565 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5566 }
5567 /* Enable reset on MTA */
5568 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5569 if (ret_val)
5570 goto release;
5571 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5572 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5573 release:
5574 if (ret_val)
5575 e_dbg("Error %d in resume workarounds\n", ret_val);
5576 hw->phy.ops.release(hw);
5577 }
5578 }
5579
5580 /**
5581 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5582 * @hw: pointer to the HW structure
5583 *
5584 * Return the LED back to the default configuration.
5585 **/
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)5586 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5587 {
5588 if (hw->phy.type == e1000_phy_ife)
5589 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5590
5591 ew32(LEDCTL, hw->mac.ledctl_default);
5592 return 0;
5593 }
5594
5595 /**
5596 * e1000_led_on_ich8lan - Turn LEDs on
5597 * @hw: pointer to the HW structure
5598 *
5599 * Turn on the LEDs.
5600 **/
e1000_led_on_ich8lan(struct e1000_hw * hw)5601 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5602 {
5603 if (hw->phy.type == e1000_phy_ife)
5604 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5605 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5606
5607 ew32(LEDCTL, hw->mac.ledctl_mode2);
5608 return 0;
5609 }
5610
5611 /**
5612 * e1000_led_off_ich8lan - Turn LEDs off
5613 * @hw: pointer to the HW structure
5614 *
5615 * Turn off the LEDs.
5616 **/
e1000_led_off_ich8lan(struct e1000_hw * hw)5617 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5618 {
5619 if (hw->phy.type == e1000_phy_ife)
5620 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5621 (IFE_PSCL_PROBE_MODE |
5622 IFE_PSCL_PROBE_LEDS_OFF));
5623
5624 ew32(LEDCTL, hw->mac.ledctl_mode1);
5625 return 0;
5626 }
5627
5628 /**
5629 * e1000_setup_led_pchlan - Configures SW controllable LED
5630 * @hw: pointer to the HW structure
5631 *
5632 * This prepares the SW controllable LED for use.
5633 **/
e1000_setup_led_pchlan(struct e1000_hw * hw)5634 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5635 {
5636 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5637 }
5638
5639 /**
5640 * e1000_cleanup_led_pchlan - Restore the default LED operation
5641 * @hw: pointer to the HW structure
5642 *
5643 * Return the LED back to the default configuration.
5644 **/
e1000_cleanup_led_pchlan(struct e1000_hw * hw)5645 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5646 {
5647 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5648 }
5649
5650 /**
5651 * e1000_led_on_pchlan - Turn LEDs on
5652 * @hw: pointer to the HW structure
5653 *
5654 * Turn on the LEDs.
5655 **/
e1000_led_on_pchlan(struct e1000_hw * hw)5656 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5657 {
5658 u16 data = (u16)hw->mac.ledctl_mode2;
5659 u32 i, led;
5660
5661 /* If no link, then turn LED on by setting the invert bit
5662 * for each LED that's mode is "link_up" in ledctl_mode2.
5663 */
5664 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5665 for (i = 0; i < 3; i++) {
5666 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5667 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5668 E1000_LEDCTL_MODE_LINK_UP)
5669 continue;
5670 if (led & E1000_PHY_LED0_IVRT)
5671 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5672 else
5673 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5674 }
5675 }
5676
5677 return e1e_wphy(hw, HV_LED_CONFIG, data);
5678 }
5679
5680 /**
5681 * e1000_led_off_pchlan - Turn LEDs off
5682 * @hw: pointer to the HW structure
5683 *
5684 * Turn off the LEDs.
5685 **/
e1000_led_off_pchlan(struct e1000_hw * hw)5686 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5687 {
5688 u16 data = (u16)hw->mac.ledctl_mode1;
5689 u32 i, led;
5690
5691 /* If no link, then turn LED off by clearing the invert bit
5692 * for each LED that's mode is "link_up" in ledctl_mode1.
5693 */
5694 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5695 for (i = 0; i < 3; i++) {
5696 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5697 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5698 E1000_LEDCTL_MODE_LINK_UP)
5699 continue;
5700 if (led & E1000_PHY_LED0_IVRT)
5701 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5702 else
5703 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5704 }
5705 }
5706
5707 return e1e_wphy(hw, HV_LED_CONFIG, data);
5708 }
5709
5710 /**
5711 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5712 * @hw: pointer to the HW structure
5713 *
5714 * Read appropriate register for the config done bit for completion status
5715 * and configure the PHY through s/w for EEPROM-less parts.
5716 *
5717 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5718 * config done bit, so only an error is logged and continues. If we were
5719 * to return with error, EEPROM-less silicon would not be able to be reset
5720 * or change link.
5721 **/
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)5722 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5723 {
5724 s32 ret_val = 0;
5725 u32 bank = 0;
5726 u32 status;
5727
5728 e1000e_get_cfg_done_generic(hw);
5729
5730 /* Wait for indication from h/w that it has completed basic config */
5731 if (hw->mac.type >= e1000_ich10lan) {
5732 e1000_lan_init_done_ich8lan(hw);
5733 } else {
5734 ret_val = e1000e_get_auto_rd_done(hw);
5735 if (ret_val) {
5736 /* When auto config read does not complete, do not
5737 * return with an error. This can happen in situations
5738 * where there is no eeprom and prevents getting link.
5739 */
5740 e_dbg("Auto Read Done did not complete\n");
5741 ret_val = 0;
5742 }
5743 }
5744
5745 /* Clear PHY Reset Asserted bit */
5746 status = er32(STATUS);
5747 if (status & E1000_STATUS_PHYRA)
5748 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5749 else
5750 e_dbg("PHY Reset Asserted not set - needs delay\n");
5751
5752 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5753 if (hw->mac.type <= e1000_ich9lan) {
5754 if (!(er32(EECD) & E1000_EECD_PRES) &&
5755 (hw->phy.type == e1000_phy_igp_3)) {
5756 e1000e_phy_init_script_igp3(hw);
5757 }
5758 } else {
5759 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5760 /* Maybe we should do a basic PHY config */
5761 e_dbg("EEPROM not present\n");
5762 ret_val = -E1000_ERR_CONFIG;
5763 }
5764 }
5765
5766 return ret_val;
5767 }
5768
5769 /**
5770 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5771 * @hw: pointer to the HW structure
5772 *
5773 * In the case of a PHY power down to save power, or to turn off link during a
5774 * driver unload, or wake on lan is not enabled, remove the link.
5775 **/
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)5776 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5777 {
5778 /* If the management interface is not enabled, then power down */
5779 if (!(hw->mac.ops.check_mng_mode(hw) ||
5780 hw->phy.ops.check_reset_block(hw)))
5781 e1000_power_down_phy_copper(hw);
5782 }
5783
5784 /**
5785 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5786 * @hw: pointer to the HW structure
5787 *
5788 * Clears hardware counters specific to the silicon family and calls
5789 * clear_hw_cntrs_generic to clear all general purpose counters.
5790 **/
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)5791 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5792 {
5793 u16 phy_data;
5794 s32 ret_val;
5795
5796 e1000e_clear_hw_cntrs_base(hw);
5797
5798 er32(ALGNERRC);
5799 er32(RXERRC);
5800 er32(TNCRS);
5801 er32(CEXTERR);
5802 er32(TSCTC);
5803 er32(TSCTFC);
5804
5805 er32(MGTPRC);
5806 er32(MGTPDC);
5807 er32(MGTPTC);
5808
5809 er32(IAC);
5810 er32(ICRXOC);
5811
5812 /* Clear PHY statistics registers */
5813 if ((hw->phy.type == e1000_phy_82578) ||
5814 (hw->phy.type == e1000_phy_82579) ||
5815 (hw->phy.type == e1000_phy_i217) ||
5816 (hw->phy.type == e1000_phy_82577)) {
5817 ret_val = hw->phy.ops.acquire(hw);
5818 if (ret_val)
5819 return;
5820 ret_val = hw->phy.ops.set_page(hw,
5821 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5822 if (ret_val)
5823 goto release;
5824 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5825 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5826 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5827 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5828 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5829 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5830 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5831 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5832 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5833 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5834 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5835 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5836 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5837 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5838 release:
5839 hw->phy.ops.release(hw);
5840 }
5841 }
5842
5843 static const struct e1000_mac_operations ich8_mac_ops = {
5844 /* check_mng_mode dependent on mac type */
5845 .check_for_link = e1000_check_for_copper_link_ich8lan,
5846 /* cleanup_led dependent on mac type */
5847 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5848 .get_bus_info = e1000_get_bus_info_ich8lan,
5849 .set_lan_id = e1000_set_lan_id_single_port,
5850 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5851 /* led_on dependent on mac type */
5852 /* led_off dependent on mac type */
5853 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5854 .reset_hw = e1000_reset_hw_ich8lan,
5855 .init_hw = e1000_init_hw_ich8lan,
5856 .setup_link = e1000_setup_link_ich8lan,
5857 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5858 /* id_led_init dependent on mac type */
5859 .config_collision_dist = e1000e_config_collision_dist_generic,
5860 .rar_set = e1000e_rar_set_generic,
5861 .rar_get_count = e1000e_rar_get_count_generic,
5862 };
5863
5864 static const struct e1000_phy_operations ich8_phy_ops = {
5865 .acquire = e1000_acquire_swflag_ich8lan,
5866 .check_reset_block = e1000_check_reset_block_ich8lan,
5867 .commit = NULL,
5868 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5869 .get_cable_length = e1000e_get_cable_length_igp_2,
5870 .read_reg = e1000e_read_phy_reg_igp,
5871 .release = e1000_release_swflag_ich8lan,
5872 .reset = e1000_phy_hw_reset_ich8lan,
5873 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5874 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5875 .write_reg = e1000e_write_phy_reg_igp,
5876 };
5877
5878 static const struct e1000_nvm_operations ich8_nvm_ops = {
5879 .acquire = e1000_acquire_nvm_ich8lan,
5880 .read = e1000_read_nvm_ich8lan,
5881 .release = e1000_release_nvm_ich8lan,
5882 .reload = e1000e_reload_nvm_generic,
5883 .update = e1000_update_nvm_checksum_ich8lan,
5884 .valid_led_default = e1000_valid_led_default_ich8lan,
5885 .validate = e1000_validate_nvm_checksum_ich8lan,
5886 .write = e1000_write_nvm_ich8lan,
5887 };
5888
5889 static const struct e1000_nvm_operations spt_nvm_ops = {
5890 .acquire = e1000_acquire_nvm_ich8lan,
5891 .release = e1000_release_nvm_ich8lan,
5892 .read = e1000_read_nvm_spt,
5893 .update = e1000_update_nvm_checksum_spt,
5894 .reload = e1000e_reload_nvm_generic,
5895 .valid_led_default = e1000_valid_led_default_ich8lan,
5896 .validate = e1000_validate_nvm_checksum_ich8lan,
5897 .write = e1000_write_nvm_ich8lan,
5898 };
5899
5900 const struct e1000_info e1000_ich8_info = {
5901 .mac = e1000_ich8lan,
5902 .flags = FLAG_HAS_WOL
5903 | FLAG_IS_ICH
5904 | FLAG_HAS_CTRLEXT_ON_LOAD
5905 | FLAG_HAS_AMT
5906 | FLAG_HAS_FLASH
5907 | FLAG_APME_IN_WUC,
5908 .pba = 8,
5909 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5910 .get_variants = e1000_get_variants_ich8lan,
5911 .mac_ops = &ich8_mac_ops,
5912 .phy_ops = &ich8_phy_ops,
5913 .nvm_ops = &ich8_nvm_ops,
5914 };
5915
5916 const struct e1000_info e1000_ich9_info = {
5917 .mac = e1000_ich9lan,
5918 .flags = FLAG_HAS_JUMBO_FRAMES
5919 | FLAG_IS_ICH
5920 | FLAG_HAS_WOL
5921 | FLAG_HAS_CTRLEXT_ON_LOAD
5922 | FLAG_HAS_AMT
5923 | FLAG_HAS_FLASH
5924 | FLAG_APME_IN_WUC,
5925 .pba = 18,
5926 .max_hw_frame_size = DEFAULT_JUMBO,
5927 .get_variants = e1000_get_variants_ich8lan,
5928 .mac_ops = &ich8_mac_ops,
5929 .phy_ops = &ich8_phy_ops,
5930 .nvm_ops = &ich8_nvm_ops,
5931 };
5932
5933 const struct e1000_info e1000_ich10_info = {
5934 .mac = e1000_ich10lan,
5935 .flags = FLAG_HAS_JUMBO_FRAMES
5936 | FLAG_IS_ICH
5937 | FLAG_HAS_WOL
5938 | FLAG_HAS_CTRLEXT_ON_LOAD
5939 | FLAG_HAS_AMT
5940 | FLAG_HAS_FLASH
5941 | FLAG_APME_IN_WUC,
5942 .pba = 18,
5943 .max_hw_frame_size = DEFAULT_JUMBO,
5944 .get_variants = e1000_get_variants_ich8lan,
5945 .mac_ops = &ich8_mac_ops,
5946 .phy_ops = &ich8_phy_ops,
5947 .nvm_ops = &ich8_nvm_ops,
5948 };
5949
5950 const struct e1000_info e1000_pch_info = {
5951 .mac = e1000_pchlan,
5952 .flags = FLAG_IS_ICH
5953 | FLAG_HAS_WOL
5954 | FLAG_HAS_CTRLEXT_ON_LOAD
5955 | FLAG_HAS_AMT
5956 | FLAG_HAS_FLASH
5957 | FLAG_HAS_JUMBO_FRAMES
5958 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5959 | FLAG_APME_IN_WUC,
5960 .flags2 = FLAG2_HAS_PHY_STATS,
5961 .pba = 26,
5962 .max_hw_frame_size = 4096,
5963 .get_variants = e1000_get_variants_ich8lan,
5964 .mac_ops = &ich8_mac_ops,
5965 .phy_ops = &ich8_phy_ops,
5966 .nvm_ops = &ich8_nvm_ops,
5967 };
5968
5969 const struct e1000_info e1000_pch2_info = {
5970 .mac = e1000_pch2lan,
5971 .flags = FLAG_IS_ICH
5972 | FLAG_HAS_WOL
5973 | FLAG_HAS_HW_TIMESTAMP
5974 | FLAG_HAS_CTRLEXT_ON_LOAD
5975 | FLAG_HAS_AMT
5976 | FLAG_HAS_FLASH
5977 | FLAG_HAS_JUMBO_FRAMES
5978 | FLAG_APME_IN_WUC,
5979 .flags2 = FLAG2_HAS_PHY_STATS
5980 | FLAG2_HAS_EEE
5981 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5982 .pba = 26,
5983 .max_hw_frame_size = 9022,
5984 .get_variants = e1000_get_variants_ich8lan,
5985 .mac_ops = &ich8_mac_ops,
5986 .phy_ops = &ich8_phy_ops,
5987 .nvm_ops = &ich8_nvm_ops,
5988 };
5989
5990 const struct e1000_info e1000_pch_lpt_info = {
5991 .mac = e1000_pch_lpt,
5992 .flags = FLAG_IS_ICH
5993 | FLAG_HAS_WOL
5994 | FLAG_HAS_HW_TIMESTAMP
5995 | FLAG_HAS_CTRLEXT_ON_LOAD
5996 | FLAG_HAS_AMT
5997 | FLAG_HAS_FLASH
5998 | FLAG_HAS_JUMBO_FRAMES
5999 | FLAG_APME_IN_WUC,
6000 .flags2 = FLAG2_HAS_PHY_STATS
6001 | FLAG2_HAS_EEE
6002 | FLAG2_CHECK_SYSTIM_OVERFLOW,
6003 .pba = 26,
6004 .max_hw_frame_size = 9022,
6005 .get_variants = e1000_get_variants_ich8lan,
6006 .mac_ops = &ich8_mac_ops,
6007 .phy_ops = &ich8_phy_ops,
6008 .nvm_ops = &ich8_nvm_ops,
6009 };
6010
6011 const struct e1000_info e1000_pch_spt_info = {
6012 .mac = e1000_pch_spt,
6013 .flags = FLAG_IS_ICH
6014 | FLAG_HAS_WOL
6015 | FLAG_HAS_HW_TIMESTAMP
6016 | FLAG_HAS_CTRLEXT_ON_LOAD
6017 | FLAG_HAS_AMT
6018 | FLAG_HAS_FLASH
6019 | FLAG_HAS_JUMBO_FRAMES
6020 | FLAG_APME_IN_WUC,
6021 .flags2 = FLAG2_HAS_PHY_STATS
6022 | FLAG2_HAS_EEE,
6023 .pba = 26,
6024 .max_hw_frame_size = 9022,
6025 .get_variants = e1000_get_variants_ich8lan,
6026 .mac_ops = &ich8_mac_ops,
6027 .phy_ops = &ich8_phy_ops,
6028 .nvm_ops = &spt_nvm_ops,
6029 };
6030
6031 const struct e1000_info e1000_pch_cnp_info = {
6032 .mac = e1000_pch_cnp,
6033 .flags = FLAG_IS_ICH
6034 | FLAG_HAS_WOL
6035 | FLAG_HAS_HW_TIMESTAMP
6036 | FLAG_HAS_CTRLEXT_ON_LOAD
6037 | FLAG_HAS_AMT
6038 | FLAG_HAS_FLASH
6039 | FLAG_HAS_JUMBO_FRAMES
6040 | FLAG_APME_IN_WUC,
6041 .flags2 = FLAG2_HAS_PHY_STATS
6042 | FLAG2_HAS_EEE,
6043 .pba = 26,
6044 .max_hw_frame_size = 9022,
6045 .get_variants = e1000_get_variants_ich8lan,
6046 .mac_ops = &ich8_mac_ops,
6047 .phy_ops = &ich8_phy_ops,
6048 .nvm_ops = &spt_nvm_ops,
6049 };
6050
6051 const struct e1000_info e1000_pch_tgp_info = {
6052 .mac = e1000_pch_tgp,
6053 .flags = FLAG_IS_ICH
6054 | FLAG_HAS_WOL
6055 | FLAG_HAS_HW_TIMESTAMP
6056 | FLAG_HAS_CTRLEXT_ON_LOAD
6057 | FLAG_HAS_AMT
6058 | FLAG_HAS_FLASH
6059 | FLAG_HAS_JUMBO_FRAMES
6060 | FLAG_APME_IN_WUC,
6061 .flags2 = FLAG2_HAS_PHY_STATS
6062 | FLAG2_HAS_EEE,
6063 .pba = 26,
6064 .max_hw_frame_size = 9022,
6065 .get_variants = e1000_get_variants_ich8lan,
6066 .mac_ops = &ich8_mac_ops,
6067 .phy_ops = &ich8_phy_ops,
6068 .nvm_ops = &spt_nvm_ops,
6069 };
6070
6071 const struct e1000_info e1000_pch_adp_info = {
6072 .mac = e1000_pch_adp,
6073 .flags = FLAG_IS_ICH
6074 | FLAG_HAS_WOL
6075 | FLAG_HAS_HW_TIMESTAMP
6076 | FLAG_HAS_CTRLEXT_ON_LOAD
6077 | FLAG_HAS_AMT
6078 | FLAG_HAS_FLASH
6079 | FLAG_HAS_JUMBO_FRAMES
6080 | FLAG_APME_IN_WUC,
6081 .flags2 = FLAG2_HAS_PHY_STATS
6082 | FLAG2_HAS_EEE,
6083 .pba = 26,
6084 .max_hw_frame_size = 9022,
6085 .get_variants = e1000_get_variants_ich8lan,
6086 .mac_ops = &ich8_mac_ops,
6087 .phy_ops = &ich8_phy_ops,
6088 .nvm_ops = &spt_nvm_ops,
6089 };
6090
6091 const struct e1000_info e1000_pch_mtp_info = {
6092 .mac = e1000_pch_mtp,
6093 .flags = FLAG_IS_ICH
6094 | FLAG_HAS_WOL
6095 | FLAG_HAS_HW_TIMESTAMP
6096 | FLAG_HAS_CTRLEXT_ON_LOAD
6097 | FLAG_HAS_AMT
6098 | FLAG_HAS_FLASH
6099 | FLAG_HAS_JUMBO_FRAMES
6100 | FLAG_APME_IN_WUC,
6101 .flags2 = FLAG2_HAS_PHY_STATS
6102 | FLAG2_HAS_EEE,
6103 .pba = 26,
6104 .max_hw_frame_size = 9022,
6105 .get_variants = e1000_get_variants_ich8lan,
6106 .mac_ops = &ich8_mac_ops,
6107 .phy_ops = &ich8_phy_ops,
6108 .nvm_ops = &spt_nvm_ops,
6109 };
6110