1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Unforce SMBus mode in PHY */ 226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 229 230 /* Unforce SMBus mode in MAC */ 231 mac_reg = er32(CTRL_EXT); 232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 233 ew32(CTRL_EXT, mac_reg); 234 } 235 } 236 237 return true; 238 } 239 240 /** 241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 242 * @hw: pointer to the HW structure 243 * 244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 245 * used to reset the PHY to a quiescent state when necessary. 246 **/ 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 248 { 249 u32 mac_reg; 250 251 /* Set Phy Config Counter to 50msec */ 252 mac_reg = er32(FEXTNVM3); 253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 255 ew32(FEXTNVM3, mac_reg); 256 257 /* Toggle LANPHYPC Value bit */ 258 mac_reg = er32(CTRL); 259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 261 ew32(CTRL, mac_reg); 262 e1e_flush(); 263 usleep_range(10, 20); 264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 265 ew32(CTRL, mac_reg); 266 e1e_flush(); 267 268 if (hw->mac.type < e1000_pch_lpt) { 269 msleep(50); 270 } else { 271 u16 count = 20; 272 273 do { 274 usleep_range(5000, 6000); 275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 276 277 msleep(30); 278 } 279 } 280 281 /** 282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 283 * @hw: pointer to the HW structure 284 * 285 * Workarounds/flow necessary for PHY initialization during driver load 286 * and resume paths. 287 **/ 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 289 { 290 struct e1000_adapter *adapter = hw->adapter; 291 u32 mac_reg, fwsm = er32(FWSM); 292 s32 ret_val; 293 294 /* Gate automatic PHY configuration by hardware on managed and 295 * non-managed 82579 and newer adapters. 296 */ 297 e1000_gate_hw_phy_config_ich8lan(hw, true); 298 299 /* It is not possible to be certain of the current state of ULP 300 * so forcibly disable it. 301 */ 302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 303 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 304 if (ret_val) 305 e_warn("Failed to disable ULP\n"); 306 307 ret_val = hw->phy.ops.acquire(hw); 308 if (ret_val) { 309 e_dbg("Failed to initialize PHY flow\n"); 310 goto out; 311 } 312 313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 314 * inaccessible and resetting the PHY is not blocked, toggle the 315 * LANPHYPC Value bit to force the interconnect to PCIe mode. 316 */ 317 switch (hw->mac.type) { 318 case e1000_pch_lpt: 319 case e1000_pch_spt: 320 case e1000_pch_cnp: 321 case e1000_pch_tgp: 322 case e1000_pch_adp: 323 case e1000_pch_mtp: 324 case e1000_pch_lnp: 325 case e1000_pch_ptp: 326 if (e1000_phy_is_accessible_pchlan(hw)) 327 break; 328 329 /* Before toggling LANPHYPC, see if PHY is accessible by 330 * forcing MAC to SMBus mode first. 331 */ 332 mac_reg = er32(CTRL_EXT); 333 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 334 ew32(CTRL_EXT, mac_reg); 335 336 /* Wait 50 milliseconds for MAC to finish any retries 337 * that it might be trying to perform from previous 338 * attempts to acknowledge any phy read requests. 339 */ 340 msleep(50); 341 342 fallthrough; 343 case e1000_pch2lan: 344 if (e1000_phy_is_accessible_pchlan(hw)) 345 break; 346 347 fallthrough; 348 case e1000_pchlan: 349 if ((hw->mac.type == e1000_pchlan) && 350 (fwsm & E1000_ICH_FWSM_FW_VALID)) 351 break; 352 353 if (hw->phy.ops.check_reset_block(hw)) { 354 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 355 ret_val = -E1000_ERR_PHY; 356 break; 357 } 358 359 /* Toggle LANPHYPC Value bit */ 360 e1000_toggle_lanphypc_pch_lpt(hw); 361 if (hw->mac.type >= e1000_pch_lpt) { 362 if (e1000_phy_is_accessible_pchlan(hw)) 363 break; 364 365 /* Toggling LANPHYPC brings the PHY out of SMBus mode 366 * so ensure that the MAC is also out of SMBus mode 367 */ 368 mac_reg = er32(CTRL_EXT); 369 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 370 ew32(CTRL_EXT, mac_reg); 371 372 if (e1000_phy_is_accessible_pchlan(hw)) 373 break; 374 375 ret_val = -E1000_ERR_PHY; 376 } 377 break; 378 default: 379 break; 380 } 381 382 hw->phy.ops.release(hw); 383 if (!ret_val) { 384 385 /* Check to see if able to reset PHY. Print error if not */ 386 if (hw->phy.ops.check_reset_block(hw)) { 387 e_err("Reset blocked by ME\n"); 388 goto out; 389 } 390 391 /* Reset the PHY before any access to it. Doing so, ensures 392 * that the PHY is in a known good state before we read/write 393 * PHY registers. The generic reset is sufficient here, 394 * because we haven't determined the PHY type yet. 395 */ 396 ret_val = e1000e_phy_hw_reset_generic(hw); 397 if (ret_val) 398 goto out; 399 400 /* On a successful reset, possibly need to wait for the PHY 401 * to quiesce to an accessible state before returning control 402 * to the calling function. If the PHY does not quiesce, then 403 * return E1000E_BLK_PHY_RESET, as this is the condition that 404 * the PHY is in. 405 */ 406 ret_val = hw->phy.ops.check_reset_block(hw); 407 if (ret_val) 408 e_err("ME blocked access to PHY after reset\n"); 409 } 410 411 out: 412 /* Ungate automatic PHY configuration on non-managed 82579 */ 413 if ((hw->mac.type == e1000_pch2lan) && 414 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 415 usleep_range(10000, 11000); 416 e1000_gate_hw_phy_config_ich8lan(hw, false); 417 } 418 419 return ret_val; 420 } 421 422 /** 423 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 424 * @hw: pointer to the HW structure 425 * 426 * Initialize family-specific PHY parameters and function pointers. 427 **/ 428 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 429 { 430 struct e1000_phy_info *phy = &hw->phy; 431 s32 ret_val; 432 433 phy->addr = 1; 434 phy->reset_delay_us = 100; 435 436 phy->ops.set_page = e1000_set_page_igp; 437 phy->ops.read_reg = e1000_read_phy_reg_hv; 438 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 439 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 440 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 441 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 442 phy->ops.write_reg = e1000_write_phy_reg_hv; 443 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 444 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 445 phy->ops.power_up = e1000_power_up_phy_copper; 446 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 447 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 448 449 phy->id = e1000_phy_unknown; 450 451 ret_val = e1000_init_phy_workarounds_pchlan(hw); 452 if (ret_val) 453 return ret_val; 454 455 if (phy->id == e1000_phy_unknown) 456 switch (hw->mac.type) { 457 default: 458 ret_val = e1000e_get_phy_id(hw); 459 if (ret_val) 460 return ret_val; 461 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 462 break; 463 fallthrough; 464 case e1000_pch2lan: 465 case e1000_pch_lpt: 466 case e1000_pch_spt: 467 case e1000_pch_cnp: 468 case e1000_pch_tgp: 469 case e1000_pch_adp: 470 case e1000_pch_mtp: 471 case e1000_pch_lnp: 472 case e1000_pch_ptp: 473 /* In case the PHY needs to be in mdio slow mode, 474 * set slow mode and try to get the PHY id again. 475 */ 476 ret_val = e1000_set_mdio_slow_mode_hv(hw); 477 if (ret_val) 478 return ret_val; 479 ret_val = e1000e_get_phy_id(hw); 480 if (ret_val) 481 return ret_val; 482 break; 483 } 484 phy->type = e1000e_get_phy_type_from_id(phy->id); 485 486 switch (phy->type) { 487 case e1000_phy_82577: 488 case e1000_phy_82579: 489 case e1000_phy_i217: 490 phy->ops.check_polarity = e1000_check_polarity_82577; 491 phy->ops.force_speed_duplex = 492 e1000_phy_force_speed_duplex_82577; 493 phy->ops.get_cable_length = e1000_get_cable_length_82577; 494 phy->ops.get_info = e1000_get_phy_info_82577; 495 phy->ops.commit = e1000e_phy_sw_reset; 496 break; 497 case e1000_phy_82578: 498 phy->ops.check_polarity = e1000_check_polarity_m88; 499 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 500 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 501 phy->ops.get_info = e1000e_get_phy_info_m88; 502 break; 503 default: 504 ret_val = -E1000_ERR_PHY; 505 break; 506 } 507 508 return ret_val; 509 } 510 511 /** 512 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 513 * @hw: pointer to the HW structure 514 * 515 * Initialize family-specific PHY parameters and function pointers. 516 **/ 517 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 518 { 519 struct e1000_phy_info *phy = &hw->phy; 520 s32 ret_val; 521 u16 i = 0; 522 523 phy->addr = 1; 524 phy->reset_delay_us = 100; 525 526 phy->ops.power_up = e1000_power_up_phy_copper; 527 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 528 529 /* We may need to do this twice - once for IGP and if that fails, 530 * we'll set BM func pointers and try again 531 */ 532 ret_val = e1000e_determine_phy_address(hw); 533 if (ret_val) { 534 phy->ops.write_reg = e1000e_write_phy_reg_bm; 535 phy->ops.read_reg = e1000e_read_phy_reg_bm; 536 ret_val = e1000e_determine_phy_address(hw); 537 if (ret_val) { 538 e_dbg("Cannot determine PHY addr. Erroring out\n"); 539 return ret_val; 540 } 541 } 542 543 phy->id = 0; 544 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 545 (i++ < 100)) { 546 usleep_range(1000, 1100); 547 ret_val = e1000e_get_phy_id(hw); 548 if (ret_val) 549 return ret_val; 550 } 551 552 /* Verify phy id */ 553 switch (phy->id) { 554 case IGP03E1000_E_PHY_ID: 555 phy->type = e1000_phy_igp_3; 556 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 557 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 558 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 559 phy->ops.get_info = e1000e_get_phy_info_igp; 560 phy->ops.check_polarity = e1000_check_polarity_igp; 561 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 562 break; 563 case IFE_E_PHY_ID: 564 case IFE_PLUS_E_PHY_ID: 565 case IFE_C_E_PHY_ID: 566 phy->type = e1000_phy_ife; 567 phy->autoneg_mask = E1000_ALL_NOT_GIG; 568 phy->ops.get_info = e1000_get_phy_info_ife; 569 phy->ops.check_polarity = e1000_check_polarity_ife; 570 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 571 break; 572 case BME1000_E_PHY_ID: 573 phy->type = e1000_phy_bm; 574 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 575 phy->ops.read_reg = e1000e_read_phy_reg_bm; 576 phy->ops.write_reg = e1000e_write_phy_reg_bm; 577 phy->ops.commit = e1000e_phy_sw_reset; 578 phy->ops.get_info = e1000e_get_phy_info_m88; 579 phy->ops.check_polarity = e1000_check_polarity_m88; 580 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 581 break; 582 default: 583 return -E1000_ERR_PHY; 584 } 585 586 return 0; 587 } 588 589 /** 590 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 591 * @hw: pointer to the HW structure 592 * 593 * Initialize family-specific NVM parameters and function 594 * pointers. 595 **/ 596 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 597 { 598 struct e1000_nvm_info *nvm = &hw->nvm; 599 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 600 u32 gfpreg, sector_base_addr, sector_end_addr; 601 u16 i; 602 u32 nvm_size; 603 604 nvm->type = e1000_nvm_flash_sw; 605 606 if (hw->mac.type >= e1000_pch_spt) { 607 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 608 * STRAP register. This is because in SPT the GbE Flash region 609 * is no longer accessed through the flash registers. Instead, 610 * the mechanism has changed, and the Flash region access 611 * registers are now implemented in GbE memory space. 612 */ 613 nvm->flash_base_addr = 0; 614 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 615 * NVM_SIZE_MULTIPLIER; 616 nvm->flash_bank_size = nvm_size / 2; 617 /* Adjust to word count */ 618 nvm->flash_bank_size /= sizeof(u16); 619 /* Set the base address for flash register access */ 620 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 621 } else { 622 /* Can't read flash registers if register set isn't mapped. */ 623 if (!hw->flash_address) { 624 e_dbg("ERROR: Flash registers not mapped\n"); 625 return -E1000_ERR_CONFIG; 626 } 627 628 gfpreg = er32flash(ICH_FLASH_GFPREG); 629 630 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 631 * Add 1 to sector_end_addr since this sector is included in 632 * the overall size. 633 */ 634 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 635 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 636 637 /* flash_base_addr is byte-aligned */ 638 nvm->flash_base_addr = sector_base_addr 639 << FLASH_SECTOR_ADDR_SHIFT; 640 641 /* find total size of the NVM, then cut in half since the total 642 * size represents two separate NVM banks. 643 */ 644 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 645 << FLASH_SECTOR_ADDR_SHIFT); 646 nvm->flash_bank_size /= 2; 647 /* Adjust to word count */ 648 nvm->flash_bank_size /= sizeof(u16); 649 } 650 651 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 652 653 /* Clear shadow ram */ 654 for (i = 0; i < nvm->word_size; i++) { 655 dev_spec->shadow_ram[i].modified = false; 656 dev_spec->shadow_ram[i].value = 0xFFFF; 657 } 658 659 return 0; 660 } 661 662 /** 663 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 664 * @hw: pointer to the HW structure 665 * 666 * Initialize family-specific MAC parameters and function 667 * pointers. 668 **/ 669 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 670 { 671 struct e1000_mac_info *mac = &hw->mac; 672 673 /* Set media type function pointer */ 674 hw->phy.media_type = e1000_media_type_copper; 675 676 /* Set mta register count */ 677 mac->mta_reg_count = 32; 678 /* Set rar entry count */ 679 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 680 if (mac->type == e1000_ich8lan) 681 mac->rar_entry_count--; 682 /* FWSM register */ 683 mac->has_fwsm = true; 684 /* ARC subsystem not supported */ 685 mac->arc_subsystem_valid = false; 686 /* Adaptive IFS supported */ 687 mac->adaptive_ifs = true; 688 689 /* LED and other operations */ 690 switch (mac->type) { 691 case e1000_ich8lan: 692 case e1000_ich9lan: 693 case e1000_ich10lan: 694 /* check management mode */ 695 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 696 /* ID LED init */ 697 mac->ops.id_led_init = e1000e_id_led_init_generic; 698 /* blink LED */ 699 mac->ops.blink_led = e1000e_blink_led_generic; 700 /* setup LED */ 701 mac->ops.setup_led = e1000e_setup_led_generic; 702 /* cleanup LED */ 703 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 704 /* turn on/off LED */ 705 mac->ops.led_on = e1000_led_on_ich8lan; 706 mac->ops.led_off = e1000_led_off_ich8lan; 707 break; 708 case e1000_pch2lan: 709 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 710 mac->ops.rar_set = e1000_rar_set_pch2lan; 711 fallthrough; 712 case e1000_pch_lpt: 713 case e1000_pch_spt: 714 case e1000_pch_cnp: 715 case e1000_pch_tgp: 716 case e1000_pch_adp: 717 case e1000_pch_mtp: 718 case e1000_pch_lnp: 719 case e1000_pch_ptp: 720 case e1000_pchlan: 721 /* check management mode */ 722 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 723 /* ID LED init */ 724 mac->ops.id_led_init = e1000_id_led_init_pchlan; 725 /* setup LED */ 726 mac->ops.setup_led = e1000_setup_led_pchlan; 727 /* cleanup LED */ 728 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 729 /* turn on/off LED */ 730 mac->ops.led_on = e1000_led_on_pchlan; 731 mac->ops.led_off = e1000_led_off_pchlan; 732 break; 733 default: 734 break; 735 } 736 737 if (mac->type >= e1000_pch_lpt) { 738 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 739 mac->ops.rar_set = e1000_rar_set_pch_lpt; 740 mac->ops.setup_physical_interface = 741 e1000_setup_copper_link_pch_lpt; 742 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 743 } 744 745 /* Enable PCS Lock-loss workaround for ICH8 */ 746 if (mac->type == e1000_ich8lan) 747 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 748 749 return 0; 750 } 751 752 /** 753 * __e1000_access_emi_reg_locked - Read/write EMI register 754 * @hw: pointer to the HW structure 755 * @address: EMI address to program 756 * @data: pointer to value to read/write from/to the EMI address 757 * @read: boolean flag to indicate read or write 758 * 759 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 760 **/ 761 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 762 u16 *data, bool read) 763 { 764 s32 ret_val; 765 766 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 767 if (ret_val) 768 return ret_val; 769 770 if (read) 771 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 772 else 773 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 774 775 return ret_val; 776 } 777 778 /** 779 * e1000_read_emi_reg_locked - Read Extended Management Interface register 780 * @hw: pointer to the HW structure 781 * @addr: EMI address to program 782 * @data: value to be read from the EMI address 783 * 784 * Assumes the SW/FW/HW Semaphore is already acquired. 785 **/ 786 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 787 { 788 return __e1000_access_emi_reg_locked(hw, addr, data, true); 789 } 790 791 /** 792 * e1000_write_emi_reg_locked - Write Extended Management Interface register 793 * @hw: pointer to the HW structure 794 * @addr: EMI address to program 795 * @data: value to be written to the EMI address 796 * 797 * Assumes the SW/FW/HW Semaphore is already acquired. 798 **/ 799 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 800 { 801 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 802 } 803 804 /** 805 * e1000_set_eee_pchlan - Enable/disable EEE support 806 * @hw: pointer to the HW structure 807 * 808 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 809 * the link and the EEE capabilities of the link partner. The LPI Control 810 * register bits will remain set only if/when link is up. 811 * 812 * EEE LPI must not be asserted earlier than one second after link is up. 813 * On 82579, EEE LPI should not be enabled until such time otherwise there 814 * can be link issues with some switches. Other devices can have EEE LPI 815 * enabled immediately upon link up since they have a timer in hardware which 816 * prevents LPI from being asserted too early. 817 **/ 818 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 819 { 820 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 821 s32 ret_val; 822 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 823 824 switch (hw->phy.type) { 825 case e1000_phy_82579: 826 lpa = I82579_EEE_LP_ABILITY; 827 pcs_status = I82579_EEE_PCS_STATUS; 828 adv_addr = I82579_EEE_ADVERTISEMENT; 829 break; 830 case e1000_phy_i217: 831 lpa = I217_EEE_LP_ABILITY; 832 pcs_status = I217_EEE_PCS_STATUS; 833 adv_addr = I217_EEE_ADVERTISEMENT; 834 break; 835 default: 836 return 0; 837 } 838 839 ret_val = hw->phy.ops.acquire(hw); 840 if (ret_val) 841 return ret_val; 842 843 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 844 if (ret_val) 845 goto release; 846 847 /* Clear bits that enable EEE in various speeds */ 848 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 849 850 /* Enable EEE if not disabled by user */ 851 if (!dev_spec->eee_disable) { 852 /* Save off link partner's EEE ability */ 853 ret_val = e1000_read_emi_reg_locked(hw, lpa, 854 &dev_spec->eee_lp_ability); 855 if (ret_val) 856 goto release; 857 858 /* Read EEE advertisement */ 859 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 860 if (ret_val) 861 goto release; 862 863 /* Enable EEE only for speeds in which the link partner is 864 * EEE capable and for which we advertise EEE. 865 */ 866 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 867 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 868 869 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 870 e1e_rphy_locked(hw, MII_LPA, &data); 871 if (data & LPA_100FULL) 872 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 873 else 874 /* EEE is not supported in 100Half, so ignore 875 * partner's EEE in 100 ability if full-duplex 876 * is not advertised. 877 */ 878 dev_spec->eee_lp_ability &= 879 ~I82579_EEE_100_SUPPORTED; 880 } 881 } 882 883 if (hw->phy.type == e1000_phy_82579) { 884 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 885 &data); 886 if (ret_val) 887 goto release; 888 889 data &= ~I82579_LPI_100_PLL_SHUT; 890 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 891 data); 892 } 893 894 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 895 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 896 if (ret_val) 897 goto release; 898 899 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 900 release: 901 hw->phy.ops.release(hw); 902 903 return ret_val; 904 } 905 906 /** 907 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 908 * @hw: pointer to the HW structure 909 * @link: link up bool flag 910 * 911 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 912 * preventing further DMA write requests. Workaround the issue by disabling 913 * the de-assertion of the clock request when in 1Gpbs mode. 914 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 915 * speeds in order to avoid Tx hangs. 916 **/ 917 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 918 { 919 u32 fextnvm6 = er32(FEXTNVM6); 920 u32 status = er32(STATUS); 921 s32 ret_val = 0; 922 u16 reg; 923 924 if (link && (status & E1000_STATUS_SPEED_1000)) { 925 ret_val = hw->phy.ops.acquire(hw); 926 if (ret_val) 927 return ret_val; 928 929 ret_val = 930 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 931 ®); 932 if (ret_val) 933 goto release; 934 935 ret_val = 936 e1000e_write_kmrn_reg_locked(hw, 937 E1000_KMRNCTRLSTA_K1_CONFIG, 938 reg & 939 ~E1000_KMRNCTRLSTA_K1_ENABLE); 940 if (ret_val) 941 goto release; 942 943 usleep_range(10, 20); 944 945 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 946 947 ret_val = 948 e1000e_write_kmrn_reg_locked(hw, 949 E1000_KMRNCTRLSTA_K1_CONFIG, 950 reg); 951 release: 952 hw->phy.ops.release(hw); 953 } else { 954 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 955 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 956 957 if ((hw->phy.revision > 5) || !link || 958 ((status & E1000_STATUS_SPEED_100) && 959 (status & E1000_STATUS_FD))) 960 goto update_fextnvm6; 961 962 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 963 if (ret_val) 964 return ret_val; 965 966 /* Clear link status transmit timeout */ 967 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 968 969 if (status & E1000_STATUS_SPEED_100) { 970 /* Set inband Tx timeout to 5x10us for 100Half */ 971 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 972 973 /* Do not extend the K1 entry latency for 100Half */ 974 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 975 } else { 976 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 977 reg |= 50 << 978 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 979 980 /* Extend the K1 entry latency for 10 Mbps */ 981 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 982 } 983 984 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 985 if (ret_val) 986 return ret_val; 987 988 update_fextnvm6: 989 ew32(FEXTNVM6, fextnvm6); 990 } 991 992 return ret_val; 993 } 994 995 /** 996 * e1000_platform_pm_pch_lpt - Set platform power management values 997 * @hw: pointer to the HW structure 998 * @link: bool indicating link status 999 * 1000 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1001 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1002 * when link is up (which must not exceed the maximum latency supported 1003 * by the platform), otherwise specify there is no LTR requirement. 1004 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1005 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1006 * Capability register set, on this device LTR is set by writing the 1007 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1008 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1009 * message to the PMC. 1010 **/ 1011 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1012 { 1013 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1014 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1015 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ 1016 u32 lat_enc_d = 0; /* latency decoded */ 1017 u16 lat_enc = 0; /* latency encoded */ 1018 1019 if (link) { 1020 u16 speed, duplex, scale = 0; 1021 u16 max_snoop, max_nosnoop; 1022 u16 max_ltr_enc; /* max LTR latency encoded */ 1023 u64 value; 1024 u32 rxa; 1025 1026 if (!hw->adapter->max_frame_size) { 1027 e_dbg("max_frame_size not set.\n"); 1028 return -E1000_ERR_CONFIG; 1029 } 1030 1031 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1032 if (!speed) { 1033 e_dbg("Speed not set.\n"); 1034 return -E1000_ERR_CONFIG; 1035 } 1036 1037 /* Rx Packet Buffer Allocation size (KB) */ 1038 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1039 1040 /* Determine the maximum latency tolerated by the device. 1041 * 1042 * Per the PCIe spec, the tolerated latencies are encoded as 1043 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1044 * a 10-bit value (0-1023) to provide a range from 1 ns to 1045 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1046 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1047 */ 1048 rxa *= 512; 1049 value = (rxa > hw->adapter->max_frame_size) ? 1050 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1051 0; 1052 1053 while (value > PCI_LTR_VALUE_MASK) { 1054 scale++; 1055 value = DIV_ROUND_UP(value, BIT(5)); 1056 } 1057 if (scale > E1000_LTRV_SCALE_MAX) { 1058 e_dbg("Invalid LTR latency scale %d\n", scale); 1059 return -E1000_ERR_CONFIG; 1060 } 1061 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1062 1063 /* Determine the maximum latency tolerated by the platform */ 1064 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1065 &max_snoop); 1066 pci_read_config_word(hw->adapter->pdev, 1067 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1068 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1069 1070 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1071 (1U << (E1000_LTRV_SCALE_FACTOR * 1072 ((lat_enc & E1000_LTRV_SCALE_MASK) 1073 >> E1000_LTRV_SCALE_SHIFT))); 1074 1075 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1076 (1U << (E1000_LTRV_SCALE_FACTOR * 1077 ((max_ltr_enc & E1000_LTRV_SCALE_MASK) 1078 >> E1000_LTRV_SCALE_SHIFT))); 1079 1080 if (lat_enc_d > max_ltr_enc_d) 1081 lat_enc = max_ltr_enc; 1082 } 1083 1084 /* Set Snoop and No-Snoop latencies the same */ 1085 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1086 ew32(LTRV, reg); 1087 1088 return 0; 1089 } 1090 1091 /** 1092 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1093 * @hw: pointer to the HW structure 1094 * @to_sx: boolean indicating a system power state transition to Sx 1095 * 1096 * When link is down, configure ULP mode to significantly reduce the power 1097 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1098 * ME firmware to start the ULP configuration. If not on an ME enabled 1099 * system, configure the ULP mode by software. 1100 */ 1101 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1102 { 1103 u32 mac_reg; 1104 s32 ret_val = 0; 1105 u16 phy_reg; 1106 u16 oem_reg = 0; 1107 1108 if ((hw->mac.type < e1000_pch_lpt) || 1109 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1110 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1111 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1112 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1113 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1114 return 0; 1115 1116 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1117 /* Request ME configure ULP mode in the PHY */ 1118 mac_reg = er32(H2ME); 1119 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1120 ew32(H2ME, mac_reg); 1121 1122 goto out; 1123 } 1124 1125 if (!to_sx) { 1126 int i = 0; 1127 1128 /* Poll up to 5 seconds for Cable Disconnected indication */ 1129 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1130 /* Bail if link is re-acquired */ 1131 if (er32(STATUS) & E1000_STATUS_LU) 1132 return -E1000_ERR_PHY; 1133 1134 if (i++ == 100) 1135 break; 1136 1137 msleep(50); 1138 } 1139 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1140 (er32(FEXT) & 1141 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1142 } 1143 1144 ret_val = hw->phy.ops.acquire(hw); 1145 if (ret_val) 1146 goto out; 1147 1148 /* Force SMBus mode in PHY */ 1149 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1150 if (ret_val) 1151 goto release; 1152 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1153 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1154 1155 /* Force SMBus mode in MAC */ 1156 mac_reg = er32(CTRL_EXT); 1157 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1158 ew32(CTRL_EXT, mac_reg); 1159 1160 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1161 * LPLU and disable Gig speed when entering ULP 1162 */ 1163 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1164 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1165 &oem_reg); 1166 if (ret_val) 1167 goto release; 1168 1169 phy_reg = oem_reg; 1170 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1171 1172 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1173 phy_reg); 1174 1175 if (ret_val) 1176 goto release; 1177 } 1178 1179 /* Set Inband ULP Exit, Reset to SMBus mode and 1180 * Disable SMBus Release on PERST# in PHY 1181 */ 1182 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1183 if (ret_val) 1184 goto release; 1185 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1186 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1187 if (to_sx) { 1188 if (er32(WUFC) & E1000_WUFC_LNKC) 1189 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1190 else 1191 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1192 1193 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1194 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1195 } else { 1196 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1197 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1198 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1199 } 1200 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1201 1202 /* Set Disable SMBus Release on PERST# in MAC */ 1203 mac_reg = er32(FEXTNVM7); 1204 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1205 ew32(FEXTNVM7, mac_reg); 1206 1207 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1208 phy_reg |= I218_ULP_CONFIG1_START; 1209 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1210 1211 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1212 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1213 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1214 oem_reg); 1215 if (ret_val) 1216 goto release; 1217 } 1218 1219 release: 1220 hw->phy.ops.release(hw); 1221 out: 1222 if (ret_val) 1223 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1224 else 1225 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1226 1227 return ret_val; 1228 } 1229 1230 /** 1231 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1232 * @hw: pointer to the HW structure 1233 * @force: boolean indicating whether or not to force disabling ULP 1234 * 1235 * Un-configure ULP mode when link is up, the system is transitioned from 1236 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1237 * system, poll for an indication from ME that ULP has been un-configured. 1238 * If not on an ME enabled system, un-configure the ULP mode by software. 1239 * 1240 * During nominal operation, this function is called when link is acquired 1241 * to disable ULP mode (force=false); otherwise, for example when unloading 1242 * the driver or during Sx->S0 transitions, this is called with force=true 1243 * to forcibly disable ULP. 1244 */ 1245 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1246 { 1247 s32 ret_val = 0; 1248 u32 mac_reg; 1249 u16 phy_reg; 1250 int i = 0; 1251 1252 if ((hw->mac.type < e1000_pch_lpt) || 1253 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1254 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1255 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1256 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1257 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1258 return 0; 1259 1260 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1261 struct e1000_adapter *adapter = hw->adapter; 1262 bool firmware_bug = false; 1263 1264 if (force) { 1265 /* Request ME un-configure ULP mode in the PHY */ 1266 mac_reg = er32(H2ME); 1267 mac_reg &= ~E1000_H2ME_ULP; 1268 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1269 ew32(H2ME, mac_reg); 1270 } 1271 1272 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1273 * If this takes more than 1 second, show a warning indicating a 1274 * firmware bug 1275 */ 1276 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1277 if (i++ == 250) { 1278 ret_val = -E1000_ERR_PHY; 1279 goto out; 1280 } 1281 if (i > 100 && !firmware_bug) 1282 firmware_bug = true; 1283 1284 usleep_range(10000, 11000); 1285 } 1286 if (firmware_bug) 1287 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1288 i * 10); 1289 else 1290 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1291 i * 10); 1292 1293 if (force) { 1294 mac_reg = er32(H2ME); 1295 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1296 ew32(H2ME, mac_reg); 1297 } else { 1298 /* Clear H2ME.ULP after ME ULP configuration */ 1299 mac_reg = er32(H2ME); 1300 mac_reg &= ~E1000_H2ME_ULP; 1301 ew32(H2ME, mac_reg); 1302 } 1303 1304 goto out; 1305 } 1306 1307 ret_val = hw->phy.ops.acquire(hw); 1308 if (ret_val) 1309 goto out; 1310 1311 if (force) 1312 /* Toggle LANPHYPC Value bit */ 1313 e1000_toggle_lanphypc_pch_lpt(hw); 1314 1315 /* Unforce SMBus mode in PHY */ 1316 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1317 if (ret_val) { 1318 /* The MAC might be in PCIe mode, so temporarily force to 1319 * SMBus mode in order to access the PHY. 1320 */ 1321 mac_reg = er32(CTRL_EXT); 1322 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1323 ew32(CTRL_EXT, mac_reg); 1324 1325 msleep(50); 1326 1327 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1328 &phy_reg); 1329 if (ret_val) 1330 goto release; 1331 } 1332 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1333 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1334 1335 /* Unforce SMBus mode in MAC */ 1336 mac_reg = er32(CTRL_EXT); 1337 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1338 ew32(CTRL_EXT, mac_reg); 1339 1340 /* When ULP mode was previously entered, K1 was disabled by the 1341 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1342 */ 1343 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1344 if (ret_val) 1345 goto release; 1346 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1347 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1348 1349 /* Clear ULP enabled configuration */ 1350 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1351 if (ret_val) 1352 goto release; 1353 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1354 I218_ULP_CONFIG1_STICKY_ULP | 1355 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1356 I218_ULP_CONFIG1_WOL_HOST | 1357 I218_ULP_CONFIG1_INBAND_EXIT | 1358 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1359 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1360 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1361 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1362 1363 /* Commit ULP changes by starting auto ULP configuration */ 1364 phy_reg |= I218_ULP_CONFIG1_START; 1365 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1366 1367 /* Clear Disable SMBus Release on PERST# in MAC */ 1368 mac_reg = er32(FEXTNVM7); 1369 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1370 ew32(FEXTNVM7, mac_reg); 1371 1372 release: 1373 hw->phy.ops.release(hw); 1374 if (force) { 1375 e1000_phy_hw_reset(hw); 1376 msleep(50); 1377 } 1378 out: 1379 if (ret_val) 1380 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1381 else 1382 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1383 1384 return ret_val; 1385 } 1386 1387 /** 1388 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1389 * @hw: pointer to the HW structure 1390 * 1391 * Checks to see of the link status of the hardware has changed. If a 1392 * change in link status has been detected, then we read the PHY registers 1393 * to get the current speed/duplex if link exists. 1394 **/ 1395 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1396 { 1397 struct e1000_mac_info *mac = &hw->mac; 1398 s32 ret_val, tipg_reg = 0; 1399 u16 emi_addr, emi_val = 0; 1400 bool link; 1401 u16 phy_reg; 1402 1403 /* We only want to go out to the PHY registers to see if Auto-Neg 1404 * has completed and/or if our link status has changed. The 1405 * get_link_status flag is set upon receiving a Link Status 1406 * Change or Rx Sequence Error interrupt. 1407 */ 1408 if (!mac->get_link_status) 1409 return 0; 1410 mac->get_link_status = false; 1411 1412 /* First we want to see if the MII Status Register reports 1413 * link. If so, then we want to get the current speed/duplex 1414 * of the PHY. 1415 */ 1416 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1417 if (ret_val) 1418 goto out; 1419 1420 if (hw->mac.type == e1000_pchlan) { 1421 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1422 if (ret_val) 1423 goto out; 1424 } 1425 1426 /* When connected at 10Mbps half-duplex, some parts are excessively 1427 * aggressive resulting in many collisions. To avoid this, increase 1428 * the IPG and reduce Rx latency in the PHY. 1429 */ 1430 if ((hw->mac.type >= e1000_pch2lan) && link) { 1431 u16 speed, duplex; 1432 1433 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1434 tipg_reg = er32(TIPG); 1435 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1436 1437 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1438 tipg_reg |= 0xFF; 1439 /* Reduce Rx latency in analog PHY */ 1440 emi_val = 0; 1441 } else if (hw->mac.type >= e1000_pch_spt && 1442 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1443 tipg_reg |= 0xC; 1444 emi_val = 1; 1445 } else { 1446 1447 /* Roll back the default values */ 1448 tipg_reg |= 0x08; 1449 emi_val = 1; 1450 } 1451 1452 ew32(TIPG, tipg_reg); 1453 1454 ret_val = hw->phy.ops.acquire(hw); 1455 if (ret_val) 1456 goto out; 1457 1458 if (hw->mac.type == e1000_pch2lan) 1459 emi_addr = I82579_RX_CONFIG; 1460 else 1461 emi_addr = I217_RX_CONFIG; 1462 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1463 1464 if (hw->mac.type >= e1000_pch_lpt) { 1465 u16 phy_reg; 1466 1467 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1468 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1469 if (speed == SPEED_100 || speed == SPEED_10) 1470 phy_reg |= 0x3E8; 1471 else 1472 phy_reg |= 0xFA; 1473 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1474 1475 if (speed == SPEED_1000) { 1476 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1477 &phy_reg); 1478 1479 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1480 1481 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1482 phy_reg); 1483 } 1484 } 1485 hw->phy.ops.release(hw); 1486 1487 if (ret_val) 1488 goto out; 1489 1490 if (hw->mac.type >= e1000_pch_spt) { 1491 u16 data; 1492 u16 ptr_gap; 1493 1494 if (speed == SPEED_1000) { 1495 ret_val = hw->phy.ops.acquire(hw); 1496 if (ret_val) 1497 goto out; 1498 1499 ret_val = e1e_rphy_locked(hw, 1500 PHY_REG(776, 20), 1501 &data); 1502 if (ret_val) { 1503 hw->phy.ops.release(hw); 1504 goto out; 1505 } 1506 1507 ptr_gap = (data & (0x3FF << 2)) >> 2; 1508 if (ptr_gap < 0x18) { 1509 data &= ~(0x3FF << 2); 1510 data |= (0x18 << 2); 1511 ret_val = 1512 e1e_wphy_locked(hw, 1513 PHY_REG(776, 20), 1514 data); 1515 } 1516 hw->phy.ops.release(hw); 1517 if (ret_val) 1518 goto out; 1519 } else { 1520 ret_val = hw->phy.ops.acquire(hw); 1521 if (ret_val) 1522 goto out; 1523 1524 ret_val = e1e_wphy_locked(hw, 1525 PHY_REG(776, 20), 1526 0xC023); 1527 hw->phy.ops.release(hw); 1528 if (ret_val) 1529 goto out; 1530 1531 } 1532 } 1533 } 1534 1535 /* I217 Packet Loss issue: 1536 * ensure that FEXTNVM4 Beacon Duration is set correctly 1537 * on power up. 1538 * Set the Beacon Duration for I217 to 8 usec 1539 */ 1540 if (hw->mac.type >= e1000_pch_lpt) { 1541 u32 mac_reg; 1542 1543 mac_reg = er32(FEXTNVM4); 1544 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1545 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1546 ew32(FEXTNVM4, mac_reg); 1547 } 1548 1549 /* Work-around I218 hang issue */ 1550 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1551 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1552 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1553 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1554 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1555 if (ret_val) 1556 goto out; 1557 } 1558 if (hw->mac.type >= e1000_pch_lpt) { 1559 /* Set platform power management values for 1560 * Latency Tolerance Reporting (LTR) 1561 */ 1562 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1563 if (ret_val) 1564 goto out; 1565 } 1566 1567 /* Clear link partner's EEE ability */ 1568 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1569 1570 if (hw->mac.type >= e1000_pch_lpt) { 1571 u32 fextnvm6 = er32(FEXTNVM6); 1572 1573 if (hw->mac.type == e1000_pch_spt) { 1574 /* FEXTNVM6 K1-off workaround - for SPT only */ 1575 u32 pcieanacfg = er32(PCIEANACFG); 1576 1577 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1578 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1579 else 1580 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1581 } 1582 1583 ew32(FEXTNVM6, fextnvm6); 1584 } 1585 1586 if (!link) 1587 goto out; 1588 1589 switch (hw->mac.type) { 1590 case e1000_pch2lan: 1591 ret_val = e1000_k1_workaround_lv(hw); 1592 if (ret_val) 1593 return ret_val; 1594 fallthrough; 1595 case e1000_pchlan: 1596 if (hw->phy.type == e1000_phy_82578) { 1597 ret_val = e1000_link_stall_workaround_hv(hw); 1598 if (ret_val) 1599 return ret_val; 1600 } 1601 1602 /* Workaround for PCHx parts in half-duplex: 1603 * Set the number of preambles removed from the packet 1604 * when it is passed from the PHY to the MAC to prevent 1605 * the MAC from misinterpreting the packet type. 1606 */ 1607 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1608 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1609 1610 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1611 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1612 1613 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1614 break; 1615 default: 1616 break; 1617 } 1618 1619 /* Check if there was DownShift, must be checked 1620 * immediately after link-up 1621 */ 1622 e1000e_check_downshift(hw); 1623 1624 /* Enable/Disable EEE after link up */ 1625 if (hw->phy.type > e1000_phy_82579) { 1626 ret_val = e1000_set_eee_pchlan(hw); 1627 if (ret_val) 1628 return ret_val; 1629 } 1630 1631 /* If we are forcing speed/duplex, then we simply return since 1632 * we have already determined whether we have link or not. 1633 */ 1634 if (!mac->autoneg) 1635 return -E1000_ERR_CONFIG; 1636 1637 /* Auto-Neg is enabled. Auto Speed Detection takes care 1638 * of MAC speed/duplex configuration. So we only need to 1639 * configure Collision Distance in the MAC. 1640 */ 1641 mac->ops.config_collision_dist(hw); 1642 1643 /* Configure Flow Control now that Auto-Neg has completed. 1644 * First, we need to restore the desired flow control 1645 * settings because we may have had to re-autoneg with a 1646 * different link partner. 1647 */ 1648 ret_val = e1000e_config_fc_after_link_up(hw); 1649 if (ret_val) 1650 e_dbg("Error configuring flow control\n"); 1651 1652 return ret_val; 1653 1654 out: 1655 mac->get_link_status = true; 1656 return ret_val; 1657 } 1658 1659 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1660 { 1661 struct e1000_hw *hw = &adapter->hw; 1662 s32 rc; 1663 1664 rc = e1000_init_mac_params_ich8lan(hw); 1665 if (rc) 1666 return rc; 1667 1668 rc = e1000_init_nvm_params_ich8lan(hw); 1669 if (rc) 1670 return rc; 1671 1672 switch (hw->mac.type) { 1673 case e1000_ich8lan: 1674 case e1000_ich9lan: 1675 case e1000_ich10lan: 1676 rc = e1000_init_phy_params_ich8lan(hw); 1677 break; 1678 case e1000_pchlan: 1679 case e1000_pch2lan: 1680 case e1000_pch_lpt: 1681 case e1000_pch_spt: 1682 case e1000_pch_cnp: 1683 case e1000_pch_tgp: 1684 case e1000_pch_adp: 1685 case e1000_pch_mtp: 1686 case e1000_pch_lnp: 1687 case e1000_pch_ptp: 1688 rc = e1000_init_phy_params_pchlan(hw); 1689 break; 1690 default: 1691 break; 1692 } 1693 if (rc) 1694 return rc; 1695 1696 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1697 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1698 */ 1699 if ((adapter->hw.phy.type == e1000_phy_ife) || 1700 ((adapter->hw.mac.type >= e1000_pch2lan) && 1701 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1702 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1703 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1704 1705 hw->mac.ops.blink_led = NULL; 1706 } 1707 1708 if ((adapter->hw.mac.type == e1000_ich8lan) && 1709 (adapter->hw.phy.type != e1000_phy_ife)) 1710 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1711 1712 /* Enable workaround for 82579 w/ ME enabled */ 1713 if ((adapter->hw.mac.type == e1000_pch2lan) && 1714 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1715 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1716 1717 return 0; 1718 } 1719 1720 static DEFINE_MUTEX(nvm_mutex); 1721 1722 /** 1723 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1724 * @hw: pointer to the HW structure 1725 * 1726 * Acquires the mutex for performing NVM operations. 1727 **/ 1728 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1729 { 1730 mutex_lock(&nvm_mutex); 1731 1732 return 0; 1733 } 1734 1735 /** 1736 * e1000_release_nvm_ich8lan - Release NVM mutex 1737 * @hw: pointer to the HW structure 1738 * 1739 * Releases the mutex used while performing NVM operations. 1740 **/ 1741 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1742 { 1743 mutex_unlock(&nvm_mutex); 1744 } 1745 1746 /** 1747 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1748 * @hw: pointer to the HW structure 1749 * 1750 * Acquires the software control flag for performing PHY and select 1751 * MAC CSR accesses. 1752 **/ 1753 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1754 { 1755 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1756 s32 ret_val = 0; 1757 1758 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1759 &hw->adapter->state)) { 1760 e_dbg("contention for Phy access\n"); 1761 return -E1000_ERR_PHY; 1762 } 1763 1764 while (timeout) { 1765 extcnf_ctrl = er32(EXTCNF_CTRL); 1766 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1767 break; 1768 1769 mdelay(1); 1770 timeout--; 1771 } 1772 1773 if (!timeout) { 1774 e_dbg("SW has already locked the resource.\n"); 1775 ret_val = -E1000_ERR_CONFIG; 1776 goto out; 1777 } 1778 1779 timeout = SW_FLAG_TIMEOUT; 1780 1781 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1782 ew32(EXTCNF_CTRL, extcnf_ctrl); 1783 1784 while (timeout) { 1785 extcnf_ctrl = er32(EXTCNF_CTRL); 1786 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1787 break; 1788 1789 mdelay(1); 1790 timeout--; 1791 } 1792 1793 if (!timeout) { 1794 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1795 er32(FWSM), extcnf_ctrl); 1796 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1797 ew32(EXTCNF_CTRL, extcnf_ctrl); 1798 ret_val = -E1000_ERR_CONFIG; 1799 goto out; 1800 } 1801 1802 out: 1803 if (ret_val) 1804 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1805 1806 return ret_val; 1807 } 1808 1809 /** 1810 * e1000_release_swflag_ich8lan - Release software control flag 1811 * @hw: pointer to the HW structure 1812 * 1813 * Releases the software control flag for performing PHY and select 1814 * MAC CSR accesses. 1815 **/ 1816 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1817 { 1818 u32 extcnf_ctrl; 1819 1820 extcnf_ctrl = er32(EXTCNF_CTRL); 1821 1822 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1823 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1824 ew32(EXTCNF_CTRL, extcnf_ctrl); 1825 } else { 1826 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1827 } 1828 1829 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1830 } 1831 1832 /** 1833 * e1000_check_mng_mode_ich8lan - Checks management mode 1834 * @hw: pointer to the HW structure 1835 * 1836 * This checks if the adapter has any manageability enabled. 1837 * This is a function pointer entry point only called by read/write 1838 * routines for the PHY and NVM parts. 1839 **/ 1840 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1841 { 1842 u32 fwsm; 1843 1844 fwsm = er32(FWSM); 1845 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1846 ((fwsm & E1000_FWSM_MODE_MASK) == 1847 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1848 } 1849 1850 /** 1851 * e1000_check_mng_mode_pchlan - Checks management mode 1852 * @hw: pointer to the HW structure 1853 * 1854 * This checks if the adapter has iAMT enabled. 1855 * This is a function pointer entry point only called by read/write 1856 * routines for the PHY and NVM parts. 1857 **/ 1858 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1859 { 1860 u32 fwsm; 1861 1862 fwsm = er32(FWSM); 1863 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1864 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1865 } 1866 1867 /** 1868 * e1000_rar_set_pch2lan - Set receive address register 1869 * @hw: pointer to the HW structure 1870 * @addr: pointer to the receive address 1871 * @index: receive address array register 1872 * 1873 * Sets the receive address array register at index to the address passed 1874 * in by addr. For 82579, RAR[0] is the base address register that is to 1875 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1876 * Use SHRA[0-3] in place of those reserved for ME. 1877 **/ 1878 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1879 { 1880 u32 rar_low, rar_high; 1881 1882 /* HW expects these in little endian so we reverse the byte order 1883 * from network order (big endian) to little endian 1884 */ 1885 rar_low = ((u32)addr[0] | 1886 ((u32)addr[1] << 8) | 1887 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1888 1889 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1890 1891 /* If MAC address zero, no need to set the AV bit */ 1892 if (rar_low || rar_high) 1893 rar_high |= E1000_RAH_AV; 1894 1895 if (index == 0) { 1896 ew32(RAL(index), rar_low); 1897 e1e_flush(); 1898 ew32(RAH(index), rar_high); 1899 e1e_flush(); 1900 return 0; 1901 } 1902 1903 /* RAR[1-6] are owned by manageability. Skip those and program the 1904 * next address into the SHRA register array. 1905 */ 1906 if (index < (u32)(hw->mac.rar_entry_count)) { 1907 s32 ret_val; 1908 1909 ret_val = e1000_acquire_swflag_ich8lan(hw); 1910 if (ret_val) 1911 goto out; 1912 1913 ew32(SHRAL(index - 1), rar_low); 1914 e1e_flush(); 1915 ew32(SHRAH(index - 1), rar_high); 1916 e1e_flush(); 1917 1918 e1000_release_swflag_ich8lan(hw); 1919 1920 /* verify the register updates */ 1921 if ((er32(SHRAL(index - 1)) == rar_low) && 1922 (er32(SHRAH(index - 1)) == rar_high)) 1923 return 0; 1924 1925 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1926 (index - 1), er32(FWSM)); 1927 } 1928 1929 out: 1930 e_dbg("Failed to write receive address at index %d\n", index); 1931 return -E1000_ERR_CONFIG; 1932 } 1933 1934 /** 1935 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1936 * @hw: pointer to the HW structure 1937 * 1938 * Get the number of available receive registers that the Host can 1939 * program. SHRA[0-10] are the shared receive address registers 1940 * that are shared between the Host and manageability engine (ME). 1941 * ME can reserve any number of addresses and the host needs to be 1942 * able to tell how many available registers it has access to. 1943 **/ 1944 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1945 { 1946 u32 wlock_mac; 1947 u32 num_entries; 1948 1949 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1950 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1951 1952 switch (wlock_mac) { 1953 case 0: 1954 /* All SHRA[0..10] and RAR[0] available */ 1955 num_entries = hw->mac.rar_entry_count; 1956 break; 1957 case 1: 1958 /* Only RAR[0] available */ 1959 num_entries = 1; 1960 break; 1961 default: 1962 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1963 num_entries = wlock_mac + 1; 1964 break; 1965 } 1966 1967 return num_entries; 1968 } 1969 1970 /** 1971 * e1000_rar_set_pch_lpt - Set receive address registers 1972 * @hw: pointer to the HW structure 1973 * @addr: pointer to the receive address 1974 * @index: receive address array register 1975 * 1976 * Sets the receive address register array at index to the address passed 1977 * in by addr. For LPT, RAR[0] is the base address register that is to 1978 * contain the MAC address. SHRA[0-10] are the shared receive address 1979 * registers that are shared between the Host and manageability engine (ME). 1980 **/ 1981 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1982 { 1983 u32 rar_low, rar_high; 1984 u32 wlock_mac; 1985 1986 /* HW expects these in little endian so we reverse the byte order 1987 * from network order (big endian) to little endian 1988 */ 1989 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1990 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1991 1992 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1993 1994 /* If MAC address zero, no need to set the AV bit */ 1995 if (rar_low || rar_high) 1996 rar_high |= E1000_RAH_AV; 1997 1998 if (index == 0) { 1999 ew32(RAL(index), rar_low); 2000 e1e_flush(); 2001 ew32(RAH(index), rar_high); 2002 e1e_flush(); 2003 return 0; 2004 } 2005 2006 /* The manageability engine (ME) can lock certain SHRAR registers that 2007 * it is using - those registers are unavailable for use. 2008 */ 2009 if (index < hw->mac.rar_entry_count) { 2010 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2011 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2012 2013 /* Check if all SHRAR registers are locked */ 2014 if (wlock_mac == 1) 2015 goto out; 2016 2017 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2018 s32 ret_val; 2019 2020 ret_val = e1000_acquire_swflag_ich8lan(hw); 2021 2022 if (ret_val) 2023 goto out; 2024 2025 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2026 e1e_flush(); 2027 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2028 e1e_flush(); 2029 2030 e1000_release_swflag_ich8lan(hw); 2031 2032 /* verify the register updates */ 2033 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2034 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2035 return 0; 2036 } 2037 } 2038 2039 out: 2040 e_dbg("Failed to write receive address at index %d\n", index); 2041 return -E1000_ERR_CONFIG; 2042 } 2043 2044 /** 2045 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2046 * @hw: pointer to the HW structure 2047 * 2048 * Checks if firmware is blocking the reset of the PHY. 2049 * This is a function pointer entry point only called by 2050 * reset routines. 2051 **/ 2052 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2053 { 2054 bool blocked = false; 2055 int i = 0; 2056 2057 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2058 (i++ < 30)) 2059 usleep_range(10000, 11000); 2060 return blocked ? E1000_BLK_PHY_RESET : 0; 2061 } 2062 2063 /** 2064 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2065 * @hw: pointer to the HW structure 2066 * 2067 * Assumes semaphore already acquired. 2068 * 2069 **/ 2070 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2071 { 2072 u16 phy_data; 2073 u32 strap = er32(STRAP); 2074 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2075 E1000_STRAP_SMT_FREQ_SHIFT; 2076 s32 ret_val; 2077 2078 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2079 2080 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2081 if (ret_val) 2082 return ret_val; 2083 2084 phy_data &= ~HV_SMB_ADDR_MASK; 2085 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2086 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2087 2088 if (hw->phy.type == e1000_phy_i217) { 2089 /* Restore SMBus frequency */ 2090 if (freq--) { 2091 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2092 phy_data |= (freq & BIT(0)) << 2093 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2094 phy_data |= (freq & BIT(1)) << 2095 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2096 } else { 2097 e_dbg("Unsupported SMB frequency in PHY\n"); 2098 } 2099 } 2100 2101 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2102 } 2103 2104 /** 2105 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2106 * @hw: pointer to the HW structure 2107 * 2108 * SW should configure the LCD from the NVM extended configuration region 2109 * as a workaround for certain parts. 2110 **/ 2111 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2112 { 2113 struct e1000_phy_info *phy = &hw->phy; 2114 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2115 s32 ret_val = 0; 2116 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2117 2118 /* Initialize the PHY from the NVM on ICH platforms. This 2119 * is needed due to an issue where the NVM configuration is 2120 * not properly autoloaded after power transitions. 2121 * Therefore, after each PHY reset, we will load the 2122 * configuration data out of the NVM manually. 2123 */ 2124 switch (hw->mac.type) { 2125 case e1000_ich8lan: 2126 if (phy->type != e1000_phy_igp_3) 2127 return ret_val; 2128 2129 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2130 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2131 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2132 break; 2133 } 2134 fallthrough; 2135 case e1000_pchlan: 2136 case e1000_pch2lan: 2137 case e1000_pch_lpt: 2138 case e1000_pch_spt: 2139 case e1000_pch_cnp: 2140 case e1000_pch_tgp: 2141 case e1000_pch_adp: 2142 case e1000_pch_mtp: 2143 case e1000_pch_lnp: 2144 case e1000_pch_ptp: 2145 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2146 break; 2147 default: 2148 return ret_val; 2149 } 2150 2151 ret_val = hw->phy.ops.acquire(hw); 2152 if (ret_val) 2153 return ret_val; 2154 2155 data = er32(FEXTNVM); 2156 if (!(data & sw_cfg_mask)) 2157 goto release; 2158 2159 /* Make sure HW does not configure LCD from PHY 2160 * extended configuration before SW configuration 2161 */ 2162 data = er32(EXTCNF_CTRL); 2163 if ((hw->mac.type < e1000_pch2lan) && 2164 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2165 goto release; 2166 2167 cnf_size = er32(EXTCNF_SIZE); 2168 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2169 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2170 if (!cnf_size) 2171 goto release; 2172 2173 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2174 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2175 2176 if (((hw->mac.type == e1000_pchlan) && 2177 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2178 (hw->mac.type > e1000_pchlan)) { 2179 /* HW configures the SMBus address and LEDs when the 2180 * OEM and LCD Write Enable bits are set in the NVM. 2181 * When both NVM bits are cleared, SW will configure 2182 * them instead. 2183 */ 2184 ret_val = e1000_write_smbus_addr(hw); 2185 if (ret_val) 2186 goto release; 2187 2188 data = er32(LEDCTL); 2189 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2190 (u16)data); 2191 if (ret_val) 2192 goto release; 2193 } 2194 2195 /* Configure LCD from extended configuration region. */ 2196 2197 /* cnf_base_addr is in DWORD */ 2198 word_addr = (u16)(cnf_base_addr << 1); 2199 2200 for (i = 0; i < cnf_size; i++) { 2201 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2202 if (ret_val) 2203 goto release; 2204 2205 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2206 1, ®_addr); 2207 if (ret_val) 2208 goto release; 2209 2210 /* Save off the PHY page for future writes. */ 2211 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2212 phy_page = reg_data; 2213 continue; 2214 } 2215 2216 reg_addr &= PHY_REG_MASK; 2217 reg_addr |= phy_page; 2218 2219 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2220 if (ret_val) 2221 goto release; 2222 } 2223 2224 release: 2225 hw->phy.ops.release(hw); 2226 return ret_val; 2227 } 2228 2229 /** 2230 * e1000_k1_gig_workaround_hv - K1 Si workaround 2231 * @hw: pointer to the HW structure 2232 * @link: link up bool flag 2233 * 2234 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2235 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2236 * If link is down, the function will restore the default K1 setting located 2237 * in the NVM. 2238 **/ 2239 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2240 { 2241 s32 ret_val = 0; 2242 u16 status_reg = 0; 2243 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2244 2245 if (hw->mac.type != e1000_pchlan) 2246 return 0; 2247 2248 /* Wrap the whole flow with the sw flag */ 2249 ret_val = hw->phy.ops.acquire(hw); 2250 if (ret_val) 2251 return ret_val; 2252 2253 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2254 if (link) { 2255 if (hw->phy.type == e1000_phy_82578) { 2256 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2257 &status_reg); 2258 if (ret_val) 2259 goto release; 2260 2261 status_reg &= (BM_CS_STATUS_LINK_UP | 2262 BM_CS_STATUS_RESOLVED | 2263 BM_CS_STATUS_SPEED_MASK); 2264 2265 if (status_reg == (BM_CS_STATUS_LINK_UP | 2266 BM_CS_STATUS_RESOLVED | 2267 BM_CS_STATUS_SPEED_1000)) 2268 k1_enable = false; 2269 } 2270 2271 if (hw->phy.type == e1000_phy_82577) { 2272 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2273 if (ret_val) 2274 goto release; 2275 2276 status_reg &= (HV_M_STATUS_LINK_UP | 2277 HV_M_STATUS_AUTONEG_COMPLETE | 2278 HV_M_STATUS_SPEED_MASK); 2279 2280 if (status_reg == (HV_M_STATUS_LINK_UP | 2281 HV_M_STATUS_AUTONEG_COMPLETE | 2282 HV_M_STATUS_SPEED_1000)) 2283 k1_enable = false; 2284 } 2285 2286 /* Link stall fix for link up */ 2287 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2288 if (ret_val) 2289 goto release; 2290 2291 } else { 2292 /* Link stall fix for link down */ 2293 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2294 if (ret_val) 2295 goto release; 2296 } 2297 2298 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2299 2300 release: 2301 hw->phy.ops.release(hw); 2302 2303 return ret_val; 2304 } 2305 2306 /** 2307 * e1000_configure_k1_ich8lan - Configure K1 power state 2308 * @hw: pointer to the HW structure 2309 * @k1_enable: K1 state to configure 2310 * 2311 * Configure the K1 power state based on the provided parameter. 2312 * Assumes semaphore already acquired. 2313 * 2314 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2315 **/ 2316 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2317 { 2318 s32 ret_val; 2319 u32 ctrl_reg = 0; 2320 u32 ctrl_ext = 0; 2321 u32 reg = 0; 2322 u16 kmrn_reg = 0; 2323 2324 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2325 &kmrn_reg); 2326 if (ret_val) 2327 return ret_val; 2328 2329 if (k1_enable) 2330 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2331 else 2332 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2333 2334 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2335 kmrn_reg); 2336 if (ret_val) 2337 return ret_val; 2338 2339 usleep_range(20, 40); 2340 ctrl_ext = er32(CTRL_EXT); 2341 ctrl_reg = er32(CTRL); 2342 2343 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2344 reg |= E1000_CTRL_FRCSPD; 2345 ew32(CTRL, reg); 2346 2347 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2348 e1e_flush(); 2349 usleep_range(20, 40); 2350 ew32(CTRL, ctrl_reg); 2351 ew32(CTRL_EXT, ctrl_ext); 2352 e1e_flush(); 2353 usleep_range(20, 40); 2354 2355 return 0; 2356 } 2357 2358 /** 2359 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2360 * @hw: pointer to the HW structure 2361 * @d0_state: boolean if entering d0 or d3 device state 2362 * 2363 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2364 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2365 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2366 **/ 2367 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2368 { 2369 s32 ret_val = 0; 2370 u32 mac_reg; 2371 u16 oem_reg; 2372 2373 if (hw->mac.type < e1000_pchlan) 2374 return ret_val; 2375 2376 ret_val = hw->phy.ops.acquire(hw); 2377 if (ret_val) 2378 return ret_val; 2379 2380 if (hw->mac.type == e1000_pchlan) { 2381 mac_reg = er32(EXTCNF_CTRL); 2382 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2383 goto release; 2384 } 2385 2386 mac_reg = er32(FEXTNVM); 2387 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2388 goto release; 2389 2390 mac_reg = er32(PHY_CTRL); 2391 2392 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2393 if (ret_val) 2394 goto release; 2395 2396 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2397 2398 if (d0_state) { 2399 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2400 oem_reg |= HV_OEM_BITS_GBE_DIS; 2401 2402 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2403 oem_reg |= HV_OEM_BITS_LPLU; 2404 } else { 2405 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2406 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2407 oem_reg |= HV_OEM_BITS_GBE_DIS; 2408 2409 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2410 E1000_PHY_CTRL_NOND0A_LPLU)) 2411 oem_reg |= HV_OEM_BITS_LPLU; 2412 } 2413 2414 /* Set Restart auto-neg to activate the bits */ 2415 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2416 !hw->phy.ops.check_reset_block(hw)) 2417 oem_reg |= HV_OEM_BITS_RESTART_AN; 2418 2419 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2420 2421 release: 2422 hw->phy.ops.release(hw); 2423 2424 return ret_val; 2425 } 2426 2427 /** 2428 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2429 * @hw: pointer to the HW structure 2430 **/ 2431 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2432 { 2433 s32 ret_val; 2434 u16 data; 2435 2436 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2437 if (ret_val) 2438 return ret_val; 2439 2440 data |= HV_KMRN_MDIO_SLOW; 2441 2442 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2443 2444 return ret_val; 2445 } 2446 2447 /** 2448 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2449 * @hw: pointer to the HW structure 2450 * 2451 * A series of PHY workarounds to be done after every PHY reset. 2452 **/ 2453 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2454 { 2455 s32 ret_val = 0; 2456 u16 phy_data; 2457 2458 if (hw->mac.type != e1000_pchlan) 2459 return 0; 2460 2461 /* Set MDIO slow mode before any other MDIO access */ 2462 if (hw->phy.type == e1000_phy_82577) { 2463 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2464 if (ret_val) 2465 return ret_val; 2466 } 2467 2468 if (((hw->phy.type == e1000_phy_82577) && 2469 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2470 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2471 /* Disable generation of early preamble */ 2472 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2473 if (ret_val) 2474 return ret_val; 2475 2476 /* Preamble tuning for SSC */ 2477 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2478 if (ret_val) 2479 return ret_val; 2480 } 2481 2482 if (hw->phy.type == e1000_phy_82578) { 2483 /* Return registers to default by doing a soft reset then 2484 * writing 0x3140 to the control register. 2485 */ 2486 if (hw->phy.revision < 2) { 2487 e1000e_phy_sw_reset(hw); 2488 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2489 if (ret_val) 2490 return ret_val; 2491 } 2492 } 2493 2494 /* Select page 0 */ 2495 ret_val = hw->phy.ops.acquire(hw); 2496 if (ret_val) 2497 return ret_val; 2498 2499 hw->phy.addr = 1; 2500 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2501 hw->phy.ops.release(hw); 2502 if (ret_val) 2503 return ret_val; 2504 2505 /* Configure the K1 Si workaround during phy reset assuming there is 2506 * link so that it disables K1 if link is in 1Gbps. 2507 */ 2508 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2509 if (ret_val) 2510 return ret_val; 2511 2512 /* Workaround for link disconnects on a busy hub in half duplex */ 2513 ret_val = hw->phy.ops.acquire(hw); 2514 if (ret_val) 2515 return ret_val; 2516 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2517 if (ret_val) 2518 goto release; 2519 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2520 if (ret_val) 2521 goto release; 2522 2523 /* set MSE higher to enable link to stay up when noise is high */ 2524 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2525 release: 2526 hw->phy.ops.release(hw); 2527 2528 return ret_val; 2529 } 2530 2531 /** 2532 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2533 * @hw: pointer to the HW structure 2534 **/ 2535 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2536 { 2537 u32 mac_reg; 2538 u16 i, phy_reg = 0; 2539 s32 ret_val; 2540 2541 ret_val = hw->phy.ops.acquire(hw); 2542 if (ret_val) 2543 return; 2544 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2545 if (ret_val) 2546 goto release; 2547 2548 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2549 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2550 mac_reg = er32(RAL(i)); 2551 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2552 (u16)(mac_reg & 0xFFFF)); 2553 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2554 (u16)((mac_reg >> 16) & 0xFFFF)); 2555 2556 mac_reg = er32(RAH(i)); 2557 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2558 (u16)(mac_reg & 0xFFFF)); 2559 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2560 (u16)((mac_reg & E1000_RAH_AV) 2561 >> 16)); 2562 } 2563 2564 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2565 2566 release: 2567 hw->phy.ops.release(hw); 2568 } 2569 2570 /** 2571 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2572 * with 82579 PHY 2573 * @hw: pointer to the HW structure 2574 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2575 **/ 2576 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2577 { 2578 s32 ret_val = 0; 2579 u16 phy_reg, data; 2580 u32 mac_reg; 2581 u16 i; 2582 2583 if (hw->mac.type < e1000_pch2lan) 2584 return 0; 2585 2586 /* disable Rx path while enabling/disabling workaround */ 2587 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2588 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2589 if (ret_val) 2590 return ret_val; 2591 2592 if (enable) { 2593 /* Write Rx addresses (rar_entry_count for RAL/H, and 2594 * SHRAL/H) and initial CRC values to the MAC 2595 */ 2596 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2597 u8 mac_addr[ETH_ALEN] = { 0 }; 2598 u32 addr_high, addr_low; 2599 2600 addr_high = er32(RAH(i)); 2601 if (!(addr_high & E1000_RAH_AV)) 2602 continue; 2603 addr_low = er32(RAL(i)); 2604 mac_addr[0] = (addr_low & 0xFF); 2605 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2606 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2607 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2608 mac_addr[4] = (addr_high & 0xFF); 2609 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2610 2611 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2612 } 2613 2614 /* Write Rx addresses to the PHY */ 2615 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2616 2617 /* Enable jumbo frame workaround in the MAC */ 2618 mac_reg = er32(FFLT_DBG); 2619 mac_reg &= ~BIT(14); 2620 mac_reg |= (7 << 15); 2621 ew32(FFLT_DBG, mac_reg); 2622 2623 mac_reg = er32(RCTL); 2624 mac_reg |= E1000_RCTL_SECRC; 2625 ew32(RCTL, mac_reg); 2626 2627 ret_val = e1000e_read_kmrn_reg(hw, 2628 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2629 &data); 2630 if (ret_val) 2631 return ret_val; 2632 ret_val = e1000e_write_kmrn_reg(hw, 2633 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2634 data | BIT(0)); 2635 if (ret_val) 2636 return ret_val; 2637 ret_val = e1000e_read_kmrn_reg(hw, 2638 E1000_KMRNCTRLSTA_HD_CTRL, 2639 &data); 2640 if (ret_val) 2641 return ret_val; 2642 data &= ~(0xF << 8); 2643 data |= (0xB << 8); 2644 ret_val = e1000e_write_kmrn_reg(hw, 2645 E1000_KMRNCTRLSTA_HD_CTRL, 2646 data); 2647 if (ret_val) 2648 return ret_val; 2649 2650 /* Enable jumbo frame workaround in the PHY */ 2651 e1e_rphy(hw, PHY_REG(769, 23), &data); 2652 data &= ~(0x7F << 5); 2653 data |= (0x37 << 5); 2654 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2655 if (ret_val) 2656 return ret_val; 2657 e1e_rphy(hw, PHY_REG(769, 16), &data); 2658 data &= ~BIT(13); 2659 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2660 if (ret_val) 2661 return ret_val; 2662 e1e_rphy(hw, PHY_REG(776, 20), &data); 2663 data &= ~(0x3FF << 2); 2664 data |= (E1000_TX_PTR_GAP << 2); 2665 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2666 if (ret_val) 2667 return ret_val; 2668 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2669 if (ret_val) 2670 return ret_val; 2671 e1e_rphy(hw, HV_PM_CTRL, &data); 2672 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2673 if (ret_val) 2674 return ret_val; 2675 } else { 2676 /* Write MAC register values back to h/w defaults */ 2677 mac_reg = er32(FFLT_DBG); 2678 mac_reg &= ~(0xF << 14); 2679 ew32(FFLT_DBG, mac_reg); 2680 2681 mac_reg = er32(RCTL); 2682 mac_reg &= ~E1000_RCTL_SECRC; 2683 ew32(RCTL, mac_reg); 2684 2685 ret_val = e1000e_read_kmrn_reg(hw, 2686 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2687 &data); 2688 if (ret_val) 2689 return ret_val; 2690 ret_val = e1000e_write_kmrn_reg(hw, 2691 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2692 data & ~BIT(0)); 2693 if (ret_val) 2694 return ret_val; 2695 ret_val = e1000e_read_kmrn_reg(hw, 2696 E1000_KMRNCTRLSTA_HD_CTRL, 2697 &data); 2698 if (ret_val) 2699 return ret_val; 2700 data &= ~(0xF << 8); 2701 data |= (0xB << 8); 2702 ret_val = e1000e_write_kmrn_reg(hw, 2703 E1000_KMRNCTRLSTA_HD_CTRL, 2704 data); 2705 if (ret_val) 2706 return ret_val; 2707 2708 /* Write PHY register values back to h/w defaults */ 2709 e1e_rphy(hw, PHY_REG(769, 23), &data); 2710 data &= ~(0x7F << 5); 2711 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2712 if (ret_val) 2713 return ret_val; 2714 e1e_rphy(hw, PHY_REG(769, 16), &data); 2715 data |= BIT(13); 2716 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2717 if (ret_val) 2718 return ret_val; 2719 e1e_rphy(hw, PHY_REG(776, 20), &data); 2720 data &= ~(0x3FF << 2); 2721 data |= (0x8 << 2); 2722 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2723 if (ret_val) 2724 return ret_val; 2725 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2726 if (ret_val) 2727 return ret_val; 2728 e1e_rphy(hw, HV_PM_CTRL, &data); 2729 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2730 if (ret_val) 2731 return ret_val; 2732 } 2733 2734 /* re-enable Rx path after enabling/disabling workaround */ 2735 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2736 } 2737 2738 /** 2739 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2740 * @hw: pointer to the HW structure 2741 * 2742 * A series of PHY workarounds to be done after every PHY reset. 2743 **/ 2744 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2745 { 2746 s32 ret_val = 0; 2747 2748 if (hw->mac.type != e1000_pch2lan) 2749 return 0; 2750 2751 /* Set MDIO slow mode before any other MDIO access */ 2752 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2753 if (ret_val) 2754 return ret_val; 2755 2756 ret_val = hw->phy.ops.acquire(hw); 2757 if (ret_val) 2758 return ret_val; 2759 /* set MSE higher to enable link to stay up when noise is high */ 2760 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2761 if (ret_val) 2762 goto release; 2763 /* drop link after 5 times MSE threshold was reached */ 2764 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2765 release: 2766 hw->phy.ops.release(hw); 2767 2768 return ret_val; 2769 } 2770 2771 /** 2772 * e1000_k1_workaround_lv - K1 Si workaround 2773 * @hw: pointer to the HW structure 2774 * 2775 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2776 * Disable K1 in 1000Mbps and 100Mbps 2777 **/ 2778 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2779 { 2780 s32 ret_val = 0; 2781 u16 status_reg = 0; 2782 2783 if (hw->mac.type != e1000_pch2lan) 2784 return 0; 2785 2786 /* Set K1 beacon duration based on 10Mbs speed */ 2787 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2788 if (ret_val) 2789 return ret_val; 2790 2791 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2792 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2793 if (status_reg & 2794 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2795 u16 pm_phy_reg; 2796 2797 /* LV 1G/100 Packet drop issue wa */ 2798 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2799 if (ret_val) 2800 return ret_val; 2801 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2802 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2803 if (ret_val) 2804 return ret_val; 2805 } else { 2806 u32 mac_reg; 2807 2808 mac_reg = er32(FEXTNVM4); 2809 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2810 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2811 ew32(FEXTNVM4, mac_reg); 2812 } 2813 } 2814 2815 return ret_val; 2816 } 2817 2818 /** 2819 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2820 * @hw: pointer to the HW structure 2821 * @gate: boolean set to true to gate, false to ungate 2822 * 2823 * Gate/ungate the automatic PHY configuration via hardware; perform 2824 * the configuration via software instead. 2825 **/ 2826 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2827 { 2828 u32 extcnf_ctrl; 2829 2830 if (hw->mac.type < e1000_pch2lan) 2831 return; 2832 2833 extcnf_ctrl = er32(EXTCNF_CTRL); 2834 2835 if (gate) 2836 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2837 else 2838 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2839 2840 ew32(EXTCNF_CTRL, extcnf_ctrl); 2841 } 2842 2843 /** 2844 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2845 * @hw: pointer to the HW structure 2846 * 2847 * Check the appropriate indication the MAC has finished configuring the 2848 * PHY after a software reset. 2849 **/ 2850 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2851 { 2852 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2853 2854 /* Wait for basic configuration completes before proceeding */ 2855 do { 2856 data = er32(STATUS); 2857 data &= E1000_STATUS_LAN_INIT_DONE; 2858 usleep_range(100, 200); 2859 } while ((!data) && --loop); 2860 2861 /* If basic configuration is incomplete before the above loop 2862 * count reaches 0, loading the configuration from NVM will 2863 * leave the PHY in a bad state possibly resulting in no link. 2864 */ 2865 if (loop == 0) 2866 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2867 2868 /* Clear the Init Done bit for the next init event */ 2869 data = er32(STATUS); 2870 data &= ~E1000_STATUS_LAN_INIT_DONE; 2871 ew32(STATUS, data); 2872 } 2873 2874 /** 2875 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2876 * @hw: pointer to the HW structure 2877 **/ 2878 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2879 { 2880 s32 ret_val = 0; 2881 u16 reg; 2882 2883 if (hw->phy.ops.check_reset_block(hw)) 2884 return 0; 2885 2886 /* Allow time for h/w to get to quiescent state after reset */ 2887 usleep_range(10000, 11000); 2888 2889 /* Perform any necessary post-reset workarounds */ 2890 switch (hw->mac.type) { 2891 case e1000_pchlan: 2892 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2893 if (ret_val) 2894 return ret_val; 2895 break; 2896 case e1000_pch2lan: 2897 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2898 if (ret_val) 2899 return ret_val; 2900 break; 2901 default: 2902 break; 2903 } 2904 2905 /* Clear the host wakeup bit after lcd reset */ 2906 if (hw->mac.type >= e1000_pchlan) { 2907 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2908 reg &= ~BM_WUC_HOST_WU_BIT; 2909 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2910 } 2911 2912 /* Configure the LCD with the extended configuration region in NVM */ 2913 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2914 if (ret_val) 2915 return ret_val; 2916 2917 /* Configure the LCD with the OEM bits in NVM */ 2918 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2919 2920 if (hw->mac.type == e1000_pch2lan) { 2921 /* Ungate automatic PHY configuration on non-managed 82579 */ 2922 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2923 usleep_range(10000, 11000); 2924 e1000_gate_hw_phy_config_ich8lan(hw, false); 2925 } 2926 2927 /* Set EEE LPI Update Timer to 200usec */ 2928 ret_val = hw->phy.ops.acquire(hw); 2929 if (ret_val) 2930 return ret_val; 2931 ret_val = e1000_write_emi_reg_locked(hw, 2932 I82579_LPI_UPDATE_TIMER, 2933 0x1387); 2934 hw->phy.ops.release(hw); 2935 } 2936 2937 return ret_val; 2938 } 2939 2940 /** 2941 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2942 * @hw: pointer to the HW structure 2943 * 2944 * Resets the PHY 2945 * This is a function pointer entry point called by drivers 2946 * or other shared routines. 2947 **/ 2948 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2949 { 2950 s32 ret_val = 0; 2951 2952 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2953 if ((hw->mac.type == e1000_pch2lan) && 2954 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2955 e1000_gate_hw_phy_config_ich8lan(hw, true); 2956 2957 ret_val = e1000e_phy_hw_reset_generic(hw); 2958 if (ret_val) 2959 return ret_val; 2960 2961 return e1000_post_phy_reset_ich8lan(hw); 2962 } 2963 2964 /** 2965 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2966 * @hw: pointer to the HW structure 2967 * @active: true to enable LPLU, false to disable 2968 * 2969 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2970 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2971 * the phy speed. This function will manually set the LPLU bit and restart 2972 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2973 * since it configures the same bit. 2974 **/ 2975 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2976 { 2977 s32 ret_val; 2978 u16 oem_reg; 2979 2980 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2981 if (ret_val) 2982 return ret_val; 2983 2984 if (active) 2985 oem_reg |= HV_OEM_BITS_LPLU; 2986 else 2987 oem_reg &= ~HV_OEM_BITS_LPLU; 2988 2989 if (!hw->phy.ops.check_reset_block(hw)) 2990 oem_reg |= HV_OEM_BITS_RESTART_AN; 2991 2992 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2993 } 2994 2995 /** 2996 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2997 * @hw: pointer to the HW structure 2998 * @active: true to enable LPLU, false to disable 2999 * 3000 * Sets the LPLU D0 state according to the active flag. When 3001 * activating LPLU this function also disables smart speed 3002 * and vice versa. LPLU will not be activated unless the 3003 * device autonegotiation advertisement meets standards of 3004 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3005 * This is a function pointer entry point only called by 3006 * PHY setup routines. 3007 **/ 3008 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3009 { 3010 struct e1000_phy_info *phy = &hw->phy; 3011 u32 phy_ctrl; 3012 s32 ret_val = 0; 3013 u16 data; 3014 3015 if (phy->type == e1000_phy_ife) 3016 return 0; 3017 3018 phy_ctrl = er32(PHY_CTRL); 3019 3020 if (active) { 3021 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3022 ew32(PHY_CTRL, phy_ctrl); 3023 3024 if (phy->type != e1000_phy_igp_3) 3025 return 0; 3026 3027 /* Call gig speed drop workaround on LPLU before accessing 3028 * any PHY registers 3029 */ 3030 if (hw->mac.type == e1000_ich8lan) 3031 e1000e_gig_downshift_workaround_ich8lan(hw); 3032 3033 /* When LPLU is enabled, we should disable SmartSpeed */ 3034 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3035 if (ret_val) 3036 return ret_val; 3037 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3038 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3039 if (ret_val) 3040 return ret_val; 3041 } else { 3042 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3043 ew32(PHY_CTRL, phy_ctrl); 3044 3045 if (phy->type != e1000_phy_igp_3) 3046 return 0; 3047 3048 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3049 * during Dx states where the power conservation is most 3050 * important. During driver activity we should enable 3051 * SmartSpeed, so performance is maintained. 3052 */ 3053 if (phy->smart_speed == e1000_smart_speed_on) { 3054 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3055 &data); 3056 if (ret_val) 3057 return ret_val; 3058 3059 data |= IGP01E1000_PSCFR_SMART_SPEED; 3060 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3061 data); 3062 if (ret_val) 3063 return ret_val; 3064 } else if (phy->smart_speed == e1000_smart_speed_off) { 3065 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3066 &data); 3067 if (ret_val) 3068 return ret_val; 3069 3070 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3071 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3072 data); 3073 if (ret_val) 3074 return ret_val; 3075 } 3076 } 3077 3078 return 0; 3079 } 3080 3081 /** 3082 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3083 * @hw: pointer to the HW structure 3084 * @active: true to enable LPLU, false to disable 3085 * 3086 * Sets the LPLU D3 state according to the active flag. When 3087 * activating LPLU this function also disables smart speed 3088 * and vice versa. LPLU will not be activated unless the 3089 * device autonegotiation advertisement meets standards of 3090 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3091 * This is a function pointer entry point only called by 3092 * PHY setup routines. 3093 **/ 3094 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3095 { 3096 struct e1000_phy_info *phy = &hw->phy; 3097 u32 phy_ctrl; 3098 s32 ret_val = 0; 3099 u16 data; 3100 3101 phy_ctrl = er32(PHY_CTRL); 3102 3103 if (!active) { 3104 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3105 ew32(PHY_CTRL, phy_ctrl); 3106 3107 if (phy->type != e1000_phy_igp_3) 3108 return 0; 3109 3110 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3111 * during Dx states where the power conservation is most 3112 * important. During driver activity we should enable 3113 * SmartSpeed, so performance is maintained. 3114 */ 3115 if (phy->smart_speed == e1000_smart_speed_on) { 3116 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3117 &data); 3118 if (ret_val) 3119 return ret_val; 3120 3121 data |= IGP01E1000_PSCFR_SMART_SPEED; 3122 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3123 data); 3124 if (ret_val) 3125 return ret_val; 3126 } else if (phy->smart_speed == e1000_smart_speed_off) { 3127 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3128 &data); 3129 if (ret_val) 3130 return ret_val; 3131 3132 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3133 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3134 data); 3135 if (ret_val) 3136 return ret_val; 3137 } 3138 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3139 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3140 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3141 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3142 ew32(PHY_CTRL, phy_ctrl); 3143 3144 if (phy->type != e1000_phy_igp_3) 3145 return 0; 3146 3147 /* Call gig speed drop workaround on LPLU before accessing 3148 * any PHY registers 3149 */ 3150 if (hw->mac.type == e1000_ich8lan) 3151 e1000e_gig_downshift_workaround_ich8lan(hw); 3152 3153 /* When LPLU is enabled, we should disable SmartSpeed */ 3154 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3155 if (ret_val) 3156 return ret_val; 3157 3158 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3159 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3160 } 3161 3162 return ret_val; 3163 } 3164 3165 /** 3166 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3167 * @hw: pointer to the HW structure 3168 * @bank: pointer to the variable that returns the active bank 3169 * 3170 * Reads signature byte from the NVM using the flash access registers. 3171 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3172 **/ 3173 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3174 { 3175 u32 eecd; 3176 struct e1000_nvm_info *nvm = &hw->nvm; 3177 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3178 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3179 u32 nvm_dword = 0; 3180 u8 sig_byte = 0; 3181 s32 ret_val; 3182 3183 switch (hw->mac.type) { 3184 case e1000_pch_spt: 3185 case e1000_pch_cnp: 3186 case e1000_pch_tgp: 3187 case e1000_pch_adp: 3188 case e1000_pch_mtp: 3189 case e1000_pch_lnp: 3190 case e1000_pch_ptp: 3191 bank1_offset = nvm->flash_bank_size; 3192 act_offset = E1000_ICH_NVM_SIG_WORD; 3193 3194 /* set bank to 0 in case flash read fails */ 3195 *bank = 0; 3196 3197 /* Check bank 0 */ 3198 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3199 &nvm_dword); 3200 if (ret_val) 3201 return ret_val; 3202 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3203 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3204 E1000_ICH_NVM_SIG_VALUE) { 3205 *bank = 0; 3206 return 0; 3207 } 3208 3209 /* Check bank 1 */ 3210 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3211 bank1_offset, 3212 &nvm_dword); 3213 if (ret_val) 3214 return ret_val; 3215 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3216 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3217 E1000_ICH_NVM_SIG_VALUE) { 3218 *bank = 1; 3219 return 0; 3220 } 3221 3222 e_dbg("ERROR: No valid NVM bank present\n"); 3223 return -E1000_ERR_NVM; 3224 case e1000_ich8lan: 3225 case e1000_ich9lan: 3226 eecd = er32(EECD); 3227 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3228 E1000_EECD_SEC1VAL_VALID_MASK) { 3229 if (eecd & E1000_EECD_SEC1VAL) 3230 *bank = 1; 3231 else 3232 *bank = 0; 3233 3234 return 0; 3235 } 3236 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3237 fallthrough; 3238 default: 3239 /* set bank to 0 in case flash read fails */ 3240 *bank = 0; 3241 3242 /* Check bank 0 */ 3243 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3244 &sig_byte); 3245 if (ret_val) 3246 return ret_val; 3247 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3248 E1000_ICH_NVM_SIG_VALUE) { 3249 *bank = 0; 3250 return 0; 3251 } 3252 3253 /* Check bank 1 */ 3254 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3255 bank1_offset, 3256 &sig_byte); 3257 if (ret_val) 3258 return ret_val; 3259 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3260 E1000_ICH_NVM_SIG_VALUE) { 3261 *bank = 1; 3262 return 0; 3263 } 3264 3265 e_dbg("ERROR: No valid NVM bank present\n"); 3266 return -E1000_ERR_NVM; 3267 } 3268 } 3269 3270 /** 3271 * e1000_read_nvm_spt - NVM access for SPT 3272 * @hw: pointer to the HW structure 3273 * @offset: The offset (in bytes) of the word(s) to read. 3274 * @words: Size of data to read in words. 3275 * @data: pointer to the word(s) to read at offset. 3276 * 3277 * Reads a word(s) from the NVM 3278 **/ 3279 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3280 u16 *data) 3281 { 3282 struct e1000_nvm_info *nvm = &hw->nvm; 3283 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3284 u32 act_offset; 3285 s32 ret_val = 0; 3286 u32 bank = 0; 3287 u32 dword = 0; 3288 u16 offset_to_read; 3289 u16 i; 3290 3291 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3292 (words == 0)) { 3293 e_dbg("nvm parameter(s) out of bounds\n"); 3294 ret_val = -E1000_ERR_NVM; 3295 goto out; 3296 } 3297 3298 nvm->ops.acquire(hw); 3299 3300 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3301 if (ret_val) { 3302 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3303 bank = 0; 3304 } 3305 3306 act_offset = (bank) ? nvm->flash_bank_size : 0; 3307 act_offset += offset; 3308 3309 ret_val = 0; 3310 3311 for (i = 0; i < words; i += 2) { 3312 if (words - i == 1) { 3313 if (dev_spec->shadow_ram[offset + i].modified) { 3314 data[i] = 3315 dev_spec->shadow_ram[offset + i].value; 3316 } else { 3317 offset_to_read = act_offset + i - 3318 ((act_offset + i) % 2); 3319 ret_val = 3320 e1000_read_flash_dword_ich8lan(hw, 3321 offset_to_read, 3322 &dword); 3323 if (ret_val) 3324 break; 3325 if ((act_offset + i) % 2 == 0) 3326 data[i] = (u16)(dword & 0xFFFF); 3327 else 3328 data[i] = (u16)((dword >> 16) & 0xFFFF); 3329 } 3330 } else { 3331 offset_to_read = act_offset + i; 3332 if (!(dev_spec->shadow_ram[offset + i].modified) || 3333 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3334 ret_val = 3335 e1000_read_flash_dword_ich8lan(hw, 3336 offset_to_read, 3337 &dword); 3338 if (ret_val) 3339 break; 3340 } 3341 if (dev_spec->shadow_ram[offset + i].modified) 3342 data[i] = 3343 dev_spec->shadow_ram[offset + i].value; 3344 else 3345 data[i] = (u16)(dword & 0xFFFF); 3346 if (dev_spec->shadow_ram[offset + i].modified) 3347 data[i + 1] = 3348 dev_spec->shadow_ram[offset + i + 1].value; 3349 else 3350 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3351 } 3352 } 3353 3354 nvm->ops.release(hw); 3355 3356 out: 3357 if (ret_val) 3358 e_dbg("NVM read error: %d\n", ret_val); 3359 3360 return ret_val; 3361 } 3362 3363 /** 3364 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3365 * @hw: pointer to the HW structure 3366 * @offset: The offset (in bytes) of the word(s) to read. 3367 * @words: Size of data to read in words 3368 * @data: Pointer to the word(s) to read at offset. 3369 * 3370 * Reads a word(s) from the NVM using the flash access registers. 3371 **/ 3372 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3373 u16 *data) 3374 { 3375 struct e1000_nvm_info *nvm = &hw->nvm; 3376 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3377 u32 act_offset; 3378 s32 ret_val = 0; 3379 u32 bank = 0; 3380 u16 i, word; 3381 3382 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3383 (words == 0)) { 3384 e_dbg("nvm parameter(s) out of bounds\n"); 3385 ret_val = -E1000_ERR_NVM; 3386 goto out; 3387 } 3388 3389 nvm->ops.acquire(hw); 3390 3391 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3392 if (ret_val) { 3393 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3394 bank = 0; 3395 } 3396 3397 act_offset = (bank) ? nvm->flash_bank_size : 0; 3398 act_offset += offset; 3399 3400 ret_val = 0; 3401 for (i = 0; i < words; i++) { 3402 if (dev_spec->shadow_ram[offset + i].modified) { 3403 data[i] = dev_spec->shadow_ram[offset + i].value; 3404 } else { 3405 ret_val = e1000_read_flash_word_ich8lan(hw, 3406 act_offset + i, 3407 &word); 3408 if (ret_val) 3409 break; 3410 data[i] = word; 3411 } 3412 } 3413 3414 nvm->ops.release(hw); 3415 3416 out: 3417 if (ret_val) 3418 e_dbg("NVM read error: %d\n", ret_val); 3419 3420 return ret_val; 3421 } 3422 3423 /** 3424 * e1000_flash_cycle_init_ich8lan - Initialize flash 3425 * @hw: pointer to the HW structure 3426 * 3427 * This function does initial flash setup so that a new read/write/erase cycle 3428 * can be started. 3429 **/ 3430 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3431 { 3432 union ich8_hws_flash_status hsfsts; 3433 s32 ret_val = -E1000_ERR_NVM; 3434 3435 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3436 3437 /* Check if the flash descriptor is valid */ 3438 if (!hsfsts.hsf_status.fldesvalid) { 3439 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3440 return -E1000_ERR_NVM; 3441 } 3442 3443 /* Clear FCERR and DAEL in hw status by writing 1 */ 3444 hsfsts.hsf_status.flcerr = 1; 3445 hsfsts.hsf_status.dael = 1; 3446 if (hw->mac.type >= e1000_pch_spt) 3447 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3448 else 3449 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3450 3451 /* Either we should have a hardware SPI cycle in progress 3452 * bit to check against, in order to start a new cycle or 3453 * FDONE bit should be changed in the hardware so that it 3454 * is 1 after hardware reset, which can then be used as an 3455 * indication whether a cycle is in progress or has been 3456 * completed. 3457 */ 3458 3459 if (!hsfsts.hsf_status.flcinprog) { 3460 /* There is no cycle running at present, 3461 * so we can start a cycle. 3462 * Begin by setting Flash Cycle Done. 3463 */ 3464 hsfsts.hsf_status.flcdone = 1; 3465 if (hw->mac.type >= e1000_pch_spt) 3466 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3467 else 3468 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3469 ret_val = 0; 3470 } else { 3471 s32 i; 3472 3473 /* Otherwise poll for sometime so the current 3474 * cycle has a chance to end before giving up. 3475 */ 3476 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3477 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3478 if (!hsfsts.hsf_status.flcinprog) { 3479 ret_val = 0; 3480 break; 3481 } 3482 udelay(1); 3483 } 3484 if (!ret_val) { 3485 /* Successful in waiting for previous cycle to timeout, 3486 * now set the Flash Cycle Done. 3487 */ 3488 hsfsts.hsf_status.flcdone = 1; 3489 if (hw->mac.type >= e1000_pch_spt) 3490 ew32flash(ICH_FLASH_HSFSTS, 3491 hsfsts.regval & 0xFFFF); 3492 else 3493 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3494 } else { 3495 e_dbg("Flash controller busy, cannot get access\n"); 3496 } 3497 } 3498 3499 return ret_val; 3500 } 3501 3502 /** 3503 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3504 * @hw: pointer to the HW structure 3505 * @timeout: maximum time to wait for completion 3506 * 3507 * This function starts a flash cycle and waits for its completion. 3508 **/ 3509 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3510 { 3511 union ich8_hws_flash_ctrl hsflctl; 3512 union ich8_hws_flash_status hsfsts; 3513 u32 i = 0; 3514 3515 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3516 if (hw->mac.type >= e1000_pch_spt) 3517 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3518 else 3519 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3520 hsflctl.hsf_ctrl.flcgo = 1; 3521 3522 if (hw->mac.type >= e1000_pch_spt) 3523 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3524 else 3525 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3526 3527 /* wait till FDONE bit is set to 1 */ 3528 do { 3529 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3530 if (hsfsts.hsf_status.flcdone) 3531 break; 3532 udelay(1); 3533 } while (i++ < timeout); 3534 3535 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3536 return 0; 3537 3538 return -E1000_ERR_NVM; 3539 } 3540 3541 /** 3542 * e1000_read_flash_dword_ich8lan - Read dword from flash 3543 * @hw: pointer to the HW structure 3544 * @offset: offset to data location 3545 * @data: pointer to the location for storing the data 3546 * 3547 * Reads the flash dword at offset into data. Offset is converted 3548 * to bytes before read. 3549 **/ 3550 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3551 u32 *data) 3552 { 3553 /* Must convert word offset into bytes. */ 3554 offset <<= 1; 3555 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3556 } 3557 3558 /** 3559 * e1000_read_flash_word_ich8lan - Read word from flash 3560 * @hw: pointer to the HW structure 3561 * @offset: offset to data location 3562 * @data: pointer to the location for storing the data 3563 * 3564 * Reads the flash word at offset into data. Offset is converted 3565 * to bytes before read. 3566 **/ 3567 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3568 u16 *data) 3569 { 3570 /* Must convert offset into bytes. */ 3571 offset <<= 1; 3572 3573 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3574 } 3575 3576 /** 3577 * e1000_read_flash_byte_ich8lan - Read byte from flash 3578 * @hw: pointer to the HW structure 3579 * @offset: The offset of the byte to read. 3580 * @data: Pointer to a byte to store the value read. 3581 * 3582 * Reads a single byte from the NVM using the flash access registers. 3583 **/ 3584 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3585 u8 *data) 3586 { 3587 s32 ret_val; 3588 u16 word = 0; 3589 3590 /* In SPT, only 32 bits access is supported, 3591 * so this function should not be called. 3592 */ 3593 if (hw->mac.type >= e1000_pch_spt) 3594 return -E1000_ERR_NVM; 3595 else 3596 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3597 3598 if (ret_val) 3599 return ret_val; 3600 3601 *data = (u8)word; 3602 3603 return 0; 3604 } 3605 3606 /** 3607 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3608 * @hw: pointer to the HW structure 3609 * @offset: The offset (in bytes) of the byte or word to read. 3610 * @size: Size of data to read, 1=byte 2=word 3611 * @data: Pointer to the word to store the value read. 3612 * 3613 * Reads a byte or word from the NVM using the flash access registers. 3614 **/ 3615 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3616 u8 size, u16 *data) 3617 { 3618 union ich8_hws_flash_status hsfsts; 3619 union ich8_hws_flash_ctrl hsflctl; 3620 u32 flash_linear_addr; 3621 u32 flash_data = 0; 3622 s32 ret_val = -E1000_ERR_NVM; 3623 u8 count = 0; 3624 3625 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3626 return -E1000_ERR_NVM; 3627 3628 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3629 hw->nvm.flash_base_addr); 3630 3631 do { 3632 udelay(1); 3633 /* Steps */ 3634 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3635 if (ret_val) 3636 break; 3637 3638 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3639 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3640 hsflctl.hsf_ctrl.fldbcount = size - 1; 3641 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3642 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3643 3644 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3645 3646 ret_val = 3647 e1000_flash_cycle_ich8lan(hw, 3648 ICH_FLASH_READ_COMMAND_TIMEOUT); 3649 3650 /* Check if FCERR is set to 1, if set to 1, clear it 3651 * and try the whole sequence a few more times, else 3652 * read in (shift in) the Flash Data0, the order is 3653 * least significant byte first msb to lsb 3654 */ 3655 if (!ret_val) { 3656 flash_data = er32flash(ICH_FLASH_FDATA0); 3657 if (size == 1) 3658 *data = (u8)(flash_data & 0x000000FF); 3659 else if (size == 2) 3660 *data = (u16)(flash_data & 0x0000FFFF); 3661 break; 3662 } else { 3663 /* If we've gotten here, then things are probably 3664 * completely hosed, but if the error condition is 3665 * detected, it won't hurt to give it another try... 3666 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3667 */ 3668 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3669 if (hsfsts.hsf_status.flcerr) { 3670 /* Repeat for some time before giving up. */ 3671 continue; 3672 } else if (!hsfsts.hsf_status.flcdone) { 3673 e_dbg("Timeout error - flash cycle did not complete.\n"); 3674 break; 3675 } 3676 } 3677 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3678 3679 return ret_val; 3680 } 3681 3682 /** 3683 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3684 * @hw: pointer to the HW structure 3685 * @offset: The offset (in bytes) of the dword to read. 3686 * @data: Pointer to the dword to store the value read. 3687 * 3688 * Reads a byte or word from the NVM using the flash access registers. 3689 **/ 3690 3691 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3692 u32 *data) 3693 { 3694 union ich8_hws_flash_status hsfsts; 3695 union ich8_hws_flash_ctrl hsflctl; 3696 u32 flash_linear_addr; 3697 s32 ret_val = -E1000_ERR_NVM; 3698 u8 count = 0; 3699 3700 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3701 return -E1000_ERR_NVM; 3702 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3703 hw->nvm.flash_base_addr); 3704 3705 do { 3706 udelay(1); 3707 /* Steps */ 3708 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3709 if (ret_val) 3710 break; 3711 /* In SPT, This register is in Lan memory space, not flash. 3712 * Therefore, only 32 bit access is supported 3713 */ 3714 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3715 3716 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3717 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3718 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3719 /* In SPT, This register is in Lan memory space, not flash. 3720 * Therefore, only 32 bit access is supported 3721 */ 3722 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3723 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3724 3725 ret_val = 3726 e1000_flash_cycle_ich8lan(hw, 3727 ICH_FLASH_READ_COMMAND_TIMEOUT); 3728 3729 /* Check if FCERR is set to 1, if set to 1, clear it 3730 * and try the whole sequence a few more times, else 3731 * read in (shift in) the Flash Data0, the order is 3732 * least significant byte first msb to lsb 3733 */ 3734 if (!ret_val) { 3735 *data = er32flash(ICH_FLASH_FDATA0); 3736 break; 3737 } else { 3738 /* If we've gotten here, then things are probably 3739 * completely hosed, but if the error condition is 3740 * detected, it won't hurt to give it another try... 3741 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3742 */ 3743 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3744 if (hsfsts.hsf_status.flcerr) { 3745 /* Repeat for some time before giving up. */ 3746 continue; 3747 } else if (!hsfsts.hsf_status.flcdone) { 3748 e_dbg("Timeout error - flash cycle did not complete.\n"); 3749 break; 3750 } 3751 } 3752 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3753 3754 return ret_val; 3755 } 3756 3757 /** 3758 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3759 * @hw: pointer to the HW structure 3760 * @offset: The offset (in bytes) of the word(s) to write. 3761 * @words: Size of data to write in words 3762 * @data: Pointer to the word(s) to write at offset. 3763 * 3764 * Writes a byte or word to the NVM using the flash access registers. 3765 **/ 3766 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3767 u16 *data) 3768 { 3769 struct e1000_nvm_info *nvm = &hw->nvm; 3770 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3771 u16 i; 3772 3773 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3774 (words == 0)) { 3775 e_dbg("nvm parameter(s) out of bounds\n"); 3776 return -E1000_ERR_NVM; 3777 } 3778 3779 nvm->ops.acquire(hw); 3780 3781 for (i = 0; i < words; i++) { 3782 dev_spec->shadow_ram[offset + i].modified = true; 3783 dev_spec->shadow_ram[offset + i].value = data[i]; 3784 } 3785 3786 nvm->ops.release(hw); 3787 3788 return 0; 3789 } 3790 3791 /** 3792 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3793 * @hw: pointer to the HW structure 3794 * 3795 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3796 * which writes the checksum to the shadow ram. The changes in the shadow 3797 * ram are then committed to the EEPROM by processing each bank at a time 3798 * checking for the modified bit and writing only the pending changes. 3799 * After a successful commit, the shadow ram is cleared and is ready for 3800 * future writes. 3801 **/ 3802 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3803 { 3804 struct e1000_nvm_info *nvm = &hw->nvm; 3805 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3806 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3807 s32 ret_val; 3808 u32 dword = 0; 3809 3810 ret_val = e1000e_update_nvm_checksum_generic(hw); 3811 if (ret_val) 3812 goto out; 3813 3814 if (nvm->type != e1000_nvm_flash_sw) 3815 goto out; 3816 3817 nvm->ops.acquire(hw); 3818 3819 /* We're writing to the opposite bank so if we're on bank 1, 3820 * write to bank 0 etc. We also need to erase the segment that 3821 * is going to be written 3822 */ 3823 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3824 if (ret_val) { 3825 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3826 bank = 0; 3827 } 3828 3829 if (bank == 0) { 3830 new_bank_offset = nvm->flash_bank_size; 3831 old_bank_offset = 0; 3832 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3833 if (ret_val) 3834 goto release; 3835 } else { 3836 old_bank_offset = nvm->flash_bank_size; 3837 new_bank_offset = 0; 3838 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3839 if (ret_val) 3840 goto release; 3841 } 3842 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3843 /* Determine whether to write the value stored 3844 * in the other NVM bank or a modified value stored 3845 * in the shadow RAM 3846 */ 3847 ret_val = e1000_read_flash_dword_ich8lan(hw, 3848 i + old_bank_offset, 3849 &dword); 3850 3851 if (dev_spec->shadow_ram[i].modified) { 3852 dword &= 0xffff0000; 3853 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3854 } 3855 if (dev_spec->shadow_ram[i + 1].modified) { 3856 dword &= 0x0000ffff; 3857 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3858 << 16); 3859 } 3860 if (ret_val) 3861 break; 3862 3863 /* If the word is 0x13, then make sure the signature bits 3864 * (15:14) are 11b until the commit has completed. 3865 * This will allow us to write 10b which indicates the 3866 * signature is valid. We want to do this after the write 3867 * has completed so that we don't mark the segment valid 3868 * while the write is still in progress 3869 */ 3870 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3871 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3872 3873 /* Convert offset to bytes. */ 3874 act_offset = (i + new_bank_offset) << 1; 3875 3876 usleep_range(100, 200); 3877 3878 /* Write the data to the new bank. Offset in words */ 3879 act_offset = i + new_bank_offset; 3880 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3881 dword); 3882 if (ret_val) 3883 break; 3884 } 3885 3886 /* Don't bother writing the segment valid bits if sector 3887 * programming failed. 3888 */ 3889 if (ret_val) { 3890 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3891 e_dbg("Flash commit failed.\n"); 3892 goto release; 3893 } 3894 3895 /* Finally validate the new segment by setting bit 15:14 3896 * to 10b in word 0x13 , this can be done without an 3897 * erase as well since these bits are 11 to start with 3898 * and we need to change bit 14 to 0b 3899 */ 3900 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3901 3902 /*offset in words but we read dword */ 3903 --act_offset; 3904 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3905 3906 if (ret_val) 3907 goto release; 3908 3909 dword &= 0xBFFFFFFF; 3910 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3911 3912 if (ret_val) 3913 goto release; 3914 3915 /* offset in words but we read dword */ 3916 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3917 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3918 3919 if (ret_val) 3920 goto release; 3921 3922 dword &= 0x00FFFFFF; 3923 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3924 3925 if (ret_val) 3926 goto release; 3927 3928 /* Great! Everything worked, we can now clear the cached entries. */ 3929 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3930 dev_spec->shadow_ram[i].modified = false; 3931 dev_spec->shadow_ram[i].value = 0xFFFF; 3932 } 3933 3934 release: 3935 nvm->ops.release(hw); 3936 3937 /* Reload the EEPROM, or else modifications will not appear 3938 * until after the next adapter reset. 3939 */ 3940 if (!ret_val) { 3941 nvm->ops.reload(hw); 3942 usleep_range(10000, 11000); 3943 } 3944 3945 out: 3946 if (ret_val) 3947 e_dbg("NVM update error: %d\n", ret_val); 3948 3949 return ret_val; 3950 } 3951 3952 /** 3953 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3954 * @hw: pointer to the HW structure 3955 * 3956 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3957 * which writes the checksum to the shadow ram. The changes in the shadow 3958 * ram are then committed to the EEPROM by processing each bank at a time 3959 * checking for the modified bit and writing only the pending changes. 3960 * After a successful commit, the shadow ram is cleared and is ready for 3961 * future writes. 3962 **/ 3963 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3964 { 3965 struct e1000_nvm_info *nvm = &hw->nvm; 3966 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3967 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3968 s32 ret_val; 3969 u16 data = 0; 3970 3971 ret_val = e1000e_update_nvm_checksum_generic(hw); 3972 if (ret_val) 3973 goto out; 3974 3975 if (nvm->type != e1000_nvm_flash_sw) 3976 goto out; 3977 3978 nvm->ops.acquire(hw); 3979 3980 /* We're writing to the opposite bank so if we're on bank 1, 3981 * write to bank 0 etc. We also need to erase the segment that 3982 * is going to be written 3983 */ 3984 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3985 if (ret_val) { 3986 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3987 bank = 0; 3988 } 3989 3990 if (bank == 0) { 3991 new_bank_offset = nvm->flash_bank_size; 3992 old_bank_offset = 0; 3993 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3994 if (ret_val) 3995 goto release; 3996 } else { 3997 old_bank_offset = nvm->flash_bank_size; 3998 new_bank_offset = 0; 3999 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4000 if (ret_val) 4001 goto release; 4002 } 4003 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4004 if (dev_spec->shadow_ram[i].modified) { 4005 data = dev_spec->shadow_ram[i].value; 4006 } else { 4007 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4008 old_bank_offset, 4009 &data); 4010 if (ret_val) 4011 break; 4012 } 4013 4014 /* If the word is 0x13, then make sure the signature bits 4015 * (15:14) are 11b until the commit has completed. 4016 * This will allow us to write 10b which indicates the 4017 * signature is valid. We want to do this after the write 4018 * has completed so that we don't mark the segment valid 4019 * while the write is still in progress 4020 */ 4021 if (i == E1000_ICH_NVM_SIG_WORD) 4022 data |= E1000_ICH_NVM_SIG_MASK; 4023 4024 /* Convert offset to bytes. */ 4025 act_offset = (i + new_bank_offset) << 1; 4026 4027 usleep_range(100, 200); 4028 /* Write the bytes to the new bank. */ 4029 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4030 act_offset, 4031 (u8)data); 4032 if (ret_val) 4033 break; 4034 4035 usleep_range(100, 200); 4036 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4037 act_offset + 1, 4038 (u8)(data >> 8)); 4039 if (ret_val) 4040 break; 4041 } 4042 4043 /* Don't bother writing the segment valid bits if sector 4044 * programming failed. 4045 */ 4046 if (ret_val) { 4047 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4048 e_dbg("Flash commit failed.\n"); 4049 goto release; 4050 } 4051 4052 /* Finally validate the new segment by setting bit 15:14 4053 * to 10b in word 0x13 , this can be done without an 4054 * erase as well since these bits are 11 to start with 4055 * and we need to change bit 14 to 0b 4056 */ 4057 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4058 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4059 if (ret_val) 4060 goto release; 4061 4062 data &= 0xBFFF; 4063 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4064 act_offset * 2 + 1, 4065 (u8)(data >> 8)); 4066 if (ret_val) 4067 goto release; 4068 4069 /* And invalidate the previously valid segment by setting 4070 * its signature word (0x13) high_byte to 0b. This can be 4071 * done without an erase because flash erase sets all bits 4072 * to 1's. We can write 1's to 0's without an erase 4073 */ 4074 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4075 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4076 if (ret_val) 4077 goto release; 4078 4079 /* Great! Everything worked, we can now clear the cached entries. */ 4080 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4081 dev_spec->shadow_ram[i].modified = false; 4082 dev_spec->shadow_ram[i].value = 0xFFFF; 4083 } 4084 4085 release: 4086 nvm->ops.release(hw); 4087 4088 /* Reload the EEPROM, or else modifications will not appear 4089 * until after the next adapter reset. 4090 */ 4091 if (!ret_val) { 4092 nvm->ops.reload(hw); 4093 usleep_range(10000, 11000); 4094 } 4095 4096 out: 4097 if (ret_val) 4098 e_dbg("NVM update error: %d\n", ret_val); 4099 4100 return ret_val; 4101 } 4102 4103 /** 4104 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4105 * @hw: pointer to the HW structure 4106 * 4107 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4108 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4109 * calculated, in which case we need to calculate the checksum and set bit 6. 4110 **/ 4111 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4112 { 4113 s32 ret_val; 4114 u16 data; 4115 u16 word; 4116 u16 valid_csum_mask; 4117 4118 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4119 * the checksum needs to be fixed. This bit is an indication that 4120 * the NVM was prepared by OEM software and did not calculate 4121 * the checksum...a likely scenario. 4122 */ 4123 switch (hw->mac.type) { 4124 case e1000_pch_lpt: 4125 case e1000_pch_spt: 4126 case e1000_pch_cnp: 4127 case e1000_pch_tgp: 4128 case e1000_pch_adp: 4129 case e1000_pch_mtp: 4130 case e1000_pch_lnp: 4131 case e1000_pch_ptp: 4132 word = NVM_COMPAT; 4133 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4134 break; 4135 default: 4136 word = NVM_FUTURE_INIT_WORD1; 4137 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4138 break; 4139 } 4140 4141 ret_val = e1000_read_nvm(hw, word, 1, &data); 4142 if (ret_val) 4143 return ret_val; 4144 4145 if (!(data & valid_csum_mask)) { 4146 e_dbg("NVM Checksum valid bit not set\n"); 4147 4148 if (hw->mac.type < e1000_pch_tgp) { 4149 data |= valid_csum_mask; 4150 ret_val = e1000_write_nvm(hw, word, 1, &data); 4151 if (ret_val) 4152 return ret_val; 4153 ret_val = e1000e_update_nvm_checksum(hw); 4154 if (ret_val) 4155 return ret_val; 4156 } 4157 } 4158 4159 return e1000e_validate_nvm_checksum_generic(hw); 4160 } 4161 4162 /** 4163 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4164 * @hw: pointer to the HW structure 4165 * 4166 * To prevent malicious write/erase of the NVM, set it to be read-only 4167 * so that the hardware ignores all write/erase cycles of the NVM via 4168 * the flash control registers. The shadow-ram copy of the NVM will 4169 * still be updated, however any updates to this copy will not stick 4170 * across driver reloads. 4171 **/ 4172 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4173 { 4174 struct e1000_nvm_info *nvm = &hw->nvm; 4175 union ich8_flash_protected_range pr0; 4176 union ich8_hws_flash_status hsfsts; 4177 u32 gfpreg; 4178 4179 nvm->ops.acquire(hw); 4180 4181 gfpreg = er32flash(ICH_FLASH_GFPREG); 4182 4183 /* Write-protect GbE Sector of NVM */ 4184 pr0.regval = er32flash(ICH_FLASH_PR0); 4185 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4186 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4187 pr0.range.wpe = true; 4188 ew32flash(ICH_FLASH_PR0, pr0.regval); 4189 4190 /* Lock down a subset of GbE Flash Control Registers, e.g. 4191 * PR0 to prevent the write-protection from being lifted. 4192 * Once FLOCKDN is set, the registers protected by it cannot 4193 * be written until FLOCKDN is cleared by a hardware reset. 4194 */ 4195 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4196 hsfsts.hsf_status.flockdn = true; 4197 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4198 4199 nvm->ops.release(hw); 4200 } 4201 4202 /** 4203 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4204 * @hw: pointer to the HW structure 4205 * @offset: The offset (in bytes) of the byte/word to read. 4206 * @size: Size of data to read, 1=byte 2=word 4207 * @data: The byte(s) to write to the NVM. 4208 * 4209 * Writes one/two bytes to the NVM using the flash access registers. 4210 **/ 4211 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4212 u8 size, u16 data) 4213 { 4214 union ich8_hws_flash_status hsfsts; 4215 union ich8_hws_flash_ctrl hsflctl; 4216 u32 flash_linear_addr; 4217 u32 flash_data = 0; 4218 s32 ret_val; 4219 u8 count = 0; 4220 4221 if (hw->mac.type >= e1000_pch_spt) { 4222 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4223 return -E1000_ERR_NVM; 4224 } else { 4225 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4226 return -E1000_ERR_NVM; 4227 } 4228 4229 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4230 hw->nvm.flash_base_addr); 4231 4232 do { 4233 udelay(1); 4234 /* Steps */ 4235 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4236 if (ret_val) 4237 break; 4238 /* In SPT, This register is in Lan memory space, not 4239 * flash. Therefore, only 32 bit access is supported 4240 */ 4241 if (hw->mac.type >= e1000_pch_spt) 4242 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4243 else 4244 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4245 4246 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4247 hsflctl.hsf_ctrl.fldbcount = size - 1; 4248 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4249 /* In SPT, This register is in Lan memory space, 4250 * not flash. Therefore, only 32 bit access is 4251 * supported 4252 */ 4253 if (hw->mac.type >= e1000_pch_spt) 4254 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4255 else 4256 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4257 4258 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4259 4260 if (size == 1) 4261 flash_data = (u32)data & 0x00FF; 4262 else 4263 flash_data = (u32)data; 4264 4265 ew32flash(ICH_FLASH_FDATA0, flash_data); 4266 4267 /* check if FCERR is set to 1 , if set to 1, clear it 4268 * and try the whole sequence a few more times else done 4269 */ 4270 ret_val = 4271 e1000_flash_cycle_ich8lan(hw, 4272 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4273 if (!ret_val) 4274 break; 4275 4276 /* If we're here, then things are most likely 4277 * completely hosed, but if the error condition 4278 * is detected, it won't hurt to give it another 4279 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4280 */ 4281 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4282 if (hsfsts.hsf_status.flcerr) 4283 /* Repeat for some time before giving up. */ 4284 continue; 4285 if (!hsfsts.hsf_status.flcdone) { 4286 e_dbg("Timeout error - flash cycle did not complete.\n"); 4287 break; 4288 } 4289 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4290 4291 return ret_val; 4292 } 4293 4294 /** 4295 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4296 * @hw: pointer to the HW structure 4297 * @offset: The offset (in bytes) of the dwords to read. 4298 * @data: The 4 bytes to write to the NVM. 4299 * 4300 * Writes one/two/four bytes to the NVM using the flash access registers. 4301 **/ 4302 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4303 u32 data) 4304 { 4305 union ich8_hws_flash_status hsfsts; 4306 union ich8_hws_flash_ctrl hsflctl; 4307 u32 flash_linear_addr; 4308 s32 ret_val; 4309 u8 count = 0; 4310 4311 if (hw->mac.type >= e1000_pch_spt) { 4312 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4313 return -E1000_ERR_NVM; 4314 } 4315 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4316 hw->nvm.flash_base_addr); 4317 do { 4318 udelay(1); 4319 /* Steps */ 4320 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4321 if (ret_val) 4322 break; 4323 4324 /* In SPT, This register is in Lan memory space, not 4325 * flash. Therefore, only 32 bit access is supported 4326 */ 4327 if (hw->mac.type >= e1000_pch_spt) 4328 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4329 >> 16; 4330 else 4331 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4332 4333 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4334 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4335 4336 /* In SPT, This register is in Lan memory space, 4337 * not flash. Therefore, only 32 bit access is 4338 * supported 4339 */ 4340 if (hw->mac.type >= e1000_pch_spt) 4341 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4342 else 4343 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4344 4345 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4346 4347 ew32flash(ICH_FLASH_FDATA0, data); 4348 4349 /* check if FCERR is set to 1 , if set to 1, clear it 4350 * and try the whole sequence a few more times else done 4351 */ 4352 ret_val = 4353 e1000_flash_cycle_ich8lan(hw, 4354 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4355 4356 if (!ret_val) 4357 break; 4358 4359 /* If we're here, then things are most likely 4360 * completely hosed, but if the error condition 4361 * is detected, it won't hurt to give it another 4362 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4363 */ 4364 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4365 4366 if (hsfsts.hsf_status.flcerr) 4367 /* Repeat for some time before giving up. */ 4368 continue; 4369 if (!hsfsts.hsf_status.flcdone) { 4370 e_dbg("Timeout error - flash cycle did not complete.\n"); 4371 break; 4372 } 4373 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4374 4375 return ret_val; 4376 } 4377 4378 /** 4379 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4380 * @hw: pointer to the HW structure 4381 * @offset: The index of the byte to read. 4382 * @data: The byte to write to the NVM. 4383 * 4384 * Writes a single byte to the NVM using the flash access registers. 4385 **/ 4386 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4387 u8 data) 4388 { 4389 u16 word = (u16)data; 4390 4391 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4392 } 4393 4394 /** 4395 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4396 * @hw: pointer to the HW structure 4397 * @offset: The offset of the word to write. 4398 * @dword: The dword to write to the NVM. 4399 * 4400 * Writes a single dword to the NVM using the flash access registers. 4401 * Goes through a retry algorithm before giving up. 4402 **/ 4403 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4404 u32 offset, u32 dword) 4405 { 4406 s32 ret_val; 4407 u16 program_retries; 4408 4409 /* Must convert word offset into bytes. */ 4410 offset <<= 1; 4411 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4412 4413 if (!ret_val) 4414 return ret_val; 4415 for (program_retries = 0; program_retries < 100; program_retries++) { 4416 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4417 usleep_range(100, 200); 4418 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4419 if (!ret_val) 4420 break; 4421 } 4422 if (program_retries == 100) 4423 return -E1000_ERR_NVM; 4424 4425 return 0; 4426 } 4427 4428 /** 4429 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4430 * @hw: pointer to the HW structure 4431 * @offset: The offset of the byte to write. 4432 * @byte: The byte to write to the NVM. 4433 * 4434 * Writes a single byte to the NVM using the flash access registers. 4435 * Goes through a retry algorithm before giving up. 4436 **/ 4437 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4438 u32 offset, u8 byte) 4439 { 4440 s32 ret_val; 4441 u16 program_retries; 4442 4443 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4444 if (!ret_val) 4445 return ret_val; 4446 4447 for (program_retries = 0; program_retries < 100; program_retries++) { 4448 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4449 usleep_range(100, 200); 4450 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4451 if (!ret_val) 4452 break; 4453 } 4454 if (program_retries == 100) 4455 return -E1000_ERR_NVM; 4456 4457 return 0; 4458 } 4459 4460 /** 4461 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4462 * @hw: pointer to the HW structure 4463 * @bank: 0 for first bank, 1 for second bank, etc. 4464 * 4465 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4466 * bank N is 4096 * N + flash_reg_addr. 4467 **/ 4468 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4469 { 4470 struct e1000_nvm_info *nvm = &hw->nvm; 4471 union ich8_hws_flash_status hsfsts; 4472 union ich8_hws_flash_ctrl hsflctl; 4473 u32 flash_linear_addr; 4474 /* bank size is in 16bit words - adjust to bytes */ 4475 u32 flash_bank_size = nvm->flash_bank_size * 2; 4476 s32 ret_val; 4477 s32 count = 0; 4478 s32 j, iteration, sector_size; 4479 4480 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4481 4482 /* Determine HW Sector size: Read BERASE bits of hw flash status 4483 * register 4484 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4485 * consecutive sectors. The start index for the nth Hw sector 4486 * can be calculated as = bank * 4096 + n * 256 4487 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4488 * The start index for the nth Hw sector can be calculated 4489 * as = bank * 4096 4490 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4491 * (ich9 only, otherwise error condition) 4492 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4493 */ 4494 switch (hsfsts.hsf_status.berasesz) { 4495 case 0: 4496 /* Hw sector size 256 */ 4497 sector_size = ICH_FLASH_SEG_SIZE_256; 4498 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4499 break; 4500 case 1: 4501 sector_size = ICH_FLASH_SEG_SIZE_4K; 4502 iteration = 1; 4503 break; 4504 case 2: 4505 sector_size = ICH_FLASH_SEG_SIZE_8K; 4506 iteration = 1; 4507 break; 4508 case 3: 4509 sector_size = ICH_FLASH_SEG_SIZE_64K; 4510 iteration = 1; 4511 break; 4512 default: 4513 return -E1000_ERR_NVM; 4514 } 4515 4516 /* Start with the base address, then add the sector offset. */ 4517 flash_linear_addr = hw->nvm.flash_base_addr; 4518 flash_linear_addr += (bank) ? flash_bank_size : 0; 4519 4520 for (j = 0; j < iteration; j++) { 4521 do { 4522 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4523 4524 /* Steps */ 4525 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4526 if (ret_val) 4527 return ret_val; 4528 4529 /* Write a value 11 (block Erase) in Flash 4530 * Cycle field in hw flash control 4531 */ 4532 if (hw->mac.type >= e1000_pch_spt) 4533 hsflctl.regval = 4534 er32flash(ICH_FLASH_HSFSTS) >> 16; 4535 else 4536 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4537 4538 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4539 if (hw->mac.type >= e1000_pch_spt) 4540 ew32flash(ICH_FLASH_HSFSTS, 4541 hsflctl.regval << 16); 4542 else 4543 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4544 4545 /* Write the last 24 bits of an index within the 4546 * block into Flash Linear address field in Flash 4547 * Address. 4548 */ 4549 flash_linear_addr += (j * sector_size); 4550 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4551 4552 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4553 if (!ret_val) 4554 break; 4555 4556 /* Check if FCERR is set to 1. If 1, 4557 * clear it and try the whole sequence 4558 * a few more times else Done 4559 */ 4560 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4561 if (hsfsts.hsf_status.flcerr) 4562 /* repeat for some time before giving up */ 4563 continue; 4564 else if (!hsfsts.hsf_status.flcdone) 4565 return ret_val; 4566 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4567 } 4568 4569 return 0; 4570 } 4571 4572 /** 4573 * e1000_valid_led_default_ich8lan - Set the default LED settings 4574 * @hw: pointer to the HW structure 4575 * @data: Pointer to the LED settings 4576 * 4577 * Reads the LED default settings from the NVM to data. If the NVM LED 4578 * settings is all 0's or F's, set the LED default to a valid LED default 4579 * setting. 4580 **/ 4581 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4582 { 4583 s32 ret_val; 4584 4585 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4586 if (ret_val) { 4587 e_dbg("NVM Read Error\n"); 4588 return ret_val; 4589 } 4590 4591 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4592 *data = ID_LED_DEFAULT_ICH8LAN; 4593 4594 return 0; 4595 } 4596 4597 /** 4598 * e1000_id_led_init_pchlan - store LED configurations 4599 * @hw: pointer to the HW structure 4600 * 4601 * PCH does not control LEDs via the LEDCTL register, rather it uses 4602 * the PHY LED configuration register. 4603 * 4604 * PCH also does not have an "always on" or "always off" mode which 4605 * complicates the ID feature. Instead of using the "on" mode to indicate 4606 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4607 * use "link_up" mode. The LEDs will still ID on request if there is no 4608 * link based on logic in e1000_led_[on|off]_pchlan(). 4609 **/ 4610 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4611 { 4612 struct e1000_mac_info *mac = &hw->mac; 4613 s32 ret_val; 4614 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4615 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4616 u16 data, i, temp, shift; 4617 4618 /* Get default ID LED modes */ 4619 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4620 if (ret_val) 4621 return ret_val; 4622 4623 mac->ledctl_default = er32(LEDCTL); 4624 mac->ledctl_mode1 = mac->ledctl_default; 4625 mac->ledctl_mode2 = mac->ledctl_default; 4626 4627 for (i = 0; i < 4; i++) { 4628 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4629 shift = (i * 5); 4630 switch (temp) { 4631 case ID_LED_ON1_DEF2: 4632 case ID_LED_ON1_ON2: 4633 case ID_LED_ON1_OFF2: 4634 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4635 mac->ledctl_mode1 |= (ledctl_on << shift); 4636 break; 4637 case ID_LED_OFF1_DEF2: 4638 case ID_LED_OFF1_ON2: 4639 case ID_LED_OFF1_OFF2: 4640 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4641 mac->ledctl_mode1 |= (ledctl_off << shift); 4642 break; 4643 default: 4644 /* Do nothing */ 4645 break; 4646 } 4647 switch (temp) { 4648 case ID_LED_DEF1_ON2: 4649 case ID_LED_ON1_ON2: 4650 case ID_LED_OFF1_ON2: 4651 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4652 mac->ledctl_mode2 |= (ledctl_on << shift); 4653 break; 4654 case ID_LED_DEF1_OFF2: 4655 case ID_LED_ON1_OFF2: 4656 case ID_LED_OFF1_OFF2: 4657 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4658 mac->ledctl_mode2 |= (ledctl_off << shift); 4659 break; 4660 default: 4661 /* Do nothing */ 4662 break; 4663 } 4664 } 4665 4666 return 0; 4667 } 4668 4669 /** 4670 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4671 * @hw: pointer to the HW structure 4672 * 4673 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4674 * register, so the bus width is hard coded. 4675 **/ 4676 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4677 { 4678 struct e1000_bus_info *bus = &hw->bus; 4679 s32 ret_val; 4680 4681 ret_val = e1000e_get_bus_info_pcie(hw); 4682 4683 /* ICH devices are "PCI Express"-ish. They have 4684 * a configuration space, but do not contain 4685 * PCI Express Capability registers, so bus width 4686 * must be hardcoded. 4687 */ 4688 if (bus->width == e1000_bus_width_unknown) 4689 bus->width = e1000_bus_width_pcie_x1; 4690 4691 return ret_val; 4692 } 4693 4694 /** 4695 * e1000_reset_hw_ich8lan - Reset the hardware 4696 * @hw: pointer to the HW structure 4697 * 4698 * Does a full reset of the hardware which includes a reset of the PHY and 4699 * MAC. 4700 **/ 4701 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4702 { 4703 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4704 u16 kum_cfg; 4705 u32 ctrl, reg; 4706 s32 ret_val; 4707 4708 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4709 * on the last TLP read/write transaction when MAC is reset. 4710 */ 4711 ret_val = e1000e_disable_pcie_master(hw); 4712 if (ret_val) 4713 e_dbg("PCI-E Master disable polling has failed.\n"); 4714 4715 e_dbg("Masking off all interrupts\n"); 4716 ew32(IMC, 0xffffffff); 4717 4718 /* Disable the Transmit and Receive units. Then delay to allow 4719 * any pending transactions to complete before we hit the MAC 4720 * with the global reset. 4721 */ 4722 ew32(RCTL, 0); 4723 ew32(TCTL, E1000_TCTL_PSP); 4724 e1e_flush(); 4725 4726 usleep_range(10000, 11000); 4727 4728 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4729 if (hw->mac.type == e1000_ich8lan) { 4730 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4731 ew32(PBA, E1000_PBA_8K); 4732 /* Set Packet Buffer Size to 16k. */ 4733 ew32(PBS, E1000_PBS_16K); 4734 } 4735 4736 if (hw->mac.type == e1000_pchlan) { 4737 /* Save the NVM K1 bit setting */ 4738 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4739 if (ret_val) 4740 return ret_val; 4741 4742 if (kum_cfg & E1000_NVM_K1_ENABLE) 4743 dev_spec->nvm_k1_enabled = true; 4744 else 4745 dev_spec->nvm_k1_enabled = false; 4746 } 4747 4748 ctrl = er32(CTRL); 4749 4750 if (!hw->phy.ops.check_reset_block(hw)) { 4751 /* Full-chip reset requires MAC and PHY reset at the same 4752 * time to make sure the interface between MAC and the 4753 * external PHY is reset. 4754 */ 4755 ctrl |= E1000_CTRL_PHY_RST; 4756 4757 /* Gate automatic PHY configuration by hardware on 4758 * non-managed 82579 4759 */ 4760 if ((hw->mac.type == e1000_pch2lan) && 4761 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4762 e1000_gate_hw_phy_config_ich8lan(hw, true); 4763 } 4764 ret_val = e1000_acquire_swflag_ich8lan(hw); 4765 e_dbg("Issuing a global reset to ich8lan\n"); 4766 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4767 /* cannot issue a flush here because it hangs the hardware */ 4768 msleep(20); 4769 4770 /* Set Phy Config Counter to 50msec */ 4771 if (hw->mac.type == e1000_pch2lan) { 4772 reg = er32(FEXTNVM3); 4773 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4774 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4775 ew32(FEXTNVM3, reg); 4776 } 4777 4778 if (!ret_val) 4779 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4780 4781 if (ctrl & E1000_CTRL_PHY_RST) { 4782 ret_val = hw->phy.ops.get_cfg_done(hw); 4783 if (ret_val) 4784 return ret_val; 4785 4786 ret_val = e1000_post_phy_reset_ich8lan(hw); 4787 if (ret_val) 4788 return ret_val; 4789 } 4790 4791 /* For PCH, this write will make sure that any noise 4792 * will be detected as a CRC error and be dropped rather than show up 4793 * as a bad packet to the DMA engine. 4794 */ 4795 if (hw->mac.type == e1000_pchlan) 4796 ew32(CRC_OFFSET, 0x65656565); 4797 4798 ew32(IMC, 0xffffffff); 4799 er32(ICR); 4800 4801 reg = er32(KABGTXD); 4802 reg |= E1000_KABGTXD_BGSQLBIAS; 4803 ew32(KABGTXD, reg); 4804 4805 return 0; 4806 } 4807 4808 /** 4809 * e1000_init_hw_ich8lan - Initialize the hardware 4810 * @hw: pointer to the HW structure 4811 * 4812 * Prepares the hardware for transmit and receive by doing the following: 4813 * - initialize hardware bits 4814 * - initialize LED identification 4815 * - setup receive address registers 4816 * - setup flow control 4817 * - setup transmit descriptors 4818 * - clear statistics 4819 **/ 4820 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4821 { 4822 struct e1000_mac_info *mac = &hw->mac; 4823 u32 ctrl_ext, txdctl, snoop, fflt_dbg; 4824 s32 ret_val; 4825 u16 i; 4826 4827 e1000_initialize_hw_bits_ich8lan(hw); 4828 4829 /* Initialize identification LED */ 4830 ret_val = mac->ops.id_led_init(hw); 4831 /* An error is not fatal and we should not stop init due to this */ 4832 if (ret_val) 4833 e_dbg("Error initializing identification LED\n"); 4834 4835 /* Setup the receive address. */ 4836 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4837 4838 /* Zero out the Multicast HASH table */ 4839 e_dbg("Zeroing the MTA\n"); 4840 for (i = 0; i < mac->mta_reg_count; i++) 4841 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4842 4843 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4844 * the ME. Disable wakeup by clearing the host wakeup bit. 4845 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4846 */ 4847 if (hw->phy.type == e1000_phy_82578) { 4848 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4849 i &= ~BM_WUC_HOST_WU_BIT; 4850 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4851 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4852 if (ret_val) 4853 return ret_val; 4854 } 4855 4856 /* Setup link and flow control */ 4857 ret_val = mac->ops.setup_link(hw); 4858 4859 /* Set the transmit descriptor write-back policy for both queues */ 4860 txdctl = er32(TXDCTL(0)); 4861 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4862 E1000_TXDCTL_FULL_TX_DESC_WB); 4863 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4864 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4865 ew32(TXDCTL(0), txdctl); 4866 txdctl = er32(TXDCTL(1)); 4867 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4868 E1000_TXDCTL_FULL_TX_DESC_WB); 4869 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4870 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4871 ew32(TXDCTL(1), txdctl); 4872 4873 /* ICH8 has opposite polarity of no_snoop bits. 4874 * By default, we should use snoop behavior. 4875 */ 4876 if (mac->type == e1000_ich8lan) 4877 snoop = PCIE_ICH8_SNOOP_ALL; 4878 else 4879 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4880 e1000e_set_pcie_no_snoop(hw, snoop); 4881 4882 /* Enable workaround for packet loss issue on TGP PCH 4883 * Do not gate DMA clock from the modPHY block 4884 */ 4885 if (mac->type >= e1000_pch_tgp) { 4886 fflt_dbg = er32(FFLT_DBG); 4887 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; 4888 ew32(FFLT_DBG, fflt_dbg); 4889 } 4890 4891 ctrl_ext = er32(CTRL_EXT); 4892 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4893 ew32(CTRL_EXT, ctrl_ext); 4894 4895 /* Clear all of the statistics registers (clear on read). It is 4896 * important that we do this after we have tried to establish link 4897 * because the symbol error count will increment wildly if there 4898 * is no link. 4899 */ 4900 e1000_clear_hw_cntrs_ich8lan(hw); 4901 4902 return ret_val; 4903 } 4904 4905 /** 4906 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4907 * @hw: pointer to the HW structure 4908 * 4909 * Sets/Clears required hardware bits necessary for correctly setting up the 4910 * hardware for transmit and receive. 4911 **/ 4912 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4913 { 4914 u32 reg; 4915 4916 /* Extended Device Control */ 4917 reg = er32(CTRL_EXT); 4918 reg |= BIT(22); 4919 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4920 if (hw->mac.type >= e1000_pchlan) 4921 reg |= E1000_CTRL_EXT_PHYPDEN; 4922 ew32(CTRL_EXT, reg); 4923 4924 /* Transmit Descriptor Control 0 */ 4925 reg = er32(TXDCTL(0)); 4926 reg |= BIT(22); 4927 ew32(TXDCTL(0), reg); 4928 4929 /* Transmit Descriptor Control 1 */ 4930 reg = er32(TXDCTL(1)); 4931 reg |= BIT(22); 4932 ew32(TXDCTL(1), reg); 4933 4934 /* Transmit Arbitration Control 0 */ 4935 reg = er32(TARC(0)); 4936 if (hw->mac.type == e1000_ich8lan) 4937 reg |= BIT(28) | BIT(29); 4938 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 4939 ew32(TARC(0), reg); 4940 4941 /* Transmit Arbitration Control 1 */ 4942 reg = er32(TARC(1)); 4943 if (er32(TCTL) & E1000_TCTL_MULR) 4944 reg &= ~BIT(28); 4945 else 4946 reg |= BIT(28); 4947 reg |= BIT(24) | BIT(26) | BIT(30); 4948 ew32(TARC(1), reg); 4949 4950 /* Device Status */ 4951 if (hw->mac.type == e1000_ich8lan) { 4952 reg = er32(STATUS); 4953 reg &= ~BIT(31); 4954 ew32(STATUS, reg); 4955 } 4956 4957 /* work-around descriptor data corruption issue during nfs v2 udp 4958 * traffic, just disable the nfs filtering capability 4959 */ 4960 reg = er32(RFCTL); 4961 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4962 4963 /* Disable IPv6 extension header parsing because some malformed 4964 * IPv6 headers can hang the Rx. 4965 */ 4966 if (hw->mac.type == e1000_ich8lan) 4967 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4968 ew32(RFCTL, reg); 4969 4970 /* Enable ECC on Lynxpoint */ 4971 if (hw->mac.type >= e1000_pch_lpt) { 4972 reg = er32(PBECCSTS); 4973 reg |= E1000_PBECCSTS_ECC_ENABLE; 4974 ew32(PBECCSTS, reg); 4975 4976 reg = er32(CTRL); 4977 reg |= E1000_CTRL_MEHE; 4978 ew32(CTRL, reg); 4979 } 4980 } 4981 4982 /** 4983 * e1000_setup_link_ich8lan - Setup flow control and link settings 4984 * @hw: pointer to the HW structure 4985 * 4986 * Determines which flow control settings to use, then configures flow 4987 * control. Calls the appropriate media-specific link configuration 4988 * function. Assuming the adapter has a valid link partner, a valid link 4989 * should be established. Assumes the hardware has previously been reset 4990 * and the transmitter and receiver are not enabled. 4991 **/ 4992 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4993 { 4994 s32 ret_val; 4995 4996 if (hw->phy.ops.check_reset_block(hw)) 4997 return 0; 4998 4999 /* ICH parts do not have a word in the NVM to determine 5000 * the default flow control setting, so we explicitly 5001 * set it to full. 5002 */ 5003 if (hw->fc.requested_mode == e1000_fc_default) { 5004 /* Workaround h/w hang when Tx flow control enabled */ 5005 if (hw->mac.type == e1000_pchlan) 5006 hw->fc.requested_mode = e1000_fc_rx_pause; 5007 else 5008 hw->fc.requested_mode = e1000_fc_full; 5009 } 5010 5011 /* Save off the requested flow control mode for use later. Depending 5012 * on the link partner's capabilities, we may or may not use this mode. 5013 */ 5014 hw->fc.current_mode = hw->fc.requested_mode; 5015 5016 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 5017 5018 /* Continue to configure the copper link. */ 5019 ret_val = hw->mac.ops.setup_physical_interface(hw); 5020 if (ret_val) 5021 return ret_val; 5022 5023 ew32(FCTTV, hw->fc.pause_time); 5024 if ((hw->phy.type == e1000_phy_82578) || 5025 (hw->phy.type == e1000_phy_82579) || 5026 (hw->phy.type == e1000_phy_i217) || 5027 (hw->phy.type == e1000_phy_82577)) { 5028 ew32(FCRTV_PCH, hw->fc.refresh_time); 5029 5030 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 5031 hw->fc.pause_time); 5032 if (ret_val) 5033 return ret_val; 5034 } 5035 5036 return e1000e_set_fc_watermarks(hw); 5037 } 5038 5039 /** 5040 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5041 * @hw: pointer to the HW structure 5042 * 5043 * Configures the kumeran interface to the PHY to wait the appropriate time 5044 * when polling the PHY, then call the generic setup_copper_link to finish 5045 * configuring the copper link. 5046 **/ 5047 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5048 { 5049 u32 ctrl; 5050 s32 ret_val; 5051 u16 reg_data; 5052 5053 ctrl = er32(CTRL); 5054 ctrl |= E1000_CTRL_SLU; 5055 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5056 ew32(CTRL, ctrl); 5057 5058 /* Set the mac to wait the maximum time between each iteration 5059 * and increase the max iterations when polling the phy; 5060 * this fixes erroneous timeouts at 10Mbps. 5061 */ 5062 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5063 if (ret_val) 5064 return ret_val; 5065 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5066 ®_data); 5067 if (ret_val) 5068 return ret_val; 5069 reg_data |= 0x3F; 5070 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5071 reg_data); 5072 if (ret_val) 5073 return ret_val; 5074 5075 switch (hw->phy.type) { 5076 case e1000_phy_igp_3: 5077 ret_val = e1000e_copper_link_setup_igp(hw); 5078 if (ret_val) 5079 return ret_val; 5080 break; 5081 case e1000_phy_bm: 5082 case e1000_phy_82578: 5083 ret_val = e1000e_copper_link_setup_m88(hw); 5084 if (ret_val) 5085 return ret_val; 5086 break; 5087 case e1000_phy_82577: 5088 case e1000_phy_82579: 5089 ret_val = e1000_copper_link_setup_82577(hw); 5090 if (ret_val) 5091 return ret_val; 5092 break; 5093 case e1000_phy_ife: 5094 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5095 if (ret_val) 5096 return ret_val; 5097 5098 reg_data &= ~IFE_PMC_AUTO_MDIX; 5099 5100 switch (hw->phy.mdix) { 5101 case 1: 5102 reg_data &= ~IFE_PMC_FORCE_MDIX; 5103 break; 5104 case 2: 5105 reg_data |= IFE_PMC_FORCE_MDIX; 5106 break; 5107 case 0: 5108 default: 5109 reg_data |= IFE_PMC_AUTO_MDIX; 5110 break; 5111 } 5112 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5113 if (ret_val) 5114 return ret_val; 5115 break; 5116 default: 5117 break; 5118 } 5119 5120 return e1000e_setup_copper_link(hw); 5121 } 5122 5123 /** 5124 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5125 * @hw: pointer to the HW structure 5126 * 5127 * Calls the PHY specific link setup function and then calls the 5128 * generic setup_copper_link to finish configuring the link for 5129 * Lynxpoint PCH devices 5130 **/ 5131 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5132 { 5133 u32 ctrl; 5134 s32 ret_val; 5135 5136 ctrl = er32(CTRL); 5137 ctrl |= E1000_CTRL_SLU; 5138 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5139 ew32(CTRL, ctrl); 5140 5141 ret_val = e1000_copper_link_setup_82577(hw); 5142 if (ret_val) 5143 return ret_val; 5144 5145 return e1000e_setup_copper_link(hw); 5146 } 5147 5148 /** 5149 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5150 * @hw: pointer to the HW structure 5151 * @speed: pointer to store current link speed 5152 * @duplex: pointer to store the current link duplex 5153 * 5154 * Calls the generic get_speed_and_duplex to retrieve the current link 5155 * information and then calls the Kumeran lock loss workaround for links at 5156 * gigabit speeds. 5157 **/ 5158 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5159 u16 *duplex) 5160 { 5161 s32 ret_val; 5162 5163 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5164 if (ret_val) 5165 return ret_val; 5166 5167 if ((hw->mac.type == e1000_ich8lan) && 5168 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5169 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5170 } 5171 5172 return ret_val; 5173 } 5174 5175 /** 5176 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5177 * @hw: pointer to the HW structure 5178 * 5179 * Work-around for 82566 Kumeran PCS lock loss: 5180 * On link status change (i.e. PCI reset, speed change) and link is up and 5181 * speed is gigabit- 5182 * 0) if workaround is optionally disabled do nothing 5183 * 1) wait 1ms for Kumeran link to come up 5184 * 2) check Kumeran Diagnostic register PCS lock loss bit 5185 * 3) if not set the link is locked (all is good), otherwise... 5186 * 4) reset the PHY 5187 * 5) repeat up to 10 times 5188 * Note: this is only called for IGP3 copper when speed is 1gb. 5189 **/ 5190 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5191 { 5192 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5193 u32 phy_ctrl; 5194 s32 ret_val; 5195 u16 i, data; 5196 bool link; 5197 5198 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5199 return 0; 5200 5201 /* Make sure link is up before proceeding. If not just return. 5202 * Attempting this while link is negotiating fouled up link 5203 * stability 5204 */ 5205 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5206 if (!link) 5207 return 0; 5208 5209 for (i = 0; i < 10; i++) { 5210 /* read once to clear */ 5211 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5212 if (ret_val) 5213 return ret_val; 5214 /* and again to get new status */ 5215 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5216 if (ret_val) 5217 return ret_val; 5218 5219 /* check for PCS lock */ 5220 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5221 return 0; 5222 5223 /* Issue PHY reset */ 5224 e1000_phy_hw_reset(hw); 5225 mdelay(5); 5226 } 5227 /* Disable GigE link negotiation */ 5228 phy_ctrl = er32(PHY_CTRL); 5229 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5230 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5231 ew32(PHY_CTRL, phy_ctrl); 5232 5233 /* Call gig speed drop workaround on Gig disable before accessing 5234 * any PHY registers 5235 */ 5236 e1000e_gig_downshift_workaround_ich8lan(hw); 5237 5238 /* unable to acquire PCS lock */ 5239 return -E1000_ERR_PHY; 5240 } 5241 5242 /** 5243 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5244 * @hw: pointer to the HW structure 5245 * @state: boolean value used to set the current Kumeran workaround state 5246 * 5247 * If ICH8, set the current Kumeran workaround state (enabled - true 5248 * /disabled - false). 5249 **/ 5250 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5251 bool state) 5252 { 5253 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5254 5255 if (hw->mac.type != e1000_ich8lan) { 5256 e_dbg("Workaround applies to ICH8 only.\n"); 5257 return; 5258 } 5259 5260 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5261 } 5262 5263 /** 5264 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5265 * @hw: pointer to the HW structure 5266 * 5267 * Workaround for 82566 power-down on D3 entry: 5268 * 1) disable gigabit link 5269 * 2) write VR power-down enable 5270 * 3) read it back 5271 * Continue if successful, else issue LCD reset and repeat 5272 **/ 5273 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5274 { 5275 u32 reg; 5276 u16 data; 5277 u8 retry = 0; 5278 5279 if (hw->phy.type != e1000_phy_igp_3) 5280 return; 5281 5282 /* Try the workaround twice (if needed) */ 5283 do { 5284 /* Disable link */ 5285 reg = er32(PHY_CTRL); 5286 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5287 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5288 ew32(PHY_CTRL, reg); 5289 5290 /* Call gig speed drop workaround on Gig disable before 5291 * accessing any PHY registers 5292 */ 5293 if (hw->mac.type == e1000_ich8lan) 5294 e1000e_gig_downshift_workaround_ich8lan(hw); 5295 5296 /* Write VR power-down enable */ 5297 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5298 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5299 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5300 5301 /* Read it back and test */ 5302 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5303 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5304 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5305 break; 5306 5307 /* Issue PHY reset and repeat at most one more time */ 5308 reg = er32(CTRL); 5309 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5310 retry++; 5311 } while (retry); 5312 } 5313 5314 /** 5315 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5316 * @hw: pointer to the HW structure 5317 * 5318 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5319 * LPLU, Gig disable, MDIC PHY reset): 5320 * 1) Set Kumeran Near-end loopback 5321 * 2) Clear Kumeran Near-end loopback 5322 * Should only be called for ICH8[m] devices with any 1G Phy. 5323 **/ 5324 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5325 { 5326 s32 ret_val; 5327 u16 reg_data; 5328 5329 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5330 return; 5331 5332 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5333 ®_data); 5334 if (ret_val) 5335 return; 5336 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5337 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5338 reg_data); 5339 if (ret_val) 5340 return; 5341 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5342 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5343 } 5344 5345 /** 5346 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5347 * @hw: pointer to the HW structure 5348 * 5349 * During S0 to Sx transition, it is possible the link remains at gig 5350 * instead of negotiating to a lower speed. Before going to Sx, set 5351 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5352 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5353 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5354 * needs to be written. 5355 * Parts that support (and are linked to a partner which support) EEE in 5356 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5357 * than 10Mbps w/o EEE. 5358 **/ 5359 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5360 { 5361 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5362 u32 phy_ctrl; 5363 s32 ret_val; 5364 5365 phy_ctrl = er32(PHY_CTRL); 5366 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5367 5368 if (hw->phy.type == e1000_phy_i217) { 5369 u16 phy_reg, device_id = hw->adapter->pdev->device; 5370 5371 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5372 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5373 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5374 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5375 (hw->mac.type >= e1000_pch_spt)) { 5376 u32 fextnvm6 = er32(FEXTNVM6); 5377 5378 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5379 } 5380 5381 ret_val = hw->phy.ops.acquire(hw); 5382 if (ret_val) 5383 goto out; 5384 5385 if (!dev_spec->eee_disable) { 5386 u16 eee_advert; 5387 5388 ret_val = 5389 e1000_read_emi_reg_locked(hw, 5390 I217_EEE_ADVERTISEMENT, 5391 &eee_advert); 5392 if (ret_val) 5393 goto release; 5394 5395 /* Disable LPLU if both link partners support 100BaseT 5396 * EEE and 100Full is advertised on both ends of the 5397 * link, and enable Auto Enable LPI since there will 5398 * be no driver to enable LPI while in Sx. 5399 */ 5400 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5401 (dev_spec->eee_lp_ability & 5402 I82579_EEE_100_SUPPORTED) && 5403 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5404 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5405 E1000_PHY_CTRL_NOND0A_LPLU); 5406 5407 /* Set Auto Enable LPI after link up */ 5408 e1e_rphy_locked(hw, 5409 I217_LPI_GPIO_CTRL, &phy_reg); 5410 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5411 e1e_wphy_locked(hw, 5412 I217_LPI_GPIO_CTRL, phy_reg); 5413 } 5414 } 5415 5416 /* For i217 Intel Rapid Start Technology support, 5417 * when the system is going into Sx and no manageability engine 5418 * is present, the driver must configure proxy to reset only on 5419 * power good. LPI (Low Power Idle) state must also reset only 5420 * on power good, as well as the MTA (Multicast table array). 5421 * The SMBus release must also be disabled on LCD reset. 5422 */ 5423 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5424 /* Enable proxy to reset only on power good. */ 5425 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5426 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5427 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5428 5429 /* Set bit enable LPI (EEE) to reset only on 5430 * power good. 5431 */ 5432 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5433 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5434 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5435 5436 /* Disable the SMB release on LCD reset. */ 5437 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5438 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5439 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5440 } 5441 5442 /* Enable MTA to reset for Intel Rapid Start Technology 5443 * Support 5444 */ 5445 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5446 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5447 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5448 5449 release: 5450 hw->phy.ops.release(hw); 5451 } 5452 out: 5453 ew32(PHY_CTRL, phy_ctrl); 5454 5455 if (hw->mac.type == e1000_ich8lan) 5456 e1000e_gig_downshift_workaround_ich8lan(hw); 5457 5458 if (hw->mac.type >= e1000_pchlan) { 5459 e1000_oem_bits_config_ich8lan(hw, false); 5460 5461 /* Reset PHY to activate OEM bits on 82577/8 */ 5462 if (hw->mac.type == e1000_pchlan) 5463 e1000e_phy_hw_reset_generic(hw); 5464 5465 ret_val = hw->phy.ops.acquire(hw); 5466 if (ret_val) 5467 return; 5468 e1000_write_smbus_addr(hw); 5469 hw->phy.ops.release(hw); 5470 } 5471 } 5472 5473 /** 5474 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5475 * @hw: pointer to the HW structure 5476 * 5477 * During Sx to S0 transitions on non-managed devices or managed devices 5478 * on which PHY resets are not blocked, if the PHY registers cannot be 5479 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5480 * the PHY. 5481 * On i217, setup Intel Rapid Start Technology. 5482 **/ 5483 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5484 { 5485 s32 ret_val; 5486 5487 if (hw->mac.type < e1000_pch2lan) 5488 return; 5489 5490 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5491 if (ret_val) { 5492 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5493 return; 5494 } 5495 5496 /* For i217 Intel Rapid Start Technology support when the system 5497 * is transitioning from Sx and no manageability engine is present 5498 * configure SMBus to restore on reset, disable proxy, and enable 5499 * the reset on MTA (Multicast table array). 5500 */ 5501 if (hw->phy.type == e1000_phy_i217) { 5502 u16 phy_reg; 5503 5504 ret_val = hw->phy.ops.acquire(hw); 5505 if (ret_val) { 5506 e_dbg("Failed to setup iRST\n"); 5507 return; 5508 } 5509 5510 /* Clear Auto Enable LPI after link up */ 5511 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5512 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5513 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5514 5515 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5516 /* Restore clear on SMB if no manageability engine 5517 * is present 5518 */ 5519 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5520 if (ret_val) 5521 goto release; 5522 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5523 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5524 5525 /* Disable Proxy */ 5526 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5527 } 5528 /* Enable reset on MTA */ 5529 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5530 if (ret_val) 5531 goto release; 5532 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5533 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5534 release: 5535 if (ret_val) 5536 e_dbg("Error %d in resume workarounds\n", ret_val); 5537 hw->phy.ops.release(hw); 5538 } 5539 } 5540 5541 /** 5542 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5543 * @hw: pointer to the HW structure 5544 * 5545 * Return the LED back to the default configuration. 5546 **/ 5547 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5548 { 5549 if (hw->phy.type == e1000_phy_ife) 5550 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5551 5552 ew32(LEDCTL, hw->mac.ledctl_default); 5553 return 0; 5554 } 5555 5556 /** 5557 * e1000_led_on_ich8lan - Turn LEDs on 5558 * @hw: pointer to the HW structure 5559 * 5560 * Turn on the LEDs. 5561 **/ 5562 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5563 { 5564 if (hw->phy.type == e1000_phy_ife) 5565 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5566 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5567 5568 ew32(LEDCTL, hw->mac.ledctl_mode2); 5569 return 0; 5570 } 5571 5572 /** 5573 * e1000_led_off_ich8lan - Turn LEDs off 5574 * @hw: pointer to the HW structure 5575 * 5576 * Turn off the LEDs. 5577 **/ 5578 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5579 { 5580 if (hw->phy.type == e1000_phy_ife) 5581 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5582 (IFE_PSCL_PROBE_MODE | 5583 IFE_PSCL_PROBE_LEDS_OFF)); 5584 5585 ew32(LEDCTL, hw->mac.ledctl_mode1); 5586 return 0; 5587 } 5588 5589 /** 5590 * e1000_setup_led_pchlan - Configures SW controllable LED 5591 * @hw: pointer to the HW structure 5592 * 5593 * This prepares the SW controllable LED for use. 5594 **/ 5595 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5596 { 5597 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5598 } 5599 5600 /** 5601 * e1000_cleanup_led_pchlan - Restore the default LED operation 5602 * @hw: pointer to the HW structure 5603 * 5604 * Return the LED back to the default configuration. 5605 **/ 5606 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5607 { 5608 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5609 } 5610 5611 /** 5612 * e1000_led_on_pchlan - Turn LEDs on 5613 * @hw: pointer to the HW structure 5614 * 5615 * Turn on the LEDs. 5616 **/ 5617 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5618 { 5619 u16 data = (u16)hw->mac.ledctl_mode2; 5620 u32 i, led; 5621 5622 /* If no link, then turn LED on by setting the invert bit 5623 * for each LED that's mode is "link_up" in ledctl_mode2. 5624 */ 5625 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5626 for (i = 0; i < 3; i++) { 5627 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5628 if ((led & E1000_PHY_LED0_MODE_MASK) != 5629 E1000_LEDCTL_MODE_LINK_UP) 5630 continue; 5631 if (led & E1000_PHY_LED0_IVRT) 5632 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5633 else 5634 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5635 } 5636 } 5637 5638 return e1e_wphy(hw, HV_LED_CONFIG, data); 5639 } 5640 5641 /** 5642 * e1000_led_off_pchlan - Turn LEDs off 5643 * @hw: pointer to the HW structure 5644 * 5645 * Turn off the LEDs. 5646 **/ 5647 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5648 { 5649 u16 data = (u16)hw->mac.ledctl_mode1; 5650 u32 i, led; 5651 5652 /* If no link, then turn LED off by clearing the invert bit 5653 * for each LED that's mode is "link_up" in ledctl_mode1. 5654 */ 5655 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5656 for (i = 0; i < 3; i++) { 5657 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5658 if ((led & E1000_PHY_LED0_MODE_MASK) != 5659 E1000_LEDCTL_MODE_LINK_UP) 5660 continue; 5661 if (led & E1000_PHY_LED0_IVRT) 5662 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5663 else 5664 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5665 } 5666 } 5667 5668 return e1e_wphy(hw, HV_LED_CONFIG, data); 5669 } 5670 5671 /** 5672 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5673 * @hw: pointer to the HW structure 5674 * 5675 * Read appropriate register for the config done bit for completion status 5676 * and configure the PHY through s/w for EEPROM-less parts. 5677 * 5678 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5679 * config done bit, so only an error is logged and continues. If we were 5680 * to return with error, EEPROM-less silicon would not be able to be reset 5681 * or change link. 5682 **/ 5683 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5684 { 5685 s32 ret_val = 0; 5686 u32 bank = 0; 5687 u32 status; 5688 5689 e1000e_get_cfg_done_generic(hw); 5690 5691 /* Wait for indication from h/w that it has completed basic config */ 5692 if (hw->mac.type >= e1000_ich10lan) { 5693 e1000_lan_init_done_ich8lan(hw); 5694 } else { 5695 ret_val = e1000e_get_auto_rd_done(hw); 5696 if (ret_val) { 5697 /* When auto config read does not complete, do not 5698 * return with an error. This can happen in situations 5699 * where there is no eeprom and prevents getting link. 5700 */ 5701 e_dbg("Auto Read Done did not complete\n"); 5702 ret_val = 0; 5703 } 5704 } 5705 5706 /* Clear PHY Reset Asserted bit */ 5707 status = er32(STATUS); 5708 if (status & E1000_STATUS_PHYRA) 5709 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5710 else 5711 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5712 5713 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5714 if (hw->mac.type <= e1000_ich9lan) { 5715 if (!(er32(EECD) & E1000_EECD_PRES) && 5716 (hw->phy.type == e1000_phy_igp_3)) { 5717 e1000e_phy_init_script_igp3(hw); 5718 } 5719 } else { 5720 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5721 /* Maybe we should do a basic PHY config */ 5722 e_dbg("EEPROM not present\n"); 5723 ret_val = -E1000_ERR_CONFIG; 5724 } 5725 } 5726 5727 return ret_val; 5728 } 5729 5730 /** 5731 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5732 * @hw: pointer to the HW structure 5733 * 5734 * In the case of a PHY power down to save power, or to turn off link during a 5735 * driver unload, or wake on lan is not enabled, remove the link. 5736 **/ 5737 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5738 { 5739 /* If the management interface is not enabled, then power down */ 5740 if (!(hw->mac.ops.check_mng_mode(hw) || 5741 hw->phy.ops.check_reset_block(hw))) 5742 e1000_power_down_phy_copper(hw); 5743 } 5744 5745 /** 5746 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5747 * @hw: pointer to the HW structure 5748 * 5749 * Clears hardware counters specific to the silicon family and calls 5750 * clear_hw_cntrs_generic to clear all general purpose counters. 5751 **/ 5752 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5753 { 5754 u16 phy_data; 5755 s32 ret_val; 5756 5757 e1000e_clear_hw_cntrs_base(hw); 5758 5759 er32(ALGNERRC); 5760 er32(RXERRC); 5761 er32(TNCRS); 5762 er32(CEXTERR); 5763 er32(TSCTC); 5764 er32(TSCTFC); 5765 5766 er32(MGTPRC); 5767 er32(MGTPDC); 5768 er32(MGTPTC); 5769 5770 er32(IAC); 5771 er32(ICRXOC); 5772 5773 /* Clear PHY statistics registers */ 5774 if ((hw->phy.type == e1000_phy_82578) || 5775 (hw->phy.type == e1000_phy_82579) || 5776 (hw->phy.type == e1000_phy_i217) || 5777 (hw->phy.type == e1000_phy_82577)) { 5778 ret_val = hw->phy.ops.acquire(hw); 5779 if (ret_val) 5780 return; 5781 ret_val = hw->phy.ops.set_page(hw, 5782 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5783 if (ret_val) 5784 goto release; 5785 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5786 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5787 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5788 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5789 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5790 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5791 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5792 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5793 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5794 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5795 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5796 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5797 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5798 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5799 release: 5800 hw->phy.ops.release(hw); 5801 } 5802 } 5803 5804 static const struct e1000_mac_operations ich8_mac_ops = { 5805 /* check_mng_mode dependent on mac type */ 5806 .check_for_link = e1000_check_for_copper_link_ich8lan, 5807 /* cleanup_led dependent on mac type */ 5808 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5809 .get_bus_info = e1000_get_bus_info_ich8lan, 5810 .set_lan_id = e1000_set_lan_id_single_port, 5811 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5812 /* led_on dependent on mac type */ 5813 /* led_off dependent on mac type */ 5814 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5815 .reset_hw = e1000_reset_hw_ich8lan, 5816 .init_hw = e1000_init_hw_ich8lan, 5817 .setup_link = e1000_setup_link_ich8lan, 5818 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5819 /* id_led_init dependent on mac type */ 5820 .config_collision_dist = e1000e_config_collision_dist_generic, 5821 .rar_set = e1000e_rar_set_generic, 5822 .rar_get_count = e1000e_rar_get_count_generic, 5823 }; 5824 5825 static const struct e1000_phy_operations ich8_phy_ops = { 5826 .acquire = e1000_acquire_swflag_ich8lan, 5827 .check_reset_block = e1000_check_reset_block_ich8lan, 5828 .commit = NULL, 5829 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5830 .get_cable_length = e1000e_get_cable_length_igp_2, 5831 .read_reg = e1000e_read_phy_reg_igp, 5832 .release = e1000_release_swflag_ich8lan, 5833 .reset = e1000_phy_hw_reset_ich8lan, 5834 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5835 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5836 .write_reg = e1000e_write_phy_reg_igp, 5837 }; 5838 5839 static const struct e1000_nvm_operations ich8_nvm_ops = { 5840 .acquire = e1000_acquire_nvm_ich8lan, 5841 .read = e1000_read_nvm_ich8lan, 5842 .release = e1000_release_nvm_ich8lan, 5843 .reload = e1000e_reload_nvm_generic, 5844 .update = e1000_update_nvm_checksum_ich8lan, 5845 .valid_led_default = e1000_valid_led_default_ich8lan, 5846 .validate = e1000_validate_nvm_checksum_ich8lan, 5847 .write = e1000_write_nvm_ich8lan, 5848 }; 5849 5850 static const struct e1000_nvm_operations spt_nvm_ops = { 5851 .acquire = e1000_acquire_nvm_ich8lan, 5852 .release = e1000_release_nvm_ich8lan, 5853 .read = e1000_read_nvm_spt, 5854 .update = e1000_update_nvm_checksum_spt, 5855 .reload = e1000e_reload_nvm_generic, 5856 .valid_led_default = e1000_valid_led_default_ich8lan, 5857 .validate = e1000_validate_nvm_checksum_ich8lan, 5858 .write = e1000_write_nvm_ich8lan, 5859 }; 5860 5861 const struct e1000_info e1000_ich8_info = { 5862 .mac = e1000_ich8lan, 5863 .flags = FLAG_HAS_WOL 5864 | FLAG_IS_ICH 5865 | FLAG_HAS_CTRLEXT_ON_LOAD 5866 | FLAG_HAS_AMT 5867 | FLAG_HAS_FLASH 5868 | FLAG_APME_IN_WUC, 5869 .pba = 8, 5870 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5871 .get_variants = e1000_get_variants_ich8lan, 5872 .mac_ops = &ich8_mac_ops, 5873 .phy_ops = &ich8_phy_ops, 5874 .nvm_ops = &ich8_nvm_ops, 5875 }; 5876 5877 const struct e1000_info e1000_ich9_info = { 5878 .mac = e1000_ich9lan, 5879 .flags = FLAG_HAS_JUMBO_FRAMES 5880 | FLAG_IS_ICH 5881 | FLAG_HAS_WOL 5882 | FLAG_HAS_CTRLEXT_ON_LOAD 5883 | FLAG_HAS_AMT 5884 | FLAG_HAS_FLASH 5885 | FLAG_APME_IN_WUC, 5886 .pba = 18, 5887 .max_hw_frame_size = DEFAULT_JUMBO, 5888 .get_variants = e1000_get_variants_ich8lan, 5889 .mac_ops = &ich8_mac_ops, 5890 .phy_ops = &ich8_phy_ops, 5891 .nvm_ops = &ich8_nvm_ops, 5892 }; 5893 5894 const struct e1000_info e1000_ich10_info = { 5895 .mac = e1000_ich10lan, 5896 .flags = FLAG_HAS_JUMBO_FRAMES 5897 | FLAG_IS_ICH 5898 | FLAG_HAS_WOL 5899 | FLAG_HAS_CTRLEXT_ON_LOAD 5900 | FLAG_HAS_AMT 5901 | FLAG_HAS_FLASH 5902 | FLAG_APME_IN_WUC, 5903 .pba = 18, 5904 .max_hw_frame_size = DEFAULT_JUMBO, 5905 .get_variants = e1000_get_variants_ich8lan, 5906 .mac_ops = &ich8_mac_ops, 5907 .phy_ops = &ich8_phy_ops, 5908 .nvm_ops = &ich8_nvm_ops, 5909 }; 5910 5911 const struct e1000_info e1000_pch_info = { 5912 .mac = e1000_pchlan, 5913 .flags = FLAG_IS_ICH 5914 | FLAG_HAS_WOL 5915 | FLAG_HAS_CTRLEXT_ON_LOAD 5916 | FLAG_HAS_AMT 5917 | FLAG_HAS_FLASH 5918 | FLAG_HAS_JUMBO_FRAMES 5919 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5920 | FLAG_APME_IN_WUC, 5921 .flags2 = FLAG2_HAS_PHY_STATS, 5922 .pba = 26, 5923 .max_hw_frame_size = 4096, 5924 .get_variants = e1000_get_variants_ich8lan, 5925 .mac_ops = &ich8_mac_ops, 5926 .phy_ops = &ich8_phy_ops, 5927 .nvm_ops = &ich8_nvm_ops, 5928 }; 5929 5930 const struct e1000_info e1000_pch2_info = { 5931 .mac = e1000_pch2lan, 5932 .flags = FLAG_IS_ICH 5933 | FLAG_HAS_WOL 5934 | FLAG_HAS_HW_TIMESTAMP 5935 | FLAG_HAS_CTRLEXT_ON_LOAD 5936 | FLAG_HAS_AMT 5937 | FLAG_HAS_FLASH 5938 | FLAG_HAS_JUMBO_FRAMES 5939 | FLAG_APME_IN_WUC, 5940 .flags2 = FLAG2_HAS_PHY_STATS 5941 | FLAG2_HAS_EEE 5942 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5943 .pba = 26, 5944 .max_hw_frame_size = 9022, 5945 .get_variants = e1000_get_variants_ich8lan, 5946 .mac_ops = &ich8_mac_ops, 5947 .phy_ops = &ich8_phy_ops, 5948 .nvm_ops = &ich8_nvm_ops, 5949 }; 5950 5951 const struct e1000_info e1000_pch_lpt_info = { 5952 .mac = e1000_pch_lpt, 5953 .flags = FLAG_IS_ICH 5954 | FLAG_HAS_WOL 5955 | FLAG_HAS_HW_TIMESTAMP 5956 | FLAG_HAS_CTRLEXT_ON_LOAD 5957 | FLAG_HAS_AMT 5958 | FLAG_HAS_FLASH 5959 | FLAG_HAS_JUMBO_FRAMES 5960 | FLAG_APME_IN_WUC, 5961 .flags2 = FLAG2_HAS_PHY_STATS 5962 | FLAG2_HAS_EEE 5963 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5964 .pba = 26, 5965 .max_hw_frame_size = 9022, 5966 .get_variants = e1000_get_variants_ich8lan, 5967 .mac_ops = &ich8_mac_ops, 5968 .phy_ops = &ich8_phy_ops, 5969 .nvm_ops = &ich8_nvm_ops, 5970 }; 5971 5972 const struct e1000_info e1000_pch_spt_info = { 5973 .mac = e1000_pch_spt, 5974 .flags = FLAG_IS_ICH 5975 | FLAG_HAS_WOL 5976 | FLAG_HAS_HW_TIMESTAMP 5977 | FLAG_HAS_CTRLEXT_ON_LOAD 5978 | FLAG_HAS_AMT 5979 | FLAG_HAS_FLASH 5980 | FLAG_HAS_JUMBO_FRAMES 5981 | FLAG_APME_IN_WUC, 5982 .flags2 = FLAG2_HAS_PHY_STATS 5983 | FLAG2_HAS_EEE, 5984 .pba = 26, 5985 .max_hw_frame_size = 9022, 5986 .get_variants = e1000_get_variants_ich8lan, 5987 .mac_ops = &ich8_mac_ops, 5988 .phy_ops = &ich8_phy_ops, 5989 .nvm_ops = &spt_nvm_ops, 5990 }; 5991 5992 const struct e1000_info e1000_pch_cnp_info = { 5993 .mac = e1000_pch_cnp, 5994 .flags = FLAG_IS_ICH 5995 | FLAG_HAS_WOL 5996 | FLAG_HAS_HW_TIMESTAMP 5997 | FLAG_HAS_CTRLEXT_ON_LOAD 5998 | FLAG_HAS_AMT 5999 | FLAG_HAS_FLASH 6000 | FLAG_HAS_JUMBO_FRAMES 6001 | FLAG_APME_IN_WUC, 6002 .flags2 = FLAG2_HAS_PHY_STATS 6003 | FLAG2_HAS_EEE, 6004 .pba = 26, 6005 .max_hw_frame_size = 9022, 6006 .get_variants = e1000_get_variants_ich8lan, 6007 .mac_ops = &ich8_mac_ops, 6008 .phy_ops = &ich8_phy_ops, 6009 .nvm_ops = &spt_nvm_ops, 6010 }; 6011 6012 const struct e1000_info e1000_pch_tgp_info = { 6013 .mac = e1000_pch_tgp, 6014 .flags = FLAG_IS_ICH 6015 | FLAG_HAS_WOL 6016 | FLAG_HAS_HW_TIMESTAMP 6017 | FLAG_HAS_CTRLEXT_ON_LOAD 6018 | FLAG_HAS_AMT 6019 | FLAG_HAS_FLASH 6020 | FLAG_HAS_JUMBO_FRAMES 6021 | FLAG_APME_IN_WUC, 6022 .flags2 = FLAG2_HAS_PHY_STATS 6023 | FLAG2_HAS_EEE, 6024 .pba = 26, 6025 .max_hw_frame_size = 9022, 6026 .get_variants = e1000_get_variants_ich8lan, 6027 .mac_ops = &ich8_mac_ops, 6028 .phy_ops = &ich8_phy_ops, 6029 .nvm_ops = &spt_nvm_ops, 6030 }; 6031 6032 const struct e1000_info e1000_pch_adp_info = { 6033 .mac = e1000_pch_adp, 6034 .flags = FLAG_IS_ICH 6035 | FLAG_HAS_WOL 6036 | FLAG_HAS_HW_TIMESTAMP 6037 | FLAG_HAS_CTRLEXT_ON_LOAD 6038 | FLAG_HAS_AMT 6039 | FLAG_HAS_FLASH 6040 | FLAG_HAS_JUMBO_FRAMES 6041 | FLAG_APME_IN_WUC, 6042 .flags2 = FLAG2_HAS_PHY_STATS 6043 | FLAG2_HAS_EEE, 6044 .pba = 26, 6045 .max_hw_frame_size = 9022, 6046 .get_variants = e1000_get_variants_ich8lan, 6047 .mac_ops = &ich8_mac_ops, 6048 .phy_ops = &ich8_phy_ops, 6049 .nvm_ops = &spt_nvm_ops, 6050 }; 6051 6052 const struct e1000_info e1000_pch_mtp_info = { 6053 .mac = e1000_pch_mtp, 6054 .flags = FLAG_IS_ICH 6055 | FLAG_HAS_WOL 6056 | FLAG_HAS_HW_TIMESTAMP 6057 | FLAG_HAS_CTRLEXT_ON_LOAD 6058 | FLAG_HAS_AMT 6059 | FLAG_HAS_FLASH 6060 | FLAG_HAS_JUMBO_FRAMES 6061 | FLAG_APME_IN_WUC, 6062 .flags2 = FLAG2_HAS_PHY_STATS 6063 | FLAG2_HAS_EEE, 6064 .pba = 26, 6065 .max_hw_frame_size = 9022, 6066 .get_variants = e1000_get_variants_ich8lan, 6067 .mac_ops = &ich8_mac_ops, 6068 .phy_ops = &ich8_phy_ops, 6069 .nvm_ops = &spt_nvm_ops, 6070 }; 6071