1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #ifndef _IGC_H_
5 #define _IGC_H_
6
7 #include <linux/kobject.h>
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/bitfield.h>
17 #include <linux/hrtimer.h>
18 #include <net/xdp.h>
19
20 #include "igc_hw.h"
21
22 void igc_ethtool_set_ops(struct net_device *);
23
24 /* Transmit and receive queues */
25 #define IGC_MAX_RX_QUEUES 4
26 #define IGC_MAX_TX_QUEUES 4
27
28 #define MAX_Q_VECTORS 8
29 #define MAX_STD_JUMBO_FRAME_SIZE 9216
30
31 #define MAX_ETYPE_FILTER 8
32 #define IGC_RETA_SIZE 128
33
34 /* SDP support */
35 #define IGC_N_EXTTS 2
36 #define IGC_N_PEROUT 2
37 #define IGC_N_SDP 4
38
39 #define MAX_FLEX_FILTER 32
40
41 #define IGC_MAX_TX_TSTAMP_REGS 4
42
43 enum igc_mac_filter_type {
44 IGC_MAC_FILTER_TYPE_DST = 0,
45 IGC_MAC_FILTER_TYPE_SRC
46 };
47
48 struct igc_tx_queue_stats {
49 u64 packets;
50 u64 bytes;
51 u64 restart_queue;
52 u64 restart_queue2;
53 };
54
55 struct igc_rx_queue_stats {
56 u64 packets;
57 u64 bytes;
58 u64 drops;
59 u64 csum_err;
60 u64 alloc_failed;
61 };
62
63 struct igc_rx_packet_stats {
64 u64 ipv4_packets; /* IPv4 headers processed */
65 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
66 u64 ipv6_packets; /* IPv6 headers processed */
67 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
68 u64 tcp_packets; /* TCP headers processed */
69 u64 udp_packets; /* UDP headers processed */
70 u64 sctp_packets; /* SCTP headers processed */
71 u64 nfs_packets; /* NFS headers processe */
72 u64 other_packets;
73 };
74
75 enum igc_tx_buffer_type {
76 IGC_TX_BUFFER_TYPE_SKB,
77 IGC_TX_BUFFER_TYPE_XDP,
78 IGC_TX_BUFFER_TYPE_XSK,
79 };
80
81 /* wrapper around a pointer to a socket buffer,
82 * so a DMA handle can be stored along with the buffer
83 */
84 struct igc_tx_buffer {
85 union igc_adv_tx_desc *next_to_watch;
86 unsigned long time_stamp;
87 enum igc_tx_buffer_type type;
88 union {
89 struct sk_buff *skb;
90 struct xdp_frame *xdpf;
91 };
92 unsigned int bytecount;
93 u16 gso_segs;
94 __be16 protocol;
95
96 DEFINE_DMA_UNMAP_ADDR(dma);
97 DEFINE_DMA_UNMAP_LEN(len);
98 u32 tx_flags;
99 bool xsk_pending_ts;
100 };
101
102 struct igc_tx_timestamp_request {
103 union { /* reference to the packet being timestamped */
104 struct sk_buff *skb;
105 struct igc_tx_buffer *xsk_tx_buffer;
106 };
107 enum igc_tx_buffer_type buffer_type;
108 unsigned long start; /* when the tstamp request started (jiffies) */
109 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */
110 u32 regl; /* which TXSTMPL_{X} register should be used */
111 u32 regh; /* which TXSTMPH_{X} register should be used */
112 u32 flags; /* flags that should be added to the tx_buffer */
113 u8 xsk_queue_index; /* Tx queue which requesting timestamp */
114 struct xsk_tx_metadata_compl xsk_meta; /* ref to xsk Tx metadata */
115 };
116
117 struct igc_inline_rx_tstamps {
118 /* Timestamps are saved in little endian at the beginning of the packet
119 * buffer following the layout:
120 *
121 * DWORD: | 0 | 1 | 2 | 3 |
122 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
123 *
124 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
125 * part of the timestamp.
126 *
127 */
128 __le32 timer1[2];
129 __le32 timer0[2];
130 };
131
132 struct igc_ring_container {
133 struct igc_ring *ring; /* pointer to linked list of rings */
134 unsigned int total_bytes; /* total bytes processed this int */
135 unsigned int total_packets; /* total packets processed this int */
136 u16 work_limit; /* total work allowed per interrupt */
137 u8 count; /* total number of rings in vector */
138 u8 itr; /* current ITR setting for ring */
139 };
140
141 struct igc_ring {
142 struct igc_q_vector *q_vector; /* backlink to q_vector */
143 struct net_device *netdev; /* back pointer to net_device */
144 struct device *dev; /* device for dma mapping */
145 union { /* array of buffer info structs */
146 struct igc_tx_buffer *tx_buffer_info;
147 struct igc_rx_buffer *rx_buffer_info;
148 };
149 void *desc; /* descriptor ring memory */
150 unsigned long flags; /* ring specific flags */
151 void __iomem *tail; /* pointer to ring tail register */
152 dma_addr_t dma; /* phys address of the ring */
153 unsigned int size; /* length of desc. ring in bytes */
154
155 u16 count; /* number of desc. in the ring */
156 u8 queue_index; /* logical index of the ring*/
157 u8 reg_idx; /* physical index of the ring */
158 bool launchtime_enable; /* true if LaunchTime is enabled */
159 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
160 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
161
162 u32 start_time;
163 u32 end_time;
164 u32 max_sdu;
165 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
166 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
167
168 /* CBS parameters */
169 bool cbs_enable; /* indicates if CBS is enabled */
170 s32 idleslope; /* idleSlope in kbps */
171 s32 sendslope; /* sendSlope in kbps */
172 s32 hicredit; /* hiCredit in bytes */
173 s32 locredit; /* loCredit in bytes */
174
175 /* everything past this point are written often */
176 u16 next_to_clean;
177 u16 next_to_use;
178 u16 next_to_alloc;
179
180 union {
181 /* TX */
182 struct {
183 struct igc_tx_queue_stats tx_stats;
184 struct u64_stats_sync tx_syncp;
185 struct u64_stats_sync tx_syncp2;
186 };
187 /* RX */
188 struct {
189 struct igc_rx_queue_stats rx_stats;
190 struct igc_rx_packet_stats pkt_stats;
191 struct u64_stats_sync rx_syncp;
192 struct sk_buff *skb;
193 };
194 };
195
196 struct xdp_rxq_info xdp_rxq;
197 struct xsk_buff_pool *xsk_pool;
198 } ____cacheline_internodealigned_in_smp;
199
200 /* Board specific private data structure */
201 struct igc_adapter {
202 struct net_device *netdev;
203
204 struct ethtool_keee eee;
205 u16 eee_advert;
206
207 unsigned long state;
208 unsigned int flags;
209 unsigned int num_q_vectors;
210
211 struct msix_entry *msix_entries;
212
213 /* TX */
214 u16 tx_work_limit;
215 u32 tx_timeout_count;
216 int num_tx_queues;
217 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
218
219 /* RX */
220 int num_rx_queues;
221 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
222
223 struct timer_list watchdog_timer;
224 struct timer_list dma_err_timer;
225 struct timer_list phy_info_timer;
226 struct hrtimer hrtimer;
227
228 u32 wol;
229 u32 en_mng_pt;
230 u16 link_speed;
231 u16 link_duplex;
232
233 u8 port_num;
234
235 u8 __iomem *io_addr;
236 /* Interrupt Throttle Rate */
237 u32 rx_itr_setting;
238 u32 tx_itr_setting;
239
240 struct work_struct reset_task;
241 struct work_struct watchdog_task;
242 struct work_struct dma_err_task;
243 bool fc_autoneg;
244
245 u8 tx_timeout_factor;
246
247 int msg_enable;
248 u32 max_frame_size;
249 u32 min_frame_size;
250
251 int tc_setup_type;
252 ktime_t base_time;
253 ktime_t cycle_time;
254 bool taprio_offload_enable;
255 u32 qbv_config_change_errors;
256 bool qbv_transition;
257 unsigned int qbv_count;
258 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition
259 * are protected by the qbv_tx_lock.
260 */
261 spinlock_t qbv_tx_lock;
262
263 /* OS defined structs */
264 struct pci_dev *pdev;
265 /* lock for statistics */
266 spinlock_t stats64_lock;
267 struct rtnl_link_stats64 stats64;
268
269 /* structs defined in igc_hw.h */
270 struct igc_hw hw;
271 struct igc_hw_stats stats;
272
273 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
274 u32 eims_enable_mask;
275 u32 eims_other;
276
277 u16 tx_ring_count;
278 u16 rx_ring_count;
279
280 u32 tx_hwtstamp_timeouts;
281 u32 tx_hwtstamp_skipped;
282 u32 rx_hwtstamp_cleared;
283
284 u32 rss_queues;
285 u32 rss_indir_tbl_init;
286
287 /* Any access to elements in nfc_rule_list is protected by the
288 * nfc_rule_lock.
289 */
290 struct mutex nfc_rule_lock;
291 struct list_head nfc_rule_list;
292 unsigned int nfc_rule_count;
293
294 u8 rss_indir_tbl[IGC_RETA_SIZE];
295
296 unsigned long link_check_timeout;
297 struct igc_info ei;
298
299 u32 test_icr;
300
301 struct ptp_clock *ptp_clock;
302 struct ptp_clock_info ptp_caps;
303 /* Access to ptp_tx_skb and ptp_tx_start are protected by the
304 * ptp_tx_lock.
305 */
306 spinlock_t ptp_tx_lock;
307 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS];
308 struct hwtstamp_config tstamp_config;
309 unsigned int ptp_flags;
310 /* System time value lock */
311 spinlock_t tmreg_lock;
312 /* Free-running timer lock */
313 spinlock_t free_timer_lock;
314 struct cyclecounter cc;
315 struct timecounter tc;
316 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
317 ktime_t ptp_reset_start; /* Reset time in clock mono */
318 struct system_time_snapshot snapshot;
319
320 char fw_version[32];
321
322 struct bpf_prog *xdp_prog;
323
324 bool pps_sys_wrap_on;
325
326 struct ptp_pin_desc sdp_config[IGC_N_SDP];
327 struct {
328 struct timespec64 start;
329 struct timespec64 period;
330 } perout[IGC_N_PEROUT];
331
332 /* LEDs */
333 struct mutex led_mutex;
334 struct igc_led_classdev *leds;
335 };
336
337 void igc_up(struct igc_adapter *adapter);
338 void igc_down(struct igc_adapter *adapter);
339 int igc_open(struct net_device *netdev);
340 int igc_close(struct net_device *netdev);
341 int igc_setup_tx_resources(struct igc_ring *ring);
342 int igc_setup_rx_resources(struct igc_ring *ring);
343 void igc_free_tx_resources(struct igc_ring *ring);
344 void igc_free_rx_resources(struct igc_ring *ring);
345 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
346 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
347 const u32 max_rss_queues);
348 int igc_reinit_queues(struct igc_adapter *adapter);
349 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
350 bool igc_has_link(struct igc_adapter *adapter);
351 void igc_reset(struct igc_adapter *adapter);
352 void igc_update_stats(struct igc_adapter *adapter);
353 void igc_disable_rx_ring(struct igc_ring *ring);
354 void igc_enable_rx_ring(struct igc_ring *ring);
355 void igc_disable_tx_ring(struct igc_ring *ring);
356 void igc_enable_tx_ring(struct igc_ring *ring);
357 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
358
359 /* AF_XDP TX metadata operations */
360 extern const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops;
361
362 /* igc_dump declarations */
363 void igc_rings_dump(struct igc_adapter *adapter);
364 void igc_regs_dump(struct igc_adapter *adapter);
365
366 extern char igc_driver_name[];
367
368 #define IGC_REGS_LEN 740
369
370 /* flags controlling PTP/1588 function */
371 #define IGC_PTP_ENABLED BIT(0)
372
373 /* Flags definitions */
374 #define IGC_FLAG_HAS_MSI BIT(0)
375 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
376 #define IGC_FLAG_DMAC BIT(4)
377 #define IGC_FLAG_PTP BIT(8)
378 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
379 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
380 #define IGC_FLAG_HAS_MSIX BIT(13)
381 #define IGC_FLAG_EEE BIT(14)
382 #define IGC_FLAG_VLAN_PROMISC BIT(15)
383 #define IGC_FLAG_RX_LEGACY BIT(16)
384 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
385 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
386
387 #define IGC_FLAG_TSN_ANY_ENABLED \
388 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
389
390 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
391 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
392
393 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
394 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
395 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
396
397 /* RX-desc Write-Back format RSS Type's */
398 enum igc_rss_type_num {
399 IGC_RSS_TYPE_NO_HASH = 0,
400 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
401 IGC_RSS_TYPE_HASH_IPV4 = 2,
402 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
403 IGC_RSS_TYPE_HASH_IPV6_EX = 4,
404 IGC_RSS_TYPE_HASH_IPV6 = 5,
405 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
406 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
407 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
408 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
409 IGC_RSS_TYPE_MAX = 10,
410 };
411 #define IGC_RSS_TYPE_MAX_TABLE 16
412 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
413
414 /* igc_rss_type - Rx descriptor RSS type field */
igc_rss_type(const union igc_adv_rx_desc * rx_desc)415 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
416 {
417 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
418 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
419 * is slightly slower than via u32 (wb.lower.lo_dword.data)
420 */
421 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
422 }
423
424 /* Interrupt defines */
425 #define IGC_START_ITR 648 /* ~6000 ints/sec */
426 #define IGC_4K_ITR 980
427 #define IGC_20K_ITR 196
428 #define IGC_70K_ITR 56
429
430 #define IGC_DEFAULT_ITR 3 /* dynamic */
431 #define IGC_MAX_ITR_USECS 10000
432 #define IGC_MIN_ITR_USECS 10
433 #define NON_Q_VECTORS 1
434 #define MAX_MSIX_ENTRIES 10
435
436 /* TX/RX descriptor defines */
437 #define IGC_DEFAULT_TXD 256
438 #define IGC_DEFAULT_TX_WORK 128
439 #define IGC_MIN_TXD 64
440 #define IGC_MAX_TXD 4096
441
442 #define IGC_DEFAULT_RXD 256
443 #define IGC_MIN_RXD 64
444 #define IGC_MAX_RXD 4096
445
446 /* Supported Rx Buffer Sizes */
447 #define IGC_RXBUFFER_256 256
448 #define IGC_RXBUFFER_2048 2048
449 #define IGC_RXBUFFER_3072 3072
450
451 #define AUTO_ALL_MODES 0
452 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
453
454 /* Transmit and receive latency (for PTP timestamps) */
455 #define IGC_I225_TX_LATENCY_10 240
456 #define IGC_I225_TX_LATENCY_100 58
457 #define IGC_I225_TX_LATENCY_1000 80
458 #define IGC_I225_TX_LATENCY_2500 1325
459 #define IGC_I225_RX_LATENCY_10 6450
460 #define IGC_I225_RX_LATENCY_100 185
461 #define IGC_I225_RX_LATENCY_1000 300
462 #define IGC_I225_RX_LATENCY_2500 1485
463
464 /* RX and TX descriptor control thresholds.
465 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
466 * descriptors available in its onboard memory.
467 * Setting this to 0 disables RX descriptor prefetch.
468 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
469 * available in host memory.
470 * If PTHRESH is 0, this should also be 0.
471 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
472 * descriptors until either it has this many to write back, or the
473 * ITR timer expires.
474 */
475 #define IGC_RX_PTHRESH 8
476 #define IGC_RX_HTHRESH 8
477 #define IGC_TX_PTHRESH 8
478 #define IGC_TX_HTHRESH 1
479 #define IGC_RX_WTHRESH 4
480 #define IGC_TX_WTHRESH 16
481
482 #define IGC_RX_DMA_ATTR \
483 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
484
485 #define IGC_TS_HDR_LEN 16
486
487 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
488
489 #if (PAGE_SIZE < 8192)
490 #define IGC_MAX_FRAME_BUILD_SKB \
491 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
492 #else
493 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
494 #endif
495
496 /* How many Rx Buffers do we bundle into one write to the hardware ? */
497 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
498
499 /* VLAN info */
500 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
501 #define IGC_TX_FLAGS_VLAN_SHIFT 16
502
503 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)504 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
505 const u32 stat_err_bits)
506 {
507 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
508 }
509
510 enum igc_state_t {
511 __IGC_TESTING,
512 __IGC_RESETTING,
513 __IGC_DOWN,
514 };
515
516 enum igc_tx_flags {
517 /* cmd_type flags */
518 IGC_TX_FLAGS_VLAN = 0x01,
519 IGC_TX_FLAGS_TSO = 0x02,
520 IGC_TX_FLAGS_TSTAMP = 0x04,
521
522 /* olinfo flags */
523 IGC_TX_FLAGS_IPV4 = 0x10,
524 IGC_TX_FLAGS_CSUM = 0x20,
525
526 IGC_TX_FLAGS_TSTAMP_1 = 0x100,
527 IGC_TX_FLAGS_TSTAMP_2 = 0x200,
528 IGC_TX_FLAGS_TSTAMP_3 = 0x400,
529
530 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800,
531 };
532
533 enum igc_boards {
534 board_base,
535 };
536
537 /* The largest size we can write to the descriptor is 65535. In order to
538 * maintain a power of two alignment we have to limit ourselves to 32K.
539 */
540 #define IGC_MAX_TXD_PWR 15
541 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
542
543 /* Tx Descriptors needed, worst case */
544 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
545 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
546
547 struct igc_rx_buffer {
548 union {
549 struct {
550 dma_addr_t dma;
551 struct page *page;
552 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
553 __u32 page_offset;
554 #else
555 __u16 page_offset;
556 #endif
557 __u16 pagecnt_bias;
558 };
559 struct xdp_buff *xdp;
560 };
561 };
562
563 /* context wrapper around xdp_buff to provide access to descriptor metadata */
564 struct igc_xdp_buff {
565 struct xdp_buff xdp;
566 union igc_adv_rx_desc *rx_desc;
567 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
568 };
569
570 struct igc_metadata_request {
571 struct igc_tx_buffer *tx_buffer;
572 struct xsk_tx_metadata *meta;
573 struct igc_ring *tx_ring;
574 u32 cmd_type;
575 };
576
577 struct igc_q_vector {
578 struct igc_adapter *adapter; /* backlink */
579 void __iomem *itr_register;
580 u32 eims_value; /* EIMS mask value */
581
582 u16 itr_val;
583 u8 set_itr;
584
585 struct igc_ring_container rx, tx;
586
587 struct napi_struct napi;
588
589 struct rcu_head rcu; /* to avoid race with update stats on free */
590 char name[IFNAMSIZ + 9];
591
592 /* for dynamic allocation of rings associated with this q_vector */
593 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
594 };
595
596 enum igc_filter_match_flags {
597 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
598 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
599 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
600 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
601 IGC_FILTER_FLAG_USER_DATA = BIT(4),
602 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
603 };
604
605 struct igc_nfc_filter {
606 u8 match_flags;
607 u16 etype;
608 u16 vlan_etype;
609 u16 vlan_tci;
610 u16 vlan_tci_mask;
611 u8 src_addr[ETH_ALEN];
612 u8 dst_addr[ETH_ALEN];
613 u8 user_data[8];
614 u8 user_mask[8];
615 u8 flex_index;
616 u8 rx_queue;
617 u8 prio;
618 u8 immediate_irq;
619 u8 drop;
620 };
621
622 struct igc_nfc_rule {
623 struct list_head list;
624 struct igc_nfc_filter filter;
625 u32 location;
626 u16 action;
627 bool flex;
628 };
629
630 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
631 * based, 8 ethertype based and 32 Flex filter based rules.
632 */
633 #define IGC_MAX_RXNFC_RULES 64
634
635 struct igc_flex_filter {
636 u8 index;
637 u8 data[128];
638 u8 mask[16];
639 u8 length;
640 u8 rx_queue;
641 u8 prio;
642 u8 immediate_irq;
643 u8 drop;
644 };
645
646 /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)647 static inline u16 igc_desc_unused(const struct igc_ring *ring)
648 {
649 u16 ntc = ring->next_to_clean;
650 u16 ntu = ring->next_to_use;
651
652 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
653 }
654
igc_get_phy_info(struct igc_hw * hw)655 static inline s32 igc_get_phy_info(struct igc_hw *hw)
656 {
657 if (hw->phy.ops.get_phy_info)
658 return hw->phy.ops.get_phy_info(hw);
659
660 return 0;
661 }
662
igc_reset_phy(struct igc_hw * hw)663 static inline s32 igc_reset_phy(struct igc_hw *hw)
664 {
665 if (hw->phy.ops.reset)
666 return hw->phy.ops.reset(hw);
667
668 return 0;
669 }
670
txring_txq(const struct igc_ring * tx_ring)671 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
672 {
673 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
674 }
675
676 enum igc_ring_flags_t {
677 IGC_RING_FLAG_RX_3K_BUFFER,
678 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
679 IGC_RING_FLAG_RX_SCTP_CSUM,
680 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
681 IGC_RING_FLAG_TX_CTX_IDX,
682 IGC_RING_FLAG_TX_DETECT_HANG,
683 IGC_RING_FLAG_AF_XDP_ZC,
684 IGC_RING_FLAG_TX_HWTSTAMP,
685 };
686
687 #define ring_uses_large_buffer(ring) \
688 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
689 #define set_ring_uses_large_buffer(ring) \
690 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
691 #define clear_ring_uses_large_buffer(ring) \
692 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
693
694 #define ring_uses_build_skb(ring) \
695 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
696
igc_rx_bufsz(struct igc_ring * ring)697 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
698 {
699 #if (PAGE_SIZE < 8192)
700 if (ring_uses_large_buffer(ring))
701 return IGC_RXBUFFER_3072;
702
703 if (ring_uses_build_skb(ring))
704 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
705 #endif
706 return IGC_RXBUFFER_2048;
707 }
708
igc_rx_pg_order(struct igc_ring * ring)709 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
710 {
711 #if (PAGE_SIZE < 8192)
712 if (ring_uses_large_buffer(ring))
713 return 1;
714 #endif
715 return 0;
716 }
717
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)718 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
719 {
720 if (hw->phy.ops.read_reg)
721 return hw->phy.ops.read_reg(hw, offset, data);
722
723 return -EOPNOTSUPP;
724 }
725
726 void igc_reinit_locked(struct igc_adapter *);
727 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
728 u32 location);
729 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
730 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
731
732 void igc_ptp_init(struct igc_adapter *adapter);
733 void igc_ptp_reset(struct igc_adapter *adapter);
734 void igc_ptp_suspend(struct igc_adapter *adapter);
735 void igc_ptp_stop(struct igc_adapter *adapter);
736 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
737 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
738 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
739 void igc_ptp_tx_hang(struct igc_adapter *adapter);
740 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
741 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
742
743 int igc_led_setup(struct igc_adapter *adapter);
744 void igc_led_free(struct igc_adapter *adapter);
745
746 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
747
748 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
749
750 #define IGC_RX_DESC(R, i) \
751 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
752 #define IGC_TX_DESC(R, i) \
753 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
754 #define IGC_TX_CTXTDESC(R, i) \
755 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
756
757 #endif /* _IGC_H_ */
758