1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/bitfield.h> 17 #include <linux/hrtimer.h> 18 #include <net/xdp.h> 19 20 #include "igc_hw.h" 21 22 void igc_ethtool_set_ops(struct net_device *); 23 24 /* Transmit and receive queues */ 25 #define IGC_MAX_RX_QUEUES 4 26 #define IGC_MAX_TX_QUEUES 4 27 28 #define MAX_Q_VECTORS 8 29 #define MAX_STD_JUMBO_FRAME_SIZE 9216 30 31 #define MAX_ETYPE_FILTER 8 32 #define IGC_RETA_SIZE 128 33 34 /* SDP support */ 35 #define IGC_N_EXTTS 2 36 #define IGC_N_PEROUT 2 37 #define IGC_N_SDP 4 38 39 #define MAX_FLEX_FILTER 32 40 41 #define IGC_MAX_TX_TSTAMP_REGS 4 42 43 enum igc_mac_filter_type { 44 IGC_MAC_FILTER_TYPE_DST = 0, 45 IGC_MAC_FILTER_TYPE_SRC 46 }; 47 48 struct igc_tx_queue_stats { 49 u64 packets; 50 u64 bytes; 51 u64 restart_queue; 52 u64 restart_queue2; 53 }; 54 55 struct igc_rx_queue_stats { 56 u64 packets; 57 u64 bytes; 58 u64 drops; 59 u64 csum_err; 60 u64 alloc_failed; 61 }; 62 63 struct igc_rx_packet_stats { 64 u64 ipv4_packets; /* IPv4 headers processed */ 65 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 66 u64 ipv6_packets; /* IPv6 headers processed */ 67 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 68 u64 tcp_packets; /* TCP headers processed */ 69 u64 udp_packets; /* UDP headers processed */ 70 u64 sctp_packets; /* SCTP headers processed */ 71 u64 nfs_packets; /* NFS headers processe */ 72 u64 other_packets; 73 }; 74 75 struct igc_tx_timestamp_request { 76 struct sk_buff *skb; /* reference to the packet being timestamped */ 77 unsigned long start; /* when the tstamp request started (jiffies) */ 78 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */ 79 u32 regl; /* which TXSTMPL_{X} register should be used */ 80 u32 regh; /* which TXSTMPH_{X} register should be used */ 81 u32 flags; /* flags that should be added to the tx_buffer */ 82 }; 83 84 struct igc_inline_rx_tstamps { 85 /* Timestamps are saved in little endian at the beginning of the packet 86 * buffer following the layout: 87 * 88 * DWORD: | 0 | 1 | 2 | 3 | 89 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH | 90 * 91 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds 92 * part of the timestamp. 93 * 94 */ 95 __le32 timer1[2]; 96 __le32 timer0[2]; 97 }; 98 99 struct igc_ring_container { 100 struct igc_ring *ring; /* pointer to linked list of rings */ 101 unsigned int total_bytes; /* total bytes processed this int */ 102 unsigned int total_packets; /* total packets processed this int */ 103 u16 work_limit; /* total work allowed per interrupt */ 104 u8 count; /* total number of rings in vector */ 105 u8 itr; /* current ITR setting for ring */ 106 }; 107 108 struct igc_ring { 109 struct igc_q_vector *q_vector; /* backlink to q_vector */ 110 struct net_device *netdev; /* back pointer to net_device */ 111 struct device *dev; /* device for dma mapping */ 112 union { /* array of buffer info structs */ 113 struct igc_tx_buffer *tx_buffer_info; 114 struct igc_rx_buffer *rx_buffer_info; 115 }; 116 void *desc; /* descriptor ring memory */ 117 unsigned long flags; /* ring specific flags */ 118 void __iomem *tail; /* pointer to ring tail register */ 119 dma_addr_t dma; /* phys address of the ring */ 120 unsigned int size; /* length of desc. ring in bytes */ 121 122 u16 count; /* number of desc. in the ring */ 123 u8 queue_index; /* logical index of the ring*/ 124 u8 reg_idx; /* physical index of the ring */ 125 bool launchtime_enable; /* true if LaunchTime is enabled */ 126 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 127 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 128 129 u32 start_time; 130 u32 end_time; 131 u32 max_sdu; 132 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 133 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 134 135 /* CBS parameters */ 136 bool cbs_enable; /* indicates if CBS is enabled */ 137 s32 idleslope; /* idleSlope in kbps */ 138 s32 sendslope; /* sendSlope in kbps */ 139 s32 hicredit; /* hiCredit in bytes */ 140 s32 locredit; /* loCredit in bytes */ 141 142 /* everything past this point are written often */ 143 u16 next_to_clean; 144 u16 next_to_use; 145 u16 next_to_alloc; 146 147 union { 148 /* TX */ 149 struct { 150 struct igc_tx_queue_stats tx_stats; 151 struct u64_stats_sync tx_syncp; 152 struct u64_stats_sync tx_syncp2; 153 }; 154 /* RX */ 155 struct { 156 struct igc_rx_queue_stats rx_stats; 157 struct igc_rx_packet_stats pkt_stats; 158 struct u64_stats_sync rx_syncp; 159 struct sk_buff *skb; 160 }; 161 }; 162 163 struct xdp_rxq_info xdp_rxq; 164 struct xsk_buff_pool *xsk_pool; 165 } ____cacheline_internodealigned_in_smp; 166 167 /* Board specific private data structure */ 168 struct igc_adapter { 169 struct net_device *netdev; 170 171 struct ethtool_eee eee; 172 u16 eee_advert; 173 174 unsigned long state; 175 unsigned int flags; 176 unsigned int num_q_vectors; 177 178 struct msix_entry *msix_entries; 179 180 /* TX */ 181 u16 tx_work_limit; 182 u32 tx_timeout_count; 183 int num_tx_queues; 184 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 185 186 /* RX */ 187 int num_rx_queues; 188 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 189 190 struct timer_list watchdog_timer; 191 struct timer_list dma_err_timer; 192 struct timer_list phy_info_timer; 193 struct hrtimer hrtimer; 194 195 u32 wol; 196 u32 en_mng_pt; 197 u16 link_speed; 198 u16 link_duplex; 199 200 u8 port_num; 201 202 u8 __iomem *io_addr; 203 /* Interrupt Throttle Rate */ 204 u32 rx_itr_setting; 205 u32 tx_itr_setting; 206 207 struct work_struct reset_task; 208 struct work_struct watchdog_task; 209 struct work_struct dma_err_task; 210 bool fc_autoneg; 211 212 u8 tx_timeout_factor; 213 214 int msg_enable; 215 u32 max_frame_size; 216 u32 min_frame_size; 217 218 int tc_setup_type; 219 ktime_t base_time; 220 ktime_t cycle_time; 221 bool taprio_offload_enable; 222 u32 qbv_config_change_errors; 223 bool qbv_transition; 224 unsigned int qbv_count; 225 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition 226 * are protected by the qbv_tx_lock. 227 */ 228 spinlock_t qbv_tx_lock; 229 230 /* OS defined structs */ 231 struct pci_dev *pdev; 232 /* lock for statistics */ 233 spinlock_t stats64_lock; 234 struct rtnl_link_stats64 stats64; 235 236 /* structs defined in igc_hw.h */ 237 struct igc_hw hw; 238 struct igc_hw_stats stats; 239 240 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 241 u32 eims_enable_mask; 242 u32 eims_other; 243 244 u16 tx_ring_count; 245 u16 rx_ring_count; 246 247 u32 tx_hwtstamp_timeouts; 248 u32 tx_hwtstamp_skipped; 249 u32 rx_hwtstamp_cleared; 250 251 u32 rss_queues; 252 u32 rss_indir_tbl_init; 253 254 /* Any access to elements in nfc_rule_list is protected by the 255 * nfc_rule_lock. 256 */ 257 struct mutex nfc_rule_lock; 258 struct list_head nfc_rule_list; 259 unsigned int nfc_rule_count; 260 261 u8 rss_indir_tbl[IGC_RETA_SIZE]; 262 263 unsigned long link_check_timeout; 264 struct igc_info ei; 265 266 u32 test_icr; 267 268 struct ptp_clock *ptp_clock; 269 struct ptp_clock_info ptp_caps; 270 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 271 * ptp_tx_lock. 272 */ 273 spinlock_t ptp_tx_lock; 274 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS]; 275 struct hwtstamp_config tstamp_config; 276 unsigned int ptp_flags; 277 /* System time value lock */ 278 spinlock_t tmreg_lock; 279 /* Free-running timer lock */ 280 spinlock_t free_timer_lock; 281 struct cyclecounter cc; 282 struct timecounter tc; 283 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 284 ktime_t ptp_reset_start; /* Reset time in clock mono */ 285 struct system_time_snapshot snapshot; 286 287 char fw_version[32]; 288 289 struct bpf_prog *xdp_prog; 290 291 bool pps_sys_wrap_on; 292 293 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 294 struct { 295 struct timespec64 start; 296 struct timespec64 period; 297 } perout[IGC_N_PEROUT]; 298 }; 299 300 void igc_up(struct igc_adapter *adapter); 301 void igc_down(struct igc_adapter *adapter); 302 int igc_open(struct net_device *netdev); 303 int igc_close(struct net_device *netdev); 304 int igc_setup_tx_resources(struct igc_ring *ring); 305 int igc_setup_rx_resources(struct igc_ring *ring); 306 void igc_free_tx_resources(struct igc_ring *ring); 307 void igc_free_rx_resources(struct igc_ring *ring); 308 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 309 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 310 const u32 max_rss_queues); 311 int igc_reinit_queues(struct igc_adapter *adapter); 312 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 313 bool igc_has_link(struct igc_adapter *adapter); 314 void igc_reset(struct igc_adapter *adapter); 315 void igc_update_stats(struct igc_adapter *adapter); 316 void igc_disable_rx_ring(struct igc_ring *ring); 317 void igc_enable_rx_ring(struct igc_ring *ring); 318 void igc_disable_tx_ring(struct igc_ring *ring); 319 void igc_enable_tx_ring(struct igc_ring *ring); 320 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 321 322 /* igc_dump declarations */ 323 void igc_rings_dump(struct igc_adapter *adapter); 324 void igc_regs_dump(struct igc_adapter *adapter); 325 326 extern char igc_driver_name[]; 327 328 #define IGC_REGS_LEN 740 329 330 /* flags controlling PTP/1588 function */ 331 #define IGC_PTP_ENABLED BIT(0) 332 333 /* Flags definitions */ 334 #define IGC_FLAG_HAS_MSI BIT(0) 335 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 336 #define IGC_FLAG_DMAC BIT(4) 337 #define IGC_FLAG_PTP BIT(8) 338 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 339 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 340 #define IGC_FLAG_HAS_MSIX BIT(13) 341 #define IGC_FLAG_EEE BIT(14) 342 #define IGC_FLAG_VLAN_PROMISC BIT(15) 343 #define IGC_FLAG_RX_LEGACY BIT(16) 344 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 345 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 346 347 #define IGC_FLAG_TSN_ANY_ENABLED \ 348 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED) 349 350 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 351 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 352 353 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 354 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 355 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 356 357 /* RX-desc Write-Back format RSS Type's */ 358 enum igc_rss_type_num { 359 IGC_RSS_TYPE_NO_HASH = 0, 360 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 361 IGC_RSS_TYPE_HASH_IPV4 = 2, 362 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 363 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 364 IGC_RSS_TYPE_HASH_IPV6 = 5, 365 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 366 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 367 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 368 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 369 IGC_RSS_TYPE_MAX = 10, 370 }; 371 #define IGC_RSS_TYPE_MAX_TABLE 16 372 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 373 374 /* igc_rss_type - Rx descriptor RSS type field */ 375 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 376 { 377 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 378 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 379 * is slightly slower than via u32 (wb.lower.lo_dword.data) 380 */ 381 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 382 } 383 384 /* Interrupt defines */ 385 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 386 #define IGC_4K_ITR 980 387 #define IGC_20K_ITR 196 388 #define IGC_70K_ITR 56 389 390 #define IGC_DEFAULT_ITR 3 /* dynamic */ 391 #define IGC_MAX_ITR_USECS 10000 392 #define IGC_MIN_ITR_USECS 10 393 #define NON_Q_VECTORS 1 394 #define MAX_MSIX_ENTRIES 10 395 396 /* TX/RX descriptor defines */ 397 #define IGC_DEFAULT_TXD 256 398 #define IGC_DEFAULT_TX_WORK 128 399 #define IGC_MIN_TXD 64 400 #define IGC_MAX_TXD 4096 401 402 #define IGC_DEFAULT_RXD 256 403 #define IGC_MIN_RXD 64 404 #define IGC_MAX_RXD 4096 405 406 /* Supported Rx Buffer Sizes */ 407 #define IGC_RXBUFFER_256 256 408 #define IGC_RXBUFFER_2048 2048 409 #define IGC_RXBUFFER_3072 3072 410 411 #define AUTO_ALL_MODES 0 412 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 413 414 /* Transmit and receive latency (for PTP timestamps) */ 415 #define IGC_I225_TX_LATENCY_10 240 416 #define IGC_I225_TX_LATENCY_100 58 417 #define IGC_I225_TX_LATENCY_1000 80 418 #define IGC_I225_TX_LATENCY_2500 1325 419 #define IGC_I225_RX_LATENCY_10 6450 420 #define IGC_I225_RX_LATENCY_100 185 421 #define IGC_I225_RX_LATENCY_1000 300 422 #define IGC_I225_RX_LATENCY_2500 1485 423 424 /* RX and TX descriptor control thresholds. 425 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 426 * descriptors available in its onboard memory. 427 * Setting this to 0 disables RX descriptor prefetch. 428 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 429 * available in host memory. 430 * If PTHRESH is 0, this should also be 0. 431 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 432 * descriptors until either it has this many to write back, or the 433 * ITR timer expires. 434 */ 435 #define IGC_RX_PTHRESH 8 436 #define IGC_RX_HTHRESH 8 437 #define IGC_TX_PTHRESH 8 438 #define IGC_TX_HTHRESH 1 439 #define IGC_RX_WTHRESH 4 440 #define IGC_TX_WTHRESH 16 441 442 #define IGC_RX_DMA_ATTR \ 443 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 444 445 #define IGC_TS_HDR_LEN 16 446 447 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 448 449 #if (PAGE_SIZE < 8192) 450 #define IGC_MAX_FRAME_BUILD_SKB \ 451 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 452 #else 453 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 454 #endif 455 456 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 457 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 458 459 /* VLAN info */ 460 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 461 #define IGC_TX_FLAGS_VLAN_SHIFT 16 462 463 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 464 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 465 const u32 stat_err_bits) 466 { 467 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 468 } 469 470 enum igc_state_t { 471 __IGC_TESTING, 472 __IGC_RESETTING, 473 __IGC_DOWN, 474 }; 475 476 enum igc_tx_flags { 477 /* cmd_type flags */ 478 IGC_TX_FLAGS_VLAN = 0x01, 479 IGC_TX_FLAGS_TSO = 0x02, 480 IGC_TX_FLAGS_TSTAMP = 0x04, 481 482 /* olinfo flags */ 483 IGC_TX_FLAGS_IPV4 = 0x10, 484 IGC_TX_FLAGS_CSUM = 0x20, 485 486 IGC_TX_FLAGS_TSTAMP_1 = 0x100, 487 IGC_TX_FLAGS_TSTAMP_2 = 0x200, 488 IGC_TX_FLAGS_TSTAMP_3 = 0x400, 489 490 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800, 491 }; 492 493 enum igc_boards { 494 board_base, 495 }; 496 497 /* The largest size we can write to the descriptor is 65535. In order to 498 * maintain a power of two alignment we have to limit ourselves to 32K. 499 */ 500 #define IGC_MAX_TXD_PWR 15 501 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 502 503 /* Tx Descriptors needed, worst case */ 504 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 505 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 506 507 enum igc_tx_buffer_type { 508 IGC_TX_BUFFER_TYPE_SKB, 509 IGC_TX_BUFFER_TYPE_XDP, 510 IGC_TX_BUFFER_TYPE_XSK, 511 }; 512 513 /* wrapper around a pointer to a socket buffer, 514 * so a DMA handle can be stored along with the buffer 515 */ 516 struct igc_tx_buffer { 517 union igc_adv_tx_desc *next_to_watch; 518 unsigned long time_stamp; 519 enum igc_tx_buffer_type type; 520 union { 521 struct sk_buff *skb; 522 struct xdp_frame *xdpf; 523 }; 524 unsigned int bytecount; 525 u16 gso_segs; 526 __be16 protocol; 527 528 DEFINE_DMA_UNMAP_ADDR(dma); 529 DEFINE_DMA_UNMAP_LEN(len); 530 u32 tx_flags; 531 }; 532 533 struct igc_rx_buffer { 534 union { 535 struct { 536 dma_addr_t dma; 537 struct page *page; 538 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 539 __u32 page_offset; 540 #else 541 __u16 page_offset; 542 #endif 543 __u16 pagecnt_bias; 544 }; 545 struct xdp_buff *xdp; 546 }; 547 }; 548 549 /* context wrapper around xdp_buff to provide access to descriptor metadata */ 550 struct igc_xdp_buff { 551 struct xdp_buff xdp; 552 union igc_adv_rx_desc *rx_desc; 553 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 554 }; 555 556 struct igc_q_vector { 557 struct igc_adapter *adapter; /* backlink */ 558 void __iomem *itr_register; 559 u32 eims_value; /* EIMS mask value */ 560 561 u16 itr_val; 562 u8 set_itr; 563 564 struct igc_ring_container rx, tx; 565 566 struct napi_struct napi; 567 568 struct rcu_head rcu; /* to avoid race with update stats on free */ 569 char name[IFNAMSIZ + 9]; 570 struct net_device poll_dev; 571 572 /* for dynamic allocation of rings associated with this q_vector */ 573 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 574 }; 575 576 enum igc_filter_match_flags { 577 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 578 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 579 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 580 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 581 IGC_FILTER_FLAG_USER_DATA = BIT(4), 582 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 583 }; 584 585 struct igc_nfc_filter { 586 u8 match_flags; 587 u16 etype; 588 __be16 vlan_etype; 589 u16 vlan_tci; 590 u16 vlan_tci_mask; 591 u8 src_addr[ETH_ALEN]; 592 u8 dst_addr[ETH_ALEN]; 593 u8 user_data[8]; 594 u8 user_mask[8]; 595 u8 flex_index; 596 u8 rx_queue; 597 u8 prio; 598 u8 immediate_irq; 599 u8 drop; 600 }; 601 602 struct igc_nfc_rule { 603 struct list_head list; 604 struct igc_nfc_filter filter; 605 u32 location; 606 u16 action; 607 bool flex; 608 }; 609 610 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 611 * based, 8 ethertype based and 32 Flex filter based rules. 612 */ 613 #define IGC_MAX_RXNFC_RULES 64 614 615 struct igc_flex_filter { 616 u8 index; 617 u8 data[128]; 618 u8 mask[16]; 619 u8 length; 620 u8 rx_queue; 621 u8 prio; 622 u8 immediate_irq; 623 u8 drop; 624 }; 625 626 /* igc_desc_unused - calculate if we have unused descriptors */ 627 static inline u16 igc_desc_unused(const struct igc_ring *ring) 628 { 629 u16 ntc = ring->next_to_clean; 630 u16 ntu = ring->next_to_use; 631 632 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 633 } 634 635 static inline s32 igc_get_phy_info(struct igc_hw *hw) 636 { 637 if (hw->phy.ops.get_phy_info) 638 return hw->phy.ops.get_phy_info(hw); 639 640 return 0; 641 } 642 643 static inline s32 igc_reset_phy(struct igc_hw *hw) 644 { 645 if (hw->phy.ops.reset) 646 return hw->phy.ops.reset(hw); 647 648 return 0; 649 } 650 651 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 652 { 653 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 654 } 655 656 enum igc_ring_flags_t { 657 IGC_RING_FLAG_RX_3K_BUFFER, 658 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 659 IGC_RING_FLAG_RX_SCTP_CSUM, 660 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 661 IGC_RING_FLAG_TX_CTX_IDX, 662 IGC_RING_FLAG_TX_DETECT_HANG, 663 IGC_RING_FLAG_AF_XDP_ZC, 664 IGC_RING_FLAG_TX_HWTSTAMP, 665 }; 666 667 #define ring_uses_large_buffer(ring) \ 668 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 669 #define set_ring_uses_large_buffer(ring) \ 670 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 671 #define clear_ring_uses_large_buffer(ring) \ 672 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 673 674 #define ring_uses_build_skb(ring) \ 675 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 676 677 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 678 { 679 #if (PAGE_SIZE < 8192) 680 if (ring_uses_large_buffer(ring)) 681 return IGC_RXBUFFER_3072; 682 683 if (ring_uses_build_skb(ring)) 684 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 685 #endif 686 return IGC_RXBUFFER_2048; 687 } 688 689 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 690 { 691 #if (PAGE_SIZE < 8192) 692 if (ring_uses_large_buffer(ring)) 693 return 1; 694 #endif 695 return 0; 696 } 697 698 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 699 { 700 if (hw->phy.ops.read_reg) 701 return hw->phy.ops.read_reg(hw, offset, data); 702 703 return -EOPNOTSUPP; 704 } 705 706 void igc_reinit_locked(struct igc_adapter *); 707 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 708 u32 location); 709 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 710 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 711 712 void igc_ptp_init(struct igc_adapter *adapter); 713 void igc_ptp_reset(struct igc_adapter *adapter); 714 void igc_ptp_suspend(struct igc_adapter *adapter); 715 void igc_ptp_stop(struct igc_adapter *adapter); 716 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 717 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 718 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 719 void igc_ptp_tx_hang(struct igc_adapter *adapter); 720 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 721 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 722 723 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 724 725 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 726 727 #define IGC_RX_DESC(R, i) \ 728 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 729 #define IGC_TX_DESC(R, i) \ 730 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 731 #define IGC_TX_CTXTDESC(R, i) \ 732 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 733 734 #endif /* _IGC_H_ */ 735