1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Texas Instruments ICSSG Ethernet driver
3 *
4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 */
7
8 #ifndef __NET_TI_ICSSG_PRUETH_H
9 #define __NET_TI_ICSSG_PRUETH_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/genalloc.h>
13 #include <linux/if_vlan.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/remoteproc/pruss.h>
27 #include <linux/pruss_driver.h>
28 #include <linux/ptp_clock_kernel.h>
29 #include <linux/remoteproc.h>
30
31 #include <linux/dma-mapping.h>
32 #include <linux/dma/ti-cppi5.h>
33 #include <linux/dma/k3-udma-glue.h>
34
35 #include <net/devlink.h>
36
37 #include "icssg_config.h"
38 #include "icss_iep.h"
39 #include "icssg_switch_map.h"
40
41 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN)
42 #define PRUETH_MIN_PKT_SIZE (VLAN_ETH_ZLEN)
43 #define PRUETH_MAX_PKT_SIZE (PRUETH_MAX_MTU + ETH_HLEN + ETH_FCS_LEN)
44
45 #define ICSS_SLICE0 0
46 #define ICSS_SLICE1 1
47
48 #define ICSS_FW_PRU 0
49 #define ICSS_FW_RTU 1
50
51 #define ICSSG_MAX_RFLOWS 8 /* per slice */
52
53 /* Number of ICSSG related stats */
54 #define ICSSG_NUM_STATS 60
55 #define ICSSG_NUM_STANDARD_STATS 31
56 #define ICSSG_NUM_ETHTOOL_STATS (ICSSG_NUM_STATS - ICSSG_NUM_STANDARD_STATS)
57
58 #define IEP_DEFAULT_CYCLE_TIME_NS 1000000 /* 1 ms */
59
60 /* Firmware status codes */
61 #define ICSS_HS_FW_READY 0x55555555
62 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */
63
64 /* Firmware command codes */
65 #define ICSS_HS_CMD_BUSY 0x40000000
66 #define ICSS_HS_CMD_DONE 0x80000000
67 #define ICSS_HS_CMD_CANCEL 0x10000000
68
69 /* Firmware commands */
70 #define ICSS_CMD_SPAD 0x20
71 #define ICSS_CMD_RXTX 0x10
72 #define ICSS_CMD_ADD_FDB 0x1
73 #define ICSS_CMD_DEL_FDB 0x2
74 #define ICSS_CMD_SET_RUN 0x4
75 #define ICSS_CMD_GET_FDB_SLOT 0x5
76 #define ICSS_CMD_ENABLE_VLAN 0x5
77 #define ICSS_CMD_DISABLE_VLAN 0x6
78 #define ICSS_CMD_ADD_FILTER 0x7
79 #define ICSS_CMD_ADD_MAC 0x8
80
81 /* In switch mode there are 3 real ports i.e. 3 mac addrs.
82 * however Linux sees only the host side port. The other 2 ports
83 * are the switch ports.
84 * In emac mode there are 2 real ports i.e. 2 mac addrs.
85 * Linux sees both the ports.
86 */
87 enum prueth_port {
88 PRUETH_PORT_HOST = 0, /* host side port */
89 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */
90 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */
91 PRUETH_PORT_INVALID, /* Invalid prueth port */
92 };
93
94 enum prueth_mac {
95 PRUETH_MAC0 = 0,
96 PRUETH_MAC1,
97 PRUETH_NUM_MACS,
98 PRUETH_MAC_INVALID,
99 };
100
101 struct prueth_tx_chn {
102 struct device *dma_dev;
103 struct napi_struct napi_tx;
104 struct k3_cppi_desc_pool *desc_pool;
105 struct k3_udma_glue_tx_channel *tx_chn;
106 struct prueth_emac *emac;
107 u32 id;
108 u32 descs_num;
109 unsigned int irq;
110 char name[32];
111 struct hrtimer tx_hrtimer;
112 unsigned long tx_pace_timeout_ns;
113 };
114
115 struct prueth_rx_chn {
116 struct device *dev;
117 struct device *dma_dev;
118 struct k3_cppi_desc_pool *desc_pool;
119 struct k3_udma_glue_rx_channel *rx_chn;
120 u32 descs_num;
121 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */
122 char name[32];
123 };
124
125 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3)
126 * and lower three are lower priority channels or threads.
127 */
128 #define PRUETH_MAX_TX_QUEUES 4
129
130 #define PRUETH_MAX_TX_TS_REQUESTS 50 /* Max simultaneous TX_TS requests */
131
132 /* Minimum coalesce time in usecs for both Tx and Rx */
133 #define ICSSG_MIN_COALESCE_USECS 20
134
135 /* data for each emac port */
136 struct prueth_emac {
137 bool is_sr1;
138 bool fw_running;
139 struct prueth *prueth;
140 struct net_device *ndev;
141 u8 mac_addr[6];
142 struct napi_struct napi_rx;
143 u32 msg_enable;
144
145 int link;
146 int speed;
147 int duplex;
148
149 const char *phy_id;
150 struct device_node *phy_node;
151 phy_interface_t phy_if;
152 enum prueth_port port_id;
153 struct icss_iep *iep;
154 unsigned int rx_ts_enabled : 1;
155 unsigned int tx_ts_enabled : 1;
156 unsigned int half_duplex : 1;
157
158 /* DMA related */
159 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES];
160 struct completion tdown_complete;
161 atomic_t tdown_cnt;
162 struct prueth_rx_chn rx_chns;
163 int rx_flow_id_base;
164 int tx_ch_num;
165
166 /* SR1.0 Management channel */
167 struct prueth_rx_chn rx_mgm_chn;
168 int rx_mgm_flow_id_base;
169
170 spinlock_t lock; /* serialize access */
171
172 /* TX HW Timestamping */
173 /* TX TS cookie will be index to the tx_ts_skb array */
174 struct sk_buff *tx_ts_skb[PRUETH_MAX_TX_TS_REQUESTS];
175 atomic_t tx_ts_pending;
176 int tx_ts_irq;
177
178 u8 cmd_seq;
179 /* shutdown related */
180 __le32 cmd_data[4];
181 struct completion cmd_complete;
182 /* Mutex to serialize access to firmware command interface */
183 struct mutex cmd_lock;
184 struct work_struct rx_mode_work;
185 struct workqueue_struct *cmd_wq;
186
187 struct pruss_mem_region dram;
188
189 struct delayed_work stats_work;
190 u64 stats[ICSSG_NUM_STATS];
191
192 /* RX IRQ Coalescing Related */
193 struct hrtimer rx_hrtimer;
194 unsigned long rx_pace_timeout_ns;
195 };
196
197 /**
198 * struct prueth_pdata - PRUeth platform data
199 * @fdqring_mode: Free desc queue mode
200 * @quirk_10m_link_issue: 10M link detect errata
201 */
202 struct prueth_pdata {
203 enum k3_ring_mode fdqring_mode;
204 u32 quirk_10m_link_issue:1;
205 };
206
207 struct icssg_firmwares {
208 char *pru;
209 char *rtu;
210 char *txpru;
211 };
212
213 /**
214 * struct prueth - PRUeth structure
215 * @dev: device
216 * @pruss: pruss handle
217 * @pru: rproc instances of PRUs
218 * @rtu: rproc instances of RTUs
219 * @txpru: rproc instances of TX_PRUs
220 * @shram: PRUSS shared RAM region
221 * @sram_pool: MSMC RAM pool for buffers
222 * @msmcram: MSMC RAM region
223 * @eth_node: DT node for the port
224 * @emac: private EMAC data structure
225 * @registered_netdevs: list of registered netdevs
226 * @miig_rt: regmap to mii_g_rt block
227 * @mii_rt: regmap to mii_rt block
228 * @pru_id: ID for each of the PRUs
229 * @pdev: pointer to ICSSG platform device
230 * @pdata: pointer to platform data for ICSSG driver
231 * @icssg_hwcmdseq: seq counter or HWQ messages
232 * @emacs_initialized: num of EMACs/ext ports that are up/running
233 * @iep0: pointer to IEP0 device
234 * @iep1: pointer to IEP1 device
235 */
236 struct prueth {
237 struct device *dev;
238 struct pruss *pruss;
239 struct rproc *pru[PRUSS_NUM_PRUS];
240 struct rproc *rtu[PRUSS_NUM_PRUS];
241 struct rproc *txpru[PRUSS_NUM_PRUS];
242 struct pruss_mem_region shram;
243 struct gen_pool *sram_pool;
244 struct pruss_mem_region msmcram;
245
246 struct device_node *eth_node[PRUETH_NUM_MACS];
247 struct prueth_emac *emac[PRUETH_NUM_MACS];
248 struct net_device *registered_netdevs[PRUETH_NUM_MACS];
249 struct regmap *miig_rt;
250 struct regmap *mii_rt;
251
252 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS];
253 struct platform_device *pdev;
254 struct prueth_pdata pdata;
255 u8 icssg_hwcmdseq;
256 int emacs_initialized;
257 struct icss_iep *iep0;
258 struct icss_iep *iep1;
259 };
260
261 struct emac_tx_ts_response {
262 u32 reserved[2];
263 u32 cookie;
264 u32 lo_ts;
265 u32 hi_ts;
266 };
267
268 struct emac_tx_ts_response_sr1 {
269 __le32 lo_ts;
270 __le32 hi_ts;
271 __le32 reserved;
272 __le32 cookie;
273 };
274
275 /* get PRUSS SLICE number from prueth_emac */
prueth_emac_slice(struct prueth_emac * emac)276 static inline int prueth_emac_slice(struct prueth_emac *emac)
277 {
278 switch (emac->port_id) {
279 case PRUETH_PORT_MII0:
280 return ICSS_SLICE0;
281 case PRUETH_PORT_MII1:
282 return ICSS_SLICE1;
283 default:
284 return -EINVAL;
285 }
286 }
287
288 extern const struct ethtool_ops icssg_ethtool_ops;
289 extern const struct dev_pm_ops prueth_dev_pm_ops;
290
291 /* Classifier helpers */
292 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
293 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);
294 void icssg_class_disable(struct regmap *miig_rt, int slice);
295 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,
296 bool is_sr1);
297 void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice);
298 void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
299 struct net_device *ndev);
300 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
301
302 /* config helpers */
303 void icssg_config_ipg(struct prueth_emac *emac);
304 int icssg_config(struct prueth *prueth, struct prueth_emac *emac,
305 int slice);
306 int emac_set_port_state(struct prueth_emac *emac,
307 enum icssg_port_state_cmd state);
308 void icssg_config_set_speed(struct prueth_emac *emac);
309 void icssg_config_half_duplex(struct prueth_emac *emac);
310
311 /* Buffer queue helpers */
312 int icssg_queue_pop(struct prueth *prueth, u8 queue);
313 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr);
314 u32 icssg_queue_level(struct prueth *prueth, int queue);
315
316 #define prueth_napi_to_tx_chn(pnapi) \
317 container_of(pnapi, struct prueth_tx_chn, napi_tx)
318
319 void emac_stats_work_handler(struct work_struct *work);
320 void emac_update_hardware_stats(struct prueth_emac *emac);
321 int emac_get_stat_by_name(struct prueth_emac *emac, char *stat_name);
322
323 /* Common functions */
324 void prueth_cleanup_rx_chns(struct prueth_emac *emac,
325 struct prueth_rx_chn *rx_chn,
326 int max_rflows);
327 void prueth_cleanup_tx_chns(struct prueth_emac *emac);
328 void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num);
329 void prueth_xmit_free(struct prueth_tx_chn *tx_chn,
330 struct cppi5_host_desc_t *desc);
331 int emac_tx_complete_packets(struct prueth_emac *emac, int chn,
332 int budget, bool *tdown);
333 int prueth_ndev_add_tx_napi(struct prueth_emac *emac);
334 int prueth_init_tx_chns(struct prueth_emac *emac);
335 int prueth_init_rx_chns(struct prueth_emac *emac,
336 struct prueth_rx_chn *rx_chn,
337 char *name, u32 max_rflows,
338 u32 max_desc_num);
339 int prueth_dma_rx_push(struct prueth_emac *emac,
340 struct sk_buff *skb,
341 struct prueth_rx_chn *rx_chn);
342 void emac_rx_timestamp(struct prueth_emac *emac,
343 struct sk_buff *skb, u32 *psdata);
344 enum netdev_tx emac_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev);
345 irqreturn_t prueth_rx_irq(int irq, void *dev_id);
346 void prueth_emac_stop(struct prueth_emac *emac);
347 void prueth_cleanup_tx_ts(struct prueth_emac *emac);
348 int emac_napi_rx_poll(struct napi_struct *napi_rx, int budget);
349 int prueth_prepare_rx_chan(struct prueth_emac *emac,
350 struct prueth_rx_chn *chn,
351 int buf_size);
352 void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num,
353 bool free_skb);
354 void prueth_reset_rx_chan(struct prueth_rx_chn *chn,
355 int num_flows, bool disable);
356 void emac_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue);
357 int emac_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);
358 void emac_ndo_get_stats64(struct net_device *ndev,
359 struct rtnl_link_stats64 *stats);
360 int emac_ndo_get_phys_port_name(struct net_device *ndev, char *name,
361 size_t len);
362 int prueth_node_port(struct device_node *eth_node);
363 int prueth_node_mac(struct device_node *eth_node);
364 void prueth_netdev_exit(struct prueth *prueth,
365 struct device_node *eth_node);
366 int prueth_get_cores(struct prueth *prueth, int slice, bool is_sr1);
367 void prueth_put_cores(struct prueth *prueth, int slice);
368
369 /* Revision specific helper */
370 u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns);
371
372 #endif /* __NET_TI_ICSSG_PRUETH_H */
373