12504ba9fSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20b56e9a7SVivek Gautam /*
30b56e9a7SVivek Gautam * Rockchip emmc PHY driver
40b56e9a7SVivek Gautam *
50b56e9a7SVivek Gautam * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
60b56e9a7SVivek Gautam * Copyright (C) 2016 ROCKCHIP, Inc.
70b56e9a7SVivek Gautam */
80b56e9a7SVivek Gautam
90b56e9a7SVivek Gautam #include <linux/clk.h>
100b56e9a7SVivek Gautam #include <linux/delay.h>
110b56e9a7SVivek Gautam #include <linux/mfd/syscon.h>
120b56e9a7SVivek Gautam #include <linux/module.h>
130b56e9a7SVivek Gautam #include <linux/of.h>
140b56e9a7SVivek Gautam #include <linux/of_address.h>
150b56e9a7SVivek Gautam #include <linux/phy/phy.h>
160b56e9a7SVivek Gautam #include <linux/platform_device.h>
170b56e9a7SVivek Gautam #include <linux/regmap.h>
180b56e9a7SVivek Gautam
190b56e9a7SVivek Gautam /*
200b56e9a7SVivek Gautam * The higher 16-bit of this register is used for write protection
210b56e9a7SVivek Gautam * only if BIT(x + 16) set to 1 the BIT(x) can be written.
220b56e9a7SVivek Gautam */
230b56e9a7SVivek Gautam #define HIWORD_UPDATE(val, mask, shift) \
240b56e9a7SVivek Gautam ((val) << (shift) | (mask) << ((shift) + 16))
250b56e9a7SVivek Gautam
260b56e9a7SVivek Gautam /* Register definition */
270b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON0 0x0
280b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON1 0x4
290b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON2 0x8
300b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON3 0xc
310b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON4 0x10
320b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON5 0x14
330b56e9a7SVivek Gautam #define GRF_EMMCPHY_CON6 0x18
340b56e9a7SVivek Gautam #define GRF_EMMCPHY_STATUS 0x20
350b56e9a7SVivek Gautam
360b56e9a7SVivek Gautam #define PHYCTRL_PDB_MASK 0x1
370b56e9a7SVivek Gautam #define PHYCTRL_PDB_SHIFT 0x0
380b56e9a7SVivek Gautam #define PHYCTRL_PDB_PWR_ON 0x1
390b56e9a7SVivek Gautam #define PHYCTRL_PDB_PWR_OFF 0x0
400b56e9a7SVivek Gautam #define PHYCTRL_ENDLL_MASK 0x1
410b56e9a7SVivek Gautam #define PHYCTRL_ENDLL_SHIFT 0x1
420b56e9a7SVivek Gautam #define PHYCTRL_ENDLL_ENABLE 0x1
430b56e9a7SVivek Gautam #define PHYCTRL_ENDLL_DISABLE 0x0
440b56e9a7SVivek Gautam #define PHYCTRL_CALDONE_MASK 0x1
450b56e9a7SVivek Gautam #define PHYCTRL_CALDONE_SHIFT 0x6
460b56e9a7SVivek Gautam #define PHYCTRL_CALDONE_DONE 0x1
470b56e9a7SVivek Gautam #define PHYCTRL_CALDONE_GOING 0x0
480b56e9a7SVivek Gautam #define PHYCTRL_DLLRDY_MASK 0x1
490b56e9a7SVivek Gautam #define PHYCTRL_DLLRDY_SHIFT 0x5
500b56e9a7SVivek Gautam #define PHYCTRL_DLLRDY_DONE 0x1
510b56e9a7SVivek Gautam #define PHYCTRL_DLLRDY_GOING 0x0
520b56e9a7SVivek Gautam #define PHYCTRL_FREQSEL_200M 0x0
530b56e9a7SVivek Gautam #define PHYCTRL_FREQSEL_50M 0x1
540b56e9a7SVivek Gautam #define PHYCTRL_FREQSEL_100M 0x2
550b56e9a7SVivek Gautam #define PHYCTRL_FREQSEL_150M 0x3
560b56e9a7SVivek Gautam #define PHYCTRL_FREQSEL_MASK 0x3
570b56e9a7SVivek Gautam #define PHYCTRL_FREQSEL_SHIFT 0xc
580b56e9a7SVivek Gautam #define PHYCTRL_DR_MASK 0x7
590b56e9a7SVivek Gautam #define PHYCTRL_DR_SHIFT 0x4
600b56e9a7SVivek Gautam #define PHYCTRL_DR_50OHM 0x0
610b56e9a7SVivek Gautam #define PHYCTRL_DR_33OHM 0x1
620b56e9a7SVivek Gautam #define PHYCTRL_DR_66OHM 0x2
630b56e9a7SVivek Gautam #define PHYCTRL_DR_100OHM 0x3
640b56e9a7SVivek Gautam #define PHYCTRL_DR_40OHM 0x4
650b56e9a7SVivek Gautam #define PHYCTRL_OTAPDLYENA 0x1
660b56e9a7SVivek Gautam #define PHYCTRL_OTAPDLYENA_MASK 0x1
670b56e9a7SVivek Gautam #define PHYCTRL_OTAPDLYENA_SHIFT 0xb
68a8cef928SChris Ruehl #define PHYCTRL_OTAPDLYSEL_DEFAULT 0x4
69a8cef928SChris Ruehl #define PHYCTRL_OTAPDLYSEL_MAXVALUE 0xf
700b56e9a7SVivek Gautam #define PHYCTRL_OTAPDLYSEL_MASK 0xf
710b56e9a7SVivek Gautam #define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
728b5c2b45SChris Ruehl #define PHYCTRL_REN_STRB_DISABLE 0x0
738b5c2b45SChris Ruehl #define PHYCTRL_REN_STRB_ENABLE 0x1
748b5c2b45SChris Ruehl #define PHYCTRL_REN_STRB_MASK 0x1
758b5c2b45SChris Ruehl #define PHYCTRL_REN_STRB_SHIFT 0x9
760b56e9a7SVivek Gautam
77a4781c2aSShawn Lin #define PHYCTRL_IS_CALDONE(x) \
78a4781c2aSShawn Lin ((((x) >> PHYCTRL_CALDONE_SHIFT) & \
79a4781c2aSShawn Lin PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
8095cc6e72SShawn Lin #define PHYCTRL_IS_DLLRDY(x) \
8195cc6e72SShawn Lin ((((x) >> PHYCTRL_DLLRDY_SHIFT) & \
8295cc6e72SShawn Lin PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
83a4781c2aSShawn Lin
840b56e9a7SVivek Gautam struct rockchip_emmc_phy {
850b56e9a7SVivek Gautam unsigned int reg_offset;
860b56e9a7SVivek Gautam struct regmap *reg_base;
870b56e9a7SVivek Gautam struct clk *emmcclk;
88043f42edSChristoph Muellner unsigned int drive_impedance;
898b5c2b45SChris Ruehl unsigned int enable_strobe_pulldown;
90a8cef928SChris Ruehl unsigned int output_tapdelay_select;
910b56e9a7SVivek Gautam };
920b56e9a7SVivek Gautam
rockchip_emmc_phy_power(struct phy * phy,bool on_off)930b56e9a7SVivek Gautam static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
940b56e9a7SVivek Gautam {
950b56e9a7SVivek Gautam struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
960b56e9a7SVivek Gautam unsigned int caldone;
970b56e9a7SVivek Gautam unsigned int dllrdy;
980b56e9a7SVivek Gautam unsigned int freqsel = PHYCTRL_FREQSEL_200M;
990b56e9a7SVivek Gautam unsigned long rate;
100a4781c2aSShawn Lin int ret;
1010b56e9a7SVivek Gautam
1020b56e9a7SVivek Gautam /*
1030b56e9a7SVivek Gautam * Keep phyctrl_pdb and phyctrl_endll low to allow
1040b56e9a7SVivek Gautam * initialization of CALIO state M/C DFFs
1050b56e9a7SVivek Gautam */
1060b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
1070b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON6,
1080b56e9a7SVivek Gautam HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
1090b56e9a7SVivek Gautam PHYCTRL_PDB_MASK,
1100b56e9a7SVivek Gautam PHYCTRL_PDB_SHIFT));
1110b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
1120b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON6,
1130b56e9a7SVivek Gautam HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
1140b56e9a7SVivek Gautam PHYCTRL_ENDLL_MASK,
1150b56e9a7SVivek Gautam PHYCTRL_ENDLL_SHIFT));
1160b56e9a7SVivek Gautam
1170b56e9a7SVivek Gautam /* Already finish power_off above */
1180b56e9a7SVivek Gautam if (on_off == PHYCTRL_PDB_PWR_OFF)
1190b56e9a7SVivek Gautam return 0;
1200b56e9a7SVivek Gautam
1210b56e9a7SVivek Gautam rate = clk_get_rate(rk_phy->emmcclk);
1220b56e9a7SVivek Gautam
1230b56e9a7SVivek Gautam if (rate != 0) {
1240b56e9a7SVivek Gautam unsigned long ideal_rate;
1250b56e9a7SVivek Gautam unsigned long diff;
1260b56e9a7SVivek Gautam
1270b56e9a7SVivek Gautam switch (rate) {
1280b56e9a7SVivek Gautam case 1 ... 74999999:
1290b56e9a7SVivek Gautam ideal_rate = 50000000;
1300b56e9a7SVivek Gautam freqsel = PHYCTRL_FREQSEL_50M;
1310b56e9a7SVivek Gautam break;
1320b56e9a7SVivek Gautam case 75000000 ... 124999999:
1330b56e9a7SVivek Gautam ideal_rate = 100000000;
1340b56e9a7SVivek Gautam freqsel = PHYCTRL_FREQSEL_100M;
1350b56e9a7SVivek Gautam break;
1360b56e9a7SVivek Gautam case 125000000 ... 174999999:
1370b56e9a7SVivek Gautam ideal_rate = 150000000;
1380b56e9a7SVivek Gautam freqsel = PHYCTRL_FREQSEL_150M;
1390b56e9a7SVivek Gautam break;
1400b56e9a7SVivek Gautam default:
1410b56e9a7SVivek Gautam ideal_rate = 200000000;
1420b56e9a7SVivek Gautam break;
1430b56e9a7SVivek Gautam }
1440b56e9a7SVivek Gautam
1450b56e9a7SVivek Gautam diff = (rate > ideal_rate) ?
1460b56e9a7SVivek Gautam rate - ideal_rate : ideal_rate - rate;
1470b56e9a7SVivek Gautam
1480b56e9a7SVivek Gautam /*
1490b56e9a7SVivek Gautam * In order for tuning delays to be accurate we need to be
1500b56e9a7SVivek Gautam * pretty spot on for the DLL range, so warn if we're too
1510b56e9a7SVivek Gautam * far off. Also warn if we're above the 200 MHz max. Don't
1520b56e9a7SVivek Gautam * warn for really slow rates since we won't be tuning then.
1530b56e9a7SVivek Gautam */
1540b56e9a7SVivek Gautam if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
1550b56e9a7SVivek Gautam dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
1560b56e9a7SVivek Gautam }
1570b56e9a7SVivek Gautam
1580b56e9a7SVivek Gautam /*
1590b56e9a7SVivek Gautam * According to the user manual, calpad calibration
1600b56e9a7SVivek Gautam * cycle takes more than 2us without the minimal recommended
1610b56e9a7SVivek Gautam * value, so we may need a little margin here
1620b56e9a7SVivek Gautam */
1630b56e9a7SVivek Gautam udelay(3);
1640b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
1650b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON6,
1660b56e9a7SVivek Gautam HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
1670b56e9a7SVivek Gautam PHYCTRL_PDB_MASK,
1680b56e9a7SVivek Gautam PHYCTRL_PDB_SHIFT));
1690b56e9a7SVivek Gautam
1700b56e9a7SVivek Gautam /*
171a4781c2aSShawn Lin * According to the user manual, it asks driver to wait 5us for
172a4781c2aSShawn Lin * calpad busy trimming. However it is documented that this value is
173a4781c2aSShawn Lin * PVT(A.K.A process,voltage and temperature) relevant, so some
174a4781c2aSShawn Lin * failure cases are found which indicates we should be more tolerant
175a4781c2aSShawn Lin * to calpad busy trimming.
1760b56e9a7SVivek Gautam */
177a4781c2aSShawn Lin ret = regmap_read_poll_timeout(rk_phy->reg_base,
1780b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
179a4781c2aSShawn Lin caldone, PHYCTRL_IS_CALDONE(caldone),
180a4781c2aSShawn Lin 0, 50);
181a4781c2aSShawn Lin if (ret) {
182a4781c2aSShawn Lin pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
183a4781c2aSShawn Lin return ret;
1840b56e9a7SVivek Gautam }
1850b56e9a7SVivek Gautam
1860b56e9a7SVivek Gautam /* Set the frequency of the DLL operation */
1870b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
1880b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON0,
1890b56e9a7SVivek Gautam HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
1900b56e9a7SVivek Gautam PHYCTRL_FREQSEL_SHIFT));
1910b56e9a7SVivek Gautam
1920b56e9a7SVivek Gautam /* Turn on the DLL */
1930b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
1940b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON6,
1950b56e9a7SVivek Gautam HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
1960b56e9a7SVivek Gautam PHYCTRL_ENDLL_MASK,
1970b56e9a7SVivek Gautam PHYCTRL_ENDLL_SHIFT));
1980b56e9a7SVivek Gautam
1990b56e9a7SVivek Gautam /*
2000b56e9a7SVivek Gautam * We turned on the DLL even though the rate was 0 because we the
2010b56e9a7SVivek Gautam * clock might be turned on later. ...but we can't wait for the DLL
2020b56e9a7SVivek Gautam * to lock when the rate is 0 because it will never lock with no
2030b56e9a7SVivek Gautam * input clock.
2040b56e9a7SVivek Gautam *
2050b56e9a7SVivek Gautam * Technically we should be checking the lock later when the clock
2060b56e9a7SVivek Gautam * is turned on, but for now we won't.
2070b56e9a7SVivek Gautam */
2080b56e9a7SVivek Gautam if (rate == 0)
2090b56e9a7SVivek Gautam return 0;
2100b56e9a7SVivek Gautam
2110b56e9a7SVivek Gautam /*
2120b56e9a7SVivek Gautam * After enabling analog DLL circuits docs say that we need 10.2 us if
2130b56e9a7SVivek Gautam * our source clock is at 50 MHz and that lock time scales linearly
2140b56e9a7SVivek Gautam * with clock speed. If we are powering on the PHY and the card clock
2150b56e9a7SVivek Gautam * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
2160b56e9a7SVivek Gautam * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
2170b56e9a7SVivek Gautam * Hopefully we won't be running at 100 kHz, but we should still make
2180b56e9a7SVivek Gautam * sure we wait long enough.
2190b56e9a7SVivek Gautam *
2200b56e9a7SVivek Gautam * NOTE: There appear to be corner cases where the DLL seems to take
2210b56e9a7SVivek Gautam * extra long to lock for reasons that aren't understood. In some
2220b56e9a7SVivek Gautam * extreme cases we've seen it take up to over 10ms (!). We'll be
22395cc6e72SShawn Lin * generous and give it 50ms.
2240b56e9a7SVivek Gautam */
22595cc6e72SShawn Lin ret = regmap_read_poll_timeout(rk_phy->reg_base,
2260b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
22795cc6e72SShawn Lin dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
22895cc6e72SShawn Lin 0, 50 * USEC_PER_MSEC);
22995cc6e72SShawn Lin if (ret) {
23095cc6e72SShawn Lin pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret);
23195cc6e72SShawn Lin return ret;
2320b56e9a7SVivek Gautam }
2330b56e9a7SVivek Gautam
2340b56e9a7SVivek Gautam return 0;
2350b56e9a7SVivek Gautam }
2360b56e9a7SVivek Gautam
rockchip_emmc_phy_init(struct phy * phy)2370b56e9a7SVivek Gautam static int rockchip_emmc_phy_init(struct phy *phy)
2380b56e9a7SVivek Gautam {
2390b56e9a7SVivek Gautam struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
2400b56e9a7SVivek Gautam int ret = 0;
2410b56e9a7SVivek Gautam
2420b56e9a7SVivek Gautam /*
2430b56e9a7SVivek Gautam * We purposely get the clock here and not in probe to avoid the
2440b56e9a7SVivek Gautam * circular dependency problem. We expect:
2450b56e9a7SVivek Gautam * - PHY driver to probe
2460b56e9a7SVivek Gautam * - SDHCI driver to start probe
2470b56e9a7SVivek Gautam * - SDHCI driver to register it's clock
2480b56e9a7SVivek Gautam * - SDHCI driver to get the PHY
2490b56e9a7SVivek Gautam * - SDHCI driver to init the PHY
2500b56e9a7SVivek Gautam *
25139961bd6SChris Ruehl * The clock is optional, using clk_get_optional() to get the clock
25239961bd6SChris Ruehl * and do error processing if the return value != NULL
2530b56e9a7SVivek Gautam *
2540b56e9a7SVivek Gautam * NOTE: we don't do anything special for EPROBE_DEFER here. Given the
2550b56e9a7SVivek Gautam * above expected use case, EPROBE_DEFER isn't sensible to expect, so
2560b56e9a7SVivek Gautam * it's just like any other error.
2570b56e9a7SVivek Gautam */
25839961bd6SChris Ruehl rk_phy->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
2590b56e9a7SVivek Gautam if (IS_ERR(rk_phy->emmcclk)) {
26039961bd6SChris Ruehl ret = PTR_ERR(rk_phy->emmcclk);
26139961bd6SChris Ruehl dev_err(&phy->dev, "Error getting emmcclk: %d\n", ret);
2620b56e9a7SVivek Gautam rk_phy->emmcclk = NULL;
2630b56e9a7SVivek Gautam }
2640b56e9a7SVivek Gautam
2650b56e9a7SVivek Gautam return ret;
2660b56e9a7SVivek Gautam }
2670b56e9a7SVivek Gautam
rockchip_emmc_phy_exit(struct phy * phy)2680b56e9a7SVivek Gautam static int rockchip_emmc_phy_exit(struct phy *phy)
2690b56e9a7SVivek Gautam {
2700b56e9a7SVivek Gautam struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
2710b56e9a7SVivek Gautam
2720b56e9a7SVivek Gautam clk_put(rk_phy->emmcclk);
2730b56e9a7SVivek Gautam
2740b56e9a7SVivek Gautam return 0;
2750b56e9a7SVivek Gautam }
2760b56e9a7SVivek Gautam
rockchip_emmc_phy_power_off(struct phy * phy)2770b56e9a7SVivek Gautam static int rockchip_emmc_phy_power_off(struct phy *phy)
2780b56e9a7SVivek Gautam {
2790b56e9a7SVivek Gautam /* Power down emmc phy analog blocks */
2800b56e9a7SVivek Gautam return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
2810b56e9a7SVivek Gautam }
2820b56e9a7SVivek Gautam
rockchip_emmc_phy_power_on(struct phy * phy)2830b56e9a7SVivek Gautam static int rockchip_emmc_phy_power_on(struct phy *phy)
2840b56e9a7SVivek Gautam {
2850b56e9a7SVivek Gautam struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
2860b56e9a7SVivek Gautam
287043f42edSChristoph Muellner /* Drive impedance: from DTS */
2880b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
2890b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON6,
290043f42edSChristoph Muellner HIWORD_UPDATE(rk_phy->drive_impedance,
2910b56e9a7SVivek Gautam PHYCTRL_DR_MASK,
2920b56e9a7SVivek Gautam PHYCTRL_DR_SHIFT));
2930b56e9a7SVivek Gautam
2940b56e9a7SVivek Gautam /* Output tap delay: enable */
2950b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
2960b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON0,
2970b56e9a7SVivek Gautam HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
2980b56e9a7SVivek Gautam PHYCTRL_OTAPDLYENA_MASK,
2990b56e9a7SVivek Gautam PHYCTRL_OTAPDLYENA_SHIFT));
3000b56e9a7SVivek Gautam
3010b56e9a7SVivek Gautam /* Output tap delay */
3020b56e9a7SVivek Gautam regmap_write(rk_phy->reg_base,
3030b56e9a7SVivek Gautam rk_phy->reg_offset + GRF_EMMCPHY_CON0,
304a8cef928SChris Ruehl HIWORD_UPDATE(rk_phy->output_tapdelay_select,
3050b56e9a7SVivek Gautam PHYCTRL_OTAPDLYSEL_MASK,
3060b56e9a7SVivek Gautam PHYCTRL_OTAPDLYSEL_SHIFT));
3070b56e9a7SVivek Gautam
3088b5c2b45SChris Ruehl /* Internal pull-down for strobe line */
3098b5c2b45SChris Ruehl regmap_write(rk_phy->reg_base,
3108b5c2b45SChris Ruehl rk_phy->reg_offset + GRF_EMMCPHY_CON2,
3118b5c2b45SChris Ruehl HIWORD_UPDATE(rk_phy->enable_strobe_pulldown,
3128b5c2b45SChris Ruehl PHYCTRL_REN_STRB_MASK,
3138b5c2b45SChris Ruehl PHYCTRL_REN_STRB_SHIFT));
3148b5c2b45SChris Ruehl
3150b56e9a7SVivek Gautam /* Power up emmc phy analog blocks */
3160b56e9a7SVivek Gautam return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
3170b56e9a7SVivek Gautam }
3180b56e9a7SVivek Gautam
3190b56e9a7SVivek Gautam static const struct phy_ops ops = {
3200b56e9a7SVivek Gautam .init = rockchip_emmc_phy_init,
3210b56e9a7SVivek Gautam .exit = rockchip_emmc_phy_exit,
3220b56e9a7SVivek Gautam .power_on = rockchip_emmc_phy_power_on,
3230b56e9a7SVivek Gautam .power_off = rockchip_emmc_phy_power_off,
3240b56e9a7SVivek Gautam .owner = THIS_MODULE,
3250b56e9a7SVivek Gautam };
3260b56e9a7SVivek Gautam
convert_drive_impedance_ohm(struct platform_device * pdev,u32 dr_ohm)327043f42edSChristoph Muellner static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm)
328043f42edSChristoph Muellner {
329043f42edSChristoph Muellner switch (dr_ohm) {
330043f42edSChristoph Muellner case 100:
331043f42edSChristoph Muellner return PHYCTRL_DR_100OHM;
332043f42edSChristoph Muellner case 66:
333043f42edSChristoph Muellner return PHYCTRL_DR_66OHM;
334043f42edSChristoph Muellner case 50:
335043f42edSChristoph Muellner return PHYCTRL_DR_50OHM;
336043f42edSChristoph Muellner case 40:
337043f42edSChristoph Muellner return PHYCTRL_DR_40OHM;
338043f42edSChristoph Muellner case 33:
339043f42edSChristoph Muellner return PHYCTRL_DR_33OHM;
340043f42edSChristoph Muellner }
341043f42edSChristoph Muellner
342043f42edSChristoph Muellner dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n",
343043f42edSChristoph Muellner dr_ohm);
344043f42edSChristoph Muellner return PHYCTRL_DR_50OHM;
345043f42edSChristoph Muellner }
346043f42edSChristoph Muellner
rockchip_emmc_phy_probe(struct platform_device * pdev)3470b56e9a7SVivek Gautam static int rockchip_emmc_phy_probe(struct platform_device *pdev)
3480b56e9a7SVivek Gautam {
3490b56e9a7SVivek Gautam struct device *dev = &pdev->dev;
3500b56e9a7SVivek Gautam struct rockchip_emmc_phy *rk_phy;
3510b56e9a7SVivek Gautam struct phy *generic_phy;
3520b56e9a7SVivek Gautam struct phy_provider *phy_provider;
3530b56e9a7SVivek Gautam struct regmap *grf;
3540b56e9a7SVivek Gautam unsigned int reg_offset;
355043f42edSChristoph Muellner u32 val;
3560b56e9a7SVivek Gautam
3570b56e9a7SVivek Gautam if (!dev->parent || !dev->parent->of_node)
3580b56e9a7SVivek Gautam return -ENODEV;
3590b56e9a7SVivek Gautam
3600b56e9a7SVivek Gautam grf = syscon_node_to_regmap(dev->parent->of_node);
3610b56e9a7SVivek Gautam if (IS_ERR(grf)) {
3620b56e9a7SVivek Gautam dev_err(dev, "Missing rockchip,grf property\n");
3630b56e9a7SVivek Gautam return PTR_ERR(grf);
3640b56e9a7SVivek Gautam }
3650b56e9a7SVivek Gautam
3660b56e9a7SVivek Gautam rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
3670b56e9a7SVivek Gautam if (!rk_phy)
3680b56e9a7SVivek Gautam return -ENOMEM;
3690b56e9a7SVivek Gautam
3700b56e9a7SVivek Gautam if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
371ac9ba7dcSRob Herring dev_err(dev, "missing reg property in node %pOFn\n",
372ac9ba7dcSRob Herring dev->of_node);
3730b56e9a7SVivek Gautam return -EINVAL;
3740b56e9a7SVivek Gautam }
3750b56e9a7SVivek Gautam
3760b56e9a7SVivek Gautam rk_phy->reg_offset = reg_offset;
3770b56e9a7SVivek Gautam rk_phy->reg_base = grf;
378043f42edSChristoph Muellner rk_phy->drive_impedance = PHYCTRL_DR_50OHM;
3798b5c2b45SChris Ruehl rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_DISABLE;
380a8cef928SChris Ruehl rk_phy->output_tapdelay_select = PHYCTRL_OTAPDLYSEL_DEFAULT;
381043f42edSChristoph Muellner
382043f42edSChristoph Muellner if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val))
383043f42edSChristoph Muellner rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val);
3840b56e9a7SVivek Gautam
385*c1883654SChris Ruehl if (of_property_read_bool(dev->of_node, "rockchip,enable-strobe-pulldown"))
3868b5c2b45SChris Ruehl rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_ENABLE;
3878b5c2b45SChris Ruehl
388*c1883654SChris Ruehl if (!of_property_read_u32(dev->of_node, "rockchip,output-tapdelay-select", &val)) {
389a8cef928SChris Ruehl if (val <= PHYCTRL_OTAPDLYSEL_MAXVALUE)
390a8cef928SChris Ruehl rk_phy->output_tapdelay_select = val;
391a8cef928SChris Ruehl else
392a8cef928SChris Ruehl dev_err(dev, "output-tapdelay-select exceeds limit, apply default\n");
393a8cef928SChris Ruehl }
394a8cef928SChris Ruehl
3950b56e9a7SVivek Gautam generic_phy = devm_phy_create(dev, dev->of_node, &ops);
3960b56e9a7SVivek Gautam if (IS_ERR(generic_phy)) {
3970b56e9a7SVivek Gautam dev_err(dev, "failed to create PHY\n");
3980b56e9a7SVivek Gautam return PTR_ERR(generic_phy);
3990b56e9a7SVivek Gautam }
4000b56e9a7SVivek Gautam
4010b56e9a7SVivek Gautam phy_set_drvdata(generic_phy, rk_phy);
4020b56e9a7SVivek Gautam phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
4030b56e9a7SVivek Gautam
4040b56e9a7SVivek Gautam return PTR_ERR_OR_ZERO(phy_provider);
4050b56e9a7SVivek Gautam }
4060b56e9a7SVivek Gautam
4070b56e9a7SVivek Gautam static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
4080b56e9a7SVivek Gautam { .compatible = "rockchip,rk3399-emmc-phy" },
4090b56e9a7SVivek Gautam {}
4100b56e9a7SVivek Gautam };
4110b56e9a7SVivek Gautam
4120b56e9a7SVivek Gautam MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
4130b56e9a7SVivek Gautam
4140b56e9a7SVivek Gautam static struct platform_driver rockchip_emmc_driver = {
4150b56e9a7SVivek Gautam .probe = rockchip_emmc_phy_probe,
4160b56e9a7SVivek Gautam .driver = {
4170b56e9a7SVivek Gautam .name = "rockchip-emmc-phy",
4180b56e9a7SVivek Gautam .of_match_table = rockchip_emmc_phy_dt_ids,
4190b56e9a7SVivek Gautam },
4200b56e9a7SVivek Gautam };
4210b56e9a7SVivek Gautam
4220b56e9a7SVivek Gautam module_platform_driver(rockchip_emmc_driver);
4230b56e9a7SVivek Gautam
4240b56e9a7SVivek Gautam MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
4250b56e9a7SVivek Gautam MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
4260b56e9a7SVivek Gautam MODULE_LICENSE("GPL v2");
427