xref: /linux/drivers/pinctrl/bcm/pinctrl-bcm2835.c (revision 6c8c1406) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4  *
5  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6  *
7  * This driver is inspired by:
8  * pinctrl-nomadik.c, please see original file for copyright information
9  * pinctrl-tegra.c, please see original file for copyright information
10  */
11 
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/types.h>
38 #include <dt-bindings/pinctrl/bcm2835.h>
39 
40 #define MODULE_NAME "pinctrl-bcm2835"
41 #define BCM2835_NUM_GPIOS 54
42 #define BCM2711_NUM_GPIOS 58
43 #define BCM2835_NUM_BANKS 2
44 #define BCM2835_NUM_IRQS  3
45 
46 /* GPIO register offsets */
47 #define GPFSEL0		0x0	/* Function Select */
48 #define GPSET0		0x1c	/* Pin Output Set */
49 #define GPCLR0		0x28	/* Pin Output Clear */
50 #define GPLEV0		0x34	/* Pin Level */
51 #define GPEDS0		0x40	/* Pin Event Detect Status */
52 #define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
53 #define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
54 #define GPHEN0		0x64	/* Pin High Detect Enable */
55 #define GPLEN0		0x70	/* Pin Low Detect Enable */
56 #define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
57 #define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
58 #define GPPUD		0x94	/* Pin Pull-up/down Enable */
59 #define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
61 
62 #define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
63 #define FSEL_SHIFT(p)		(((p) % 10) * 3)
64 #define GPIO_REG_OFFSET(p)	((p) / 32)
65 #define GPIO_REG_SHIFT(p)	((p) % 32)
66 
67 #define PUD_2711_MASK		0x3
68 #define PUD_2711_REG_OFFSET(p)	((p) / 16)
69 #define PUD_2711_REG_SHIFT(p)	(((p) % 16) * 2)
70 
71 /* argument: bcm2835_pinconf_pull */
72 #define BCM2835_PINCONF_PARAM_PULL	(PIN_CONFIG_END + 1)
73 
74 #define BCM2711_PULL_NONE	0x0
75 #define BCM2711_PULL_UP		0x1
76 #define BCM2711_PULL_DOWN	0x2
77 
78 struct bcm2835_pinctrl {
79 	struct device *dev;
80 	void __iomem *base;
81 	int *wake_irq;
82 
83 	/* note: locking assumes each bank will have its own unsigned long */
84 	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
85 	unsigned int irq_type[BCM2711_NUM_GPIOS];
86 
87 	struct pinctrl_dev *pctl_dev;
88 	struct gpio_chip gpio_chip;
89 	struct pinctrl_desc pctl_desc;
90 	struct pinctrl_gpio_range gpio_range;
91 
92 	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
93 };
94 
95 /* pins are just named GPIO0..GPIO53 */
96 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
97 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
98 	BCM2835_GPIO_PIN(0),
99 	BCM2835_GPIO_PIN(1),
100 	BCM2835_GPIO_PIN(2),
101 	BCM2835_GPIO_PIN(3),
102 	BCM2835_GPIO_PIN(4),
103 	BCM2835_GPIO_PIN(5),
104 	BCM2835_GPIO_PIN(6),
105 	BCM2835_GPIO_PIN(7),
106 	BCM2835_GPIO_PIN(8),
107 	BCM2835_GPIO_PIN(9),
108 	BCM2835_GPIO_PIN(10),
109 	BCM2835_GPIO_PIN(11),
110 	BCM2835_GPIO_PIN(12),
111 	BCM2835_GPIO_PIN(13),
112 	BCM2835_GPIO_PIN(14),
113 	BCM2835_GPIO_PIN(15),
114 	BCM2835_GPIO_PIN(16),
115 	BCM2835_GPIO_PIN(17),
116 	BCM2835_GPIO_PIN(18),
117 	BCM2835_GPIO_PIN(19),
118 	BCM2835_GPIO_PIN(20),
119 	BCM2835_GPIO_PIN(21),
120 	BCM2835_GPIO_PIN(22),
121 	BCM2835_GPIO_PIN(23),
122 	BCM2835_GPIO_PIN(24),
123 	BCM2835_GPIO_PIN(25),
124 	BCM2835_GPIO_PIN(26),
125 	BCM2835_GPIO_PIN(27),
126 	BCM2835_GPIO_PIN(28),
127 	BCM2835_GPIO_PIN(29),
128 	BCM2835_GPIO_PIN(30),
129 	BCM2835_GPIO_PIN(31),
130 	BCM2835_GPIO_PIN(32),
131 	BCM2835_GPIO_PIN(33),
132 	BCM2835_GPIO_PIN(34),
133 	BCM2835_GPIO_PIN(35),
134 	BCM2835_GPIO_PIN(36),
135 	BCM2835_GPIO_PIN(37),
136 	BCM2835_GPIO_PIN(38),
137 	BCM2835_GPIO_PIN(39),
138 	BCM2835_GPIO_PIN(40),
139 	BCM2835_GPIO_PIN(41),
140 	BCM2835_GPIO_PIN(42),
141 	BCM2835_GPIO_PIN(43),
142 	BCM2835_GPIO_PIN(44),
143 	BCM2835_GPIO_PIN(45),
144 	BCM2835_GPIO_PIN(46),
145 	BCM2835_GPIO_PIN(47),
146 	BCM2835_GPIO_PIN(48),
147 	BCM2835_GPIO_PIN(49),
148 	BCM2835_GPIO_PIN(50),
149 	BCM2835_GPIO_PIN(51),
150 	BCM2835_GPIO_PIN(52),
151 	BCM2835_GPIO_PIN(53),
152 	BCM2835_GPIO_PIN(54),
153 	BCM2835_GPIO_PIN(55),
154 	BCM2835_GPIO_PIN(56),
155 	BCM2835_GPIO_PIN(57),
156 };
157 
158 /* one pin per group */
159 static const char * const bcm2835_gpio_groups[] = {
160 	"gpio0",
161 	"gpio1",
162 	"gpio2",
163 	"gpio3",
164 	"gpio4",
165 	"gpio5",
166 	"gpio6",
167 	"gpio7",
168 	"gpio8",
169 	"gpio9",
170 	"gpio10",
171 	"gpio11",
172 	"gpio12",
173 	"gpio13",
174 	"gpio14",
175 	"gpio15",
176 	"gpio16",
177 	"gpio17",
178 	"gpio18",
179 	"gpio19",
180 	"gpio20",
181 	"gpio21",
182 	"gpio22",
183 	"gpio23",
184 	"gpio24",
185 	"gpio25",
186 	"gpio26",
187 	"gpio27",
188 	"gpio28",
189 	"gpio29",
190 	"gpio30",
191 	"gpio31",
192 	"gpio32",
193 	"gpio33",
194 	"gpio34",
195 	"gpio35",
196 	"gpio36",
197 	"gpio37",
198 	"gpio38",
199 	"gpio39",
200 	"gpio40",
201 	"gpio41",
202 	"gpio42",
203 	"gpio43",
204 	"gpio44",
205 	"gpio45",
206 	"gpio46",
207 	"gpio47",
208 	"gpio48",
209 	"gpio49",
210 	"gpio50",
211 	"gpio51",
212 	"gpio52",
213 	"gpio53",
214 	"gpio54",
215 	"gpio55",
216 	"gpio56",
217 	"gpio57",
218 };
219 
220 enum bcm2835_fsel {
221 	BCM2835_FSEL_COUNT = 8,
222 	BCM2835_FSEL_MASK = 0x7,
223 };
224 
225 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
226 	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
227 	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
228 	[BCM2835_FSEL_ALT0] = "alt0",
229 	[BCM2835_FSEL_ALT1] = "alt1",
230 	[BCM2835_FSEL_ALT2] = "alt2",
231 	[BCM2835_FSEL_ALT3] = "alt3",
232 	[BCM2835_FSEL_ALT4] = "alt4",
233 	[BCM2835_FSEL_ALT5] = "alt5",
234 };
235 
236 static const char * const irq_type_names[] = {
237 	[IRQ_TYPE_NONE] = "none",
238 	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
239 	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
240 	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
241 	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
242 	[IRQ_TYPE_LEVEL_LOW] = "level-low",
243 };
244 
245 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
246 {
247 	return readl(pc->base + reg);
248 }
249 
250 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
251 		u32 val)
252 {
253 	writel(val, pc->base + reg);
254 }
255 
256 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
257 		unsigned bit)
258 {
259 	reg += GPIO_REG_OFFSET(bit) * 4;
260 	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
261 }
262 
263 /* note NOT a read/modify/write cycle */
264 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
265 		unsigned reg, unsigned bit)
266 {
267 	reg += GPIO_REG_OFFSET(bit) * 4;
268 	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
269 }
270 
271 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
272 		struct bcm2835_pinctrl *pc, unsigned pin)
273 {
274 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
275 	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
276 
277 	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
278 			bcm2835_functions[status]);
279 
280 	return status;
281 }
282 
283 static inline void bcm2835_pinctrl_fsel_set(
284 		struct bcm2835_pinctrl *pc, unsigned pin,
285 		enum bcm2835_fsel fsel)
286 {
287 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
288 	enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
289 
290 	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
291 			bcm2835_functions[cur]);
292 
293 	if (cur == fsel)
294 		return;
295 
296 	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
297 		/* always transition through GPIO_IN */
298 		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
299 		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
300 
301 		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
302 				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
303 		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
304 	}
305 
306 	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
307 	val |= fsel << FSEL_SHIFT(pin);
308 
309 	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
310 			bcm2835_functions[fsel]);
311 	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
312 }
313 
314 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
315 {
316 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
317 
318 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
319 	return 0;
320 }
321 
322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
323 {
324 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
325 
326 	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
327 }
328 
329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
330 {
331 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
332 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
333 
334 	/* Alternative function doesn't clearly provide a direction */
335 	if (fsel > BCM2835_FSEL_GPIO_OUT)
336 		return -EINVAL;
337 
338 	if (fsel == BCM2835_FSEL_GPIO_IN)
339 		return GPIO_LINE_DIRECTION_IN;
340 
341 	return GPIO_LINE_DIRECTION_OUT;
342 }
343 
344 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
345 {
346 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
347 
348 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
349 }
350 
351 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
352 		unsigned offset, int value)
353 {
354 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
355 
356 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
357 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
358 	return 0;
359 }
360 
361 static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
362 					   struct device_node *np)
363 {
364 	struct pinctrl_dev *pctldev = of_pinctrl_get(np);
365 
366 	of_node_put(np);
367 
368 	if (!pctldev)
369 		return 0;
370 
371 	gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
372 			       gc->ngpio);
373 
374 	return 0;
375 }
376 
377 static const struct gpio_chip bcm2835_gpio_chip = {
378 	.label = MODULE_NAME,
379 	.owner = THIS_MODULE,
380 	.request = gpiochip_generic_request,
381 	.free = gpiochip_generic_free,
382 	.direction_input = bcm2835_gpio_direction_input,
383 	.direction_output = bcm2835_gpio_direction_output,
384 	.get_direction = bcm2835_gpio_get_direction,
385 	.get = bcm2835_gpio_get,
386 	.set = bcm2835_gpio_set,
387 	.set_config = gpiochip_generic_config,
388 	.base = -1,
389 	.ngpio = BCM2835_NUM_GPIOS,
390 	.can_sleep = false,
391 	.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
392 };
393 
394 static const struct gpio_chip bcm2711_gpio_chip = {
395 	.label = "pinctrl-bcm2711",
396 	.owner = THIS_MODULE,
397 	.request = gpiochip_generic_request,
398 	.free = gpiochip_generic_free,
399 	.direction_input = bcm2835_gpio_direction_input,
400 	.direction_output = bcm2835_gpio_direction_output,
401 	.get_direction = bcm2835_gpio_get_direction,
402 	.get = bcm2835_gpio_get,
403 	.set = bcm2835_gpio_set,
404 	.set_config = gpiochip_generic_config,
405 	.base = -1,
406 	.ngpio = BCM2711_NUM_GPIOS,
407 	.can_sleep = false,
408 	.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
409 };
410 
411 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
412 					 unsigned int bank, u32 mask)
413 {
414 	unsigned long events;
415 	unsigned offset;
416 	unsigned gpio;
417 
418 	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
419 	events &= mask;
420 	events &= pc->enabled_irq_map[bank];
421 	for_each_set_bit(offset, &events, 32) {
422 		gpio = (32 * bank) + offset;
423 		generic_handle_domain_irq(pc->gpio_chip.irq.domain,
424 					  gpio);
425 	}
426 }
427 
428 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
429 {
430 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
431 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
432 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
433 	int irq = irq_desc_get_irq(desc);
434 	int group = 0;
435 	int i;
436 
437 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
438 		if (chip->irq.parents[i] == irq) {
439 			group = i;
440 			break;
441 		}
442 	}
443 	/* This should not happen, every IRQ has a bank */
444 	BUG_ON(i == BCM2835_NUM_IRQS);
445 
446 	chained_irq_enter(host_chip, desc);
447 
448 	switch (group) {
449 	case 0: /* IRQ0 covers GPIOs 0-27 */
450 		bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
451 		break;
452 	case 1: /* IRQ1 covers GPIOs 28-45 */
453 		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
454 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
455 		break;
456 	case 2: /* IRQ2 covers GPIOs 46-57 */
457 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
458 		break;
459 	}
460 
461 	chained_irq_exit(host_chip, desc);
462 }
463 
464 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
465 {
466 	return IRQ_HANDLED;
467 }
468 
469 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
470 	unsigned reg, unsigned offset, bool enable)
471 {
472 	u32 value;
473 	reg += GPIO_REG_OFFSET(offset) * 4;
474 	value = bcm2835_gpio_rd(pc, reg);
475 	if (enable)
476 		value |= BIT(GPIO_REG_SHIFT(offset));
477 	else
478 		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
479 	bcm2835_gpio_wr(pc, reg, value);
480 }
481 
482 /* fast path for IRQ handler */
483 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
484 	unsigned offset, bool enable)
485 {
486 	switch (pc->irq_type[offset]) {
487 	case IRQ_TYPE_EDGE_RISING:
488 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
489 		break;
490 
491 	case IRQ_TYPE_EDGE_FALLING:
492 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
493 		break;
494 
495 	case IRQ_TYPE_EDGE_BOTH:
496 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
497 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
498 		break;
499 
500 	case IRQ_TYPE_LEVEL_HIGH:
501 		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
502 		break;
503 
504 	case IRQ_TYPE_LEVEL_LOW:
505 		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
506 		break;
507 	}
508 }
509 
510 static void bcm2835_gpio_irq_unmask(struct irq_data *data)
511 {
512 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
513 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
514 	unsigned gpio = irqd_to_hwirq(data);
515 	unsigned offset = GPIO_REG_SHIFT(gpio);
516 	unsigned bank = GPIO_REG_OFFSET(gpio);
517 	unsigned long flags;
518 
519 	gpiochip_enable_irq(chip, gpio);
520 
521 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
522 	set_bit(offset, &pc->enabled_irq_map[bank]);
523 	bcm2835_gpio_irq_config(pc, gpio, true);
524 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
525 }
526 
527 static void bcm2835_gpio_irq_mask(struct irq_data *data)
528 {
529 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
530 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
531 	unsigned gpio = irqd_to_hwirq(data);
532 	unsigned offset = GPIO_REG_SHIFT(gpio);
533 	unsigned bank = GPIO_REG_OFFSET(gpio);
534 	unsigned long flags;
535 
536 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
537 	bcm2835_gpio_irq_config(pc, gpio, false);
538 	/* Clear events that were latched prior to clearing event sources */
539 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
540 	clear_bit(offset, &pc->enabled_irq_map[bank]);
541 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
542 
543 	gpiochip_disable_irq(chip, gpio);
544 }
545 
546 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
547 	unsigned offset, unsigned int type)
548 {
549 	switch (type) {
550 	case IRQ_TYPE_NONE:
551 	case IRQ_TYPE_EDGE_RISING:
552 	case IRQ_TYPE_EDGE_FALLING:
553 	case IRQ_TYPE_EDGE_BOTH:
554 	case IRQ_TYPE_LEVEL_HIGH:
555 	case IRQ_TYPE_LEVEL_LOW:
556 		pc->irq_type[offset] = type;
557 		break;
558 
559 	default:
560 		return -EINVAL;
561 	}
562 	return 0;
563 }
564 
565 /* slower path for reconfiguring IRQ type */
566 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
567 	unsigned offset, unsigned int type)
568 {
569 	switch (type) {
570 	case IRQ_TYPE_NONE:
571 		if (pc->irq_type[offset] != type) {
572 			bcm2835_gpio_irq_config(pc, offset, false);
573 			pc->irq_type[offset] = type;
574 		}
575 		break;
576 
577 	case IRQ_TYPE_EDGE_RISING:
578 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
579 			/* RISING already enabled, disable FALLING */
580 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
581 			bcm2835_gpio_irq_config(pc, offset, false);
582 			pc->irq_type[offset] = type;
583 		} else if (pc->irq_type[offset] != type) {
584 			bcm2835_gpio_irq_config(pc, offset, false);
585 			pc->irq_type[offset] = type;
586 			bcm2835_gpio_irq_config(pc, offset, true);
587 		}
588 		break;
589 
590 	case IRQ_TYPE_EDGE_FALLING:
591 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
592 			/* FALLING already enabled, disable RISING */
593 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
594 			bcm2835_gpio_irq_config(pc, offset, false);
595 			pc->irq_type[offset] = type;
596 		} else if (pc->irq_type[offset] != type) {
597 			bcm2835_gpio_irq_config(pc, offset, false);
598 			pc->irq_type[offset] = type;
599 			bcm2835_gpio_irq_config(pc, offset, true);
600 		}
601 		break;
602 
603 	case IRQ_TYPE_EDGE_BOTH:
604 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
605 			/* RISING already enabled, enable FALLING too */
606 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
607 			bcm2835_gpio_irq_config(pc, offset, true);
608 			pc->irq_type[offset] = type;
609 		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
610 			/* FALLING already enabled, enable RISING too */
611 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
612 			bcm2835_gpio_irq_config(pc, offset, true);
613 			pc->irq_type[offset] = type;
614 		} else if (pc->irq_type[offset] != type) {
615 			bcm2835_gpio_irq_config(pc, offset, false);
616 			pc->irq_type[offset] = type;
617 			bcm2835_gpio_irq_config(pc, offset, true);
618 		}
619 		break;
620 
621 	case IRQ_TYPE_LEVEL_HIGH:
622 	case IRQ_TYPE_LEVEL_LOW:
623 		if (pc->irq_type[offset] != type) {
624 			bcm2835_gpio_irq_config(pc, offset, false);
625 			pc->irq_type[offset] = type;
626 			bcm2835_gpio_irq_config(pc, offset, true);
627 		}
628 		break;
629 
630 	default:
631 		return -EINVAL;
632 	}
633 	return 0;
634 }
635 
636 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
637 {
638 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
639 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
640 	unsigned gpio = irqd_to_hwirq(data);
641 	unsigned offset = GPIO_REG_SHIFT(gpio);
642 	unsigned bank = GPIO_REG_OFFSET(gpio);
643 	unsigned long flags;
644 	int ret;
645 
646 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
647 
648 	if (test_bit(offset, &pc->enabled_irq_map[bank]))
649 		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
650 	else
651 		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
652 
653 	if (type & IRQ_TYPE_EDGE_BOTH)
654 		irq_set_handler_locked(data, handle_edge_irq);
655 	else
656 		irq_set_handler_locked(data, handle_level_irq);
657 
658 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
659 
660 	return ret;
661 }
662 
663 static void bcm2835_gpio_irq_ack(struct irq_data *data)
664 {
665 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
666 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
667 	unsigned gpio = irqd_to_hwirq(data);
668 
669 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
670 }
671 
672 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
673 {
674 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
675 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
676 	unsigned gpio = irqd_to_hwirq(data);
677 	unsigned int irqgroup;
678 	int ret = -EINVAL;
679 
680 	if (!pc->wake_irq)
681 		return ret;
682 
683 	if (gpio <= 27)
684 		irqgroup = 0;
685 	else if (gpio >= 28 && gpio <= 45)
686 		irqgroup = 1;
687 	else if (gpio >= 46 && gpio <= 57)
688 		irqgroup = 2;
689 	else
690 		return ret;
691 
692 	if (on)
693 		ret = enable_irq_wake(pc->wake_irq[irqgroup]);
694 	else
695 		ret = disable_irq_wake(pc->wake_irq[irqgroup]);
696 
697 	return ret;
698 }
699 
700 static const struct irq_chip bcm2835_gpio_irq_chip = {
701 	.name = MODULE_NAME,
702 	.irq_set_type = bcm2835_gpio_irq_set_type,
703 	.irq_ack = bcm2835_gpio_irq_ack,
704 	.irq_mask = bcm2835_gpio_irq_mask,
705 	.irq_unmask = bcm2835_gpio_irq_unmask,
706 	.irq_set_wake = bcm2835_gpio_irq_set_wake,
707 	.flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
708 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
709 };
710 
711 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
712 {
713 	return BCM2835_NUM_GPIOS;
714 }
715 
716 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
717 		unsigned selector)
718 {
719 	return bcm2835_gpio_groups[selector];
720 }
721 
722 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
723 		unsigned selector,
724 		const unsigned **pins,
725 		unsigned *num_pins)
726 {
727 	*pins = &bcm2835_gpio_pins[selector].number;
728 	*num_pins = 1;
729 
730 	return 0;
731 }
732 
733 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
734 		struct seq_file *s,
735 		unsigned offset)
736 {
737 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
738 	struct gpio_chip *chip = &pc->gpio_chip;
739 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
740 	const char *fname = bcm2835_functions[fsel];
741 	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
742 	int irq = irq_find_mapping(chip->irq.domain, offset);
743 
744 	seq_printf(s, "function %s in %s; irq %d (%s)",
745 		fname, value ? "hi" : "lo",
746 		irq, irq_type_names[pc->irq_type[offset]]);
747 }
748 
749 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
750 		struct pinctrl_map *maps, unsigned num_maps)
751 {
752 	int i;
753 
754 	for (i = 0; i < num_maps; i++)
755 		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
756 			kfree(maps[i].data.configs.configs);
757 
758 	kfree(maps);
759 }
760 
761 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
762 		struct device_node *np, u32 pin, u32 fnum,
763 		struct pinctrl_map **maps)
764 {
765 	struct pinctrl_map *map = *maps;
766 
767 	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
768 		dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
769 		return -EINVAL;
770 	}
771 
772 	map->type = PIN_MAP_TYPE_MUX_GROUP;
773 	map->data.mux.group = bcm2835_gpio_groups[pin];
774 	map->data.mux.function = bcm2835_functions[fnum];
775 	(*maps)++;
776 
777 	return 0;
778 }
779 
780 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
781 		struct device_node *np, u32 pin, u32 pull,
782 		struct pinctrl_map **maps)
783 {
784 	struct pinctrl_map *map = *maps;
785 	unsigned long *configs;
786 
787 	if (pull > 2) {
788 		dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
789 		return -EINVAL;
790 	}
791 
792 	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
793 	if (!configs)
794 		return -ENOMEM;
795 	configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
796 
797 	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
798 	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
799 	map->data.configs.configs = configs;
800 	map->data.configs.num_configs = 1;
801 	(*maps)++;
802 
803 	return 0;
804 }
805 
806 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
807 		struct device_node *np,
808 		struct pinctrl_map **map, unsigned int *num_maps)
809 {
810 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
811 	struct property *pins, *funcs, *pulls;
812 	int num_pins, num_funcs, num_pulls, maps_per_pin;
813 	struct pinctrl_map *maps, *cur_map;
814 	int i, err;
815 	u32 pin, func, pull;
816 
817 	/* Check for generic binding in this node */
818 	err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
819 	if (err || *num_maps)
820 		return err;
821 
822 	/* Generic binding did not find anything continue with legacy parse */
823 	pins = of_find_property(np, "brcm,pins", NULL);
824 	if (!pins) {
825 		dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
826 		return -EINVAL;
827 	}
828 
829 	funcs = of_find_property(np, "brcm,function", NULL);
830 	pulls = of_find_property(np, "brcm,pull", NULL);
831 
832 	if (!funcs && !pulls) {
833 		dev_err(pc->dev,
834 			"%pOF: neither brcm,function nor brcm,pull specified\n",
835 			np);
836 		return -EINVAL;
837 	}
838 
839 	num_pins = pins->length / 4;
840 	num_funcs = funcs ? (funcs->length / 4) : 0;
841 	num_pulls = pulls ? (pulls->length / 4) : 0;
842 
843 	if (num_funcs > 1 && num_funcs != num_pins) {
844 		dev_err(pc->dev,
845 			"%pOF: brcm,function must have 1 or %d entries\n",
846 			np, num_pins);
847 		return -EINVAL;
848 	}
849 
850 	if (num_pulls > 1 && num_pulls != num_pins) {
851 		dev_err(pc->dev,
852 			"%pOF: brcm,pull must have 1 or %d entries\n",
853 			np, num_pins);
854 		return -EINVAL;
855 	}
856 
857 	maps_per_pin = 0;
858 	if (num_funcs)
859 		maps_per_pin++;
860 	if (num_pulls)
861 		maps_per_pin++;
862 	cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
863 				 GFP_KERNEL);
864 	if (!maps)
865 		return -ENOMEM;
866 
867 	for (i = 0; i < num_pins; i++) {
868 		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
869 		if (err)
870 			goto out;
871 		if (pin >= pc->pctl_desc.npins) {
872 			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
873 				np, pin);
874 			err = -EINVAL;
875 			goto out;
876 		}
877 
878 		if (num_funcs) {
879 			err = of_property_read_u32_index(np, "brcm,function",
880 					(num_funcs > 1) ? i : 0, &func);
881 			if (err)
882 				goto out;
883 			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
884 							func, &cur_map);
885 			if (err)
886 				goto out;
887 		}
888 		if (num_pulls) {
889 			err = of_property_read_u32_index(np, "brcm,pull",
890 					(num_pulls > 1) ? i : 0, &pull);
891 			if (err)
892 				goto out;
893 			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
894 							pull, &cur_map);
895 			if (err)
896 				goto out;
897 		}
898 	}
899 
900 	*map = maps;
901 	*num_maps = num_pins * maps_per_pin;
902 
903 	return 0;
904 
905 out:
906 	bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
907 	return err;
908 }
909 
910 static const struct pinctrl_ops bcm2835_pctl_ops = {
911 	.get_groups_count = bcm2835_pctl_get_groups_count,
912 	.get_group_name = bcm2835_pctl_get_group_name,
913 	.get_group_pins = bcm2835_pctl_get_group_pins,
914 	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
915 	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
916 	.dt_free_map = bcm2835_pctl_dt_free_map,
917 };
918 
919 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
920 		unsigned offset)
921 {
922 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
923 
924 	/* disable by setting to GPIO_IN */
925 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
926 	return 0;
927 }
928 
929 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
930 {
931 	return BCM2835_FSEL_COUNT;
932 }
933 
934 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
935 		unsigned selector)
936 {
937 	return bcm2835_functions[selector];
938 }
939 
940 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
941 		unsigned selector,
942 		const char * const **groups,
943 		unsigned * const num_groups)
944 {
945 	/* every pin can do every function */
946 	*groups = bcm2835_gpio_groups;
947 	*num_groups = BCM2835_NUM_GPIOS;
948 
949 	return 0;
950 }
951 
952 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
953 		unsigned func_selector,
954 		unsigned group_selector)
955 {
956 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
957 
958 	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
959 
960 	return 0;
961 }
962 
963 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
964 		struct pinctrl_gpio_range *range,
965 		unsigned offset)
966 {
967 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
968 
969 	/* disable by setting to GPIO_IN */
970 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
971 }
972 
973 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
974 		struct pinctrl_gpio_range *range,
975 		unsigned offset,
976 		bool input)
977 {
978 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
979 	enum bcm2835_fsel fsel = input ?
980 		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
981 
982 	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
983 
984 	return 0;
985 }
986 
987 static const struct pinmux_ops bcm2835_pmx_ops = {
988 	.free = bcm2835_pmx_free,
989 	.get_functions_count = bcm2835_pmx_get_functions_count,
990 	.get_function_name = bcm2835_pmx_get_function_name,
991 	.get_function_groups = bcm2835_pmx_get_function_groups,
992 	.set_mux = bcm2835_pmx_set,
993 	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
994 	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
995 };
996 
997 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
998 			unsigned pin, unsigned long *config)
999 {
1000 	/* No way to read back config in HW */
1001 	return -ENOTSUPP;
1002 }
1003 
1004 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1005 		unsigned int pin, unsigned int arg)
1006 {
1007 	u32 off, bit;
1008 
1009 	off = GPIO_REG_OFFSET(pin);
1010 	bit = GPIO_REG_SHIFT(pin);
1011 
1012 	bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1013 	/*
1014 	 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1015 	 * But the VideoCore firmware delay for this operation
1016 	 * based nearly on the same amount of VPU cycles and this clock
1017 	 * runs at 250 MHz.
1018 	 */
1019 	udelay(1);
1020 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1021 	udelay(1);
1022 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1023 }
1024 
1025 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1026 			unsigned int pin, unsigned long *configs,
1027 			unsigned int num_configs)
1028 {
1029 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1030 	u32 param, arg;
1031 	int i;
1032 
1033 	for (i = 0; i < num_configs; i++) {
1034 		param = pinconf_to_config_param(configs[i]);
1035 		arg = pinconf_to_config_argument(configs[i]);
1036 
1037 		switch (param) {
1038 		/* Set legacy brcm,pull */
1039 		case BCM2835_PINCONF_PARAM_PULL:
1040 			bcm2835_pull_config_set(pc, pin, arg);
1041 			break;
1042 
1043 		/* Set pull generic bindings */
1044 		case PIN_CONFIG_BIAS_DISABLE:
1045 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1046 			break;
1047 
1048 		case PIN_CONFIG_BIAS_PULL_DOWN:
1049 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1050 			break;
1051 
1052 		case PIN_CONFIG_BIAS_PULL_UP:
1053 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1054 			break;
1055 
1056 		/* Set output-high or output-low */
1057 		case PIN_CONFIG_OUTPUT:
1058 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1059 			break;
1060 
1061 		default:
1062 			return -ENOTSUPP;
1063 
1064 		} /* switch param type */
1065 	} /* for each config */
1066 
1067 	return 0;
1068 }
1069 
1070 static const struct pinconf_ops bcm2835_pinconf_ops = {
1071 	.is_generic = true,
1072 	.pin_config_get = bcm2835_pinconf_get,
1073 	.pin_config_set = bcm2835_pinconf_set,
1074 };
1075 
1076 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1077 				    unsigned int pin, unsigned int arg)
1078 {
1079 	u32 shifter;
1080 	u32 value;
1081 	u32 off;
1082 
1083 	off = PUD_2711_REG_OFFSET(pin);
1084 	shifter = PUD_2711_REG_SHIFT(pin);
1085 
1086 	value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1087 	value &= ~(PUD_2711_MASK << shifter);
1088 	value |= (arg << shifter);
1089 	bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1090 }
1091 
1092 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1093 			       unsigned int pin, unsigned long *configs,
1094 			       unsigned int num_configs)
1095 {
1096 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1097 	u32 param, arg;
1098 	int i;
1099 
1100 	for (i = 0; i < num_configs; i++) {
1101 		param = pinconf_to_config_param(configs[i]);
1102 		arg = pinconf_to_config_argument(configs[i]);
1103 
1104 		switch (param) {
1105 		/* convert legacy brcm,pull */
1106 		case BCM2835_PINCONF_PARAM_PULL:
1107 			if (arg == BCM2835_PUD_UP)
1108 				arg = BCM2711_PULL_UP;
1109 			else if (arg == BCM2835_PUD_DOWN)
1110 				arg = BCM2711_PULL_DOWN;
1111 			else
1112 				arg = BCM2711_PULL_NONE;
1113 
1114 			bcm2711_pull_config_set(pc, pin, arg);
1115 			break;
1116 
1117 		/* Set pull generic bindings */
1118 		case PIN_CONFIG_BIAS_DISABLE:
1119 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1120 			break;
1121 		case PIN_CONFIG_BIAS_PULL_DOWN:
1122 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1123 			break;
1124 		case PIN_CONFIG_BIAS_PULL_UP:
1125 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1126 			break;
1127 
1128 		/* Set output-high or output-low */
1129 		case PIN_CONFIG_OUTPUT:
1130 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1131 			break;
1132 
1133 		default:
1134 			return -ENOTSUPP;
1135 		}
1136 	} /* for each config */
1137 
1138 	return 0;
1139 }
1140 
1141 static const struct pinconf_ops bcm2711_pinconf_ops = {
1142 	.is_generic = true,
1143 	.pin_config_get = bcm2835_pinconf_get,
1144 	.pin_config_set = bcm2711_pinconf_set,
1145 };
1146 
1147 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1148 	.name = MODULE_NAME,
1149 	.pins = bcm2835_gpio_pins,
1150 	.npins = BCM2835_NUM_GPIOS,
1151 	.pctlops = &bcm2835_pctl_ops,
1152 	.pmxops = &bcm2835_pmx_ops,
1153 	.confops = &bcm2835_pinconf_ops,
1154 	.owner = THIS_MODULE,
1155 };
1156 
1157 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1158 	.name = "pinctrl-bcm2711",
1159 	.pins = bcm2835_gpio_pins,
1160 	.npins = BCM2711_NUM_GPIOS,
1161 	.pctlops = &bcm2835_pctl_ops,
1162 	.pmxops = &bcm2835_pmx_ops,
1163 	.confops = &bcm2711_pinconf_ops,
1164 	.owner = THIS_MODULE,
1165 };
1166 
1167 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1168 	.name = MODULE_NAME,
1169 	.npins = BCM2835_NUM_GPIOS,
1170 };
1171 
1172 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1173 	.name = "pinctrl-bcm2711",
1174 	.npins = BCM2711_NUM_GPIOS,
1175 };
1176 
1177 struct bcm_plat_data {
1178 	const struct gpio_chip *gpio_chip;
1179 	const struct pinctrl_desc *pctl_desc;
1180 	const struct pinctrl_gpio_range *gpio_range;
1181 };
1182 
1183 static const struct bcm_plat_data bcm2835_plat_data = {
1184 	.gpio_chip = &bcm2835_gpio_chip,
1185 	.pctl_desc = &bcm2835_pinctrl_desc,
1186 	.gpio_range = &bcm2835_pinctrl_gpio_range,
1187 };
1188 
1189 static const struct bcm_plat_data bcm2711_plat_data = {
1190 	.gpio_chip = &bcm2711_gpio_chip,
1191 	.pctl_desc = &bcm2711_pinctrl_desc,
1192 	.gpio_range = &bcm2711_pinctrl_gpio_range,
1193 };
1194 
1195 static const struct of_device_id bcm2835_pinctrl_match[] = {
1196 	{
1197 		.compatible = "brcm,bcm2835-gpio",
1198 		.data = &bcm2835_plat_data,
1199 	},
1200 	{
1201 		.compatible = "brcm,bcm2711-gpio",
1202 		.data = &bcm2711_plat_data,
1203 	},
1204 	{
1205 		.compatible = "brcm,bcm7211-gpio",
1206 		.data = &bcm2711_plat_data,
1207 	},
1208 	{}
1209 };
1210 
1211 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1212 {
1213 	struct device *dev = &pdev->dev;
1214 	struct device_node *np = dev->of_node;
1215 	const struct bcm_plat_data *pdata;
1216 	struct bcm2835_pinctrl *pc;
1217 	struct gpio_irq_chip *girq;
1218 	struct resource iomem;
1219 	int err, i;
1220 	const struct of_device_id *match;
1221 	int is_7211 = 0;
1222 
1223 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1224 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1225 
1226 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1227 	if (!pc)
1228 		return -ENOMEM;
1229 
1230 	platform_set_drvdata(pdev, pc);
1231 	pc->dev = dev;
1232 
1233 	err = of_address_to_resource(np, 0, &iomem);
1234 	if (err) {
1235 		dev_err(dev, "could not get IO memory\n");
1236 		return err;
1237 	}
1238 
1239 	pc->base = devm_ioremap_resource(dev, &iomem);
1240 	if (IS_ERR(pc->base))
1241 		return PTR_ERR(pc->base);
1242 
1243 	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1244 	if (!match)
1245 		return -EINVAL;
1246 
1247 	pdata = match->data;
1248 	is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1249 
1250 	pc->gpio_chip = *pdata->gpio_chip;
1251 	pc->gpio_chip.parent = dev;
1252 
1253 	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1254 		unsigned long events;
1255 		unsigned offset;
1256 
1257 		/* clear event detection flags */
1258 		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1259 		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1260 		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1261 		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1262 		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1263 		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1264 
1265 		/* clear all the events */
1266 		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1267 		for_each_set_bit(offset, &events, 32)
1268 			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1269 
1270 		raw_spin_lock_init(&pc->irq_lock[i]);
1271 	}
1272 
1273 	pc->pctl_desc = *pdata->pctl_desc;
1274 	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1275 	if (IS_ERR(pc->pctl_dev)) {
1276 		gpiochip_remove(&pc->gpio_chip);
1277 		return PTR_ERR(pc->pctl_dev);
1278 	}
1279 
1280 	pc->gpio_range = *pdata->gpio_range;
1281 	pc->gpio_range.base = pc->gpio_chip.base;
1282 	pc->gpio_range.gc = &pc->gpio_chip;
1283 	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1284 
1285 	girq = &pc->gpio_chip.irq;
1286 	gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
1287 	girq->parent_handler = bcm2835_gpio_irq_handler;
1288 	girq->num_parents = BCM2835_NUM_IRQS;
1289 	girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1290 				     sizeof(*girq->parents),
1291 				     GFP_KERNEL);
1292 	if (!girq->parents) {
1293 		err = -ENOMEM;
1294 		goto out_remove;
1295 	}
1296 
1297 	if (is_7211) {
1298 		pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1299 					    sizeof(*pc->wake_irq),
1300 					    GFP_KERNEL);
1301 		if (!pc->wake_irq) {
1302 			err = -ENOMEM;
1303 			goto out_remove;
1304 		}
1305 	}
1306 
1307 	/*
1308 	 * Use the same handler for all groups: this is necessary
1309 	 * since we use one gpiochip to cover all lines - the
1310 	 * irq handler then needs to figure out which group and
1311 	 * bank that was firing the IRQ and look up the per-group
1312 	 * and bank data.
1313 	 */
1314 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1315 		int len;
1316 		char *name;
1317 
1318 		girq->parents[i] = irq_of_parse_and_map(np, i);
1319 		if (!is_7211) {
1320 			if (!girq->parents[i]) {
1321 				girq->num_parents = i;
1322 				break;
1323 			}
1324 			continue;
1325 		}
1326 		/* Skip over the all banks interrupts */
1327 		pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1328 						       BCM2835_NUM_IRQS + 1);
1329 
1330 		len = strlen(dev_name(pc->dev)) + 16;
1331 		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1332 		if (!name) {
1333 			err = -ENOMEM;
1334 			goto out_remove;
1335 		}
1336 
1337 		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1338 
1339 		/* These are optional interrupts */
1340 		err = devm_request_irq(dev, pc->wake_irq[i],
1341 				       bcm2835_gpio_wake_irq_handler,
1342 				       IRQF_SHARED, name, pc);
1343 		if (err)
1344 			dev_warn(dev, "unable to request wake IRQ %d\n",
1345 				 pc->wake_irq[i]);
1346 	}
1347 
1348 	girq->default_type = IRQ_TYPE_NONE;
1349 	girq->handler = handle_level_irq;
1350 
1351 	err = gpiochip_add_data(&pc->gpio_chip, pc);
1352 	if (err) {
1353 		dev_err(dev, "could not add GPIO chip\n");
1354 		goto out_remove;
1355 	}
1356 
1357 	return 0;
1358 
1359 out_remove:
1360 	pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1361 	return err;
1362 }
1363 
1364 static struct platform_driver bcm2835_pinctrl_driver = {
1365 	.probe = bcm2835_pinctrl_probe,
1366 	.driver = {
1367 		.name = MODULE_NAME,
1368 		.of_match_table = bcm2835_pinctrl_match,
1369 		.suppress_bind_attrs = true,
1370 	},
1371 };
1372 module_platform_driver(bcm2835_pinctrl_driver);
1373 
1374 MODULE_AUTHOR("Chris Boot");
1375 MODULE_AUTHOR("Simon Arlott");
1376 MODULE_AUTHOR("Stephen Warren");
1377 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1378 MODULE_LICENSE("GPL");
1379