xref: /linux/drivers/pinctrl/bcm/pinctrl-bcm2835.c (revision 908fc4c2) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4  *
5  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6  *
7  * This driver is inspired by:
8  * pinctrl-nomadik.c, please see original file for copyright information
9  * pinctrl-tegra.c, please see original file for copyright information
10  */
11 
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/types.h>
38 #include <dt-bindings/pinctrl/bcm2835.h>
39 
40 #define MODULE_NAME "pinctrl-bcm2835"
41 #define BCM2835_NUM_GPIOS 54
42 #define BCM2711_NUM_GPIOS 58
43 #define BCM2835_NUM_BANKS 2
44 #define BCM2835_NUM_IRQS  3
45 
46 /* GPIO register offsets */
47 #define GPFSEL0		0x0	/* Function Select */
48 #define GPSET0		0x1c	/* Pin Output Set */
49 #define GPCLR0		0x28	/* Pin Output Clear */
50 #define GPLEV0		0x34	/* Pin Level */
51 #define GPEDS0		0x40	/* Pin Event Detect Status */
52 #define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
53 #define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
54 #define GPHEN0		0x64	/* Pin High Detect Enable */
55 #define GPLEN0		0x70	/* Pin Low Detect Enable */
56 #define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
57 #define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
58 #define GPPUD		0x94	/* Pin Pull-up/down Enable */
59 #define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
61 
62 #define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
63 #define FSEL_SHIFT(p)		(((p) % 10) * 3)
64 #define GPIO_REG_OFFSET(p)	((p) / 32)
65 #define GPIO_REG_SHIFT(p)	((p) % 32)
66 
67 #define PUD_2711_MASK		0x3
68 #define PUD_2711_REG_OFFSET(p)	((p) / 16)
69 #define PUD_2711_REG_SHIFT(p)	(((p) % 16) * 2)
70 
71 /* argument: bcm2835_pinconf_pull */
72 #define BCM2835_PINCONF_PARAM_PULL	(PIN_CONFIG_END + 1)
73 
74 #define BCM2711_PULL_NONE	0x0
75 #define BCM2711_PULL_UP		0x1
76 #define BCM2711_PULL_DOWN	0x2
77 
78 struct bcm2835_pinctrl {
79 	struct device *dev;
80 	void __iomem *base;
81 	int *wake_irq;
82 
83 	/* note: locking assumes each bank will have its own unsigned long */
84 	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
85 	unsigned int irq_type[BCM2711_NUM_GPIOS];
86 
87 	struct pinctrl_dev *pctl_dev;
88 	struct gpio_chip gpio_chip;
89 	struct pinctrl_desc pctl_desc;
90 	struct pinctrl_gpio_range gpio_range;
91 
92 	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
93 };
94 
95 /* pins are just named GPIO0..GPIO53 */
96 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
97 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
98 	BCM2835_GPIO_PIN(0),
99 	BCM2835_GPIO_PIN(1),
100 	BCM2835_GPIO_PIN(2),
101 	BCM2835_GPIO_PIN(3),
102 	BCM2835_GPIO_PIN(4),
103 	BCM2835_GPIO_PIN(5),
104 	BCM2835_GPIO_PIN(6),
105 	BCM2835_GPIO_PIN(7),
106 	BCM2835_GPIO_PIN(8),
107 	BCM2835_GPIO_PIN(9),
108 	BCM2835_GPIO_PIN(10),
109 	BCM2835_GPIO_PIN(11),
110 	BCM2835_GPIO_PIN(12),
111 	BCM2835_GPIO_PIN(13),
112 	BCM2835_GPIO_PIN(14),
113 	BCM2835_GPIO_PIN(15),
114 	BCM2835_GPIO_PIN(16),
115 	BCM2835_GPIO_PIN(17),
116 	BCM2835_GPIO_PIN(18),
117 	BCM2835_GPIO_PIN(19),
118 	BCM2835_GPIO_PIN(20),
119 	BCM2835_GPIO_PIN(21),
120 	BCM2835_GPIO_PIN(22),
121 	BCM2835_GPIO_PIN(23),
122 	BCM2835_GPIO_PIN(24),
123 	BCM2835_GPIO_PIN(25),
124 	BCM2835_GPIO_PIN(26),
125 	BCM2835_GPIO_PIN(27),
126 	BCM2835_GPIO_PIN(28),
127 	BCM2835_GPIO_PIN(29),
128 	BCM2835_GPIO_PIN(30),
129 	BCM2835_GPIO_PIN(31),
130 	BCM2835_GPIO_PIN(32),
131 	BCM2835_GPIO_PIN(33),
132 	BCM2835_GPIO_PIN(34),
133 	BCM2835_GPIO_PIN(35),
134 	BCM2835_GPIO_PIN(36),
135 	BCM2835_GPIO_PIN(37),
136 	BCM2835_GPIO_PIN(38),
137 	BCM2835_GPIO_PIN(39),
138 	BCM2835_GPIO_PIN(40),
139 	BCM2835_GPIO_PIN(41),
140 	BCM2835_GPIO_PIN(42),
141 	BCM2835_GPIO_PIN(43),
142 	BCM2835_GPIO_PIN(44),
143 	BCM2835_GPIO_PIN(45),
144 	BCM2835_GPIO_PIN(46),
145 	BCM2835_GPIO_PIN(47),
146 	BCM2835_GPIO_PIN(48),
147 	BCM2835_GPIO_PIN(49),
148 	BCM2835_GPIO_PIN(50),
149 	BCM2835_GPIO_PIN(51),
150 	BCM2835_GPIO_PIN(52),
151 	BCM2835_GPIO_PIN(53),
152 	BCM2835_GPIO_PIN(54),
153 	BCM2835_GPIO_PIN(55),
154 	BCM2835_GPIO_PIN(56),
155 	BCM2835_GPIO_PIN(57),
156 };
157 
158 /* one pin per group */
159 static const char * const bcm2835_gpio_groups[] = {
160 	"gpio0",
161 	"gpio1",
162 	"gpio2",
163 	"gpio3",
164 	"gpio4",
165 	"gpio5",
166 	"gpio6",
167 	"gpio7",
168 	"gpio8",
169 	"gpio9",
170 	"gpio10",
171 	"gpio11",
172 	"gpio12",
173 	"gpio13",
174 	"gpio14",
175 	"gpio15",
176 	"gpio16",
177 	"gpio17",
178 	"gpio18",
179 	"gpio19",
180 	"gpio20",
181 	"gpio21",
182 	"gpio22",
183 	"gpio23",
184 	"gpio24",
185 	"gpio25",
186 	"gpio26",
187 	"gpio27",
188 	"gpio28",
189 	"gpio29",
190 	"gpio30",
191 	"gpio31",
192 	"gpio32",
193 	"gpio33",
194 	"gpio34",
195 	"gpio35",
196 	"gpio36",
197 	"gpio37",
198 	"gpio38",
199 	"gpio39",
200 	"gpio40",
201 	"gpio41",
202 	"gpio42",
203 	"gpio43",
204 	"gpio44",
205 	"gpio45",
206 	"gpio46",
207 	"gpio47",
208 	"gpio48",
209 	"gpio49",
210 	"gpio50",
211 	"gpio51",
212 	"gpio52",
213 	"gpio53",
214 	"gpio54",
215 	"gpio55",
216 	"gpio56",
217 	"gpio57",
218 };
219 
220 enum bcm2835_fsel {
221 	BCM2835_FSEL_COUNT = 8,
222 	BCM2835_FSEL_MASK = 0x7,
223 };
224 
225 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
226 	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
227 	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
228 	[BCM2835_FSEL_ALT0] = "alt0",
229 	[BCM2835_FSEL_ALT1] = "alt1",
230 	[BCM2835_FSEL_ALT2] = "alt2",
231 	[BCM2835_FSEL_ALT3] = "alt3",
232 	[BCM2835_FSEL_ALT4] = "alt4",
233 	[BCM2835_FSEL_ALT5] = "alt5",
234 };
235 
236 static const char * const irq_type_names[] = {
237 	[IRQ_TYPE_NONE] = "none",
238 	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
239 	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
240 	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
241 	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
242 	[IRQ_TYPE_LEVEL_LOW] = "level-low",
243 };
244 
245 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
246 {
247 	return readl(pc->base + reg);
248 }
249 
250 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
251 		u32 val)
252 {
253 	writel(val, pc->base + reg);
254 }
255 
256 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
257 		unsigned bit)
258 {
259 	reg += GPIO_REG_OFFSET(bit) * 4;
260 	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
261 }
262 
263 /* note NOT a read/modify/write cycle */
264 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
265 		unsigned reg, unsigned bit)
266 {
267 	reg += GPIO_REG_OFFSET(bit) * 4;
268 	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
269 }
270 
271 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
272 		struct bcm2835_pinctrl *pc, unsigned pin)
273 {
274 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
275 	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
276 
277 	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
278 			bcm2835_functions[status]);
279 
280 	return status;
281 }
282 
283 static inline void bcm2835_pinctrl_fsel_set(
284 		struct bcm2835_pinctrl *pc, unsigned pin,
285 		enum bcm2835_fsel fsel)
286 {
287 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
288 	enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
289 
290 	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
291 			bcm2835_functions[cur]);
292 
293 	if (cur == fsel)
294 		return;
295 
296 	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
297 		/* always transition through GPIO_IN */
298 		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
299 		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
300 
301 		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
302 				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
303 		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
304 	}
305 
306 	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
307 	val |= fsel << FSEL_SHIFT(pin);
308 
309 	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
310 			bcm2835_functions[fsel]);
311 	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
312 }
313 
314 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
315 {
316 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
317 
318 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
319 	return 0;
320 }
321 
322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
323 {
324 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
325 
326 	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
327 }
328 
329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
330 {
331 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
332 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
333 
334 	/* Alternative function doesn't clearly provide a direction */
335 	if (fsel > BCM2835_FSEL_GPIO_OUT)
336 		return -EINVAL;
337 
338 	if (fsel == BCM2835_FSEL_GPIO_IN)
339 		return GPIO_LINE_DIRECTION_IN;
340 
341 	return GPIO_LINE_DIRECTION_OUT;
342 }
343 
344 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
345 {
346 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
347 
348 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
349 }
350 
351 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
352 		unsigned offset, int value)
353 {
354 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
355 
356 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
357 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
358 	return 0;
359 }
360 
361 static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
362 					   struct device_node *np)
363 {
364 	struct pinctrl_dev *pctldev = of_pinctrl_get(np);
365 
366 	of_node_put(np);
367 
368 	if (!pctldev)
369 		return 0;
370 
371 	gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
372 			       gc->ngpio);
373 
374 	return 0;
375 }
376 
377 static const struct gpio_chip bcm2835_gpio_chip = {
378 	.label = MODULE_NAME,
379 	.owner = THIS_MODULE,
380 	.request = gpiochip_generic_request,
381 	.free = gpiochip_generic_free,
382 	.direction_input = bcm2835_gpio_direction_input,
383 	.direction_output = bcm2835_gpio_direction_output,
384 	.get_direction = bcm2835_gpio_get_direction,
385 	.get = bcm2835_gpio_get,
386 	.set = bcm2835_gpio_set,
387 	.set_config = gpiochip_generic_config,
388 	.base = -1,
389 	.ngpio = BCM2835_NUM_GPIOS,
390 	.can_sleep = false,
391 	.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
392 };
393 
394 static const struct gpio_chip bcm2711_gpio_chip = {
395 	.label = "pinctrl-bcm2711",
396 	.owner = THIS_MODULE,
397 	.request = gpiochip_generic_request,
398 	.free = gpiochip_generic_free,
399 	.direction_input = bcm2835_gpio_direction_input,
400 	.direction_output = bcm2835_gpio_direction_output,
401 	.get_direction = bcm2835_gpio_get_direction,
402 	.get = bcm2835_gpio_get,
403 	.set = bcm2835_gpio_set,
404 	.set_config = gpiochip_generic_config,
405 	.base = -1,
406 	.ngpio = BCM2711_NUM_GPIOS,
407 	.can_sleep = false,
408 	.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
409 };
410 
411 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
412 					 unsigned int bank, u32 mask)
413 {
414 	unsigned long events;
415 	unsigned offset;
416 	unsigned gpio;
417 
418 	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
419 	events &= mask;
420 	events &= pc->enabled_irq_map[bank];
421 	for_each_set_bit(offset, &events, 32) {
422 		gpio = (32 * bank) + offset;
423 		generic_handle_domain_irq(pc->gpio_chip.irq.domain,
424 					  gpio);
425 	}
426 }
427 
428 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
429 {
430 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
431 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
432 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
433 	int irq = irq_desc_get_irq(desc);
434 	int group = 0;
435 	int i;
436 
437 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
438 		if (chip->irq.parents[i] == irq) {
439 			group = i;
440 			break;
441 		}
442 	}
443 	/* This should not happen, every IRQ has a bank */
444 	BUG_ON(i == BCM2835_NUM_IRQS);
445 
446 	chained_irq_enter(host_chip, desc);
447 
448 	switch (group) {
449 	case 0: /* IRQ0 covers GPIOs 0-27 */
450 		bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
451 		break;
452 	case 1: /* IRQ1 covers GPIOs 28-45 */
453 		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
454 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
455 		break;
456 	case 2: /* IRQ2 covers GPIOs 46-57 */
457 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
458 		break;
459 	}
460 
461 	chained_irq_exit(host_chip, desc);
462 }
463 
464 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
465 {
466 	return IRQ_HANDLED;
467 }
468 
469 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
470 	unsigned reg, unsigned offset, bool enable)
471 {
472 	u32 value;
473 	reg += GPIO_REG_OFFSET(offset) * 4;
474 	value = bcm2835_gpio_rd(pc, reg);
475 	if (enable)
476 		value |= BIT(GPIO_REG_SHIFT(offset));
477 	else
478 		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
479 	bcm2835_gpio_wr(pc, reg, value);
480 }
481 
482 /* fast path for IRQ handler */
483 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
484 	unsigned offset, bool enable)
485 {
486 	switch (pc->irq_type[offset]) {
487 	case IRQ_TYPE_EDGE_RISING:
488 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
489 		break;
490 
491 	case IRQ_TYPE_EDGE_FALLING:
492 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
493 		break;
494 
495 	case IRQ_TYPE_EDGE_BOTH:
496 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
497 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
498 		break;
499 
500 	case IRQ_TYPE_LEVEL_HIGH:
501 		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
502 		break;
503 
504 	case IRQ_TYPE_LEVEL_LOW:
505 		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
506 		break;
507 	}
508 }
509 
510 static void bcm2835_gpio_irq_enable(struct irq_data *data)
511 {
512 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
513 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
514 	unsigned gpio = irqd_to_hwirq(data);
515 	unsigned offset = GPIO_REG_SHIFT(gpio);
516 	unsigned bank = GPIO_REG_OFFSET(gpio);
517 	unsigned long flags;
518 
519 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
520 	set_bit(offset, &pc->enabled_irq_map[bank]);
521 	bcm2835_gpio_irq_config(pc, gpio, true);
522 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
523 }
524 
525 static void bcm2835_gpio_irq_disable(struct irq_data *data)
526 {
527 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
528 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
529 	unsigned gpio = irqd_to_hwirq(data);
530 	unsigned offset = GPIO_REG_SHIFT(gpio);
531 	unsigned bank = GPIO_REG_OFFSET(gpio);
532 	unsigned long flags;
533 
534 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
535 	bcm2835_gpio_irq_config(pc, gpio, false);
536 	/* Clear events that were latched prior to clearing event sources */
537 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
538 	clear_bit(offset, &pc->enabled_irq_map[bank]);
539 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
540 }
541 
542 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
543 	unsigned offset, unsigned int type)
544 {
545 	switch (type) {
546 	case IRQ_TYPE_NONE:
547 	case IRQ_TYPE_EDGE_RISING:
548 	case IRQ_TYPE_EDGE_FALLING:
549 	case IRQ_TYPE_EDGE_BOTH:
550 	case IRQ_TYPE_LEVEL_HIGH:
551 	case IRQ_TYPE_LEVEL_LOW:
552 		pc->irq_type[offset] = type;
553 		break;
554 
555 	default:
556 		return -EINVAL;
557 	}
558 	return 0;
559 }
560 
561 /* slower path for reconfiguring IRQ type */
562 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
563 	unsigned offset, unsigned int type)
564 {
565 	switch (type) {
566 	case IRQ_TYPE_NONE:
567 		if (pc->irq_type[offset] != type) {
568 			bcm2835_gpio_irq_config(pc, offset, false);
569 			pc->irq_type[offset] = type;
570 		}
571 		break;
572 
573 	case IRQ_TYPE_EDGE_RISING:
574 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
575 			/* RISING already enabled, disable FALLING */
576 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
577 			bcm2835_gpio_irq_config(pc, offset, false);
578 			pc->irq_type[offset] = type;
579 		} else if (pc->irq_type[offset] != type) {
580 			bcm2835_gpio_irq_config(pc, offset, false);
581 			pc->irq_type[offset] = type;
582 			bcm2835_gpio_irq_config(pc, offset, true);
583 		}
584 		break;
585 
586 	case IRQ_TYPE_EDGE_FALLING:
587 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
588 			/* FALLING already enabled, disable RISING */
589 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
590 			bcm2835_gpio_irq_config(pc, offset, false);
591 			pc->irq_type[offset] = type;
592 		} else if (pc->irq_type[offset] != type) {
593 			bcm2835_gpio_irq_config(pc, offset, false);
594 			pc->irq_type[offset] = type;
595 			bcm2835_gpio_irq_config(pc, offset, true);
596 		}
597 		break;
598 
599 	case IRQ_TYPE_EDGE_BOTH:
600 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
601 			/* RISING already enabled, enable FALLING too */
602 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
603 			bcm2835_gpio_irq_config(pc, offset, true);
604 			pc->irq_type[offset] = type;
605 		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
606 			/* FALLING already enabled, enable RISING too */
607 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
608 			bcm2835_gpio_irq_config(pc, offset, true);
609 			pc->irq_type[offset] = type;
610 		} else if (pc->irq_type[offset] != type) {
611 			bcm2835_gpio_irq_config(pc, offset, false);
612 			pc->irq_type[offset] = type;
613 			bcm2835_gpio_irq_config(pc, offset, true);
614 		}
615 		break;
616 
617 	case IRQ_TYPE_LEVEL_HIGH:
618 	case IRQ_TYPE_LEVEL_LOW:
619 		if (pc->irq_type[offset] != type) {
620 			bcm2835_gpio_irq_config(pc, offset, false);
621 			pc->irq_type[offset] = type;
622 			bcm2835_gpio_irq_config(pc, offset, true);
623 		}
624 		break;
625 
626 	default:
627 		return -EINVAL;
628 	}
629 	return 0;
630 }
631 
632 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
633 {
634 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
635 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
636 	unsigned gpio = irqd_to_hwirq(data);
637 	unsigned offset = GPIO_REG_SHIFT(gpio);
638 	unsigned bank = GPIO_REG_OFFSET(gpio);
639 	unsigned long flags;
640 	int ret;
641 
642 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
643 
644 	if (test_bit(offset, &pc->enabled_irq_map[bank]))
645 		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
646 	else
647 		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
648 
649 	if (type & IRQ_TYPE_EDGE_BOTH)
650 		irq_set_handler_locked(data, handle_edge_irq);
651 	else
652 		irq_set_handler_locked(data, handle_level_irq);
653 
654 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
655 
656 	return ret;
657 }
658 
659 static void bcm2835_gpio_irq_ack(struct irq_data *data)
660 {
661 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
662 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
663 	unsigned gpio = irqd_to_hwirq(data);
664 
665 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
666 }
667 
668 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
669 {
670 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
671 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
672 	unsigned gpio = irqd_to_hwirq(data);
673 	unsigned int irqgroup;
674 	int ret = -EINVAL;
675 
676 	if (!pc->wake_irq)
677 		return ret;
678 
679 	if (gpio <= 27)
680 		irqgroup = 0;
681 	else if (gpio >= 28 && gpio <= 45)
682 		irqgroup = 1;
683 	else if (gpio >= 46 && gpio <= 57)
684 		irqgroup = 2;
685 	else
686 		return ret;
687 
688 	if (on)
689 		ret = enable_irq_wake(pc->wake_irq[irqgroup]);
690 	else
691 		ret = disable_irq_wake(pc->wake_irq[irqgroup]);
692 
693 	return ret;
694 }
695 
696 static struct irq_chip bcm2835_gpio_irq_chip = {
697 	.name = MODULE_NAME,
698 	.irq_enable = bcm2835_gpio_irq_enable,
699 	.irq_disable = bcm2835_gpio_irq_disable,
700 	.irq_set_type = bcm2835_gpio_irq_set_type,
701 	.irq_ack = bcm2835_gpio_irq_ack,
702 	.irq_mask = bcm2835_gpio_irq_disable,
703 	.irq_unmask = bcm2835_gpio_irq_enable,
704 	.irq_set_wake = bcm2835_gpio_irq_set_wake,
705 	.flags = IRQCHIP_MASK_ON_SUSPEND,
706 };
707 
708 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
709 {
710 	return BCM2835_NUM_GPIOS;
711 }
712 
713 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
714 		unsigned selector)
715 {
716 	return bcm2835_gpio_groups[selector];
717 }
718 
719 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
720 		unsigned selector,
721 		const unsigned **pins,
722 		unsigned *num_pins)
723 {
724 	*pins = &bcm2835_gpio_pins[selector].number;
725 	*num_pins = 1;
726 
727 	return 0;
728 }
729 
730 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
731 		struct seq_file *s,
732 		unsigned offset)
733 {
734 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
735 	struct gpio_chip *chip = &pc->gpio_chip;
736 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
737 	const char *fname = bcm2835_functions[fsel];
738 	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
739 	int irq = irq_find_mapping(chip->irq.domain, offset);
740 
741 	seq_printf(s, "function %s in %s; irq %d (%s)",
742 		fname, value ? "hi" : "lo",
743 		irq, irq_type_names[pc->irq_type[offset]]);
744 }
745 
746 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
747 		struct pinctrl_map *maps, unsigned num_maps)
748 {
749 	int i;
750 
751 	for (i = 0; i < num_maps; i++)
752 		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
753 			kfree(maps[i].data.configs.configs);
754 
755 	kfree(maps);
756 }
757 
758 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
759 		struct device_node *np, u32 pin, u32 fnum,
760 		struct pinctrl_map **maps)
761 {
762 	struct pinctrl_map *map = *maps;
763 
764 	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
765 		dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
766 		return -EINVAL;
767 	}
768 
769 	map->type = PIN_MAP_TYPE_MUX_GROUP;
770 	map->data.mux.group = bcm2835_gpio_groups[pin];
771 	map->data.mux.function = bcm2835_functions[fnum];
772 	(*maps)++;
773 
774 	return 0;
775 }
776 
777 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
778 		struct device_node *np, u32 pin, u32 pull,
779 		struct pinctrl_map **maps)
780 {
781 	struct pinctrl_map *map = *maps;
782 	unsigned long *configs;
783 
784 	if (pull > 2) {
785 		dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
786 		return -EINVAL;
787 	}
788 
789 	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
790 	if (!configs)
791 		return -ENOMEM;
792 	configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
793 
794 	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
795 	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
796 	map->data.configs.configs = configs;
797 	map->data.configs.num_configs = 1;
798 	(*maps)++;
799 
800 	return 0;
801 }
802 
803 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
804 		struct device_node *np,
805 		struct pinctrl_map **map, unsigned int *num_maps)
806 {
807 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
808 	struct property *pins, *funcs, *pulls;
809 	int num_pins, num_funcs, num_pulls, maps_per_pin;
810 	struct pinctrl_map *maps, *cur_map;
811 	int i, err;
812 	u32 pin, func, pull;
813 
814 	/* Check for generic binding in this node */
815 	err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
816 	if (err || *num_maps)
817 		return err;
818 
819 	/* Generic binding did not find anything continue with legacy parse */
820 	pins = of_find_property(np, "brcm,pins", NULL);
821 	if (!pins) {
822 		dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
823 		return -EINVAL;
824 	}
825 
826 	funcs = of_find_property(np, "brcm,function", NULL);
827 	pulls = of_find_property(np, "brcm,pull", NULL);
828 
829 	if (!funcs && !pulls) {
830 		dev_err(pc->dev,
831 			"%pOF: neither brcm,function nor brcm,pull specified\n",
832 			np);
833 		return -EINVAL;
834 	}
835 
836 	num_pins = pins->length / 4;
837 	num_funcs = funcs ? (funcs->length / 4) : 0;
838 	num_pulls = pulls ? (pulls->length / 4) : 0;
839 
840 	if (num_funcs > 1 && num_funcs != num_pins) {
841 		dev_err(pc->dev,
842 			"%pOF: brcm,function must have 1 or %d entries\n",
843 			np, num_pins);
844 		return -EINVAL;
845 	}
846 
847 	if (num_pulls > 1 && num_pulls != num_pins) {
848 		dev_err(pc->dev,
849 			"%pOF: brcm,pull must have 1 or %d entries\n",
850 			np, num_pins);
851 		return -EINVAL;
852 	}
853 
854 	maps_per_pin = 0;
855 	if (num_funcs)
856 		maps_per_pin++;
857 	if (num_pulls)
858 		maps_per_pin++;
859 	cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
860 				 GFP_KERNEL);
861 	if (!maps)
862 		return -ENOMEM;
863 
864 	for (i = 0; i < num_pins; i++) {
865 		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
866 		if (err)
867 			goto out;
868 		if (pin >= pc->pctl_desc.npins) {
869 			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
870 				np, pin);
871 			err = -EINVAL;
872 			goto out;
873 		}
874 
875 		if (num_funcs) {
876 			err = of_property_read_u32_index(np, "brcm,function",
877 					(num_funcs > 1) ? i : 0, &func);
878 			if (err)
879 				goto out;
880 			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
881 							func, &cur_map);
882 			if (err)
883 				goto out;
884 		}
885 		if (num_pulls) {
886 			err = of_property_read_u32_index(np, "brcm,pull",
887 					(num_pulls > 1) ? i : 0, &pull);
888 			if (err)
889 				goto out;
890 			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
891 							pull, &cur_map);
892 			if (err)
893 				goto out;
894 		}
895 	}
896 
897 	*map = maps;
898 	*num_maps = num_pins * maps_per_pin;
899 
900 	return 0;
901 
902 out:
903 	bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
904 	return err;
905 }
906 
907 static const struct pinctrl_ops bcm2835_pctl_ops = {
908 	.get_groups_count = bcm2835_pctl_get_groups_count,
909 	.get_group_name = bcm2835_pctl_get_group_name,
910 	.get_group_pins = bcm2835_pctl_get_group_pins,
911 	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
912 	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
913 	.dt_free_map = bcm2835_pctl_dt_free_map,
914 };
915 
916 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
917 		unsigned offset)
918 {
919 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
920 
921 	/* disable by setting to GPIO_IN */
922 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
923 	return 0;
924 }
925 
926 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
927 {
928 	return BCM2835_FSEL_COUNT;
929 }
930 
931 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
932 		unsigned selector)
933 {
934 	return bcm2835_functions[selector];
935 }
936 
937 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
938 		unsigned selector,
939 		const char * const **groups,
940 		unsigned * const num_groups)
941 {
942 	/* every pin can do every function */
943 	*groups = bcm2835_gpio_groups;
944 	*num_groups = BCM2835_NUM_GPIOS;
945 
946 	return 0;
947 }
948 
949 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
950 		unsigned func_selector,
951 		unsigned group_selector)
952 {
953 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
954 
955 	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
956 
957 	return 0;
958 }
959 
960 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
961 		struct pinctrl_gpio_range *range,
962 		unsigned offset)
963 {
964 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
965 
966 	/* disable by setting to GPIO_IN */
967 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
968 }
969 
970 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
971 		struct pinctrl_gpio_range *range,
972 		unsigned offset,
973 		bool input)
974 {
975 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
976 	enum bcm2835_fsel fsel = input ?
977 		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
978 
979 	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
980 
981 	return 0;
982 }
983 
984 static const struct pinmux_ops bcm2835_pmx_ops = {
985 	.free = bcm2835_pmx_free,
986 	.get_functions_count = bcm2835_pmx_get_functions_count,
987 	.get_function_name = bcm2835_pmx_get_function_name,
988 	.get_function_groups = bcm2835_pmx_get_function_groups,
989 	.set_mux = bcm2835_pmx_set,
990 	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
991 	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
992 };
993 
994 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
995 			unsigned pin, unsigned long *config)
996 {
997 	/* No way to read back config in HW */
998 	return -ENOTSUPP;
999 }
1000 
1001 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1002 		unsigned int pin, unsigned int arg)
1003 {
1004 	u32 off, bit;
1005 
1006 	off = GPIO_REG_OFFSET(pin);
1007 	bit = GPIO_REG_SHIFT(pin);
1008 
1009 	bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1010 	/*
1011 	 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1012 	 * But the VideoCore firmware delay for this operation
1013 	 * based nearly on the same amount of VPU cycles and this clock
1014 	 * runs at 250 MHz.
1015 	 */
1016 	udelay(1);
1017 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1018 	udelay(1);
1019 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1020 }
1021 
1022 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1023 			unsigned int pin, unsigned long *configs,
1024 			unsigned int num_configs)
1025 {
1026 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1027 	u32 param, arg;
1028 	int i;
1029 
1030 	for (i = 0; i < num_configs; i++) {
1031 		param = pinconf_to_config_param(configs[i]);
1032 		arg = pinconf_to_config_argument(configs[i]);
1033 
1034 		switch (param) {
1035 		/* Set legacy brcm,pull */
1036 		case BCM2835_PINCONF_PARAM_PULL:
1037 			bcm2835_pull_config_set(pc, pin, arg);
1038 			break;
1039 
1040 		/* Set pull generic bindings */
1041 		case PIN_CONFIG_BIAS_DISABLE:
1042 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1043 			break;
1044 
1045 		case PIN_CONFIG_BIAS_PULL_DOWN:
1046 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1047 			break;
1048 
1049 		case PIN_CONFIG_BIAS_PULL_UP:
1050 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1051 			break;
1052 
1053 		/* Set output-high or output-low */
1054 		case PIN_CONFIG_OUTPUT:
1055 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1056 			break;
1057 
1058 		default:
1059 			return -ENOTSUPP;
1060 
1061 		} /* switch param type */
1062 	} /* for each config */
1063 
1064 	return 0;
1065 }
1066 
1067 static const struct pinconf_ops bcm2835_pinconf_ops = {
1068 	.is_generic = true,
1069 	.pin_config_get = bcm2835_pinconf_get,
1070 	.pin_config_set = bcm2835_pinconf_set,
1071 };
1072 
1073 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1074 				    unsigned int pin, unsigned int arg)
1075 {
1076 	u32 shifter;
1077 	u32 value;
1078 	u32 off;
1079 
1080 	off = PUD_2711_REG_OFFSET(pin);
1081 	shifter = PUD_2711_REG_SHIFT(pin);
1082 
1083 	value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1084 	value &= ~(PUD_2711_MASK << shifter);
1085 	value |= (arg << shifter);
1086 	bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1087 }
1088 
1089 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1090 			       unsigned int pin, unsigned long *configs,
1091 			       unsigned int num_configs)
1092 {
1093 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1094 	u32 param, arg;
1095 	int i;
1096 
1097 	for (i = 0; i < num_configs; i++) {
1098 		param = pinconf_to_config_param(configs[i]);
1099 		arg = pinconf_to_config_argument(configs[i]);
1100 
1101 		switch (param) {
1102 		/* convert legacy brcm,pull */
1103 		case BCM2835_PINCONF_PARAM_PULL:
1104 			if (arg == BCM2835_PUD_UP)
1105 				arg = BCM2711_PULL_UP;
1106 			else if (arg == BCM2835_PUD_DOWN)
1107 				arg = BCM2711_PULL_DOWN;
1108 			else
1109 				arg = BCM2711_PULL_NONE;
1110 
1111 			bcm2711_pull_config_set(pc, pin, arg);
1112 			break;
1113 
1114 		/* Set pull generic bindings */
1115 		case PIN_CONFIG_BIAS_DISABLE:
1116 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1117 			break;
1118 		case PIN_CONFIG_BIAS_PULL_DOWN:
1119 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1120 			break;
1121 		case PIN_CONFIG_BIAS_PULL_UP:
1122 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1123 			break;
1124 
1125 		/* Set output-high or output-low */
1126 		case PIN_CONFIG_OUTPUT:
1127 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1128 			break;
1129 
1130 		default:
1131 			return -ENOTSUPP;
1132 		}
1133 	} /* for each config */
1134 
1135 	return 0;
1136 }
1137 
1138 static const struct pinconf_ops bcm2711_pinconf_ops = {
1139 	.is_generic = true,
1140 	.pin_config_get = bcm2835_pinconf_get,
1141 	.pin_config_set = bcm2711_pinconf_set,
1142 };
1143 
1144 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1145 	.name = MODULE_NAME,
1146 	.pins = bcm2835_gpio_pins,
1147 	.npins = BCM2835_NUM_GPIOS,
1148 	.pctlops = &bcm2835_pctl_ops,
1149 	.pmxops = &bcm2835_pmx_ops,
1150 	.confops = &bcm2835_pinconf_ops,
1151 	.owner = THIS_MODULE,
1152 };
1153 
1154 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1155 	.name = "pinctrl-bcm2711",
1156 	.pins = bcm2835_gpio_pins,
1157 	.npins = BCM2711_NUM_GPIOS,
1158 	.pctlops = &bcm2835_pctl_ops,
1159 	.pmxops = &bcm2835_pmx_ops,
1160 	.confops = &bcm2711_pinconf_ops,
1161 	.owner = THIS_MODULE,
1162 };
1163 
1164 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1165 	.name = MODULE_NAME,
1166 	.npins = BCM2835_NUM_GPIOS,
1167 };
1168 
1169 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1170 	.name = "pinctrl-bcm2711",
1171 	.npins = BCM2711_NUM_GPIOS,
1172 };
1173 
1174 struct bcm_plat_data {
1175 	const struct gpio_chip *gpio_chip;
1176 	const struct pinctrl_desc *pctl_desc;
1177 	const struct pinctrl_gpio_range *gpio_range;
1178 };
1179 
1180 static const struct bcm_plat_data bcm2835_plat_data = {
1181 	.gpio_chip = &bcm2835_gpio_chip,
1182 	.pctl_desc = &bcm2835_pinctrl_desc,
1183 	.gpio_range = &bcm2835_pinctrl_gpio_range,
1184 };
1185 
1186 static const struct bcm_plat_data bcm2711_plat_data = {
1187 	.gpio_chip = &bcm2711_gpio_chip,
1188 	.pctl_desc = &bcm2711_pinctrl_desc,
1189 	.gpio_range = &bcm2711_pinctrl_gpio_range,
1190 };
1191 
1192 static const struct of_device_id bcm2835_pinctrl_match[] = {
1193 	{
1194 		.compatible = "brcm,bcm2835-gpio",
1195 		.data = &bcm2835_plat_data,
1196 	},
1197 	{
1198 		.compatible = "brcm,bcm2711-gpio",
1199 		.data = &bcm2711_plat_data,
1200 	},
1201 	{
1202 		.compatible = "brcm,bcm7211-gpio",
1203 		.data = &bcm2711_plat_data,
1204 	},
1205 	{}
1206 };
1207 
1208 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1209 {
1210 	struct device *dev = &pdev->dev;
1211 	struct device_node *np = dev->of_node;
1212 	const struct bcm_plat_data *pdata;
1213 	struct bcm2835_pinctrl *pc;
1214 	struct gpio_irq_chip *girq;
1215 	struct resource iomem;
1216 	int err, i;
1217 	const struct of_device_id *match;
1218 	int is_7211 = 0;
1219 
1220 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1221 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1222 
1223 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1224 	if (!pc)
1225 		return -ENOMEM;
1226 
1227 	platform_set_drvdata(pdev, pc);
1228 	pc->dev = dev;
1229 
1230 	err = of_address_to_resource(np, 0, &iomem);
1231 	if (err) {
1232 		dev_err(dev, "could not get IO memory\n");
1233 		return err;
1234 	}
1235 
1236 	pc->base = devm_ioremap_resource(dev, &iomem);
1237 	if (IS_ERR(pc->base))
1238 		return PTR_ERR(pc->base);
1239 
1240 	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1241 	if (!match)
1242 		return -EINVAL;
1243 
1244 	pdata = match->data;
1245 	is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1246 
1247 	pc->gpio_chip = *pdata->gpio_chip;
1248 	pc->gpio_chip.parent = dev;
1249 
1250 	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1251 		unsigned long events;
1252 		unsigned offset;
1253 
1254 		/* clear event detection flags */
1255 		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1256 		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1257 		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1258 		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1259 		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1260 		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1261 
1262 		/* clear all the events */
1263 		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1264 		for_each_set_bit(offset, &events, 32)
1265 			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1266 
1267 		raw_spin_lock_init(&pc->irq_lock[i]);
1268 	}
1269 
1270 	pc->pctl_desc = *pdata->pctl_desc;
1271 	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1272 	if (IS_ERR(pc->pctl_dev)) {
1273 		gpiochip_remove(&pc->gpio_chip);
1274 		return PTR_ERR(pc->pctl_dev);
1275 	}
1276 
1277 	pc->gpio_range = *pdata->gpio_range;
1278 	pc->gpio_range.base = pc->gpio_chip.base;
1279 	pc->gpio_range.gc = &pc->gpio_chip;
1280 	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1281 
1282 	girq = &pc->gpio_chip.irq;
1283 	girq->chip = &bcm2835_gpio_irq_chip;
1284 	girq->parent_handler = bcm2835_gpio_irq_handler;
1285 	girq->num_parents = BCM2835_NUM_IRQS;
1286 	girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1287 				     sizeof(*girq->parents),
1288 				     GFP_KERNEL);
1289 	if (!girq->parents) {
1290 		err = -ENOMEM;
1291 		goto out_remove;
1292 	}
1293 
1294 	if (is_7211) {
1295 		pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1296 					    sizeof(*pc->wake_irq),
1297 					    GFP_KERNEL);
1298 		if (!pc->wake_irq) {
1299 			err = -ENOMEM;
1300 			goto out_remove;
1301 		}
1302 	}
1303 
1304 	/*
1305 	 * Use the same handler for all groups: this is necessary
1306 	 * since we use one gpiochip to cover all lines - the
1307 	 * irq handler then needs to figure out which group and
1308 	 * bank that was firing the IRQ and look up the per-group
1309 	 * and bank data.
1310 	 */
1311 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1312 		int len;
1313 		char *name;
1314 
1315 		girq->parents[i] = irq_of_parse_and_map(np, i);
1316 		if (!is_7211) {
1317 			if (!girq->parents[i]) {
1318 				girq->num_parents = i;
1319 				break;
1320 			}
1321 			continue;
1322 		}
1323 		/* Skip over the all banks interrupts */
1324 		pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1325 						       BCM2835_NUM_IRQS + 1);
1326 
1327 		len = strlen(dev_name(pc->dev)) + 16;
1328 		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1329 		if (!name) {
1330 			err = -ENOMEM;
1331 			goto out_remove;
1332 		}
1333 
1334 		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1335 
1336 		/* These are optional interrupts */
1337 		err = devm_request_irq(dev, pc->wake_irq[i],
1338 				       bcm2835_gpio_wake_irq_handler,
1339 				       IRQF_SHARED, name, pc);
1340 		if (err)
1341 			dev_warn(dev, "unable to request wake IRQ %d\n",
1342 				 pc->wake_irq[i]);
1343 	}
1344 
1345 	girq->default_type = IRQ_TYPE_NONE;
1346 	girq->handler = handle_level_irq;
1347 
1348 	err = gpiochip_add_data(&pc->gpio_chip, pc);
1349 	if (err) {
1350 		dev_err(dev, "could not add GPIO chip\n");
1351 		goto out_remove;
1352 	}
1353 
1354 	return 0;
1355 
1356 out_remove:
1357 	pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1358 	return err;
1359 }
1360 
1361 static struct platform_driver bcm2835_pinctrl_driver = {
1362 	.probe = bcm2835_pinctrl_probe,
1363 	.driver = {
1364 		.name = MODULE_NAME,
1365 		.of_match_table = bcm2835_pinctrl_match,
1366 		.suppress_bind_attrs = true,
1367 	},
1368 };
1369 module_platform_driver(bcm2835_pinctrl_driver);
1370 
1371 MODULE_AUTHOR("Chris Boot");
1372 MODULE_AUTHOR("Simon Arlott");
1373 MODULE_AUTHOR("Stephen Warren");
1374 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1375 MODULE_LICENSE("GPL");
1376