xref: /linux/drivers/pinctrl/bcm/pinctrl-bcm2835.c (revision d6fd48ef) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4  *
5  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6  *
7  * This driver is inspired by:
8  * pinctrl-nomadik.c, please see original file for copyright information
9  * pinctrl-tegra.c, please see original file for copyright information
10  */
11 
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/types.h>
38 #include <dt-bindings/pinctrl/bcm2835.h>
39 
40 #define MODULE_NAME "pinctrl-bcm2835"
41 #define BCM2835_NUM_GPIOS 54
42 #define BCM2711_NUM_GPIOS 58
43 #define BCM2835_NUM_BANKS 2
44 #define BCM2835_NUM_IRQS  3
45 
46 /* GPIO register offsets */
47 #define GPFSEL0		0x0	/* Function Select */
48 #define GPSET0		0x1c	/* Pin Output Set */
49 #define GPCLR0		0x28	/* Pin Output Clear */
50 #define GPLEV0		0x34	/* Pin Level */
51 #define GPEDS0		0x40	/* Pin Event Detect Status */
52 #define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
53 #define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
54 #define GPHEN0		0x64	/* Pin High Detect Enable */
55 #define GPLEN0		0x70	/* Pin Low Detect Enable */
56 #define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
57 #define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
58 #define GPPUD		0x94	/* Pin Pull-up/down Enable */
59 #define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
61 
62 #define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
63 #define FSEL_SHIFT(p)		(((p) % 10) * 3)
64 #define GPIO_REG_OFFSET(p)	((p) / 32)
65 #define GPIO_REG_SHIFT(p)	((p) % 32)
66 
67 #define PUD_2711_MASK		0x3
68 #define PUD_2711_REG_OFFSET(p)	((p) / 16)
69 #define PUD_2711_REG_SHIFT(p)	(((p) % 16) * 2)
70 
71 /* argument: bcm2835_pinconf_pull */
72 #define BCM2835_PINCONF_PARAM_PULL	(PIN_CONFIG_END + 1)
73 
74 #define BCM2711_PULL_NONE	0x0
75 #define BCM2711_PULL_UP		0x1
76 #define BCM2711_PULL_DOWN	0x2
77 
78 struct bcm2835_pinctrl {
79 	struct device *dev;
80 	void __iomem *base;
81 	int *wake_irq;
82 
83 	/* note: locking assumes each bank will have its own unsigned long */
84 	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
85 	unsigned int irq_type[BCM2711_NUM_GPIOS];
86 
87 	struct pinctrl_dev *pctl_dev;
88 	struct gpio_chip gpio_chip;
89 	struct pinctrl_desc pctl_desc;
90 	struct pinctrl_gpio_range gpio_range;
91 
92 	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
93 };
94 
95 /* pins are just named GPIO0..GPIO53 */
96 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
97 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
98 	BCM2835_GPIO_PIN(0),
99 	BCM2835_GPIO_PIN(1),
100 	BCM2835_GPIO_PIN(2),
101 	BCM2835_GPIO_PIN(3),
102 	BCM2835_GPIO_PIN(4),
103 	BCM2835_GPIO_PIN(5),
104 	BCM2835_GPIO_PIN(6),
105 	BCM2835_GPIO_PIN(7),
106 	BCM2835_GPIO_PIN(8),
107 	BCM2835_GPIO_PIN(9),
108 	BCM2835_GPIO_PIN(10),
109 	BCM2835_GPIO_PIN(11),
110 	BCM2835_GPIO_PIN(12),
111 	BCM2835_GPIO_PIN(13),
112 	BCM2835_GPIO_PIN(14),
113 	BCM2835_GPIO_PIN(15),
114 	BCM2835_GPIO_PIN(16),
115 	BCM2835_GPIO_PIN(17),
116 	BCM2835_GPIO_PIN(18),
117 	BCM2835_GPIO_PIN(19),
118 	BCM2835_GPIO_PIN(20),
119 	BCM2835_GPIO_PIN(21),
120 	BCM2835_GPIO_PIN(22),
121 	BCM2835_GPIO_PIN(23),
122 	BCM2835_GPIO_PIN(24),
123 	BCM2835_GPIO_PIN(25),
124 	BCM2835_GPIO_PIN(26),
125 	BCM2835_GPIO_PIN(27),
126 	BCM2835_GPIO_PIN(28),
127 	BCM2835_GPIO_PIN(29),
128 	BCM2835_GPIO_PIN(30),
129 	BCM2835_GPIO_PIN(31),
130 	BCM2835_GPIO_PIN(32),
131 	BCM2835_GPIO_PIN(33),
132 	BCM2835_GPIO_PIN(34),
133 	BCM2835_GPIO_PIN(35),
134 	BCM2835_GPIO_PIN(36),
135 	BCM2835_GPIO_PIN(37),
136 	BCM2835_GPIO_PIN(38),
137 	BCM2835_GPIO_PIN(39),
138 	BCM2835_GPIO_PIN(40),
139 	BCM2835_GPIO_PIN(41),
140 	BCM2835_GPIO_PIN(42),
141 	BCM2835_GPIO_PIN(43),
142 	BCM2835_GPIO_PIN(44),
143 	BCM2835_GPIO_PIN(45),
144 	BCM2835_GPIO_PIN(46),
145 	BCM2835_GPIO_PIN(47),
146 	BCM2835_GPIO_PIN(48),
147 	BCM2835_GPIO_PIN(49),
148 	BCM2835_GPIO_PIN(50),
149 	BCM2835_GPIO_PIN(51),
150 	BCM2835_GPIO_PIN(52),
151 	BCM2835_GPIO_PIN(53),
152 	BCM2835_GPIO_PIN(54),
153 	BCM2835_GPIO_PIN(55),
154 	BCM2835_GPIO_PIN(56),
155 	BCM2835_GPIO_PIN(57),
156 };
157 
158 /* one pin per group */
159 static const char * const bcm2835_gpio_groups[] = {
160 	"gpio0",
161 	"gpio1",
162 	"gpio2",
163 	"gpio3",
164 	"gpio4",
165 	"gpio5",
166 	"gpio6",
167 	"gpio7",
168 	"gpio8",
169 	"gpio9",
170 	"gpio10",
171 	"gpio11",
172 	"gpio12",
173 	"gpio13",
174 	"gpio14",
175 	"gpio15",
176 	"gpio16",
177 	"gpio17",
178 	"gpio18",
179 	"gpio19",
180 	"gpio20",
181 	"gpio21",
182 	"gpio22",
183 	"gpio23",
184 	"gpio24",
185 	"gpio25",
186 	"gpio26",
187 	"gpio27",
188 	"gpio28",
189 	"gpio29",
190 	"gpio30",
191 	"gpio31",
192 	"gpio32",
193 	"gpio33",
194 	"gpio34",
195 	"gpio35",
196 	"gpio36",
197 	"gpio37",
198 	"gpio38",
199 	"gpio39",
200 	"gpio40",
201 	"gpio41",
202 	"gpio42",
203 	"gpio43",
204 	"gpio44",
205 	"gpio45",
206 	"gpio46",
207 	"gpio47",
208 	"gpio48",
209 	"gpio49",
210 	"gpio50",
211 	"gpio51",
212 	"gpio52",
213 	"gpio53",
214 	"gpio54",
215 	"gpio55",
216 	"gpio56",
217 	"gpio57",
218 };
219 
220 enum bcm2835_fsel {
221 	BCM2835_FSEL_COUNT = 8,
222 	BCM2835_FSEL_MASK = 0x7,
223 };
224 
225 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
226 	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
227 	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
228 	[BCM2835_FSEL_ALT0] = "alt0",
229 	[BCM2835_FSEL_ALT1] = "alt1",
230 	[BCM2835_FSEL_ALT2] = "alt2",
231 	[BCM2835_FSEL_ALT3] = "alt3",
232 	[BCM2835_FSEL_ALT4] = "alt4",
233 	[BCM2835_FSEL_ALT5] = "alt5",
234 };
235 
236 static const char * const irq_type_names[] = {
237 	[IRQ_TYPE_NONE] = "none",
238 	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
239 	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
240 	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
241 	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
242 	[IRQ_TYPE_LEVEL_LOW] = "level-low",
243 };
244 
245 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
246 {
247 	return readl(pc->base + reg);
248 }
249 
250 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
251 		u32 val)
252 {
253 	writel(val, pc->base + reg);
254 }
255 
256 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
257 		unsigned bit)
258 {
259 	reg += GPIO_REG_OFFSET(bit) * 4;
260 	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
261 }
262 
263 /* note NOT a read/modify/write cycle */
264 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
265 		unsigned reg, unsigned bit)
266 {
267 	reg += GPIO_REG_OFFSET(bit) * 4;
268 	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
269 }
270 
271 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
272 		struct bcm2835_pinctrl *pc, unsigned pin)
273 {
274 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
275 	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
276 
277 	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
278 			bcm2835_functions[status]);
279 
280 	return status;
281 }
282 
283 static inline void bcm2835_pinctrl_fsel_set(
284 		struct bcm2835_pinctrl *pc, unsigned pin,
285 		enum bcm2835_fsel fsel)
286 {
287 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
288 	enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
289 
290 	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
291 			bcm2835_functions[cur]);
292 
293 	if (cur == fsel)
294 		return;
295 
296 	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
297 		/* always transition through GPIO_IN */
298 		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
299 		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
300 
301 		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
302 				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
303 		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
304 	}
305 
306 	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
307 	val |= fsel << FSEL_SHIFT(pin);
308 
309 	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
310 			bcm2835_functions[fsel]);
311 	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
312 }
313 
314 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
315 {
316 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
317 
318 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
319 	return 0;
320 }
321 
322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
323 {
324 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
325 
326 	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
327 }
328 
329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
330 {
331 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
332 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
333 
334 	/* Alternative function doesn't clearly provide a direction */
335 	if (fsel > BCM2835_FSEL_GPIO_OUT)
336 		return -EINVAL;
337 
338 	if (fsel == BCM2835_FSEL_GPIO_IN)
339 		return GPIO_LINE_DIRECTION_IN;
340 
341 	return GPIO_LINE_DIRECTION_OUT;
342 }
343 
344 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
345 {
346 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
347 
348 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
349 }
350 
351 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
352 		unsigned offset, int value)
353 {
354 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
355 
356 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
357 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
358 	return 0;
359 }
360 
361 static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc)
362 {
363 	struct device_node *np = dev_of_node(gc->parent);
364 	struct pinctrl_dev *pctldev = of_pinctrl_get(np);
365 
366 	if (!pctldev)
367 		return 0;
368 
369 	gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
370 			       gc->ngpio);
371 
372 	return 0;
373 }
374 
375 static const struct gpio_chip bcm2835_gpio_chip = {
376 	.label = MODULE_NAME,
377 	.owner = THIS_MODULE,
378 	.request = gpiochip_generic_request,
379 	.free = gpiochip_generic_free,
380 	.direction_input = bcm2835_gpio_direction_input,
381 	.direction_output = bcm2835_gpio_direction_output,
382 	.get_direction = bcm2835_gpio_get_direction,
383 	.get = bcm2835_gpio_get,
384 	.set = bcm2835_gpio_set,
385 	.set_config = gpiochip_generic_config,
386 	.base = -1,
387 	.ngpio = BCM2835_NUM_GPIOS,
388 	.can_sleep = false,
389 	.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
390 };
391 
392 static const struct gpio_chip bcm2711_gpio_chip = {
393 	.label = "pinctrl-bcm2711",
394 	.owner = THIS_MODULE,
395 	.request = gpiochip_generic_request,
396 	.free = gpiochip_generic_free,
397 	.direction_input = bcm2835_gpio_direction_input,
398 	.direction_output = bcm2835_gpio_direction_output,
399 	.get_direction = bcm2835_gpio_get_direction,
400 	.get = bcm2835_gpio_get,
401 	.set = bcm2835_gpio_set,
402 	.set_config = gpiochip_generic_config,
403 	.base = -1,
404 	.ngpio = BCM2711_NUM_GPIOS,
405 	.can_sleep = false,
406 	.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
407 };
408 
409 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
410 					 unsigned int bank, u32 mask)
411 {
412 	unsigned long events;
413 	unsigned offset;
414 	unsigned gpio;
415 
416 	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
417 	events &= mask;
418 	events &= pc->enabled_irq_map[bank];
419 	for_each_set_bit(offset, &events, 32) {
420 		gpio = (32 * bank) + offset;
421 		generic_handle_domain_irq(pc->gpio_chip.irq.domain,
422 					  gpio);
423 	}
424 }
425 
426 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
427 {
428 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
429 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
430 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
431 	int irq = irq_desc_get_irq(desc);
432 	int group = 0;
433 	int i;
434 
435 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
436 		if (chip->irq.parents[i] == irq) {
437 			group = i;
438 			break;
439 		}
440 	}
441 	/* This should not happen, every IRQ has a bank */
442 	BUG_ON(i == BCM2835_NUM_IRQS);
443 
444 	chained_irq_enter(host_chip, desc);
445 
446 	switch (group) {
447 	case 0: /* IRQ0 covers GPIOs 0-27 */
448 		bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
449 		break;
450 	case 1: /* IRQ1 covers GPIOs 28-45 */
451 		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
452 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
453 		break;
454 	case 2: /* IRQ2 covers GPIOs 46-57 */
455 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
456 		break;
457 	}
458 
459 	chained_irq_exit(host_chip, desc);
460 }
461 
462 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
463 {
464 	return IRQ_HANDLED;
465 }
466 
467 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
468 	unsigned reg, unsigned offset, bool enable)
469 {
470 	u32 value;
471 	reg += GPIO_REG_OFFSET(offset) * 4;
472 	value = bcm2835_gpio_rd(pc, reg);
473 	if (enable)
474 		value |= BIT(GPIO_REG_SHIFT(offset));
475 	else
476 		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
477 	bcm2835_gpio_wr(pc, reg, value);
478 }
479 
480 /* fast path for IRQ handler */
481 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
482 	unsigned offset, bool enable)
483 {
484 	switch (pc->irq_type[offset]) {
485 	case IRQ_TYPE_EDGE_RISING:
486 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
487 		break;
488 
489 	case IRQ_TYPE_EDGE_FALLING:
490 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
491 		break;
492 
493 	case IRQ_TYPE_EDGE_BOTH:
494 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
495 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
496 		break;
497 
498 	case IRQ_TYPE_LEVEL_HIGH:
499 		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
500 		break;
501 
502 	case IRQ_TYPE_LEVEL_LOW:
503 		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
504 		break;
505 	}
506 }
507 
508 static void bcm2835_gpio_irq_unmask(struct irq_data *data)
509 {
510 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
511 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
512 	unsigned gpio = irqd_to_hwirq(data);
513 	unsigned offset = GPIO_REG_SHIFT(gpio);
514 	unsigned bank = GPIO_REG_OFFSET(gpio);
515 	unsigned long flags;
516 
517 	gpiochip_enable_irq(chip, gpio);
518 
519 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
520 	set_bit(offset, &pc->enabled_irq_map[bank]);
521 	bcm2835_gpio_irq_config(pc, gpio, true);
522 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
523 }
524 
525 static void bcm2835_gpio_irq_mask(struct irq_data *data)
526 {
527 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
528 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
529 	unsigned gpio = irqd_to_hwirq(data);
530 	unsigned offset = GPIO_REG_SHIFT(gpio);
531 	unsigned bank = GPIO_REG_OFFSET(gpio);
532 	unsigned long flags;
533 
534 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
535 	bcm2835_gpio_irq_config(pc, gpio, false);
536 	/* Clear events that were latched prior to clearing event sources */
537 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
538 	clear_bit(offset, &pc->enabled_irq_map[bank]);
539 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
540 
541 	gpiochip_disable_irq(chip, gpio);
542 }
543 
544 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
545 	unsigned offset, unsigned int type)
546 {
547 	switch (type) {
548 	case IRQ_TYPE_NONE:
549 	case IRQ_TYPE_EDGE_RISING:
550 	case IRQ_TYPE_EDGE_FALLING:
551 	case IRQ_TYPE_EDGE_BOTH:
552 	case IRQ_TYPE_LEVEL_HIGH:
553 	case IRQ_TYPE_LEVEL_LOW:
554 		pc->irq_type[offset] = type;
555 		break;
556 
557 	default:
558 		return -EINVAL;
559 	}
560 	return 0;
561 }
562 
563 /* slower path for reconfiguring IRQ type */
564 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
565 	unsigned offset, unsigned int type)
566 {
567 	switch (type) {
568 	case IRQ_TYPE_NONE:
569 		if (pc->irq_type[offset] != type) {
570 			bcm2835_gpio_irq_config(pc, offset, false);
571 			pc->irq_type[offset] = type;
572 		}
573 		break;
574 
575 	case IRQ_TYPE_EDGE_RISING:
576 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
577 			/* RISING already enabled, disable FALLING */
578 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
579 			bcm2835_gpio_irq_config(pc, offset, false);
580 			pc->irq_type[offset] = type;
581 		} else if (pc->irq_type[offset] != type) {
582 			bcm2835_gpio_irq_config(pc, offset, false);
583 			pc->irq_type[offset] = type;
584 			bcm2835_gpio_irq_config(pc, offset, true);
585 		}
586 		break;
587 
588 	case IRQ_TYPE_EDGE_FALLING:
589 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
590 			/* FALLING already enabled, disable RISING */
591 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
592 			bcm2835_gpio_irq_config(pc, offset, false);
593 			pc->irq_type[offset] = type;
594 		} else if (pc->irq_type[offset] != type) {
595 			bcm2835_gpio_irq_config(pc, offset, false);
596 			pc->irq_type[offset] = type;
597 			bcm2835_gpio_irq_config(pc, offset, true);
598 		}
599 		break;
600 
601 	case IRQ_TYPE_EDGE_BOTH:
602 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
603 			/* RISING already enabled, enable FALLING too */
604 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
605 			bcm2835_gpio_irq_config(pc, offset, true);
606 			pc->irq_type[offset] = type;
607 		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
608 			/* FALLING already enabled, enable RISING too */
609 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
610 			bcm2835_gpio_irq_config(pc, offset, true);
611 			pc->irq_type[offset] = type;
612 		} else if (pc->irq_type[offset] != type) {
613 			bcm2835_gpio_irq_config(pc, offset, false);
614 			pc->irq_type[offset] = type;
615 			bcm2835_gpio_irq_config(pc, offset, true);
616 		}
617 		break;
618 
619 	case IRQ_TYPE_LEVEL_HIGH:
620 	case IRQ_TYPE_LEVEL_LOW:
621 		if (pc->irq_type[offset] != type) {
622 			bcm2835_gpio_irq_config(pc, offset, false);
623 			pc->irq_type[offset] = type;
624 			bcm2835_gpio_irq_config(pc, offset, true);
625 		}
626 		break;
627 
628 	default:
629 		return -EINVAL;
630 	}
631 	return 0;
632 }
633 
634 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
635 {
636 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
637 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
638 	unsigned gpio = irqd_to_hwirq(data);
639 	unsigned offset = GPIO_REG_SHIFT(gpio);
640 	unsigned bank = GPIO_REG_OFFSET(gpio);
641 	unsigned long flags;
642 	int ret;
643 
644 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
645 
646 	if (test_bit(offset, &pc->enabled_irq_map[bank]))
647 		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
648 	else
649 		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
650 
651 	if (type & IRQ_TYPE_EDGE_BOTH)
652 		irq_set_handler_locked(data, handle_edge_irq);
653 	else
654 		irq_set_handler_locked(data, handle_level_irq);
655 
656 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
657 
658 	return ret;
659 }
660 
661 static void bcm2835_gpio_irq_ack(struct irq_data *data)
662 {
663 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
664 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
665 	unsigned gpio = irqd_to_hwirq(data);
666 
667 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
668 }
669 
670 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
671 {
672 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
673 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
674 	unsigned gpio = irqd_to_hwirq(data);
675 	unsigned int irqgroup;
676 	int ret = -EINVAL;
677 
678 	if (!pc->wake_irq)
679 		return ret;
680 
681 	if (gpio <= 27)
682 		irqgroup = 0;
683 	else if (gpio >= 28 && gpio <= 45)
684 		irqgroup = 1;
685 	else if (gpio >= 46 && gpio <= 57)
686 		irqgroup = 2;
687 	else
688 		return ret;
689 
690 	if (on)
691 		ret = enable_irq_wake(pc->wake_irq[irqgroup]);
692 	else
693 		ret = disable_irq_wake(pc->wake_irq[irqgroup]);
694 
695 	return ret;
696 }
697 
698 static const struct irq_chip bcm2835_gpio_irq_chip = {
699 	.name = MODULE_NAME,
700 	.irq_set_type = bcm2835_gpio_irq_set_type,
701 	.irq_ack = bcm2835_gpio_irq_ack,
702 	.irq_mask = bcm2835_gpio_irq_mask,
703 	.irq_unmask = bcm2835_gpio_irq_unmask,
704 	.irq_set_wake = bcm2835_gpio_irq_set_wake,
705 	.flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
706 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
707 };
708 
709 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
710 {
711 	return BCM2835_NUM_GPIOS;
712 }
713 
714 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
715 		unsigned selector)
716 {
717 	return bcm2835_gpio_groups[selector];
718 }
719 
720 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
721 		unsigned selector,
722 		const unsigned **pins,
723 		unsigned *num_pins)
724 {
725 	*pins = &bcm2835_gpio_pins[selector].number;
726 	*num_pins = 1;
727 
728 	return 0;
729 }
730 
731 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
732 		struct seq_file *s,
733 		unsigned offset)
734 {
735 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
736 	struct gpio_chip *chip = &pc->gpio_chip;
737 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
738 	const char *fname = bcm2835_functions[fsel];
739 	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
740 	int irq = irq_find_mapping(chip->irq.domain, offset);
741 
742 	seq_printf(s, "function %s in %s; irq %d (%s)",
743 		fname, value ? "hi" : "lo",
744 		irq, irq_type_names[pc->irq_type[offset]]);
745 }
746 
747 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
748 		struct pinctrl_map *maps, unsigned num_maps)
749 {
750 	int i;
751 
752 	for (i = 0; i < num_maps; i++)
753 		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
754 			kfree(maps[i].data.configs.configs);
755 
756 	kfree(maps);
757 }
758 
759 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
760 		struct device_node *np, u32 pin, u32 fnum,
761 		struct pinctrl_map **maps)
762 {
763 	struct pinctrl_map *map = *maps;
764 
765 	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
766 		dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
767 		return -EINVAL;
768 	}
769 
770 	map->type = PIN_MAP_TYPE_MUX_GROUP;
771 	map->data.mux.group = bcm2835_gpio_groups[pin];
772 	map->data.mux.function = bcm2835_functions[fnum];
773 	(*maps)++;
774 
775 	return 0;
776 }
777 
778 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
779 		struct device_node *np, u32 pin, u32 pull,
780 		struct pinctrl_map **maps)
781 {
782 	struct pinctrl_map *map = *maps;
783 	unsigned long *configs;
784 
785 	if (pull > 2) {
786 		dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
787 		return -EINVAL;
788 	}
789 
790 	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
791 	if (!configs)
792 		return -ENOMEM;
793 	configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
794 
795 	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
796 	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
797 	map->data.configs.configs = configs;
798 	map->data.configs.num_configs = 1;
799 	(*maps)++;
800 
801 	return 0;
802 }
803 
804 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
805 		struct device_node *np,
806 		struct pinctrl_map **map, unsigned int *num_maps)
807 {
808 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
809 	struct property *pins, *funcs, *pulls;
810 	int num_pins, num_funcs, num_pulls, maps_per_pin;
811 	struct pinctrl_map *maps, *cur_map;
812 	int i, err;
813 	u32 pin, func, pull;
814 
815 	/* Check for generic binding in this node */
816 	err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
817 	if (err || *num_maps)
818 		return err;
819 
820 	/* Generic binding did not find anything continue with legacy parse */
821 	pins = of_find_property(np, "brcm,pins", NULL);
822 	if (!pins) {
823 		dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
824 		return -EINVAL;
825 	}
826 
827 	funcs = of_find_property(np, "brcm,function", NULL);
828 	pulls = of_find_property(np, "brcm,pull", NULL);
829 
830 	if (!funcs && !pulls) {
831 		dev_err(pc->dev,
832 			"%pOF: neither brcm,function nor brcm,pull specified\n",
833 			np);
834 		return -EINVAL;
835 	}
836 
837 	num_pins = pins->length / 4;
838 	num_funcs = funcs ? (funcs->length / 4) : 0;
839 	num_pulls = pulls ? (pulls->length / 4) : 0;
840 
841 	if (num_funcs > 1 && num_funcs != num_pins) {
842 		dev_err(pc->dev,
843 			"%pOF: brcm,function must have 1 or %d entries\n",
844 			np, num_pins);
845 		return -EINVAL;
846 	}
847 
848 	if (num_pulls > 1 && num_pulls != num_pins) {
849 		dev_err(pc->dev,
850 			"%pOF: brcm,pull must have 1 or %d entries\n",
851 			np, num_pins);
852 		return -EINVAL;
853 	}
854 
855 	maps_per_pin = 0;
856 	if (num_funcs)
857 		maps_per_pin++;
858 	if (num_pulls)
859 		maps_per_pin++;
860 	cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
861 				 GFP_KERNEL);
862 	if (!maps)
863 		return -ENOMEM;
864 
865 	for (i = 0; i < num_pins; i++) {
866 		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
867 		if (err)
868 			goto out;
869 		if (pin >= pc->pctl_desc.npins) {
870 			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
871 				np, pin);
872 			err = -EINVAL;
873 			goto out;
874 		}
875 
876 		if (num_funcs) {
877 			err = of_property_read_u32_index(np, "brcm,function",
878 					(num_funcs > 1) ? i : 0, &func);
879 			if (err)
880 				goto out;
881 			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
882 							func, &cur_map);
883 			if (err)
884 				goto out;
885 		}
886 		if (num_pulls) {
887 			err = of_property_read_u32_index(np, "brcm,pull",
888 					(num_pulls > 1) ? i : 0, &pull);
889 			if (err)
890 				goto out;
891 			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
892 							pull, &cur_map);
893 			if (err)
894 				goto out;
895 		}
896 	}
897 
898 	*map = maps;
899 	*num_maps = num_pins * maps_per_pin;
900 
901 	return 0;
902 
903 out:
904 	bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
905 	return err;
906 }
907 
908 static const struct pinctrl_ops bcm2835_pctl_ops = {
909 	.get_groups_count = bcm2835_pctl_get_groups_count,
910 	.get_group_name = bcm2835_pctl_get_group_name,
911 	.get_group_pins = bcm2835_pctl_get_group_pins,
912 	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
913 	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
914 	.dt_free_map = bcm2835_pctl_dt_free_map,
915 };
916 
917 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
918 		unsigned offset)
919 {
920 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
921 
922 	/* disable by setting to GPIO_IN */
923 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
924 	return 0;
925 }
926 
927 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
928 {
929 	return BCM2835_FSEL_COUNT;
930 }
931 
932 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
933 		unsigned selector)
934 {
935 	return bcm2835_functions[selector];
936 }
937 
938 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
939 		unsigned selector,
940 		const char * const **groups,
941 		unsigned * const num_groups)
942 {
943 	/* every pin can do every function */
944 	*groups = bcm2835_gpio_groups;
945 	*num_groups = BCM2835_NUM_GPIOS;
946 
947 	return 0;
948 }
949 
950 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
951 		unsigned func_selector,
952 		unsigned group_selector)
953 {
954 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
955 
956 	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
957 
958 	return 0;
959 }
960 
961 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
962 		struct pinctrl_gpio_range *range,
963 		unsigned offset)
964 {
965 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
966 
967 	/* disable by setting to GPIO_IN */
968 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
969 }
970 
971 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
972 		struct pinctrl_gpio_range *range,
973 		unsigned offset,
974 		bool input)
975 {
976 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
977 	enum bcm2835_fsel fsel = input ?
978 		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
979 
980 	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
981 
982 	return 0;
983 }
984 
985 static const struct pinmux_ops bcm2835_pmx_ops = {
986 	.free = bcm2835_pmx_free,
987 	.get_functions_count = bcm2835_pmx_get_functions_count,
988 	.get_function_name = bcm2835_pmx_get_function_name,
989 	.get_function_groups = bcm2835_pmx_get_function_groups,
990 	.set_mux = bcm2835_pmx_set,
991 	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
992 	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
993 };
994 
995 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
996 			unsigned pin, unsigned long *config)
997 {
998 	/* No way to read back config in HW */
999 	return -ENOTSUPP;
1000 }
1001 
1002 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1003 		unsigned int pin, unsigned int arg)
1004 {
1005 	u32 off, bit;
1006 
1007 	off = GPIO_REG_OFFSET(pin);
1008 	bit = GPIO_REG_SHIFT(pin);
1009 
1010 	bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1011 	/*
1012 	 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1013 	 * But the VideoCore firmware delay for this operation
1014 	 * based nearly on the same amount of VPU cycles and this clock
1015 	 * runs at 250 MHz.
1016 	 */
1017 	udelay(1);
1018 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1019 	udelay(1);
1020 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1021 }
1022 
1023 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1024 			unsigned int pin, unsigned long *configs,
1025 			unsigned int num_configs)
1026 {
1027 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1028 	u32 param, arg;
1029 	int i;
1030 
1031 	for (i = 0; i < num_configs; i++) {
1032 		param = pinconf_to_config_param(configs[i]);
1033 		arg = pinconf_to_config_argument(configs[i]);
1034 
1035 		switch (param) {
1036 		/* Set legacy brcm,pull */
1037 		case BCM2835_PINCONF_PARAM_PULL:
1038 			bcm2835_pull_config_set(pc, pin, arg);
1039 			break;
1040 
1041 		/* Set pull generic bindings */
1042 		case PIN_CONFIG_BIAS_DISABLE:
1043 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1044 			break;
1045 
1046 		case PIN_CONFIG_BIAS_PULL_DOWN:
1047 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1048 			break;
1049 
1050 		case PIN_CONFIG_BIAS_PULL_UP:
1051 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1052 			break;
1053 
1054 		/* Set output-high or output-low */
1055 		case PIN_CONFIG_OUTPUT:
1056 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1057 			break;
1058 
1059 		default:
1060 			return -ENOTSUPP;
1061 
1062 		} /* switch param type */
1063 	} /* for each config */
1064 
1065 	return 0;
1066 }
1067 
1068 static const struct pinconf_ops bcm2835_pinconf_ops = {
1069 	.is_generic = true,
1070 	.pin_config_get = bcm2835_pinconf_get,
1071 	.pin_config_set = bcm2835_pinconf_set,
1072 };
1073 
1074 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1075 				    unsigned int pin, unsigned int arg)
1076 {
1077 	u32 shifter;
1078 	u32 value;
1079 	u32 off;
1080 
1081 	off = PUD_2711_REG_OFFSET(pin);
1082 	shifter = PUD_2711_REG_SHIFT(pin);
1083 
1084 	value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1085 	value &= ~(PUD_2711_MASK << shifter);
1086 	value |= (arg << shifter);
1087 	bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1088 }
1089 
1090 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1091 			       unsigned int pin, unsigned long *configs,
1092 			       unsigned int num_configs)
1093 {
1094 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1095 	u32 param, arg;
1096 	int i;
1097 
1098 	for (i = 0; i < num_configs; i++) {
1099 		param = pinconf_to_config_param(configs[i]);
1100 		arg = pinconf_to_config_argument(configs[i]);
1101 
1102 		switch (param) {
1103 		/* convert legacy brcm,pull */
1104 		case BCM2835_PINCONF_PARAM_PULL:
1105 			if (arg == BCM2835_PUD_UP)
1106 				arg = BCM2711_PULL_UP;
1107 			else if (arg == BCM2835_PUD_DOWN)
1108 				arg = BCM2711_PULL_DOWN;
1109 			else
1110 				arg = BCM2711_PULL_NONE;
1111 
1112 			bcm2711_pull_config_set(pc, pin, arg);
1113 			break;
1114 
1115 		/* Set pull generic bindings */
1116 		case PIN_CONFIG_BIAS_DISABLE:
1117 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1118 			break;
1119 		case PIN_CONFIG_BIAS_PULL_DOWN:
1120 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1121 			break;
1122 		case PIN_CONFIG_BIAS_PULL_UP:
1123 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1124 			break;
1125 
1126 		/* Set output-high or output-low */
1127 		case PIN_CONFIG_OUTPUT:
1128 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1129 			break;
1130 
1131 		default:
1132 			return -ENOTSUPP;
1133 		}
1134 	} /* for each config */
1135 
1136 	return 0;
1137 }
1138 
1139 static const struct pinconf_ops bcm2711_pinconf_ops = {
1140 	.is_generic = true,
1141 	.pin_config_get = bcm2835_pinconf_get,
1142 	.pin_config_set = bcm2711_pinconf_set,
1143 };
1144 
1145 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1146 	.name = MODULE_NAME,
1147 	.pins = bcm2835_gpio_pins,
1148 	.npins = BCM2835_NUM_GPIOS,
1149 	.pctlops = &bcm2835_pctl_ops,
1150 	.pmxops = &bcm2835_pmx_ops,
1151 	.confops = &bcm2835_pinconf_ops,
1152 	.owner = THIS_MODULE,
1153 };
1154 
1155 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1156 	.name = "pinctrl-bcm2711",
1157 	.pins = bcm2835_gpio_pins,
1158 	.npins = BCM2711_NUM_GPIOS,
1159 	.pctlops = &bcm2835_pctl_ops,
1160 	.pmxops = &bcm2835_pmx_ops,
1161 	.confops = &bcm2711_pinconf_ops,
1162 	.owner = THIS_MODULE,
1163 };
1164 
1165 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1166 	.name = MODULE_NAME,
1167 	.npins = BCM2835_NUM_GPIOS,
1168 };
1169 
1170 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1171 	.name = "pinctrl-bcm2711",
1172 	.npins = BCM2711_NUM_GPIOS,
1173 };
1174 
1175 struct bcm_plat_data {
1176 	const struct gpio_chip *gpio_chip;
1177 	const struct pinctrl_desc *pctl_desc;
1178 	const struct pinctrl_gpio_range *gpio_range;
1179 };
1180 
1181 static const struct bcm_plat_data bcm2835_plat_data = {
1182 	.gpio_chip = &bcm2835_gpio_chip,
1183 	.pctl_desc = &bcm2835_pinctrl_desc,
1184 	.gpio_range = &bcm2835_pinctrl_gpio_range,
1185 };
1186 
1187 static const struct bcm_plat_data bcm2711_plat_data = {
1188 	.gpio_chip = &bcm2711_gpio_chip,
1189 	.pctl_desc = &bcm2711_pinctrl_desc,
1190 	.gpio_range = &bcm2711_pinctrl_gpio_range,
1191 };
1192 
1193 static const struct of_device_id bcm2835_pinctrl_match[] = {
1194 	{
1195 		.compatible = "brcm,bcm2835-gpio",
1196 		.data = &bcm2835_plat_data,
1197 	},
1198 	{
1199 		.compatible = "brcm,bcm2711-gpio",
1200 		.data = &bcm2711_plat_data,
1201 	},
1202 	{
1203 		.compatible = "brcm,bcm7211-gpio",
1204 		.data = &bcm2711_plat_data,
1205 	},
1206 	{}
1207 };
1208 
1209 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1210 {
1211 	struct device *dev = &pdev->dev;
1212 	struct device_node *np = dev->of_node;
1213 	const struct bcm_plat_data *pdata;
1214 	struct bcm2835_pinctrl *pc;
1215 	struct gpio_irq_chip *girq;
1216 	struct resource iomem;
1217 	int err, i;
1218 	const struct of_device_id *match;
1219 	int is_7211 = 0;
1220 
1221 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1222 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1223 
1224 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1225 	if (!pc)
1226 		return -ENOMEM;
1227 
1228 	platform_set_drvdata(pdev, pc);
1229 	pc->dev = dev;
1230 
1231 	err = of_address_to_resource(np, 0, &iomem);
1232 	if (err) {
1233 		dev_err(dev, "could not get IO memory\n");
1234 		return err;
1235 	}
1236 
1237 	pc->base = devm_ioremap_resource(dev, &iomem);
1238 	if (IS_ERR(pc->base))
1239 		return PTR_ERR(pc->base);
1240 
1241 	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1242 	if (!match)
1243 		return -EINVAL;
1244 
1245 	pdata = match->data;
1246 	is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1247 
1248 	pc->gpio_chip = *pdata->gpio_chip;
1249 	pc->gpio_chip.parent = dev;
1250 
1251 	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1252 		unsigned long events;
1253 		unsigned offset;
1254 
1255 		/* clear event detection flags */
1256 		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1257 		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1258 		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1259 		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1260 		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1261 		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1262 
1263 		/* clear all the events */
1264 		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1265 		for_each_set_bit(offset, &events, 32)
1266 			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1267 
1268 		raw_spin_lock_init(&pc->irq_lock[i]);
1269 	}
1270 
1271 	pc->pctl_desc = *pdata->pctl_desc;
1272 	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1273 	if (IS_ERR(pc->pctl_dev)) {
1274 		gpiochip_remove(&pc->gpio_chip);
1275 		return PTR_ERR(pc->pctl_dev);
1276 	}
1277 
1278 	pc->gpio_range = *pdata->gpio_range;
1279 	pc->gpio_range.base = pc->gpio_chip.base;
1280 	pc->gpio_range.gc = &pc->gpio_chip;
1281 	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1282 
1283 	girq = &pc->gpio_chip.irq;
1284 	gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
1285 	girq->parent_handler = bcm2835_gpio_irq_handler;
1286 	girq->num_parents = BCM2835_NUM_IRQS;
1287 	girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1288 				     sizeof(*girq->parents),
1289 				     GFP_KERNEL);
1290 	if (!girq->parents) {
1291 		err = -ENOMEM;
1292 		goto out_remove;
1293 	}
1294 
1295 	if (is_7211) {
1296 		pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1297 					    sizeof(*pc->wake_irq),
1298 					    GFP_KERNEL);
1299 		if (!pc->wake_irq) {
1300 			err = -ENOMEM;
1301 			goto out_remove;
1302 		}
1303 	}
1304 
1305 	/*
1306 	 * Use the same handler for all groups: this is necessary
1307 	 * since we use one gpiochip to cover all lines - the
1308 	 * irq handler then needs to figure out which group and
1309 	 * bank that was firing the IRQ and look up the per-group
1310 	 * and bank data.
1311 	 */
1312 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1313 		int len;
1314 		char *name;
1315 
1316 		girq->parents[i] = irq_of_parse_and_map(np, i);
1317 		if (!is_7211) {
1318 			if (!girq->parents[i]) {
1319 				girq->num_parents = i;
1320 				break;
1321 			}
1322 			continue;
1323 		}
1324 		/* Skip over the all banks interrupts */
1325 		pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1326 						       BCM2835_NUM_IRQS + 1);
1327 
1328 		len = strlen(dev_name(pc->dev)) + 16;
1329 		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1330 		if (!name) {
1331 			err = -ENOMEM;
1332 			goto out_remove;
1333 		}
1334 
1335 		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1336 
1337 		/* These are optional interrupts */
1338 		err = devm_request_irq(dev, pc->wake_irq[i],
1339 				       bcm2835_gpio_wake_irq_handler,
1340 				       IRQF_SHARED, name, pc);
1341 		if (err)
1342 			dev_warn(dev, "unable to request wake IRQ %d\n",
1343 				 pc->wake_irq[i]);
1344 	}
1345 
1346 	girq->default_type = IRQ_TYPE_NONE;
1347 	girq->handler = handle_level_irq;
1348 
1349 	err = gpiochip_add_data(&pc->gpio_chip, pc);
1350 	if (err) {
1351 		dev_err(dev, "could not add GPIO chip\n");
1352 		goto out_remove;
1353 	}
1354 
1355 	return 0;
1356 
1357 out_remove:
1358 	pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1359 	return err;
1360 }
1361 
1362 static struct platform_driver bcm2835_pinctrl_driver = {
1363 	.probe = bcm2835_pinctrl_probe,
1364 	.driver = {
1365 		.name = MODULE_NAME,
1366 		.of_match_table = bcm2835_pinctrl_match,
1367 		.suppress_bind_attrs = true,
1368 	},
1369 };
1370 module_platform_driver(bcm2835_pinctrl_driver);
1371 
1372 MODULE_AUTHOR("Chris Boot");
1373 MODULE_AUTHOR("Simon Arlott");
1374 MODULE_AUTHOR("Stephen Warren");
1375 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1376 MODULE_LICENSE("GPL");
1377