1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020 Linaro Ltd.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/seq_file.h>
14
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinmux.h>
18
19 #include "../pinctrl-utils.h"
20
21 #include "pinctrl-lpass-lpi.h"
22
23 #define MAX_NR_GPIO 23
24 #define GPIO_FUNC 0
25 #define MAX_LPI_NUM_CLKS 2
26
27 struct lpi_pinctrl {
28 struct device *dev;
29 struct pinctrl_dev *ctrl;
30 struct gpio_chip chip;
31 struct pinctrl_desc desc;
32 char __iomem *tlmm_base;
33 char __iomem *slew_base;
34 struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
35 /* Protects from concurrent register updates */
36 struct mutex lock;
37 DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
38 const struct lpi_pinctrl_variant_data *data;
39 };
40
lpi_gpio_read(struct lpi_pinctrl * state,unsigned int pin,unsigned int addr)41 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
42 unsigned int addr)
43 {
44 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
45 }
46
lpi_gpio_write(struct lpi_pinctrl * state,unsigned int pin,unsigned int addr,unsigned int val)47 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
48 unsigned int addr, unsigned int val)
49 {
50 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
51
52 return 0;
53 }
54
55 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
56 .get_groups_count = pinctrl_generic_get_group_count,
57 .get_group_name = pinctrl_generic_get_group_name,
58 .get_group_pins = pinctrl_generic_get_group_pins,
59 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
60 .dt_free_map = pinctrl_utils_free_map,
61 };
62
lpi_gpio_get_functions_count(struct pinctrl_dev * pctldev)63 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
64 {
65 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
66
67 return pctrl->data->nfunctions;
68 }
69
lpi_gpio_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)70 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
71 unsigned int function)
72 {
73 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
74
75 return pctrl->data->functions[function].name;
76 }
77
lpi_gpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned * const num_qgroups)78 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
79 unsigned int function,
80 const char *const **groups,
81 unsigned *const num_qgroups)
82 {
83 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
84
85 *groups = pctrl->data->functions[function].groups;
86 *num_qgroups = pctrl->data->functions[function].ngroups;
87
88 return 0;
89 }
90
lpi_gpio_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)91 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
92 unsigned int group)
93 {
94 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95 const struct lpi_pingroup *g = &pctrl->data->groups[group];
96 u32 val;
97 int i, pin = g->pin;
98
99 for (i = 0; i < g->nfuncs; i++) {
100 if (g->funcs[i] == function)
101 break;
102 }
103
104 if (WARN_ON(i == g->nfuncs))
105 return -EINVAL;
106
107 mutex_lock(&pctrl->lock);
108 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
109
110 /*
111 * If this is the first time muxing to GPIO and the direction is
112 * output, make sure that we're not going to be glitching the pin
113 * by reading the current state of the pin and setting it as the
114 * output.
115 */
116 if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
117 !test_and_set_bit(group, pctrl->ever_gpio)) {
118 u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);
119
120 if (io_val & LPI_GPIO_VALUE_IN_MASK) {
121 if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
122 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
123 io_val | LPI_GPIO_VALUE_OUT_MASK);
124 } else {
125 if (io_val & LPI_GPIO_VALUE_OUT_MASK)
126 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
127 io_val & ~LPI_GPIO_VALUE_OUT_MASK);
128 }
129 }
130
131 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
132 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
133 mutex_unlock(&pctrl->lock);
134
135 return 0;
136 }
137
138 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
139 .get_functions_count = lpi_gpio_get_functions_count,
140 .get_function_name = lpi_gpio_get_function_name,
141 .get_function_groups = lpi_gpio_get_function_groups,
142 .set_mux = lpi_gpio_set_mux,
143 };
144
lpi_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)145 static int lpi_config_get(struct pinctrl_dev *pctldev,
146 unsigned int pin, unsigned long *config)
147 {
148 unsigned int param = pinconf_to_config_param(*config);
149 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
150 unsigned int arg = 0;
151 int is_out;
152 int pull;
153 u32 ctl_reg;
154
155 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
156 is_out = ctl_reg & LPI_GPIO_OE_MASK;
157 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
158
159 switch (param) {
160 case PIN_CONFIG_BIAS_DISABLE:
161 if (pull == LPI_GPIO_BIAS_DISABLE)
162 arg = 1;
163 break;
164 case PIN_CONFIG_BIAS_PULL_DOWN:
165 if (pull == LPI_GPIO_PULL_DOWN)
166 arg = 1;
167 break;
168 case PIN_CONFIG_BIAS_BUS_HOLD:
169 if (pull == LPI_GPIO_KEEPER)
170 arg = 1;
171 break;
172 case PIN_CONFIG_BIAS_PULL_UP:
173 if (pull == LPI_GPIO_PULL_UP)
174 arg = 1;
175 break;
176 case PIN_CONFIG_INPUT_ENABLE:
177 case PIN_CONFIG_OUTPUT:
178 if (is_out)
179 arg = 1;
180 break;
181 default:
182 return -EINVAL;
183 }
184
185 *config = pinconf_to_config_packed(param, arg);
186 return 0;
187 }
188
lpi_config_set_slew_rate(struct lpi_pinctrl * pctrl,const struct lpi_pingroup * g,unsigned int group,unsigned int slew)189 static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
190 const struct lpi_pingroup *g,
191 unsigned int group, unsigned int slew)
192 {
193 unsigned long sval;
194 void __iomem *reg;
195 int slew_offset;
196
197 if (slew > LPI_SLEW_RATE_MAX) {
198 dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
199 slew, group);
200 return -EINVAL;
201 }
202
203 slew_offset = g->slew_offset;
204 if (slew_offset == LPI_NO_SLEW)
205 return 0;
206
207 if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
208 reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
209 else
210 reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
211
212 mutex_lock(&pctrl->lock);
213
214 sval = ioread32(reg);
215 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
216 sval |= slew << slew_offset;
217 iowrite32(sval, reg);
218
219 mutex_unlock(&pctrl->lock);
220
221 return 0;
222 }
223
lpi_config_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int nconfs)224 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
225 unsigned long *configs, unsigned int nconfs)
226 {
227 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
228 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
229 bool value, output_enabled = false;
230 const struct lpi_pingroup *g;
231 int i, ret;
232 u32 val;
233
234 g = &pctrl->data->groups[group];
235 for (i = 0; i < nconfs; i++) {
236 param = pinconf_to_config_param(configs[i]);
237 arg = pinconf_to_config_argument(configs[i]);
238
239 switch (param) {
240 case PIN_CONFIG_BIAS_DISABLE:
241 pullup = LPI_GPIO_BIAS_DISABLE;
242 break;
243 case PIN_CONFIG_BIAS_PULL_DOWN:
244 pullup = LPI_GPIO_PULL_DOWN;
245 break;
246 case PIN_CONFIG_BIAS_BUS_HOLD:
247 pullup = LPI_GPIO_KEEPER;
248 break;
249 case PIN_CONFIG_BIAS_PULL_UP:
250 pullup = LPI_GPIO_PULL_UP;
251 break;
252 case PIN_CONFIG_INPUT_ENABLE:
253 output_enabled = false;
254 break;
255 case PIN_CONFIG_OUTPUT:
256 output_enabled = true;
257 value = arg;
258 break;
259 case PIN_CONFIG_DRIVE_STRENGTH:
260 strength = arg;
261 break;
262 case PIN_CONFIG_SLEW_RATE:
263 ret = lpi_config_set_slew_rate(pctrl, g, group, arg);
264 if (ret)
265 return ret;
266 break;
267 default:
268 return -EINVAL;
269 }
270 }
271
272 /*
273 * As per Hardware Programming Guide, when configuring pin as output,
274 * set the pin value before setting output-enable (OE).
275 */
276 if (output_enabled) {
277 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
278 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
279 }
280
281 mutex_lock(&pctrl->lock);
282 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
283
284 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
285 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
286 LPI_GPIO_OUT_STRENGTH_MASK);
287 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
288
289 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
290 mutex_unlock(&pctrl->lock);
291
292 return 0;
293 }
294
295 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
296 .is_generic = true,
297 .pin_config_group_get = lpi_config_get,
298 .pin_config_group_set = lpi_config_set,
299 };
300
lpi_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)301 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
302 {
303 struct lpi_pinctrl *state = gpiochip_get_data(chip);
304 unsigned long config;
305
306 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
307
308 return lpi_config_set(state->ctrl, pin, &config, 1);
309 }
310
lpi_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int val)311 static int lpi_gpio_direction_output(struct gpio_chip *chip,
312 unsigned int pin, int val)
313 {
314 struct lpi_pinctrl *state = gpiochip_get_data(chip);
315 unsigned long config;
316
317 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
318
319 return lpi_config_set(state->ctrl, pin, &config, 1);
320 }
321
lpi_gpio_get(struct gpio_chip * chip,unsigned int pin)322 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
323 {
324 struct lpi_pinctrl *state = gpiochip_get_data(chip);
325
326 return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
327 LPI_GPIO_VALUE_IN_MASK;
328 }
329
lpi_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)330 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
331 {
332 struct lpi_pinctrl *state = gpiochip_get_data(chip);
333 unsigned long config;
334
335 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
336
337 lpi_config_set(state->ctrl, pin, &config, 1);
338 }
339
340 #ifdef CONFIG_DEBUG_FS
341
lpi_regval_to_drive(u32 val)342 static unsigned int lpi_regval_to_drive(u32 val)
343 {
344 return (val + 1) * 2;
345 }
346
lpi_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned int offset,unsigned int gpio)347 static void lpi_gpio_dbg_show_one(struct seq_file *s,
348 struct pinctrl_dev *pctldev,
349 struct gpio_chip *chip,
350 unsigned int offset,
351 unsigned int gpio)
352 {
353 struct lpi_pinctrl *state = gpiochip_get_data(chip);
354 struct pinctrl_pin_desc pindesc;
355 unsigned int func;
356 int is_out;
357 int drive;
358 int pull;
359 u32 ctl_reg;
360
361 static const char * const pulls[] = {
362 "no pull",
363 "pull down",
364 "keeper",
365 "pull up"
366 };
367
368 pctldev = pctldev ? : state->ctrl;
369 pindesc = pctldev->desc->pins[offset];
370 ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
371 is_out = ctl_reg & LPI_GPIO_OE_MASK;
372
373 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
374 drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
375 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
376
377 seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
378 seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
379 seq_printf(s, " %s", pulls[pull]);
380 }
381
lpi_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)382 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
383 {
384 unsigned int gpio = chip->base;
385 unsigned int i;
386
387 for (i = 0; i < chip->ngpio; i++, gpio++) {
388 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
389 seq_puts(s, "\n");
390 }
391 }
392
393 #else
394 #define lpi_gpio_dbg_show NULL
395 #endif
396
397 static const struct gpio_chip lpi_gpio_template = {
398 .direction_input = lpi_gpio_direction_input,
399 .direction_output = lpi_gpio_direction_output,
400 .get = lpi_gpio_get,
401 .set = lpi_gpio_set,
402 .request = gpiochip_generic_request,
403 .free = gpiochip_generic_free,
404 .dbg_show = lpi_gpio_dbg_show,
405 };
406
lpi_build_pin_desc_groups(struct lpi_pinctrl * pctrl)407 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
408 {
409 int i, ret;
410
411 for (i = 0; i < pctrl->data->npins; i++) {
412 const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
413
414 ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
415 (int *)&pin_info->number, 1, NULL);
416 if (ret < 0)
417 goto err_pinctrl;
418 }
419
420 return 0;
421
422 err_pinctrl:
423 for (; i > 0; i--)
424 pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
425
426 return ret;
427 }
428
lpi_pinctrl_probe(struct platform_device * pdev)429 int lpi_pinctrl_probe(struct platform_device *pdev)
430 {
431 const struct lpi_pinctrl_variant_data *data;
432 struct device *dev = &pdev->dev;
433 struct lpi_pinctrl *pctrl;
434 int ret;
435
436 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
437 if (!pctrl)
438 return -ENOMEM;
439
440 platform_set_drvdata(pdev, pctrl);
441
442 data = of_device_get_match_data(dev);
443 if (!data)
444 return -EINVAL;
445
446 if (WARN_ON(data->npins > MAX_NR_GPIO))
447 return -EINVAL;
448
449 pctrl->data = data;
450 pctrl->dev = &pdev->dev;
451
452 pctrl->clks[0].id = "core";
453 pctrl->clks[1].id = "audio";
454
455 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
456 if (IS_ERR(pctrl->tlmm_base))
457 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
458 "TLMM resource not provided\n");
459
460 if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) {
461 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
462 if (IS_ERR(pctrl->slew_base))
463 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
464 "Slew resource not provided\n");
465 }
466
467 ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
468 if (ret)
469 return ret;
470
471 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
472 if (ret)
473 return dev_err_probe(dev, ret, "Can't enable clocks\n");
474
475 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
476 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
477 pctrl->desc.confops = &lpi_gpio_pinconf_ops;
478 pctrl->desc.owner = THIS_MODULE;
479 pctrl->desc.name = dev_name(dev);
480 pctrl->desc.pins = data->pins;
481 pctrl->desc.npins = data->npins;
482 pctrl->chip = lpi_gpio_template;
483 pctrl->chip.parent = dev;
484 pctrl->chip.base = -1;
485 pctrl->chip.ngpio = data->npins;
486 pctrl->chip.label = dev_name(dev);
487 pctrl->chip.can_sleep = false;
488
489 mutex_init(&pctrl->lock);
490
491 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
492 if (IS_ERR(pctrl->ctrl)) {
493 ret = PTR_ERR(pctrl->ctrl);
494 dev_err(dev, "failed to add pin controller\n");
495 goto err_pinctrl;
496 }
497
498 ret = lpi_build_pin_desc_groups(pctrl);
499 if (ret)
500 goto err_pinctrl;
501
502 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
503 if (ret) {
504 dev_err(pctrl->dev, "can't add gpio chip\n");
505 goto err_pinctrl;
506 }
507
508 return 0;
509
510 err_pinctrl:
511 mutex_destroy(&pctrl->lock);
512 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
513
514 return ret;
515 }
516 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
517
lpi_pinctrl_remove(struct platform_device * pdev)518 void lpi_pinctrl_remove(struct platform_device *pdev)
519 {
520 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
521 int i;
522
523 mutex_destroy(&pctrl->lock);
524 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
525
526 for (i = 0; i < pctrl->data->npins; i++)
527 pinctrl_generic_remove_group(pctrl->ctrl, i);
528 }
529 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
530
531 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
532 MODULE_LICENSE("GPL");
533