1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018 Intel Corporation */ 3 4 #ifndef __IPU3_CSS_FW_H 5 #define __IPU3_CSS_FW_H 6 7 /******************* Firmware file definitions *******************/ 8 9 #define IMGU_FW_NAME "intel/ipu3-fw.bin" 10 #define IMGU_FW_NAME_20161208 \ 11 "intel/irci_irci_ecr-master_20161208_0213_20170112_1500.bin" 12 #define IMGU_FW_NAME_IPU_20161208 \ 13 "intel/ipu/irci_irci_ecr-master_20161208_0213_20170112_1500.bin" 14 15 typedef u32 imgu_fw_ptr; 16 17 enum imgu_fw_type { 18 IMGU_FW_SP_FIRMWARE, /* Firmware for the SP */ 19 IMGU_FW_SP1_FIRMWARE, /* Firmware for the SP1 */ 20 IMGU_FW_ISP_FIRMWARE, /* Firmware for the ISP */ 21 IMGU_FW_BOOTLOADER_FIRMWARE, /* Firmware for the BootLoader */ 22 IMGU_FW_ACC_FIRMWARE /* Firmware for accelerations */ 23 }; 24 25 enum imgu_fw_acc_type { 26 IMGU_FW_ACC_NONE, /* Normal binary */ 27 IMGU_FW_ACC_OUTPUT, /* Accelerator stage on output frame */ 28 IMGU_FW_ACC_VIEWFINDER, /* Accelerator stage on viewfinder frame */ 29 IMGU_FW_ACC_STANDALONE, /* Stand-alone acceleration */ 30 }; 31 32 struct imgu_fw_isp_parameter { 33 u32 offset; /* Offset in isp_<mem> config, params, etc. */ 34 u32 size; /* Disabled if 0 */ 35 }; 36 37 struct imgu_fw_param_memory_offsets { 38 struct { 39 struct imgu_fw_isp_parameter lin; /* lin_vmem_params */ 40 struct imgu_fw_isp_parameter tnr3; /* tnr3_vmem_params */ 41 struct imgu_fw_isp_parameter xnr3; /* xnr3_vmem_params */ 42 } vmem; 43 struct { 44 struct imgu_fw_isp_parameter tnr; 45 struct imgu_fw_isp_parameter tnr3; /* tnr3_params */ 46 struct imgu_fw_isp_parameter xnr3; /* xnr3_params */ 47 struct imgu_fw_isp_parameter plane_io_config; /* 192 bytes */ 48 struct imgu_fw_isp_parameter rgbir; /* rgbir_params */ 49 } dmem; 50 }; 51 52 struct imgu_fw_config_memory_offsets { 53 struct { 54 struct imgu_fw_isp_parameter iterator; 55 struct imgu_fw_isp_parameter dvs; 56 struct imgu_fw_isp_parameter output; 57 struct imgu_fw_isp_parameter raw; 58 struct imgu_fw_isp_parameter input_yuv; 59 struct imgu_fw_isp_parameter tnr; 60 struct imgu_fw_isp_parameter tnr3; 61 struct imgu_fw_isp_parameter ref; 62 } dmem; 63 }; 64 65 struct imgu_fw_state_memory_offsets { 66 struct { 67 struct imgu_fw_isp_parameter tnr; 68 struct imgu_fw_isp_parameter tnr3; 69 struct imgu_fw_isp_parameter ref; 70 } dmem; 71 }; 72 73 union imgu_fw_all_memory_offsets { 74 struct { 75 u64 imgu_fw_mem_offsets[3]; /* params, config, state */ 76 } offsets; 77 struct { 78 u64 ptr; 79 } array[IMGU_ABI_PARAM_CLASS_NUM]; 80 }; 81 82 struct imgu_fw_binary_xinfo { 83 /* Part that is of interest to the SP. */ 84 struct imgu_abi_binary_info sp; 85 86 /* Rest of the binary info, only interesting to the host. */ 87 u32 type; /* enum imgu_fw_acc_type */ 88 89 u32 num_output_formats __aligned(8); 90 u32 output_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */ 91 92 /* number of supported vf formats */ 93 u32 num_vf_formats __aligned(8); 94 /* types of supported vf formats */ 95 u32 vf_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */ 96 u8 num_output_pins; 97 imgu_fw_ptr xmem_addr; 98 99 u64 imgu_fw_blob_descr_ptr __aligned(8); 100 u32 blob_index __aligned(8); 101 union imgu_fw_all_memory_offsets mem_offsets __aligned(8); 102 struct imgu_fw_binary_xinfo *next __aligned(8); 103 }; 104 105 struct imgu_fw_sp_info { 106 u32 init_dmem_data; /* data sect config, stored to dmem */ 107 u32 per_frame_data; /* Per frame data, stored to dmem */ 108 u32 group; /* Per pipeline data, loaded by dma */ 109 u32 output; /* SP output data, loaded by dmem */ 110 u32 host_sp_queue; /* Host <-> SP queues */ 111 u32 host_sp_com; /* Host <-> SP commands */ 112 u32 isp_started; /* P'ed from sensor thread, csim only */ 113 u32 sw_state; /* Polled from css, enum imgu_abi_sp_swstate */ 114 u32 host_sp_queues_initialized; /* Polled from the SP */ 115 u32 sleep_mode; /* different mode to halt SP */ 116 u32 invalidate_tlb; /* inform SP to invalidate mmu TLB */ 117 u32 debug_buffer_ddr_address; /* the addr of DDR debug queue */ 118 119 /* input system perf count array */ 120 u32 perf_counter_input_system_error; 121 u32 threads_stack; /* sp thread's stack pointers */ 122 u32 threads_stack_size; /* sp thread's stack sizes */ 123 u32 curr_binary_id; /* current binary id */ 124 u32 raw_copy_line_count; /* raw copy line counter */ 125 u32 ddr_parameter_address; /* acc param ddrptr, sp dmem */ 126 u32 ddr_parameter_size; /* acc param size, sp dmem */ 127 /* Entry functions */ 128 u32 sp_entry; /* The SP entry function */ 129 u32 tagger_frames_addr; /* Base address of tagger state */ 130 }; 131 132 struct imgu_fw_bl_info { 133 u32 num_dma_cmds; /* Number of cmds sent by CSS */ 134 u32 dma_cmd_list; /* Dma command list sent by CSS */ 135 u32 sw_state; /* Polled from css, enum imgu_abi_bl_swstate */ 136 /* Entry functions */ 137 u32 bl_entry; /* The SP entry function */ 138 }; 139 140 struct imgu_fw_acc_info { 141 u32 per_frame_data; /* Dummy for now */ 142 }; 143 144 union imgu_fw_union { 145 struct imgu_fw_binary_xinfo isp; /* ISP info */ 146 struct imgu_fw_sp_info sp; /* SP info */ 147 struct imgu_fw_sp_info sp1; /* SP1 info */ 148 struct imgu_fw_bl_info bl; /* Bootloader info */ 149 struct imgu_fw_acc_info acc; /* Accelerator info */ 150 }; 151 152 struct imgu_fw_info { 153 size_t header_size; /* size of fw header */ 154 u32 type __aligned(8); /* enum imgu_fw_type */ 155 156 union imgu_fw_union info; /* Binary info */ 157 struct imgu_abi_blob_info blob; /* Blob info */ 158 /* Dynamic part */ 159 u64 next; 160 161 u32 loaded __aligned(8); /* Firmware has been loaded */ 162 const u64 isp_code __aligned(8); /* ISP pointer to code */ 163 /* Firmware handle between user space and kernel */ 164 u32 handle __aligned(8); 165 /* Sections to copy from/to ISP */ 166 struct imgu_abi_isp_param_segments mem_initializers; 167 /* Initializer for local ISP memories */ 168 }; 169 170 struct imgu_fw_bi_file_h { 171 char version[64]; /* branch tag + week day + time */ 172 int binary_nr; /* Number of binaries */ 173 unsigned int h_size; /* sizeof(struct imgu_fw_bi_file_h) */ 174 }; 175 176 struct imgu_fw_header { 177 struct imgu_fw_bi_file_h file_header; 178 struct imgu_fw_info binary_header[]; /* binary_nr items */ 179 }; 180 181 /******************* Firmware functions *******************/ 182 183 int imgu_css_fw_init(struct imgu_css *css); 184 void imgu_css_fw_cleanup(struct imgu_css *css); 185 186 unsigned int imgu_css_fw_obgrid_size(const struct imgu_fw_info *bi); 187 void *imgu_css_fw_pipeline_params(struct imgu_css *css, unsigned int pipe, 188 enum imgu_abi_param_class cls, 189 enum imgu_abi_memories mem, 190 struct imgu_fw_isp_parameter *par, 191 size_t par_size, void *binary_params); 192 193 #endif 194