1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67 #define PCI_VENDOR_ID_WCH 0x4348
68 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
70 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
71 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
72 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
73 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
74 #define PCI_VENDOR_ID_AGESTAR 0x5372
75 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
76 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
77 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
78
79 #define PCIE_VENDOR_ID_WCH 0x1c00
80 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
81 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
82 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
83 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
84
85 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
86 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
87 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
88 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
89 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
90 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
91 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
92 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
93 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
94 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
95 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
96 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
97 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
98 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
99 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
100 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
101 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
102 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
103
104 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
107
108 /*
109 * init function returns:
110 * > 0 - number of ports
111 * = 0 - use board->num_ports
112 * < 0 - error
113 */
114 struct pci_serial_quirk {
115 u32 vendor;
116 u32 device;
117 u32 subvendor;
118 u32 subdevice;
119 int (*probe)(struct pci_dev *dev);
120 int (*init)(struct pci_dev *dev);
121 int (*setup)(struct serial_private *,
122 const struct pciserial_board *,
123 struct uart_8250_port *, int);
124 void (*exit)(struct pci_dev *dev);
125 };
126
127 struct f815xxa_data {
128 spinlock_t lock;
129 int idx;
130 };
131
132 struct serial_private {
133 struct pci_dev *dev;
134 unsigned int nr;
135 struct pci_serial_quirk *quirk;
136 const struct pciserial_board *board;
137 int line[];
138 };
139
140 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
141
142 static const struct pci_device_id pci_use_msi[] = {
143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
144 0xA000, 0x1000) },
145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
146 0xA000, 0x1000) },
147 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
148 0xA000, 0x1000) },
149 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
150 0xA000, 0x1000) },
151 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
152 PCI_ANY_ID, PCI_ANY_ID) },
153 { }
154 };
155
156 static int pci_default_setup(struct serial_private*,
157 const struct pciserial_board*, struct uart_8250_port *, int);
158
moan_device(const char * str,struct pci_dev * dev)159 static void moan_device(const char *str, struct pci_dev *dev)
160 {
161 pci_err(dev, "%s\n"
162 "Please send the output of lspci -vv, this\n"
163 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
164 "manufacturer and name of serial board or\n"
165 "modem board to <linux-serial@vger.kernel.org>.\n",
166 str, dev->vendor, dev->device,
167 dev->subsystem_vendor, dev->subsystem_device);
168 }
169
170 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)171 setup_port(struct serial_private *priv, struct uart_8250_port *port,
172 u8 bar, unsigned int offset, int regshift)
173 {
174 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
175 }
176
177 /*
178 * ADDI-DATA GmbH communication cards <info@addi-data.com>
179 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)180 static int addidata_apci7800_setup(struct serial_private *priv,
181 const struct pciserial_board *board,
182 struct uart_8250_port *port, int idx)
183 {
184 unsigned int bar = 0, offset = board->first_offset;
185 bar = FL_GET_BASE(board->flags);
186
187 if (idx < 2) {
188 offset += idx * board->uart_offset;
189 } else if ((idx >= 2) && (idx < 4)) {
190 bar += 1;
191 offset += ((idx - 2) * board->uart_offset);
192 } else if ((idx >= 4) && (idx < 6)) {
193 bar += 2;
194 offset += ((idx - 4) * board->uart_offset);
195 } else if (idx >= 6) {
196 bar += 3;
197 offset += ((idx - 6) * board->uart_offset);
198 }
199
200 return setup_port(priv, port, bar, offset, board->reg_shift);
201 }
202
203 /*
204 * AFAVLAB uses a different mixture of BARs and offsets
205 * Not that ugly ;) -- HW
206 */
207 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)208 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
209 struct uart_8250_port *port, int idx)
210 {
211 unsigned int bar, offset = board->first_offset;
212
213 bar = FL_GET_BASE(board->flags);
214 if (idx < 4)
215 bar += idx;
216 else {
217 bar = 4;
218 offset += (idx - 4) * board->uart_offset;
219 }
220
221 return setup_port(priv, port, bar, offset, board->reg_shift);
222 }
223
224 /*
225 * HP's Remote Management Console. The Diva chip came in several
226 * different versions. N-class, L2000 and A500 have two Diva chips, each
227 * with 3 UARTs (the third UART on the second chip is unused). Superdome
228 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
229 * one Diva chip, but it has been expanded to 5 UARTs.
230 */
pci_hp_diva_init(struct pci_dev * dev)231 static int pci_hp_diva_init(struct pci_dev *dev)
232 {
233 int rc = 0;
234
235 switch (dev->subsystem_device) {
236 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
237 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
238 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
239 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
240 rc = 3;
241 break;
242 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
243 rc = 2;
244 break;
245 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
246 rc = 4;
247 break;
248 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
249 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
250 rc = 1;
251 break;
252 }
253
254 return rc;
255 }
256
257 /*
258 * HP's Diva chip puts the 4th/5th serial port further out, and
259 * some serial ports are supposed to be hidden on certain models.
260 */
261 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)262 pci_hp_diva_setup(struct serial_private *priv,
263 const struct pciserial_board *board,
264 struct uart_8250_port *port, int idx)
265 {
266 unsigned int offset = board->first_offset;
267 unsigned int bar = FL_GET_BASE(board->flags);
268
269 switch (priv->dev->subsystem_device) {
270 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
271 if (idx == 3)
272 idx++;
273 break;
274 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
275 if (idx > 0)
276 idx++;
277 if (idx > 2)
278 idx++;
279 break;
280 }
281 if (idx > 2)
282 offset = 0x18;
283
284 offset += idx * board->uart_offset;
285
286 return setup_port(priv, port, bar, offset, board->reg_shift);
287 }
288
289 /*
290 * Added for EKF Intel i960 serial boards
291 */
pci_inteli960ni_init(struct pci_dev * dev)292 static int pci_inteli960ni_init(struct pci_dev *dev)
293 {
294 u32 oldval;
295
296 if (!(dev->subsystem_device & 0x1000))
297 return -ENODEV;
298
299 /* is firmware started? */
300 pci_read_config_dword(dev, 0x44, &oldval);
301 if (oldval == 0x00001000L) { /* RESET value */
302 pci_dbg(dev, "Local i960 firmware missing\n");
303 return -ENODEV;
304 }
305 return 0;
306 }
307
308 /*
309 * Some PCI serial cards using the PLX 9050 PCI interface chip require
310 * that the card interrupt be explicitly enabled or disabled. This
311 * seems to be mainly needed on card using the PLX which also use I/O
312 * mapped memory.
313 */
pci_plx9050_init(struct pci_dev * dev)314 static int pci_plx9050_init(struct pci_dev *dev)
315 {
316 u8 irq_config;
317 void __iomem *p;
318
319 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar 0", dev);
321 return 0;
322 }
323
324 irq_config = 0x41;
325 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
326 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
327 irq_config = 0x43;
328
329 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
330 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
331 /*
332 * As the megawolf cards have the int pins active
333 * high, and have 2 UART chips, both ints must be
334 * enabled on the 9050. Also, the UARTS are set in
335 * 16450 mode by default, so we have to enable the
336 * 16C950 'enhanced' mode so that we can use the
337 * deep FIFOs
338 */
339 irq_config = 0x5b;
340 /*
341 * enable/disable interrupts
342 */
343 p = ioremap(pci_resource_start(dev, 0), 0x80);
344 if (p == NULL)
345 return -ENOMEM;
346 writel(irq_config, p + 0x4c);
347
348 /*
349 * Read the register back to ensure that it took effect.
350 */
351 readl(p + 0x4c);
352 iounmap(p);
353
354 return 0;
355 }
356
pci_plx9050_exit(struct pci_dev * dev)357 static void pci_plx9050_exit(struct pci_dev *dev)
358 {
359 u8 __iomem *p;
360
361 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
362 return;
363
364 /*
365 * disable interrupts
366 */
367 p = ioremap(pci_resource_start(dev, 0), 0x80);
368 if (p != NULL) {
369 writel(0, p + 0x4c);
370
371 /*
372 * Read the register back to ensure that it took effect.
373 */
374 readl(p + 0x4c);
375 iounmap(p);
376 }
377 }
378
379 #define NI8420_INT_ENABLE_REG 0x38
380 #define NI8420_INT_ENABLE_BIT 0x2000
381
pci_ni8420_exit(struct pci_dev * dev)382 static void pci_ni8420_exit(struct pci_dev *dev)
383 {
384 void __iomem *p;
385 unsigned int bar = 0;
386
387 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
388 moan_device("no memory in bar", dev);
389 return;
390 }
391
392 p = pci_ioremap_bar(dev, bar);
393 if (p == NULL)
394 return;
395
396 /* Disable the CPU Interrupt */
397 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
398 p + NI8420_INT_ENABLE_REG);
399 iounmap(p);
400 }
401
402
403 /* MITE registers */
404 #define MITE_IOWBSR1 0xc4
405 #define MITE_IOWCR1 0xf4
406 #define MITE_LCIMR1 0x08
407 #define MITE_LCIMR2 0x10
408
409 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
410
pci_ni8430_exit(struct pci_dev * dev)411 static void pci_ni8430_exit(struct pci_dev *dev)
412 {
413 void __iomem *p;
414 unsigned int bar = 0;
415
416 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
417 moan_device("no memory in bar", dev);
418 return;
419 }
420
421 p = pci_ioremap_bar(dev, bar);
422 if (p == NULL)
423 return;
424
425 /* Disable the CPU Interrupt */
426 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
427 iounmap(p);
428 }
429
430 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
431 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)432 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
433 struct uart_8250_port *port, int idx)
434 {
435 unsigned int bar, offset = board->first_offset;
436
437 bar = 0;
438
439 if (idx < 4) {
440 /* first four channels map to 0, 0x100, 0x200, 0x300 */
441 offset += idx * board->uart_offset;
442 } else if (idx < 8) {
443 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
444 offset += idx * board->uart_offset + 0xC00;
445 } else /* we have only 8 ports on PMC-OCTALPRO */
446 return 1;
447
448 return setup_port(priv, port, bar, offset, board->reg_shift);
449 }
450
451 /*
452 * This does initialization for PMC OCTALPRO cards:
453 * maps the device memory, resets the UARTs (needed, bc
454 * if the module is removed and inserted again, the card
455 * is in the sleep mode) and enables global interrupt.
456 */
457
458 /* global control register offset for SBS PMC-OctalPro */
459 #define OCT_REG_CR_OFF 0x500
460
sbs_init(struct pci_dev * dev)461 static int sbs_init(struct pci_dev *dev)
462 {
463 u8 __iomem *p;
464
465 p = pci_ioremap_bar(dev, 0);
466
467 if (p == NULL)
468 return -ENOMEM;
469 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
470 writeb(0x10, p + OCT_REG_CR_OFF);
471 udelay(50);
472 writeb(0x0, p + OCT_REG_CR_OFF);
473
474 /* Set bit-2 (INTENABLE) of Control Register */
475 writeb(0x4, p + OCT_REG_CR_OFF);
476 iounmap(p);
477
478 return 0;
479 }
480
481 /*
482 * Disables the global interrupt of PMC-OctalPro
483 */
484
sbs_exit(struct pci_dev * dev)485 static void sbs_exit(struct pci_dev *dev)
486 {
487 u8 __iomem *p;
488
489 p = pci_ioremap_bar(dev, 0);
490 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
491 if (p != NULL)
492 writeb(0, p + OCT_REG_CR_OFF);
493 iounmap(p);
494 }
495
496 /*
497 * SIIG serial cards have an PCI interface chip which also controls
498 * the UART clocking frequency. Each UART can be clocked independently
499 * (except cards equipped with 4 UARTs) and initial clocking settings
500 * are stored in the EEPROM chip. It can cause problems because this
501 * version of serial driver doesn't support differently clocked UART's
502 * on single PCI card. To prevent this, initialization functions set
503 * high frequency clocking for all UART's on given card. It is safe (I
504 * hope) because it doesn't touch EEPROM settings to prevent conflicts
505 * with other OSes (like M$ DOS).
506 *
507 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
508 *
509 * There is two family of SIIG serial cards with different PCI
510 * interface chip and different configuration methods:
511 * - 10x cards have control registers in IO and/or memory space;
512 * - 20x cards have control registers in standard PCI configuration space.
513 *
514 * Note: all 10x cards have PCI device ids 0x10..
515 * all 20x cards have PCI device ids 0x20..
516 *
517 * There are also Quartet Serial cards which use Oxford Semiconductor
518 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
519 *
520 * Note: some SIIG cards are probed by the parport_serial object.
521 */
522
523 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
524 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
525
pci_siig10x_init(struct pci_dev * dev)526 static int pci_siig10x_init(struct pci_dev *dev)
527 {
528 u16 data;
529 void __iomem *p;
530
531 switch (dev->device & 0xfff8) {
532 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
533 data = 0xffdf;
534 break;
535 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
536 data = 0xf7ff;
537 break;
538 default: /* 1S1P, 4S */
539 data = 0xfffb;
540 break;
541 }
542
543 p = ioremap(pci_resource_start(dev, 0), 0x80);
544 if (p == NULL)
545 return -ENOMEM;
546
547 writew(readw(p + 0x28) & data, p + 0x28);
548 readw(p + 0x28);
549 iounmap(p);
550 return 0;
551 }
552
553 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
554 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
555
pci_siig20x_init(struct pci_dev * dev)556 static int pci_siig20x_init(struct pci_dev *dev)
557 {
558 u8 data;
559
560 /* Change clock frequency for the first UART. */
561 pci_read_config_byte(dev, 0x6f, &data);
562 pci_write_config_byte(dev, 0x6f, data & 0xef);
563
564 /* If this card has 2 UART, we have to do the same with second UART. */
565 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
566 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
567 pci_read_config_byte(dev, 0x73, &data);
568 pci_write_config_byte(dev, 0x73, data & 0xef);
569 }
570 return 0;
571 }
572
pci_siig_init(struct pci_dev * dev)573 static int pci_siig_init(struct pci_dev *dev)
574 {
575 unsigned int type = dev->device & 0xff00;
576
577 if (type == 0x1000)
578 return pci_siig10x_init(dev);
579 if (type == 0x2000)
580 return pci_siig20x_init(dev);
581
582 moan_device("Unknown SIIG card", dev);
583 return -ENODEV;
584 }
585
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)586 static int pci_siig_setup(struct serial_private *priv,
587 const struct pciserial_board *board,
588 struct uart_8250_port *port, int idx)
589 {
590 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
591
592 if (idx > 3) {
593 bar = 4;
594 offset = (idx - 4) * 8;
595 }
596
597 return setup_port(priv, port, bar, offset, 0);
598 }
599
600 /*
601 * Timedia has an explosion of boards, and to avoid the PCI table from
602 * growing *huge*, we use this function to collapse some 70 entries
603 * in the PCI table into one, for sanity's and compactness's sake.
604 */
605 static const unsigned short timedia_single_port[] = {
606 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
607 };
608
609 static const unsigned short timedia_dual_port[] = {
610 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
611 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
612 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
613 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
614 0xD079, 0
615 };
616
617 static const unsigned short timedia_quad_port[] = {
618 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
619 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
620 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
621 0xB157, 0
622 };
623
624 static const unsigned short timedia_eight_port[] = {
625 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
626 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
627 };
628
629 static const struct timedia_struct {
630 int num;
631 const unsigned short *ids;
632 } timedia_data[] = {
633 { 1, timedia_single_port },
634 { 2, timedia_dual_port },
635 { 4, timedia_quad_port },
636 { 8, timedia_eight_port }
637 };
638
639 /*
640 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
641 * listing them individually, this driver merely grabs them all with
642 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
643 * and should be left free to be claimed by parport_serial instead.
644 */
pci_timedia_probe(struct pci_dev * dev)645 static int pci_timedia_probe(struct pci_dev *dev)
646 {
647 /*
648 * Check the third digit of the subdevice ID
649 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
650 */
651 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
652 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
653 dev->subsystem_device);
654 return -ENODEV;
655 }
656
657 return 0;
658 }
659
pci_timedia_init(struct pci_dev * dev)660 static int pci_timedia_init(struct pci_dev *dev)
661 {
662 const unsigned short *ids;
663 int i, j;
664
665 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
666 ids = timedia_data[i].ids;
667 for (j = 0; ids[j]; j++)
668 if (dev->subsystem_device == ids[j])
669 return timedia_data[i].num;
670 }
671 return 0;
672 }
673
674 /*
675 * Timedia/SUNIX uses a mixture of BARs and offsets
676 * Ugh, this is ugly as all hell --- TYT
677 */
678 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)679 pci_timedia_setup(struct serial_private *priv,
680 const struct pciserial_board *board,
681 struct uart_8250_port *port, int idx)
682 {
683 unsigned int bar = 0, offset = board->first_offset;
684
685 switch (idx) {
686 case 0:
687 bar = 0;
688 break;
689 case 1:
690 offset = board->uart_offset;
691 bar = 0;
692 break;
693 case 2:
694 bar = 1;
695 break;
696 case 3:
697 offset = board->uart_offset;
698 fallthrough;
699 case 4: /* BAR 2 */
700 case 5: /* BAR 3 */
701 case 6: /* BAR 4 */
702 case 7: /* BAR 5 */
703 bar = idx - 2;
704 }
705
706 return setup_port(priv, port, bar, offset, board->reg_shift);
707 }
708
709 /*
710 * Some Titan cards are also a little weird
711 */
712 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)713 titan_400l_800l_setup(struct serial_private *priv,
714 const struct pciserial_board *board,
715 struct uart_8250_port *port, int idx)
716 {
717 unsigned int bar, offset = board->first_offset;
718
719 switch (idx) {
720 case 0:
721 bar = 1;
722 break;
723 case 1:
724 bar = 2;
725 break;
726 default:
727 bar = 4;
728 offset = (idx - 2) * board->uart_offset;
729 }
730
731 return setup_port(priv, port, bar, offset, board->reg_shift);
732 }
733
pci_xircom_init(struct pci_dev * dev)734 static int pci_xircom_init(struct pci_dev *dev)
735 {
736 msleep(100);
737 return 0;
738 }
739
pci_ni8420_init(struct pci_dev * dev)740 static int pci_ni8420_init(struct pci_dev *dev)
741 {
742 void __iomem *p;
743 unsigned int bar = 0;
744
745 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
746 moan_device("no memory in bar", dev);
747 return 0;
748 }
749
750 p = pci_ioremap_bar(dev, bar);
751 if (p == NULL)
752 return -ENOMEM;
753
754 /* Enable CPU Interrupt */
755 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
756 p + NI8420_INT_ENABLE_REG);
757
758 iounmap(p);
759 return 0;
760 }
761
762 #define MITE_IOWBSR1_WSIZE 0xa
763 #define MITE_IOWBSR1_WIN_OFFSET 0x800
764 #define MITE_IOWBSR1_WENAB (1 << 7)
765 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
766 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
767 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
768
pci_ni8430_init(struct pci_dev * dev)769 static int pci_ni8430_init(struct pci_dev *dev)
770 {
771 void __iomem *p;
772 struct pci_bus_region region;
773 u32 device_window;
774 unsigned int bar = 0;
775
776 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
777 moan_device("no memory in bar", dev);
778 return 0;
779 }
780
781 p = pci_ioremap_bar(dev, bar);
782 if (p == NULL)
783 return -ENOMEM;
784
785 /*
786 * Set device window address and size in BAR0, while acknowledging that
787 * the resource structure may contain a translated address that differs
788 * from the address the device responds to.
789 */
790 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
791 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
792 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
793 writel(device_window, p + MITE_IOWBSR1);
794
795 /* Set window access to go to RAMSEL IO address space */
796 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
797 p + MITE_IOWCR1);
798
799 /* Enable IO Bus Interrupt 0 */
800 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
801
802 /* Enable CPU Interrupt */
803 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
804
805 iounmap(p);
806 return 0;
807 }
808
809 /* UART Port Control Register */
810 #define NI8430_PORTCON 0x0f
811 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
812
813 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)814 pci_ni8430_setup(struct serial_private *priv,
815 const struct pciserial_board *board,
816 struct uart_8250_port *port, int idx)
817 {
818 struct pci_dev *dev = priv->dev;
819 void __iomem *p;
820 unsigned int bar, offset = board->first_offset;
821
822 if (idx >= board->num_ports)
823 return 1;
824
825 bar = FL_GET_BASE(board->flags);
826 offset += idx * board->uart_offset;
827
828 p = pci_ioremap_bar(dev, bar);
829 if (!p)
830 return -ENOMEM;
831
832 /* enable the transceiver */
833 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
834 p + offset + NI8430_PORTCON);
835
836 iounmap(p);
837
838 return setup_port(priv, port, bar, offset, board->reg_shift);
839 }
840
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)841 static int pci_netmos_9900_setup(struct serial_private *priv,
842 const struct pciserial_board *board,
843 struct uart_8250_port *port, int idx)
844 {
845 unsigned int bar;
846
847 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
848 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
849 /* netmos apparently orders BARs by datasheet layout, so serial
850 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
851 */
852 bar = 3 * idx;
853
854 return setup_port(priv, port, bar, 0, board->reg_shift);
855 }
856
857 return pci_default_setup(priv, board, port, idx);
858 }
859
860 /* the 99xx series comes with a range of device IDs and a variety
861 * of capabilities:
862 *
863 * 9900 has varying capabilities and can cascade to sub-controllers
864 * (cascading should be purely internal)
865 * 9904 is hardwired with 4 serial ports
866 * 9912 and 9922 are hardwired with 2 serial ports
867 */
pci_netmos_9900_numports(struct pci_dev * dev)868 static int pci_netmos_9900_numports(struct pci_dev *dev)
869 {
870 unsigned int c = dev->class;
871 unsigned int pi;
872 unsigned short sub_serports;
873
874 pi = c & 0xff;
875
876 if (pi == 2)
877 return 1;
878
879 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
880 /* two possibilities: 0x30ps encodes number of parallel and
881 * serial ports, or 0x1000 indicates *something*. This is not
882 * immediately obvious, since the 2s1p+4s configuration seems
883 * to offer all functionality on functions 0..2, while still
884 * advertising the same function 3 as the 4s+2s1p config.
885 */
886 sub_serports = dev->subsystem_device & 0xf;
887 if (sub_serports > 0)
888 return sub_serports;
889
890 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
891 return 0;
892 }
893
894 moan_device("unknown NetMos/Mostech program interface", dev);
895 return 0;
896 }
897
pci_netmos_init(struct pci_dev * dev)898 static int pci_netmos_init(struct pci_dev *dev)
899 {
900 /* subdevice 0x00PS means <P> parallel, <S> serial */
901 unsigned int num_serial = dev->subsystem_device & 0xf;
902
903 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
904 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
905 return 0;
906
907 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
908 dev->subsystem_device == 0x0299)
909 return 0;
910
911 switch (dev->device) { /* FALLTHROUGH on all */
912 case PCI_DEVICE_ID_NETMOS_9904:
913 case PCI_DEVICE_ID_NETMOS_9912:
914 case PCI_DEVICE_ID_NETMOS_9922:
915 case PCI_DEVICE_ID_NETMOS_9900:
916 num_serial = pci_netmos_9900_numports(dev);
917 break;
918
919 default:
920 break;
921 }
922
923 if (num_serial == 0) {
924 moan_device("unknown NetMos/Mostech device", dev);
925 return -ENODEV;
926 }
927
928 return num_serial;
929 }
930
931 /*
932 * These chips are available with optionally one parallel port and up to
933 * two serial ports. Unfortunately they all have the same product id.
934 *
935 * Basic configuration is done over a region of 32 I/O ports. The base
936 * ioport is called INTA or INTC, depending on docs/other drivers.
937 *
938 * The region of the 32 I/O ports is configured in POSIO0R...
939 */
940
941 /* registers */
942 #define ITE_887x_MISCR 0x9c
943 #define ITE_887x_INTCBAR 0x78
944 #define ITE_887x_UARTBAR 0x7c
945 #define ITE_887x_PS0BAR 0x10
946 #define ITE_887x_POSIO0 0x60
947
948 /* I/O space size */
949 #define ITE_887x_IOSIZE 32
950 /* I/O space size (bits 26-24; 8 bytes = 011b) */
951 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
952 /* I/O space size (bits 26-24; 32 bytes = 101b) */
953 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
954 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
955 #define ITE_887x_POSIO_SPEED (3 << 29)
956 /* enable IO_Space bit */
957 #define ITE_887x_POSIO_ENABLE (1 << 31)
958
959 /* inta_addr are the configuration addresses of the ITE */
960 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)961 static int pci_ite887x_init(struct pci_dev *dev)
962 {
963 int ret, i, type;
964 struct resource *iobase = NULL;
965 u32 miscr, uartbar, ioport;
966
967 /* search for the base-ioport */
968 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
969 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
970 "ite887x");
971 if (iobase != NULL) {
972 /* write POSIO0R - speed | size | ioport */
973 pci_write_config_dword(dev, ITE_887x_POSIO0,
974 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
975 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
976 /* write INTCBAR - ioport */
977 pci_write_config_dword(dev, ITE_887x_INTCBAR,
978 inta_addr[i]);
979 ret = inb(inta_addr[i]);
980 if (ret != 0xff) {
981 /* ioport connected */
982 break;
983 }
984 release_region(iobase->start, ITE_887x_IOSIZE);
985 }
986 }
987
988 if (i == ARRAY_SIZE(inta_addr)) {
989 pci_err(dev, "could not find iobase\n");
990 return -ENODEV;
991 }
992
993 /* start of undocumented type checking (see parport_pc.c) */
994 type = inb(iobase->start + 0x18) & 0x0f;
995
996 switch (type) {
997 case 0x2: /* ITE8871 (1P) */
998 case 0xa: /* ITE8875 (1P) */
999 ret = 0;
1000 break;
1001 case 0xe: /* ITE8872 (2S1P) */
1002 ret = 2;
1003 break;
1004 case 0x6: /* ITE8873 (1S) */
1005 ret = 1;
1006 break;
1007 case 0x8: /* ITE8874 (2S) */
1008 ret = 2;
1009 break;
1010 default:
1011 moan_device("Unknown ITE887x", dev);
1012 ret = -ENODEV;
1013 }
1014
1015 /* configure all serial ports */
1016 for (i = 0; i < ret; i++) {
1017 /* read the I/O port from the device */
1018 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1019 &ioport);
1020 ioport &= 0x0000FF00; /* the actual base address */
1021 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1022 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1023 ITE_887x_POSIO_IOSIZE_8 | ioport);
1024
1025 /* write the ioport to the UARTBAR */
1026 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1027 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1028 uartbar |= (ioport << (16 * i)); /* set the ioport */
1029 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1030
1031 /* get current config */
1032 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1033 /* disable interrupts (UARTx_Routing[3:0]) */
1034 miscr &= ~(0xf << (12 - 4 * i));
1035 /* activate the UART (UARTx_En) */
1036 miscr |= 1 << (23 - i);
1037 /* write new config with activated UART */
1038 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1039 }
1040
1041 if (ret <= 0) {
1042 /* the device has no UARTs if we get here */
1043 release_region(iobase->start, ITE_887x_IOSIZE);
1044 }
1045
1046 return ret;
1047 }
1048
pci_ite887x_exit(struct pci_dev * dev)1049 static void pci_ite887x_exit(struct pci_dev *dev)
1050 {
1051 u32 ioport;
1052 /* the ioport is bit 0-15 in POSIO0R */
1053 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1054 ioport &= 0xffff;
1055 release_region(ioport, ITE_887x_IOSIZE);
1056 }
1057
1058 /*
1059 * Oxford Semiconductor Inc.
1060 * Check if an OxSemi device is part of the Tornado range of devices.
1061 */
1062 #define PCI_VENDOR_ID_ENDRUN 0x7401
1063 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1064
pci_oxsemi_tornado_p(struct pci_dev * dev)1065 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1066 {
1067 /* OxSemi Tornado devices are all 0xCxxx */
1068 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1069 (dev->device & 0xf000) != 0xc000)
1070 return false;
1071
1072 /* EndRun devices are all 0xExxx */
1073 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1074 (dev->device & 0xf000) != 0xe000)
1075 return false;
1076
1077 return true;
1078 }
1079
1080 /*
1081 * Determine the number of ports available on a Tornado device.
1082 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1083 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1084 {
1085 u8 __iomem *p;
1086 unsigned long deviceID;
1087 unsigned int number_uarts = 0;
1088
1089 if (!pci_oxsemi_tornado_p(dev))
1090 return 0;
1091
1092 p = pci_iomap(dev, 0, 5);
1093 if (p == NULL)
1094 return -ENOMEM;
1095
1096 deviceID = ioread32(p);
1097 /* Tornado device */
1098 if (deviceID == 0x07000200) {
1099 number_uarts = ioread8(p + 4);
1100 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1101 number_uarts,
1102 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1103 "EndRun" : "Oxford");
1104 }
1105 pci_iounmap(dev, p);
1106 return number_uarts;
1107 }
1108
1109 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1110 #define OXSEMI_TORNADO_TCR_MASK 0xf
1111 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1112 #define OXSEMI_TORNADO_CPR_MIN 0x008
1113 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1114
1115 /*
1116 * Determine the oversampling rate, the clock prescaler, and the clock
1117 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1118 * which is four times the baud base, and the prescaler increments in
1119 * steps of 1/8. Therefore to make calculations on integers we need
1120 * to use a scaled clock rate, which is the baud base multiplied by 32
1121 * (or our assumed UART clock rate multiplied by 2).
1122 *
1123 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1124 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1125 * values between 1.000 and 63.875 inclusive (operation for values from
1126 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1127 * unsigned 16-bit integer.
1128 *
1129 * For the most accurate baud rate we use a table of predetermined
1130 * oversampling rates and clock prescalers that records all possible
1131 * products of the two parameters in the range from 4 up to 255 inclusive,
1132 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1133 * by 8. The table is sorted by the decreasing value of the oversampling
1134 * rate and ties are resolved by sorting by the decreasing value of the
1135 * product. This way preference is given to higher oversampling rates.
1136 *
1137 * We iterate over the table and choose the product of an oversampling
1138 * rate and a clock prescaler that gives the lowest integer division
1139 * result deviation, or if an exact integer divider is found we stop
1140 * looking for it right away. We do some fixup if the resulting clock
1141 * divisor required would be out of its unsigned 16-bit integer range.
1142 *
1143 * Finally we abuse the supposed fractional part returned to encode the
1144 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1145 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1146 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1147 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1148 unsigned int baud,
1149 unsigned int *frac)
1150 {
1151 static u8 p[][2] = {
1152 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1153 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1154 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1155 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1156 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1157 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1158 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1159 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1160 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1161 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1162 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1163 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1164 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1165 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1166 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1167 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1168 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1169 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1170 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1171 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1172 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1173 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1174 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1175 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1176 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1177 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1178 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1179 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1180 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1181 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1182 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1183 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1184 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1185 { 4, 9, }, { 4, 8, },
1186 };
1187 /* Scale the quotient for comparison to get the fractional part. */
1188 const unsigned int quot_scale = 65536;
1189 unsigned int sclk = port->uartclk * 2;
1190 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1191 unsigned int best_squot;
1192 unsigned int squot;
1193 unsigned int quot;
1194 u16 cpr;
1195 u8 tcr;
1196 int i;
1197
1198 /* Old custom speed handling. */
1199 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1200 unsigned int cust_div = port->custom_divisor;
1201
1202 quot = cust_div & UART_DIV_MAX;
1203 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1204 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1205 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1206 cpr = OXSEMI_TORNADO_CPR_DEF;
1207 } else {
1208 best_squot = quot_scale;
1209 for (i = 0; i < ARRAY_SIZE(p); i++) {
1210 unsigned int spre;
1211 unsigned int srem;
1212 u8 cp;
1213 u8 tc;
1214
1215 tc = p[i][0];
1216 cp = p[i][1];
1217 spre = tc * cp;
1218
1219 srem = sdiv % spre;
1220 if (srem > spre / 2)
1221 srem = spre - srem;
1222 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1223
1224 if (srem == 0) {
1225 tcr = tc;
1226 cpr = cp;
1227 quot = sdiv / spre;
1228 break;
1229 } else if (squot < best_squot) {
1230 best_squot = squot;
1231 tcr = tc;
1232 cpr = cp;
1233 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1234 }
1235 }
1236 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1237 quot % 2 == 0) {
1238 quot >>= 1;
1239 tcr <<= 1;
1240 }
1241 while (quot > UART_DIV_MAX) {
1242 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1243 quot >>= 1;
1244 tcr <<= 1;
1245 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1246 quot >>= 1;
1247 cpr <<= 1;
1248 } else {
1249 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1250 cpr = OXSEMI_TORNADO_CPR_MASK;
1251 }
1252 }
1253 }
1254
1255 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1256 return quot;
1257 }
1258
1259 /*
1260 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1261 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1262 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1263 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1264 * has to be written first, followed by CPR2, which occupies the location
1265 * of CKS used with earlier UART designs.
1266 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1267 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1268 unsigned int baud,
1269 unsigned int quot,
1270 unsigned int quot_frac)
1271 {
1272 struct uart_8250_port *up = up_to_u8250p(port);
1273 u8 cpr2 = quot_frac >> 16;
1274 u8 cpr = quot_frac >> 8;
1275 u8 tcr = quot_frac;
1276
1277 serial_icr_write(up, UART_TCR, tcr);
1278 serial_icr_write(up, UART_CPR, cpr);
1279 serial_icr_write(up, UART_CKS, cpr2);
1280 serial8250_do_set_divisor(port, baud, quot, 0);
1281 }
1282
1283 /*
1284 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1285 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1286 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1287 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1288 unsigned int mctrl)
1289 {
1290 struct uart_8250_port *up = up_to_u8250p(port);
1291
1292 up->mcr |= UART_MCR_CLKSEL;
1293 serial8250_do_set_mctrl(port, mctrl);
1294 }
1295
1296 /*
1297 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1298 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1299 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1300 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1301 const struct pciserial_board *board,
1302 struct uart_8250_port *up, int idx)
1303 {
1304 struct pci_dev *dev = priv->dev;
1305
1306 if (pci_oxsemi_tornado_p(dev)) {
1307 up->port.flags |= UPF_FULL_PROBE;
1308 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1309 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1310 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1311 }
1312
1313 return pci_default_setup(priv, board, up, idx);
1314 }
1315
1316 #define QPCR_TEST_FOR1 0x3F
1317 #define QPCR_TEST_GET1 0x00
1318 #define QPCR_TEST_FOR2 0x40
1319 #define QPCR_TEST_GET2 0x40
1320 #define QPCR_TEST_FOR3 0x80
1321 #define QPCR_TEST_GET3 0x40
1322 #define QPCR_TEST_FOR4 0xC0
1323 #define QPCR_TEST_GET4 0x80
1324
1325 #define QOPR_CLOCK_X1 0x0000
1326 #define QOPR_CLOCK_X2 0x0001
1327 #define QOPR_CLOCK_X4 0x0002
1328 #define QOPR_CLOCK_X8 0x0003
1329 #define QOPR_CLOCK_RATE_MASK 0x0003
1330
1331 /* Quatech devices have their own extra interface features */
1332 static struct pci_device_id quatech_cards[] = {
1333 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1334 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1335 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1336 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1337 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1338 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1339 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1340 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1341 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1342 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1343 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1344 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1345 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1346 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1347 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1349 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1350 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1351 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1352 { 0, }
1353 };
1354
pci_quatech_rqopr(struct uart_8250_port * port)1355 static int pci_quatech_rqopr(struct uart_8250_port *port)
1356 {
1357 unsigned long base = port->port.iobase;
1358 u8 LCR, val;
1359
1360 LCR = inb(base + UART_LCR);
1361 outb(0xBF, base + UART_LCR);
1362 val = inb(base + UART_SCR);
1363 outb(LCR, base + UART_LCR);
1364 return val;
1365 }
1366
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1367 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1368 {
1369 unsigned long base = port->port.iobase;
1370 u8 LCR;
1371
1372 LCR = inb(base + UART_LCR);
1373 outb(0xBF, base + UART_LCR);
1374 inb(base + UART_SCR);
1375 outb(qopr, base + UART_SCR);
1376 outb(LCR, base + UART_LCR);
1377 }
1378
pci_quatech_rqmcr(struct uart_8250_port * port)1379 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1380 {
1381 unsigned long base = port->port.iobase;
1382 u8 LCR, val, qmcr;
1383
1384 LCR = inb(base + UART_LCR);
1385 outb(0xBF, base + UART_LCR);
1386 val = inb(base + UART_SCR);
1387 outb(val | 0x10, base + UART_SCR);
1388 qmcr = inb(base + UART_MCR);
1389 outb(val, base + UART_SCR);
1390 outb(LCR, base + UART_LCR);
1391
1392 return qmcr;
1393 }
1394
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1395 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1396 {
1397 unsigned long base = port->port.iobase;
1398 u8 LCR, val;
1399
1400 LCR = inb(base + UART_LCR);
1401 outb(0xBF, base + UART_LCR);
1402 val = inb(base + UART_SCR);
1403 outb(val | 0x10, base + UART_SCR);
1404 outb(qmcr, base + UART_MCR);
1405 outb(val, base + UART_SCR);
1406 outb(LCR, base + UART_LCR);
1407 }
1408
pci_quatech_has_qmcr(struct uart_8250_port * port)1409 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1410 {
1411 unsigned long base = port->port.iobase;
1412 u8 LCR, val;
1413
1414 LCR = inb(base + UART_LCR);
1415 outb(0xBF, base + UART_LCR);
1416 val = inb(base + UART_SCR);
1417 if (val & 0x20) {
1418 outb(0x80, UART_LCR);
1419 if (!(inb(UART_SCR) & 0x20)) {
1420 outb(LCR, base + UART_LCR);
1421 return 1;
1422 }
1423 }
1424 return 0;
1425 }
1426
pci_quatech_test(struct uart_8250_port * port)1427 static int pci_quatech_test(struct uart_8250_port *port)
1428 {
1429 u8 reg, qopr;
1430
1431 qopr = pci_quatech_rqopr(port);
1432 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1433 reg = pci_quatech_rqopr(port) & 0xC0;
1434 if (reg != QPCR_TEST_GET1)
1435 return -EINVAL;
1436 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1437 reg = pci_quatech_rqopr(port) & 0xC0;
1438 if (reg != QPCR_TEST_GET2)
1439 return -EINVAL;
1440 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1441 reg = pci_quatech_rqopr(port) & 0xC0;
1442 if (reg != QPCR_TEST_GET3)
1443 return -EINVAL;
1444 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1445 reg = pci_quatech_rqopr(port) & 0xC0;
1446 if (reg != QPCR_TEST_GET4)
1447 return -EINVAL;
1448
1449 pci_quatech_wqopr(port, qopr);
1450 return 0;
1451 }
1452
pci_quatech_clock(struct uart_8250_port * port)1453 static int pci_quatech_clock(struct uart_8250_port *port)
1454 {
1455 u8 qopr, reg, set;
1456 unsigned long clock;
1457
1458 if (pci_quatech_test(port) < 0)
1459 return 1843200;
1460
1461 qopr = pci_quatech_rqopr(port);
1462
1463 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1464 reg = pci_quatech_rqopr(port);
1465 if (reg & QOPR_CLOCK_X8) {
1466 clock = 1843200;
1467 goto out;
1468 }
1469 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1470 reg = pci_quatech_rqopr(port);
1471 if (!(reg & QOPR_CLOCK_X8)) {
1472 clock = 1843200;
1473 goto out;
1474 }
1475 reg &= QOPR_CLOCK_X8;
1476 if (reg == QOPR_CLOCK_X2) {
1477 clock = 3685400;
1478 set = QOPR_CLOCK_X2;
1479 } else if (reg == QOPR_CLOCK_X4) {
1480 clock = 7372800;
1481 set = QOPR_CLOCK_X4;
1482 } else if (reg == QOPR_CLOCK_X8) {
1483 clock = 14745600;
1484 set = QOPR_CLOCK_X8;
1485 } else {
1486 clock = 1843200;
1487 set = QOPR_CLOCK_X1;
1488 }
1489 qopr &= ~QOPR_CLOCK_RATE_MASK;
1490 qopr |= set;
1491
1492 out:
1493 pci_quatech_wqopr(port, qopr);
1494 return clock;
1495 }
1496
pci_quatech_rs422(struct uart_8250_port * port)1497 static int pci_quatech_rs422(struct uart_8250_port *port)
1498 {
1499 u8 qmcr;
1500 int rs422 = 0;
1501
1502 if (!pci_quatech_has_qmcr(port))
1503 return 0;
1504 qmcr = pci_quatech_rqmcr(port);
1505 pci_quatech_wqmcr(port, 0xFF);
1506 if (pci_quatech_rqmcr(port))
1507 rs422 = 1;
1508 pci_quatech_wqmcr(port, qmcr);
1509 return rs422;
1510 }
1511
pci_quatech_init(struct pci_dev * dev)1512 static int pci_quatech_init(struct pci_dev *dev)
1513 {
1514 const struct pci_device_id *match;
1515 bool amcc = false;
1516
1517 match = pci_match_id(quatech_cards, dev);
1518 if (match)
1519 amcc = match->driver_data;
1520 else
1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1522
1523 if (amcc) {
1524 unsigned long base = pci_resource_start(dev, 0);
1525 if (base) {
1526 u32 tmp;
1527
1528 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1529 tmp = inl(base + 0x3c);
1530 outl(tmp | 0x01000000, base + 0x3c);
1531 outl(tmp & ~0x01000000, base + 0x3c);
1532 }
1533 }
1534 return 0;
1535 }
1536
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1537 static int pci_quatech_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1540 {
1541 /* Needed by pci_quatech calls below */
1542 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1543 /* Set up the clocking */
1544 port->port.uartclk = pci_quatech_clock(port);
1545 /* For now just warn about RS422 */
1546 if (pci_quatech_rs422(port))
1547 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1548 return pci_default_setup(priv, board, port, idx);
1549 }
1550
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1551 static int pci_default_setup(struct serial_private *priv,
1552 const struct pciserial_board *board,
1553 struct uart_8250_port *port, int idx)
1554 {
1555 unsigned int bar, offset = board->first_offset, maxnr;
1556
1557 bar = FL_GET_BASE(board->flags);
1558 if (board->flags & FL_BASE_BARS)
1559 bar += idx;
1560 else
1561 offset += idx * board->uart_offset;
1562
1563 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1564 (board->reg_shift + 3);
1565
1566 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1567 return 1;
1568
1569 return setup_port(priv, port, bar, offset, board->reg_shift);
1570 }
1571
1572 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1573 ce4100_serial_setup(struct serial_private *priv,
1574 const struct pciserial_board *board,
1575 struct uart_8250_port *port, int idx)
1576 {
1577 int ret;
1578
1579 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1580 port->port.iotype = UPIO_MEM32;
1581 port->port.type = PORT_XSCALE;
1582 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1583 port->port.regshift = 2;
1584
1585 return ret;
1586 }
1587
1588 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1589 pci_omegapci_setup(struct serial_private *priv,
1590 const struct pciserial_board *board,
1591 struct uart_8250_port *port, int idx)
1592 {
1593 return setup_port(priv, port, 2, idx * 8, 0);
1594 }
1595
1596 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1597 pci_brcm_trumanage_setup(struct serial_private *priv,
1598 const struct pciserial_board *board,
1599 struct uart_8250_port *port, int idx)
1600 {
1601 int ret = pci_default_setup(priv, board, port, idx);
1602
1603 port->port.type = PORT_BRCM_TRUMANAGE;
1604 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1605 return ret;
1606 }
1607
1608 /* RTS will control by MCR if this bit is 0 */
1609 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1610 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1611 #define FINTEK_RTS_INVERT BIT(5)
1612
1613 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1614 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1615 struct serial_rs485 *rs485)
1616 {
1617 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1618 u8 setting;
1619 u8 *index = (u8 *) port->private_data;
1620
1621 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1622
1623 if (rs485->flags & SER_RS485_ENABLED) {
1624 /* Enable RTS H/W control mode */
1625 setting |= FINTEK_RTS_CONTROL_BY_HW;
1626
1627 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1628 /* RTS driving high on TX */
1629 setting &= ~FINTEK_RTS_INVERT;
1630 } else {
1631 /* RTS driving low on TX */
1632 setting |= FINTEK_RTS_INVERT;
1633 }
1634 } else {
1635 /* Disable RTS H/W control mode */
1636 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1637 }
1638
1639 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1640
1641 return 0;
1642 }
1643
1644 static const struct serial_rs485 pci_fintek_rs485_supported = {
1645 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1646 /* F81504/508/512 does not support RTS delay before or after send */
1647 };
1648
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1649 static int pci_fintek_setup(struct serial_private *priv,
1650 const struct pciserial_board *board,
1651 struct uart_8250_port *port, int idx)
1652 {
1653 struct pci_dev *pdev = priv->dev;
1654 u8 *data;
1655 u8 config_base;
1656 u16 iobase;
1657
1658 config_base = 0x40 + 0x08 * idx;
1659
1660 /* Get the io address from configuration space */
1661 pci_read_config_word(pdev, config_base + 4, &iobase);
1662
1663 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1664
1665 port->port.iotype = UPIO_PORT;
1666 port->port.iobase = iobase;
1667 port->port.rs485_config = pci_fintek_rs485_config;
1668 port->port.rs485_supported = pci_fintek_rs485_supported;
1669
1670 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1671 if (!data)
1672 return -ENOMEM;
1673
1674 /* preserve index in PCI configuration space */
1675 *data = idx;
1676 port->port.private_data = data;
1677
1678 return 0;
1679 }
1680
pci_fintek_init(struct pci_dev * dev)1681 static int pci_fintek_init(struct pci_dev *dev)
1682 {
1683 unsigned long iobase;
1684 u32 max_port, i;
1685 resource_size_t bar_data[3];
1686 u8 config_base;
1687 struct serial_private *priv = pci_get_drvdata(dev);
1688
1689 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1690 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1691 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1692 return -ENODEV;
1693
1694 switch (dev->device) {
1695 case 0x1104: /* 4 ports */
1696 case 0x1108: /* 8 ports */
1697 max_port = dev->device & 0xff;
1698 break;
1699 case 0x1112: /* 12 ports */
1700 max_port = 12;
1701 break;
1702 default:
1703 return -EINVAL;
1704 }
1705
1706 /* Get the io address dispatch from the BIOS */
1707 bar_data[0] = pci_resource_start(dev, 5);
1708 bar_data[1] = pci_resource_start(dev, 4);
1709 bar_data[2] = pci_resource_start(dev, 3);
1710
1711 for (i = 0; i < max_port; ++i) {
1712 /* UART0 configuration offset start from 0x40 */
1713 config_base = 0x40 + 0x08 * i;
1714
1715 /* Calculate Real IO Port */
1716 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1717
1718 /* Enable UART I/O port */
1719 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1720
1721 /* Select 128-byte FIFO and 8x FIFO threshold */
1722 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1723
1724 /* LSB UART */
1725 pci_write_config_byte(dev, config_base + 0x04,
1726 (u8)(iobase & 0xff));
1727
1728 /* MSB UART */
1729 pci_write_config_byte(dev, config_base + 0x05,
1730 (u8)((iobase & 0xff00) >> 8));
1731
1732 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1733
1734 if (!priv) {
1735 /* First init without port data
1736 * force init to RS232 Mode
1737 */
1738 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1739 }
1740 }
1741
1742 return max_port;
1743 }
1744
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1745 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1746 {
1747 struct f815xxa_data *data = p->private_data;
1748 unsigned long flags;
1749
1750 spin_lock_irqsave(&data->lock, flags);
1751 writeb(value, p->membase + offset);
1752 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1753 spin_unlock_irqrestore(&data->lock, flags);
1754 }
1755
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1756 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1757 const struct pciserial_board *board,
1758 struct uart_8250_port *port, int idx)
1759 {
1760 struct pci_dev *pdev = priv->dev;
1761 struct f815xxa_data *data;
1762
1763 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1764 if (!data)
1765 return -ENOMEM;
1766
1767 data->idx = idx;
1768 spin_lock_init(&data->lock);
1769
1770 port->port.private_data = data;
1771 port->port.iotype = UPIO_MEM;
1772 port->port.flags |= UPF_IOREMAP;
1773 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1774 port->port.serial_out = f815xxa_mem_serial_out;
1775
1776 return 0;
1777 }
1778
pci_fintek_f815xxa_init(struct pci_dev * dev)1779 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1780 {
1781 u32 max_port, i;
1782 int config_base;
1783
1784 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1785 return -ENODEV;
1786
1787 switch (dev->device) {
1788 case 0x1204: /* 4 ports */
1789 case 0x1208: /* 8 ports */
1790 max_port = dev->device & 0xff;
1791 break;
1792 case 0x1212: /* 12 ports */
1793 max_port = 12;
1794 break;
1795 default:
1796 return -EINVAL;
1797 }
1798
1799 /* Set to mmio decode */
1800 pci_write_config_byte(dev, 0x209, 0x40);
1801
1802 for (i = 0; i < max_port; ++i) {
1803 /* UART0 configuration offset start from 0x2A0 */
1804 config_base = 0x2A0 + 0x08 * i;
1805
1806 /* Select 128-byte FIFO and 8x FIFO threshold */
1807 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1808
1809 /* Enable UART I/O port */
1810 pci_write_config_byte(dev, config_base + 0, 0x01);
1811 }
1812
1813 return max_port;
1814 }
1815
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1816 static int skip_tx_en_setup(struct serial_private *priv,
1817 const struct pciserial_board *board,
1818 struct uart_8250_port *port, int idx)
1819 {
1820 port->port.quirks |= UPQ_NO_TXEN_TEST;
1821 pci_dbg(priv->dev,
1822 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1823 priv->dev->vendor, priv->dev->device,
1824 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1825
1826 return pci_default_setup(priv, board, port, idx);
1827 }
1828
kt_handle_break(struct uart_port * p)1829 static void kt_handle_break(struct uart_port *p)
1830 {
1831 struct uart_8250_port *up = up_to_u8250p(p);
1832 /*
1833 * On receipt of a BI, serial device in Intel ME (Intel
1834 * management engine) needs to have its fifos cleared for sane
1835 * SOL (Serial Over Lan) output.
1836 */
1837 serial8250_clear_and_reinit_fifos(up);
1838 }
1839
kt_serial_in(struct uart_port * p,int offset)1840 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1841 {
1842 struct uart_8250_port *up = up_to_u8250p(p);
1843 unsigned int val;
1844
1845 /*
1846 * When the Intel ME (management engine) gets reset its serial
1847 * port registers could return 0 momentarily. Functions like
1848 * serial8250_console_write, read and save the IER, perform
1849 * some operation and then restore it. In order to avoid
1850 * setting IER register inadvertently to 0, if the value read
1851 * is 0, double check with ier value in uart_8250_port and use
1852 * that instead. up->ier should be the same value as what is
1853 * currently configured.
1854 */
1855 val = inb(p->iobase + offset);
1856 if (offset == UART_IER) {
1857 if (val == 0)
1858 val = up->ier;
1859 }
1860 return val;
1861 }
1862
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1863 static int kt_serial_setup(struct serial_private *priv,
1864 const struct pciserial_board *board,
1865 struct uart_8250_port *port, int idx)
1866 {
1867 port->port.flags |= UPF_BUG_THRE;
1868 port->port.serial_in = kt_serial_in;
1869 port->port.handle_break = kt_handle_break;
1870 return skip_tx_en_setup(priv, board, port, idx);
1871 }
1872
pci_eg20t_init(struct pci_dev * dev)1873 static int pci_eg20t_init(struct pci_dev *dev)
1874 {
1875 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1876 return -ENODEV;
1877 #else
1878 return 0;
1879 #endif
1880 }
1881
1882 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1883 pci_wch_ch353_setup(struct serial_private *priv,
1884 const struct pciserial_board *board,
1885 struct uart_8250_port *port, int idx)
1886 {
1887 port->port.flags |= UPF_FIXED_TYPE;
1888 port->port.type = PORT_16550A;
1889 return pci_default_setup(priv, board, port, idx);
1890 }
1891
1892 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1893 pci_wch_ch355_setup(struct serial_private *priv,
1894 const struct pciserial_board *board,
1895 struct uart_8250_port *port, int idx)
1896 {
1897 port->port.flags |= UPF_FIXED_TYPE;
1898 port->port.type = PORT_16550A;
1899 return pci_default_setup(priv, board, port, idx);
1900 }
1901
1902 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1903 pci_wch_ch38x_setup(struct serial_private *priv,
1904 const struct pciserial_board *board,
1905 struct uart_8250_port *port, int idx)
1906 {
1907 port->port.flags |= UPF_FIXED_TYPE;
1908 port->port.type = PORT_16850;
1909 return pci_default_setup(priv, board, port, idx);
1910 }
1911
1912
1913 #define CH384_XINT_ENABLE_REG 0xEB
1914 #define CH384_XINT_ENABLE_BIT 0x02
1915
pci_wch_ch38x_init(struct pci_dev * dev)1916 static int pci_wch_ch38x_init(struct pci_dev *dev)
1917 {
1918 int max_port;
1919 unsigned long iobase;
1920
1921
1922 switch (dev->device) {
1923 case 0x3853: /* 8 ports */
1924 max_port = 8;
1925 break;
1926 default:
1927 return -EINVAL;
1928 }
1929
1930 iobase = pci_resource_start(dev, 0);
1931 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1932
1933 return max_port;
1934 }
1935
pci_wch_ch38x_exit(struct pci_dev * dev)1936 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1937 {
1938 unsigned long iobase;
1939
1940 iobase = pci_resource_start(dev, 0);
1941 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1942 }
1943
1944
1945 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1946 pci_sunix_setup(struct serial_private *priv,
1947 const struct pciserial_board *board,
1948 struct uart_8250_port *port, int idx)
1949 {
1950 int bar;
1951 int offset;
1952
1953 port->port.flags |= UPF_FIXED_TYPE;
1954 port->port.type = PORT_SUNIX;
1955
1956 if (idx < 4) {
1957 bar = 0;
1958 offset = idx * board->uart_offset;
1959 } else {
1960 bar = 1;
1961 idx -= 4;
1962 idx = div_s64_rem(idx, 4, &offset);
1963 offset = idx * 64 + offset * board->uart_offset;
1964 }
1965
1966 return setup_port(priv, port, bar, offset, 0);
1967 }
1968
1969 #define MOXA_PUART_GPIO_EN 0x09
1970 #define MOXA_PUART_GPIO_OUT 0x0A
1971
1972 #define MOXA_GPIO_PIN2 BIT(2)
1973
1974 #define MOXA_RS232 0x00
1975 #define MOXA_RS422 0x01
1976 #define MOXA_RS485_4W 0x0B
1977 #define MOXA_RS485_2W 0x0F
1978 #define MOXA_UIR_OFFSET 0x04
1979 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
1980 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
1981
1982 enum {
1983 MOXA_SUPP_RS232 = BIT(0),
1984 MOXA_SUPP_RS422 = BIT(1),
1985 MOXA_SUPP_RS485 = BIT(2),
1986 };
1987
moxa_get_nports(unsigned short device)1988 static unsigned short moxa_get_nports(unsigned short device)
1989 {
1990 switch (device) {
1991 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
1992 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
1993 return 8;
1994 }
1995
1996 return FIELD_GET(0x00F0, device);
1997 }
1998
pci_moxa_is_mini_pcie(unsigned short device)1999 static bool pci_moxa_is_mini_pcie(unsigned short device)
2000 {
2001 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2002 device == PCI_DEVICE_ID_MOXA_CP104N ||
2003 device == PCI_DEVICE_ID_MOXA_CP112N ||
2004 device == PCI_DEVICE_ID_MOXA_CP114N ||
2005 device == PCI_DEVICE_ID_MOXA_CP132N ||
2006 device == PCI_DEVICE_ID_MOXA_CP134N)
2007 return true;
2008
2009 return false;
2010 }
2011
pci_moxa_supported_rs(struct pci_dev * dev)2012 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2013 {
2014 switch (dev->device & 0x0F00) {
2015 case 0x0000:
2016 case 0x0600:
2017 return MOXA_SUPP_RS232;
2018 case 0x0100:
2019 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2020 case 0x0300:
2021 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2022 }
2023 return 0;
2024 }
2025
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2026 static int pci_moxa_set_interface(const struct pci_dev *dev,
2027 unsigned int port_idx,
2028 u8 mode)
2029 {
2030 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2031 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2032 u8 val;
2033
2034 val = inb(UIR_addr);
2035
2036 if (port_idx % 2) {
2037 val &= ~MOXA_ODD_RS_MASK;
2038 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2039 } else {
2040 val &= ~MOXA_EVEN_RS_MASK;
2041 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2042 }
2043 outb(val, UIR_addr);
2044
2045 return 0;
2046 }
2047
pci_moxa_init(struct pci_dev * dev)2048 static int pci_moxa_init(struct pci_dev *dev)
2049 {
2050 unsigned short device = dev->device;
2051 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2052 unsigned int i, num_ports = moxa_get_nports(device);
2053 u8 val, init_mode = MOXA_RS232;
2054
2055 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2056 init_mode = MOXA_RS422;
2057 }
2058 for (i = 0; i < num_ports; ++i)
2059 pci_moxa_set_interface(dev, i, init_mode);
2060
2061 /*
2062 * Enable hardware buffer to prevent break signal output when system boots up.
2063 * This hardware buffer is only supported on Mini PCIe series.
2064 */
2065 if (pci_moxa_is_mini_pcie(device)) {
2066 /* Set GPIO direction */
2067 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2068 val |= MOXA_GPIO_PIN2;
2069 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2070 /* Enable low GPIO */
2071 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2072 val &= ~MOXA_GPIO_PIN2;
2073 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2074 }
2075
2076 return num_ports;
2077 }
2078
2079 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2080 pci_moxa_setup(struct serial_private *priv,
2081 const struct pciserial_board *board,
2082 struct uart_8250_port *port, int idx)
2083 {
2084 unsigned int bar = FL_GET_BASE(board->flags);
2085 int offset;
2086
2087 if (board->num_ports == 4 && idx == 3)
2088 offset = 7 * board->uart_offset;
2089 else
2090 offset = idx * board->uart_offset;
2091
2092 return setup_port(priv, port, bar, offset, 0);
2093 }
2094
2095 /*
2096 * Master list of serial port init/setup/exit quirks.
2097 * This does not describe the general nature of the port.
2098 * (ie, baud base, number and location of ports, etc)
2099 *
2100 * This list is ordered alphabetically by vendor then device.
2101 * Specific entries must come before more generic entries.
2102 */
2103 static struct pci_serial_quirk pci_serial_quirks[] = {
2104 /*
2105 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2106 */
2107 {
2108 .vendor = PCI_VENDOR_ID_AMCC,
2109 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2110 .subvendor = PCI_ANY_ID,
2111 .subdevice = PCI_ANY_ID,
2112 .setup = addidata_apci7800_setup,
2113 },
2114 /*
2115 * AFAVLAB cards - these may be called via parport_serial
2116 * It is not clear whether this applies to all products.
2117 */
2118 {
2119 .vendor = PCI_VENDOR_ID_AFAVLAB,
2120 .device = PCI_ANY_ID,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = afavlab_setup,
2124 },
2125 /*
2126 * HP Diva
2127 */
2128 {
2129 .vendor = PCI_VENDOR_ID_HP,
2130 .device = PCI_DEVICE_ID_HP_DIVA,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .init = pci_hp_diva_init,
2134 .setup = pci_hp_diva_setup,
2135 },
2136 /*
2137 * HPE PCI serial device
2138 */
2139 {
2140 .vendor = PCI_VENDOR_ID_HP_3PAR,
2141 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2142 .subvendor = PCI_ANY_ID,
2143 .subdevice = PCI_ANY_ID,
2144 .setup = pci_hp_diva_setup,
2145 },
2146 /*
2147 * Intel
2148 */
2149 {
2150 .vendor = PCI_VENDOR_ID_INTEL,
2151 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2152 .subvendor = 0xe4bf,
2153 .subdevice = PCI_ANY_ID,
2154 .init = pci_inteli960ni_init,
2155 .setup = pci_default_setup,
2156 },
2157 {
2158 .vendor = PCI_VENDOR_ID_INTEL,
2159 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2160 .subvendor = PCI_ANY_ID,
2161 .subdevice = PCI_ANY_ID,
2162 .setup = skip_tx_en_setup,
2163 },
2164 {
2165 .vendor = PCI_VENDOR_ID_INTEL,
2166 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2167 .subvendor = PCI_ANY_ID,
2168 .subdevice = PCI_ANY_ID,
2169 .setup = skip_tx_en_setup,
2170 },
2171 {
2172 .vendor = PCI_VENDOR_ID_INTEL,
2173 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2174 .subvendor = PCI_ANY_ID,
2175 .subdevice = PCI_ANY_ID,
2176 .setup = skip_tx_en_setup,
2177 },
2178 {
2179 .vendor = PCI_VENDOR_ID_INTEL,
2180 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2181 .subvendor = PCI_ANY_ID,
2182 .subdevice = PCI_ANY_ID,
2183 .setup = ce4100_serial_setup,
2184 },
2185 {
2186 .vendor = PCI_VENDOR_ID_INTEL,
2187 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2188 .subvendor = PCI_ANY_ID,
2189 .subdevice = PCI_ANY_ID,
2190 .setup = kt_serial_setup,
2191 },
2192 /*
2193 * ITE
2194 */
2195 {
2196 .vendor = PCI_VENDOR_ID_ITE,
2197 .device = PCI_DEVICE_ID_ITE_8872,
2198 .subvendor = PCI_ANY_ID,
2199 .subdevice = PCI_ANY_ID,
2200 .init = pci_ite887x_init,
2201 .setup = pci_default_setup,
2202 .exit = pci_ite887x_exit,
2203 },
2204 /*
2205 * National Instruments
2206 */
2207 {
2208 .vendor = PCI_VENDOR_ID_NI,
2209 .device = PCI_DEVICE_ID_NI_PCI23216,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .init = pci_ni8420_init,
2213 .setup = pci_default_setup,
2214 .exit = pci_ni8420_exit,
2215 },
2216 {
2217 .vendor = PCI_VENDOR_ID_NI,
2218 .device = PCI_DEVICE_ID_NI_PCI2328,
2219 .subvendor = PCI_ANY_ID,
2220 .subdevice = PCI_ANY_ID,
2221 .init = pci_ni8420_init,
2222 .setup = pci_default_setup,
2223 .exit = pci_ni8420_exit,
2224 },
2225 {
2226 .vendor = PCI_VENDOR_ID_NI,
2227 .device = PCI_DEVICE_ID_NI_PCI2324,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .init = pci_ni8420_init,
2231 .setup = pci_default_setup,
2232 .exit = pci_ni8420_exit,
2233 },
2234 {
2235 .vendor = PCI_VENDOR_ID_NI,
2236 .device = PCI_DEVICE_ID_NI_PCI2322,
2237 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID,
2239 .init = pci_ni8420_init,
2240 .setup = pci_default_setup,
2241 .exit = pci_ni8420_exit,
2242 },
2243 {
2244 .vendor = PCI_VENDOR_ID_NI,
2245 .device = PCI_DEVICE_ID_NI_PCI2324I,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .init = pci_ni8420_init,
2249 .setup = pci_default_setup,
2250 .exit = pci_ni8420_exit,
2251 },
2252 {
2253 .vendor = PCI_VENDOR_ID_NI,
2254 .device = PCI_DEVICE_ID_NI_PCI2322I,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .init = pci_ni8420_init,
2258 .setup = pci_default_setup,
2259 .exit = pci_ni8420_exit,
2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_NI,
2263 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .init = pci_ni8420_init,
2267 .setup = pci_default_setup,
2268 .exit = pci_ni8420_exit,
2269 },
2270 {
2271 .vendor = PCI_VENDOR_ID_NI,
2272 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .init = pci_ni8420_init,
2276 .setup = pci_default_setup,
2277 .exit = pci_ni8420_exit,
2278 },
2279 {
2280 .vendor = PCI_VENDOR_ID_NI,
2281 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2282 .subvendor = PCI_ANY_ID,
2283 .subdevice = PCI_ANY_ID,
2284 .init = pci_ni8420_init,
2285 .setup = pci_default_setup,
2286 .exit = pci_ni8420_exit,
2287 },
2288 {
2289 .vendor = PCI_VENDOR_ID_NI,
2290 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .init = pci_ni8420_init,
2294 .setup = pci_default_setup,
2295 .exit = pci_ni8420_exit,
2296 },
2297 {
2298 .vendor = PCI_VENDOR_ID_NI,
2299 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2300 .subvendor = PCI_ANY_ID,
2301 .subdevice = PCI_ANY_ID,
2302 .init = pci_ni8420_init,
2303 .setup = pci_default_setup,
2304 .exit = pci_ni8420_exit,
2305 },
2306 {
2307 .vendor = PCI_VENDOR_ID_NI,
2308 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2309 .subvendor = PCI_ANY_ID,
2310 .subdevice = PCI_ANY_ID,
2311 .init = pci_ni8420_init,
2312 .setup = pci_default_setup,
2313 .exit = pci_ni8420_exit,
2314 },
2315 {
2316 .vendor = PCI_VENDOR_ID_NI,
2317 .device = PCI_ANY_ID,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .init = pci_ni8430_init,
2321 .setup = pci_ni8430_setup,
2322 .exit = pci_ni8430_exit,
2323 },
2324 /* Quatech */
2325 {
2326 .vendor = PCI_VENDOR_ID_QUATECH,
2327 .device = PCI_ANY_ID,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .init = pci_quatech_init,
2331 .setup = pci_quatech_setup,
2332 },
2333 /*
2334 * Panacom
2335 */
2336 {
2337 .vendor = PCI_VENDOR_ID_PANACOM,
2338 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2339 .subvendor = PCI_ANY_ID,
2340 .subdevice = PCI_ANY_ID,
2341 .init = pci_plx9050_init,
2342 .setup = pci_default_setup,
2343 .exit = pci_plx9050_exit,
2344 },
2345 {
2346 .vendor = PCI_VENDOR_ID_PANACOM,
2347 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2348 .subvendor = PCI_ANY_ID,
2349 .subdevice = PCI_ANY_ID,
2350 .init = pci_plx9050_init,
2351 .setup = pci_default_setup,
2352 .exit = pci_plx9050_exit,
2353 },
2354 /*
2355 * PLX
2356 */
2357 {
2358 .vendor = PCI_VENDOR_ID_PLX,
2359 .device = PCI_DEVICE_ID_PLX_9050,
2360 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2361 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2362 .init = pci_plx9050_init,
2363 .setup = pci_default_setup,
2364 .exit = pci_plx9050_exit,
2365 },
2366 {
2367 .vendor = PCI_VENDOR_ID_PLX,
2368 .device = PCI_DEVICE_ID_PLX_9050,
2369 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2370 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2371 .init = pci_plx9050_init,
2372 .setup = pci_default_setup,
2373 .exit = pci_plx9050_exit,
2374 },
2375 {
2376 .vendor = PCI_VENDOR_ID_PLX,
2377 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2378 .subvendor = PCI_VENDOR_ID_PLX,
2379 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2380 .init = pci_plx9050_init,
2381 .setup = pci_default_setup,
2382 .exit = pci_plx9050_exit,
2383 },
2384 /*
2385 * SBS Technologies, Inc., PMC-OCTALPRO 232
2386 */
2387 {
2388 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2389 .device = PCI_DEVICE_ID_OCTPRO,
2390 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2391 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2392 .init = sbs_init,
2393 .setup = sbs_setup,
2394 .exit = sbs_exit,
2395 },
2396 /*
2397 * SBS Technologies, Inc., PMC-OCTALPRO 422
2398 */
2399 {
2400 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2401 .device = PCI_DEVICE_ID_OCTPRO,
2402 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2403 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2404 .init = sbs_init,
2405 .setup = sbs_setup,
2406 .exit = sbs_exit,
2407 },
2408 /*
2409 * SBS Technologies, Inc., P-Octal 232
2410 */
2411 {
2412 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2413 .device = PCI_DEVICE_ID_OCTPRO,
2414 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2415 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2416 .init = sbs_init,
2417 .setup = sbs_setup,
2418 .exit = sbs_exit,
2419 },
2420 /*
2421 * SBS Technologies, Inc., P-Octal 422
2422 */
2423 {
2424 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2425 .device = PCI_DEVICE_ID_OCTPRO,
2426 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2427 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2428 .init = sbs_init,
2429 .setup = sbs_setup,
2430 .exit = sbs_exit,
2431 },
2432 /*
2433 * SIIG cards - these may be called via parport_serial
2434 */
2435 {
2436 .vendor = PCI_VENDOR_ID_SIIG,
2437 .device = PCI_ANY_ID,
2438 .subvendor = PCI_ANY_ID,
2439 .subdevice = PCI_ANY_ID,
2440 .init = pci_siig_init,
2441 .setup = pci_siig_setup,
2442 },
2443 /*
2444 * Titan cards
2445 */
2446 {
2447 .vendor = PCI_VENDOR_ID_TITAN,
2448 .device = PCI_DEVICE_ID_TITAN_400L,
2449 .subvendor = PCI_ANY_ID,
2450 .subdevice = PCI_ANY_ID,
2451 .setup = titan_400l_800l_setup,
2452 },
2453 {
2454 .vendor = PCI_VENDOR_ID_TITAN,
2455 .device = PCI_DEVICE_ID_TITAN_800L,
2456 .subvendor = PCI_ANY_ID,
2457 .subdevice = PCI_ANY_ID,
2458 .setup = titan_400l_800l_setup,
2459 },
2460 /*
2461 * Timedia cards
2462 */
2463 {
2464 .vendor = PCI_VENDOR_ID_TIMEDIA,
2465 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2466 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2467 .subdevice = PCI_ANY_ID,
2468 .probe = pci_timedia_probe,
2469 .init = pci_timedia_init,
2470 .setup = pci_timedia_setup,
2471 },
2472 {
2473 .vendor = PCI_VENDOR_ID_TIMEDIA,
2474 .device = PCI_ANY_ID,
2475 .subvendor = PCI_ANY_ID,
2476 .subdevice = PCI_ANY_ID,
2477 .setup = pci_timedia_setup,
2478 },
2479 /*
2480 * Sunix PCI serial boards
2481 */
2482 {
2483 .vendor = PCI_VENDOR_ID_SUNIX,
2484 .device = PCI_DEVICE_ID_SUNIX_1999,
2485 .subvendor = PCI_VENDOR_ID_SUNIX,
2486 .subdevice = PCI_ANY_ID,
2487 .setup = pci_sunix_setup,
2488 },
2489 /*
2490 * Xircom cards
2491 */
2492 {
2493 .vendor = PCI_VENDOR_ID_XIRCOM,
2494 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .init = pci_xircom_init,
2498 .setup = pci_default_setup,
2499 },
2500 /*
2501 * Netmos cards - these may be called via parport_serial
2502 */
2503 {
2504 .vendor = PCI_VENDOR_ID_NETMOS,
2505 .device = PCI_ANY_ID,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .init = pci_netmos_init,
2509 .setup = pci_netmos_9900_setup,
2510 },
2511 /*
2512 * EndRun Technologies
2513 */
2514 {
2515 .vendor = PCI_VENDOR_ID_ENDRUN,
2516 .device = PCI_ANY_ID,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .init = pci_oxsemi_tornado_init,
2520 .setup = pci_default_setup,
2521 },
2522 /*
2523 * For Oxford Semiconductor Tornado based devices
2524 */
2525 {
2526 .vendor = PCI_VENDOR_ID_OXSEMI,
2527 .device = PCI_ANY_ID,
2528 .subvendor = PCI_ANY_ID,
2529 .subdevice = PCI_ANY_ID,
2530 .init = pci_oxsemi_tornado_init,
2531 .setup = pci_oxsemi_tornado_setup,
2532 },
2533 {
2534 .vendor = PCI_VENDOR_ID_MAINPINE,
2535 .device = PCI_ANY_ID,
2536 .subvendor = PCI_ANY_ID,
2537 .subdevice = PCI_ANY_ID,
2538 .init = pci_oxsemi_tornado_init,
2539 .setup = pci_oxsemi_tornado_setup,
2540 },
2541 {
2542 .vendor = PCI_VENDOR_ID_DIGI,
2543 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2544 .subvendor = PCI_SUBVENDOR_ID_IBM,
2545 .subdevice = PCI_ANY_ID,
2546 .init = pci_oxsemi_tornado_init,
2547 .setup = pci_oxsemi_tornado_setup,
2548 },
2549 /*
2550 * Brainboxes devices - all Oxsemi based
2551 */
2552 {
2553 .vendor = PCI_VENDOR_ID_INTASHIELD,
2554 .device = 0x4027,
2555 .subvendor = PCI_ANY_ID,
2556 .subdevice = PCI_ANY_ID,
2557 .init = pci_oxsemi_tornado_init,
2558 .setup = pci_oxsemi_tornado_setup,
2559 },
2560 {
2561 .vendor = PCI_VENDOR_ID_INTASHIELD,
2562 .device = 0x4028,
2563 .subvendor = PCI_ANY_ID,
2564 .subdevice = PCI_ANY_ID,
2565 .init = pci_oxsemi_tornado_init,
2566 .setup = pci_oxsemi_tornado_setup,
2567 },
2568 {
2569 .vendor = PCI_VENDOR_ID_INTASHIELD,
2570 .device = 0x4029,
2571 .subvendor = PCI_ANY_ID,
2572 .subdevice = PCI_ANY_ID,
2573 .init = pci_oxsemi_tornado_init,
2574 .setup = pci_oxsemi_tornado_setup,
2575 },
2576 {
2577 .vendor = PCI_VENDOR_ID_INTASHIELD,
2578 .device = 0x4019,
2579 .subvendor = PCI_ANY_ID,
2580 .subdevice = PCI_ANY_ID,
2581 .init = pci_oxsemi_tornado_init,
2582 .setup = pci_oxsemi_tornado_setup,
2583 },
2584 {
2585 .vendor = PCI_VENDOR_ID_INTASHIELD,
2586 .device = 0x4016,
2587 .subvendor = PCI_ANY_ID,
2588 .subdevice = PCI_ANY_ID,
2589 .init = pci_oxsemi_tornado_init,
2590 .setup = pci_oxsemi_tornado_setup,
2591 },
2592 {
2593 .vendor = PCI_VENDOR_ID_INTASHIELD,
2594 .device = 0x4015,
2595 .subvendor = PCI_ANY_ID,
2596 .subdevice = PCI_ANY_ID,
2597 .init = pci_oxsemi_tornado_init,
2598 .setup = pci_oxsemi_tornado_setup,
2599 },
2600 {
2601 .vendor = PCI_VENDOR_ID_INTASHIELD,
2602 .device = 0x400A,
2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
2605 .init = pci_oxsemi_tornado_init,
2606 .setup = pci_oxsemi_tornado_setup,
2607 },
2608 {
2609 .vendor = PCI_VENDOR_ID_INTASHIELD,
2610 .device = 0x400E,
2611 .subvendor = PCI_ANY_ID,
2612 .subdevice = PCI_ANY_ID,
2613 .init = pci_oxsemi_tornado_init,
2614 .setup = pci_oxsemi_tornado_setup,
2615 },
2616 {
2617 .vendor = PCI_VENDOR_ID_INTASHIELD,
2618 .device = 0x400C,
2619 .subvendor = PCI_ANY_ID,
2620 .subdevice = PCI_ANY_ID,
2621 .init = pci_oxsemi_tornado_init,
2622 .setup = pci_oxsemi_tornado_setup,
2623 },
2624 {
2625 .vendor = PCI_VENDOR_ID_INTASHIELD,
2626 .device = 0x400B,
2627 .subvendor = PCI_ANY_ID,
2628 .subdevice = PCI_ANY_ID,
2629 .init = pci_oxsemi_tornado_init,
2630 .setup = pci_oxsemi_tornado_setup,
2631 },
2632 {
2633 .vendor = PCI_VENDOR_ID_INTASHIELD,
2634 .device = 0x400F,
2635 .subvendor = PCI_ANY_ID,
2636 .subdevice = PCI_ANY_ID,
2637 .init = pci_oxsemi_tornado_init,
2638 .setup = pci_oxsemi_tornado_setup,
2639 },
2640 {
2641 .vendor = PCI_VENDOR_ID_INTASHIELD,
2642 .device = 0x4010,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .init = pci_oxsemi_tornado_init,
2646 .setup = pci_oxsemi_tornado_setup,
2647 },
2648 {
2649 .vendor = PCI_VENDOR_ID_INTASHIELD,
2650 .device = 0x4011,
2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
2653 .init = pci_oxsemi_tornado_init,
2654 .setup = pci_oxsemi_tornado_setup,
2655 },
2656 {
2657 .vendor = PCI_VENDOR_ID_INTASHIELD,
2658 .device = 0x401D,
2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
2661 .init = pci_oxsemi_tornado_init,
2662 .setup = pci_oxsemi_tornado_setup,
2663 },
2664 {
2665 .vendor = PCI_VENDOR_ID_INTASHIELD,
2666 .device = 0x401E,
2667 .subvendor = PCI_ANY_ID,
2668 .subdevice = PCI_ANY_ID,
2669 .init = pci_oxsemi_tornado_init,
2670 .setup = pci_oxsemi_tornado_setup,
2671 },
2672 {
2673 .vendor = PCI_VENDOR_ID_INTASHIELD,
2674 .device = 0x4013,
2675 .subvendor = PCI_ANY_ID,
2676 .subdevice = PCI_ANY_ID,
2677 .init = pci_oxsemi_tornado_init,
2678 .setup = pci_oxsemi_tornado_setup,
2679 },
2680 {
2681 .vendor = PCI_VENDOR_ID_INTASHIELD,
2682 .device = 0x4017,
2683 .subvendor = PCI_ANY_ID,
2684 .subdevice = PCI_ANY_ID,
2685 .init = pci_oxsemi_tornado_init,
2686 .setup = pci_oxsemi_tornado_setup,
2687 },
2688 {
2689 .vendor = PCI_VENDOR_ID_INTASHIELD,
2690 .device = 0x4018,
2691 .subvendor = PCI_ANY_ID,
2692 .subdevice = PCI_ANY_ID,
2693 .init = pci_oxsemi_tornado_init,
2694 .setup = pci_oxsemi_tornado_setup,
2695 },
2696 {
2697 .vendor = PCI_VENDOR_ID_INTEL,
2698 .device = 0x8811,
2699 .subvendor = PCI_ANY_ID,
2700 .subdevice = PCI_ANY_ID,
2701 .init = pci_eg20t_init,
2702 .setup = pci_default_setup,
2703 },
2704 {
2705 .vendor = PCI_VENDOR_ID_INTEL,
2706 .device = 0x8812,
2707 .subvendor = PCI_ANY_ID,
2708 .subdevice = PCI_ANY_ID,
2709 .init = pci_eg20t_init,
2710 .setup = pci_default_setup,
2711 },
2712 {
2713 .vendor = PCI_VENDOR_ID_INTEL,
2714 .device = 0x8813,
2715 .subvendor = PCI_ANY_ID,
2716 .subdevice = PCI_ANY_ID,
2717 .init = pci_eg20t_init,
2718 .setup = pci_default_setup,
2719 },
2720 {
2721 .vendor = PCI_VENDOR_ID_INTEL,
2722 .device = 0x8814,
2723 .subvendor = PCI_ANY_ID,
2724 .subdevice = PCI_ANY_ID,
2725 .init = pci_eg20t_init,
2726 .setup = pci_default_setup,
2727 },
2728 {
2729 .vendor = 0x10DB,
2730 .device = 0x8027,
2731 .subvendor = PCI_ANY_ID,
2732 .subdevice = PCI_ANY_ID,
2733 .init = pci_eg20t_init,
2734 .setup = pci_default_setup,
2735 },
2736 {
2737 .vendor = 0x10DB,
2738 .device = 0x8028,
2739 .subvendor = PCI_ANY_ID,
2740 .subdevice = PCI_ANY_ID,
2741 .init = pci_eg20t_init,
2742 .setup = pci_default_setup,
2743 },
2744 {
2745 .vendor = 0x10DB,
2746 .device = 0x8029,
2747 .subvendor = PCI_ANY_ID,
2748 .subdevice = PCI_ANY_ID,
2749 .init = pci_eg20t_init,
2750 .setup = pci_default_setup,
2751 },
2752 {
2753 .vendor = 0x10DB,
2754 .device = 0x800C,
2755 .subvendor = PCI_ANY_ID,
2756 .subdevice = PCI_ANY_ID,
2757 .init = pci_eg20t_init,
2758 .setup = pci_default_setup,
2759 },
2760 {
2761 .vendor = 0x10DB,
2762 .device = 0x800D,
2763 .subvendor = PCI_ANY_ID,
2764 .subdevice = PCI_ANY_ID,
2765 .init = pci_eg20t_init,
2766 .setup = pci_default_setup,
2767 },
2768 /*
2769 * Cronyx Omega PCI (PLX-chip based)
2770 */
2771 {
2772 .vendor = PCI_VENDOR_ID_PLX,
2773 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2774 .subvendor = PCI_ANY_ID,
2775 .subdevice = PCI_ANY_ID,
2776 .setup = pci_omegapci_setup,
2777 },
2778 /* WCH CH353 1S1P card (16550 clone) */
2779 {
2780 .vendor = PCI_VENDOR_ID_WCH,
2781 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2782 .subvendor = PCI_ANY_ID,
2783 .subdevice = PCI_ANY_ID,
2784 .setup = pci_wch_ch353_setup,
2785 },
2786 /* WCH CH353 2S1P card (16550 clone) */
2787 {
2788 .vendor = PCI_VENDOR_ID_WCH,
2789 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2790 .subvendor = PCI_ANY_ID,
2791 .subdevice = PCI_ANY_ID,
2792 .setup = pci_wch_ch353_setup,
2793 },
2794 /* WCH CH353 4S card (16550 clone) */
2795 {
2796 .vendor = PCI_VENDOR_ID_WCH,
2797 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2798 .subvendor = PCI_ANY_ID,
2799 .subdevice = PCI_ANY_ID,
2800 .setup = pci_wch_ch353_setup,
2801 },
2802 /* WCH CH353 2S1PF card (16550 clone) */
2803 {
2804 .vendor = PCI_VENDOR_ID_WCH,
2805 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2806 .subvendor = PCI_ANY_ID,
2807 .subdevice = PCI_ANY_ID,
2808 .setup = pci_wch_ch353_setup,
2809 },
2810 /* WCH CH352 2S card (16550 clone) */
2811 {
2812 .vendor = PCI_VENDOR_ID_WCH,
2813 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2814 .subvendor = PCI_ANY_ID,
2815 .subdevice = PCI_ANY_ID,
2816 .setup = pci_wch_ch353_setup,
2817 },
2818 /* WCH CH355 4S card (16550 clone) */
2819 {
2820 .vendor = PCI_VENDOR_ID_WCH,
2821 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2822 .subvendor = PCI_ANY_ID,
2823 .subdevice = PCI_ANY_ID,
2824 .setup = pci_wch_ch355_setup,
2825 },
2826 /* WCH CH382 2S card (16850 clone) */
2827 {
2828 .vendor = PCIE_VENDOR_ID_WCH,
2829 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2830 .subvendor = PCI_ANY_ID,
2831 .subdevice = PCI_ANY_ID,
2832 .setup = pci_wch_ch38x_setup,
2833 },
2834 /* WCH CH382 2S1P card (16850 clone) */
2835 {
2836 .vendor = PCIE_VENDOR_ID_WCH,
2837 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2838 .subvendor = PCI_ANY_ID,
2839 .subdevice = PCI_ANY_ID,
2840 .setup = pci_wch_ch38x_setup,
2841 },
2842 /* WCH CH384 4S card (16850 clone) */
2843 {
2844 .vendor = PCIE_VENDOR_ID_WCH,
2845 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2846 .subvendor = PCI_ANY_ID,
2847 .subdevice = PCI_ANY_ID,
2848 .setup = pci_wch_ch38x_setup,
2849 },
2850 /* WCH CH384 8S card (16850 clone) */
2851 {
2852 .vendor = PCIE_VENDOR_ID_WCH,
2853 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2854 .subvendor = PCI_ANY_ID,
2855 .subdevice = PCI_ANY_ID,
2856 .init = pci_wch_ch38x_init,
2857 .exit = pci_wch_ch38x_exit,
2858 .setup = pci_wch_ch38x_setup,
2859 },
2860 /*
2861 * Broadcom TruManage (NetXtreme)
2862 */
2863 {
2864 .vendor = PCI_VENDOR_ID_BROADCOM,
2865 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2866 .subvendor = PCI_ANY_ID,
2867 .subdevice = PCI_ANY_ID,
2868 .setup = pci_brcm_trumanage_setup,
2869 },
2870 {
2871 .vendor = 0x1c29,
2872 .device = 0x1104,
2873 .subvendor = PCI_ANY_ID,
2874 .subdevice = PCI_ANY_ID,
2875 .setup = pci_fintek_setup,
2876 .init = pci_fintek_init,
2877 },
2878 {
2879 .vendor = 0x1c29,
2880 .device = 0x1108,
2881 .subvendor = PCI_ANY_ID,
2882 .subdevice = PCI_ANY_ID,
2883 .setup = pci_fintek_setup,
2884 .init = pci_fintek_init,
2885 },
2886 {
2887 .vendor = 0x1c29,
2888 .device = 0x1112,
2889 .subvendor = PCI_ANY_ID,
2890 .subdevice = PCI_ANY_ID,
2891 .setup = pci_fintek_setup,
2892 .init = pci_fintek_init,
2893 },
2894 /*
2895 * MOXA
2896 */
2897 {
2898 .vendor = PCI_VENDOR_ID_MOXA,
2899 .device = PCI_ANY_ID,
2900 .subvendor = PCI_ANY_ID,
2901 .subdevice = PCI_ANY_ID,
2902 .init = pci_moxa_init,
2903 .setup = pci_moxa_setup,
2904 },
2905 {
2906 .vendor = 0x1c29,
2907 .device = 0x1204,
2908 .subvendor = PCI_ANY_ID,
2909 .subdevice = PCI_ANY_ID,
2910 .setup = pci_fintek_f815xxa_setup,
2911 .init = pci_fintek_f815xxa_init,
2912 },
2913 {
2914 .vendor = 0x1c29,
2915 .device = 0x1208,
2916 .subvendor = PCI_ANY_ID,
2917 .subdevice = PCI_ANY_ID,
2918 .setup = pci_fintek_f815xxa_setup,
2919 .init = pci_fintek_f815xxa_init,
2920 },
2921 {
2922 .vendor = 0x1c29,
2923 .device = 0x1212,
2924 .subvendor = PCI_ANY_ID,
2925 .subdevice = PCI_ANY_ID,
2926 .setup = pci_fintek_f815xxa_setup,
2927 .init = pci_fintek_f815xxa_init,
2928 },
2929
2930 /*
2931 * Default "match everything" terminator entry
2932 */
2933 {
2934 .vendor = PCI_ANY_ID,
2935 .device = PCI_ANY_ID,
2936 .subvendor = PCI_ANY_ID,
2937 .subdevice = PCI_ANY_ID,
2938 .setup = pci_default_setup,
2939 }
2940 };
2941
quirk_id_matches(u32 quirk_id,u32 dev_id)2942 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2943 {
2944 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2945 }
2946
find_quirk(struct pci_dev * dev)2947 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2948 {
2949 struct pci_serial_quirk *quirk;
2950
2951 for (quirk = pci_serial_quirks; ; quirk++)
2952 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2953 quirk_id_matches(quirk->device, dev->device) &&
2954 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2955 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2956 break;
2957 return quirk;
2958 }
2959
2960 /*
2961 * This is the configuration table for all of the PCI serial boards
2962 * which we support. It is directly indexed by the pci_board_num_t enum
2963 * value, which is encoded in the pci_device_id PCI probe table's
2964 * driver_data member.
2965 *
2966 * The makeup of these names are:
2967 * pbn_bn{_bt}_n_baud{_offsetinhex}
2968 *
2969 * bn = PCI BAR number
2970 * bt = Index using PCI BARs
2971 * n = number of serial ports
2972 * baud = baud rate
2973 * offsetinhex = offset for each sequential port (in hex)
2974 *
2975 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2976 *
2977 * Please note: in theory if n = 1, _bt infix should make no difference.
2978 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2979 */
2980 enum pci_board_num_t {
2981 pbn_default = 0,
2982
2983 pbn_b0_1_115200,
2984 pbn_b0_2_115200,
2985 pbn_b0_4_115200,
2986 pbn_b0_5_115200,
2987 pbn_b0_8_115200,
2988
2989 pbn_b0_1_921600,
2990 pbn_b0_2_921600,
2991 pbn_b0_4_921600,
2992
2993 pbn_b0_2_1130000,
2994
2995 pbn_b0_4_1152000,
2996
2997 pbn_b0_4_1250000,
2998
2999 pbn_b0_2_1843200,
3000 pbn_b0_4_1843200,
3001
3002 pbn_b0_1_15625000,
3003
3004 pbn_b0_bt_1_115200,
3005 pbn_b0_bt_2_115200,
3006 pbn_b0_bt_4_115200,
3007 pbn_b0_bt_8_115200,
3008
3009 pbn_b0_bt_1_460800,
3010 pbn_b0_bt_2_460800,
3011 pbn_b0_bt_4_460800,
3012
3013 pbn_b0_bt_1_921600,
3014 pbn_b0_bt_2_921600,
3015 pbn_b0_bt_4_921600,
3016 pbn_b0_bt_8_921600,
3017
3018 pbn_b1_1_115200,
3019 pbn_b1_2_115200,
3020 pbn_b1_4_115200,
3021 pbn_b1_8_115200,
3022 pbn_b1_16_115200,
3023
3024 pbn_b1_1_921600,
3025 pbn_b1_2_921600,
3026 pbn_b1_4_921600,
3027 pbn_b1_8_921600,
3028
3029 pbn_b1_2_1250000,
3030
3031 pbn_b1_bt_1_115200,
3032 pbn_b1_bt_2_115200,
3033 pbn_b1_bt_4_115200,
3034
3035 pbn_b1_bt_2_921600,
3036
3037 pbn_b1_1_1382400,
3038 pbn_b1_2_1382400,
3039 pbn_b1_4_1382400,
3040 pbn_b1_8_1382400,
3041
3042 pbn_b2_1_115200,
3043 pbn_b2_2_115200,
3044 pbn_b2_4_115200,
3045 pbn_b2_8_115200,
3046
3047 pbn_b2_1_460800,
3048 pbn_b2_4_460800,
3049 pbn_b2_8_460800,
3050 pbn_b2_16_460800,
3051
3052 pbn_b2_1_921600,
3053 pbn_b2_4_921600,
3054 pbn_b2_8_921600,
3055
3056 pbn_b2_8_1152000,
3057
3058 pbn_b2_bt_1_115200,
3059 pbn_b2_bt_2_115200,
3060 pbn_b2_bt_4_115200,
3061
3062 pbn_b2_bt_2_921600,
3063 pbn_b2_bt_4_921600,
3064
3065 pbn_b3_2_115200,
3066 pbn_b3_4_115200,
3067 pbn_b3_8_115200,
3068
3069 pbn_b4_bt_2_921600,
3070 pbn_b4_bt_4_921600,
3071 pbn_b4_bt_8_921600,
3072
3073 /*
3074 * Board-specific versions.
3075 */
3076 pbn_panacom,
3077 pbn_panacom2,
3078 pbn_panacom4,
3079 pbn_plx_romulus,
3080 pbn_oxsemi,
3081 pbn_oxsemi_1_15625000,
3082 pbn_oxsemi_2_15625000,
3083 pbn_oxsemi_4_15625000,
3084 pbn_oxsemi_8_15625000,
3085 pbn_intel_i960,
3086 pbn_sgi_ioc3,
3087 pbn_computone_4,
3088 pbn_computone_6,
3089 pbn_computone_8,
3090 pbn_sbsxrsio,
3091 pbn_pasemi_1682M,
3092 pbn_ni8430_2,
3093 pbn_ni8430_4,
3094 pbn_ni8430_8,
3095 pbn_ni8430_16,
3096 pbn_ADDIDATA_PCIe_1_3906250,
3097 pbn_ADDIDATA_PCIe_2_3906250,
3098 pbn_ADDIDATA_PCIe_4_3906250,
3099 pbn_ADDIDATA_PCIe_8_3906250,
3100 pbn_ce4100_1_115200,
3101 pbn_omegapci,
3102 pbn_NETMOS9900_2s_115200,
3103 pbn_brcm_trumanage,
3104 pbn_fintek_4,
3105 pbn_fintek_8,
3106 pbn_fintek_12,
3107 pbn_fintek_F81504A,
3108 pbn_fintek_F81508A,
3109 pbn_fintek_F81512A,
3110 pbn_wch382_2,
3111 pbn_wch384_4,
3112 pbn_wch384_8,
3113 pbn_sunix_pci_1s,
3114 pbn_sunix_pci_2s,
3115 pbn_sunix_pci_4s,
3116 pbn_sunix_pci_8s,
3117 pbn_sunix_pci_16s,
3118 pbn_titan_1_4000000,
3119 pbn_titan_2_4000000,
3120 pbn_titan_4_4000000,
3121 pbn_titan_8_4000000,
3122 pbn_moxa_2,
3123 pbn_moxa_4,
3124 pbn_moxa_8,
3125 };
3126
3127 /*
3128 * uart_offset - the space between channels
3129 * reg_shift - describes how the UART registers are mapped
3130 * to PCI memory by the card.
3131 * For example IER register on SBS, Inc. PMC-OctPro is located at
3132 * offset 0x10 from the UART base, while UART_IER is defined as 1
3133 * in include/linux/serial_reg.h,
3134 * see first lines of serial_in() and serial_out() in 8250.c
3135 */
3136
3137 static struct pciserial_board pci_boards[] = {
3138 [pbn_default] = {
3139 .flags = FL_BASE0,
3140 .num_ports = 1,
3141 .base_baud = 115200,
3142 .uart_offset = 8,
3143 },
3144 [pbn_b0_1_115200] = {
3145 .flags = FL_BASE0,
3146 .num_ports = 1,
3147 .base_baud = 115200,
3148 .uart_offset = 8,
3149 },
3150 [pbn_b0_2_115200] = {
3151 .flags = FL_BASE0,
3152 .num_ports = 2,
3153 .base_baud = 115200,
3154 .uart_offset = 8,
3155 },
3156 [pbn_b0_4_115200] = {
3157 .flags = FL_BASE0,
3158 .num_ports = 4,
3159 .base_baud = 115200,
3160 .uart_offset = 8,
3161 },
3162 [pbn_b0_5_115200] = {
3163 .flags = FL_BASE0,
3164 .num_ports = 5,
3165 .base_baud = 115200,
3166 .uart_offset = 8,
3167 },
3168 [pbn_b0_8_115200] = {
3169 .flags = FL_BASE0,
3170 .num_ports = 8,
3171 .base_baud = 115200,
3172 .uart_offset = 8,
3173 },
3174 [pbn_b0_1_921600] = {
3175 .flags = FL_BASE0,
3176 .num_ports = 1,
3177 .base_baud = 921600,
3178 .uart_offset = 8,
3179 },
3180 [pbn_b0_2_921600] = {
3181 .flags = FL_BASE0,
3182 .num_ports = 2,
3183 .base_baud = 921600,
3184 .uart_offset = 8,
3185 },
3186 [pbn_b0_4_921600] = {
3187 .flags = FL_BASE0,
3188 .num_ports = 4,
3189 .base_baud = 921600,
3190 .uart_offset = 8,
3191 },
3192
3193 [pbn_b0_2_1130000] = {
3194 .flags = FL_BASE0,
3195 .num_ports = 2,
3196 .base_baud = 1130000,
3197 .uart_offset = 8,
3198 },
3199
3200 [pbn_b0_4_1152000] = {
3201 .flags = FL_BASE0,
3202 .num_ports = 4,
3203 .base_baud = 1152000,
3204 .uart_offset = 8,
3205 },
3206
3207 [pbn_b0_4_1250000] = {
3208 .flags = FL_BASE0,
3209 .num_ports = 4,
3210 .base_baud = 1250000,
3211 .uart_offset = 8,
3212 },
3213
3214 [pbn_b0_2_1843200] = {
3215 .flags = FL_BASE0,
3216 .num_ports = 2,
3217 .base_baud = 1843200,
3218 .uart_offset = 8,
3219 },
3220 [pbn_b0_4_1843200] = {
3221 .flags = FL_BASE0,
3222 .num_ports = 4,
3223 .base_baud = 1843200,
3224 .uart_offset = 8,
3225 },
3226
3227 [pbn_b0_1_15625000] = {
3228 .flags = FL_BASE0,
3229 .num_ports = 1,
3230 .base_baud = 15625000,
3231 .uart_offset = 8,
3232 },
3233
3234 [pbn_b0_bt_1_115200] = {
3235 .flags = FL_BASE0|FL_BASE_BARS,
3236 .num_ports = 1,
3237 .base_baud = 115200,
3238 .uart_offset = 8,
3239 },
3240 [pbn_b0_bt_2_115200] = {
3241 .flags = FL_BASE0|FL_BASE_BARS,
3242 .num_ports = 2,
3243 .base_baud = 115200,
3244 .uart_offset = 8,
3245 },
3246 [pbn_b0_bt_4_115200] = {
3247 .flags = FL_BASE0|FL_BASE_BARS,
3248 .num_ports = 4,
3249 .base_baud = 115200,
3250 .uart_offset = 8,
3251 },
3252 [pbn_b0_bt_8_115200] = {
3253 .flags = FL_BASE0|FL_BASE_BARS,
3254 .num_ports = 8,
3255 .base_baud = 115200,
3256 .uart_offset = 8,
3257 },
3258
3259 [pbn_b0_bt_1_460800] = {
3260 .flags = FL_BASE0|FL_BASE_BARS,
3261 .num_ports = 1,
3262 .base_baud = 460800,
3263 .uart_offset = 8,
3264 },
3265 [pbn_b0_bt_2_460800] = {
3266 .flags = FL_BASE0|FL_BASE_BARS,
3267 .num_ports = 2,
3268 .base_baud = 460800,
3269 .uart_offset = 8,
3270 },
3271 [pbn_b0_bt_4_460800] = {
3272 .flags = FL_BASE0|FL_BASE_BARS,
3273 .num_ports = 4,
3274 .base_baud = 460800,
3275 .uart_offset = 8,
3276 },
3277
3278 [pbn_b0_bt_1_921600] = {
3279 .flags = FL_BASE0|FL_BASE_BARS,
3280 .num_ports = 1,
3281 .base_baud = 921600,
3282 .uart_offset = 8,
3283 },
3284 [pbn_b0_bt_2_921600] = {
3285 .flags = FL_BASE0|FL_BASE_BARS,
3286 .num_ports = 2,
3287 .base_baud = 921600,
3288 .uart_offset = 8,
3289 },
3290 [pbn_b0_bt_4_921600] = {
3291 .flags = FL_BASE0|FL_BASE_BARS,
3292 .num_ports = 4,
3293 .base_baud = 921600,
3294 .uart_offset = 8,
3295 },
3296 [pbn_b0_bt_8_921600] = {
3297 .flags = FL_BASE0|FL_BASE_BARS,
3298 .num_ports = 8,
3299 .base_baud = 921600,
3300 .uart_offset = 8,
3301 },
3302
3303 [pbn_b1_1_115200] = {
3304 .flags = FL_BASE1,
3305 .num_ports = 1,
3306 .base_baud = 115200,
3307 .uart_offset = 8,
3308 },
3309 [pbn_b1_2_115200] = {
3310 .flags = FL_BASE1,
3311 .num_ports = 2,
3312 .base_baud = 115200,
3313 .uart_offset = 8,
3314 },
3315 [pbn_b1_4_115200] = {
3316 .flags = FL_BASE1,
3317 .num_ports = 4,
3318 .base_baud = 115200,
3319 .uart_offset = 8,
3320 },
3321 [pbn_b1_8_115200] = {
3322 .flags = FL_BASE1,
3323 .num_ports = 8,
3324 .base_baud = 115200,
3325 .uart_offset = 8,
3326 },
3327 [pbn_b1_16_115200] = {
3328 .flags = FL_BASE1,
3329 .num_ports = 16,
3330 .base_baud = 115200,
3331 .uart_offset = 8,
3332 },
3333
3334 [pbn_b1_1_921600] = {
3335 .flags = FL_BASE1,
3336 .num_ports = 1,
3337 .base_baud = 921600,
3338 .uart_offset = 8,
3339 },
3340 [pbn_b1_2_921600] = {
3341 .flags = FL_BASE1,
3342 .num_ports = 2,
3343 .base_baud = 921600,
3344 .uart_offset = 8,
3345 },
3346 [pbn_b1_4_921600] = {
3347 .flags = FL_BASE1,
3348 .num_ports = 4,
3349 .base_baud = 921600,
3350 .uart_offset = 8,
3351 },
3352 [pbn_b1_8_921600] = {
3353 .flags = FL_BASE1,
3354 .num_ports = 8,
3355 .base_baud = 921600,
3356 .uart_offset = 8,
3357 },
3358 [pbn_b1_2_1250000] = {
3359 .flags = FL_BASE1,
3360 .num_ports = 2,
3361 .base_baud = 1250000,
3362 .uart_offset = 8,
3363 },
3364
3365 [pbn_b1_bt_1_115200] = {
3366 .flags = FL_BASE1|FL_BASE_BARS,
3367 .num_ports = 1,
3368 .base_baud = 115200,
3369 .uart_offset = 8,
3370 },
3371 [pbn_b1_bt_2_115200] = {
3372 .flags = FL_BASE1|FL_BASE_BARS,
3373 .num_ports = 2,
3374 .base_baud = 115200,
3375 .uart_offset = 8,
3376 },
3377 [pbn_b1_bt_4_115200] = {
3378 .flags = FL_BASE1|FL_BASE_BARS,
3379 .num_ports = 4,
3380 .base_baud = 115200,
3381 .uart_offset = 8,
3382 },
3383
3384 [pbn_b1_bt_2_921600] = {
3385 .flags = FL_BASE1|FL_BASE_BARS,
3386 .num_ports = 2,
3387 .base_baud = 921600,
3388 .uart_offset = 8,
3389 },
3390
3391 [pbn_b1_1_1382400] = {
3392 .flags = FL_BASE1,
3393 .num_ports = 1,
3394 .base_baud = 1382400,
3395 .uart_offset = 8,
3396 },
3397 [pbn_b1_2_1382400] = {
3398 .flags = FL_BASE1,
3399 .num_ports = 2,
3400 .base_baud = 1382400,
3401 .uart_offset = 8,
3402 },
3403 [pbn_b1_4_1382400] = {
3404 .flags = FL_BASE1,
3405 .num_ports = 4,
3406 .base_baud = 1382400,
3407 .uart_offset = 8,
3408 },
3409 [pbn_b1_8_1382400] = {
3410 .flags = FL_BASE1,
3411 .num_ports = 8,
3412 .base_baud = 1382400,
3413 .uart_offset = 8,
3414 },
3415
3416 [pbn_b2_1_115200] = {
3417 .flags = FL_BASE2,
3418 .num_ports = 1,
3419 .base_baud = 115200,
3420 .uart_offset = 8,
3421 },
3422 [pbn_b2_2_115200] = {
3423 .flags = FL_BASE2,
3424 .num_ports = 2,
3425 .base_baud = 115200,
3426 .uart_offset = 8,
3427 },
3428 [pbn_b2_4_115200] = {
3429 .flags = FL_BASE2,
3430 .num_ports = 4,
3431 .base_baud = 115200,
3432 .uart_offset = 8,
3433 },
3434 [pbn_b2_8_115200] = {
3435 .flags = FL_BASE2,
3436 .num_ports = 8,
3437 .base_baud = 115200,
3438 .uart_offset = 8,
3439 },
3440
3441 [pbn_b2_1_460800] = {
3442 .flags = FL_BASE2,
3443 .num_ports = 1,
3444 .base_baud = 460800,
3445 .uart_offset = 8,
3446 },
3447 [pbn_b2_4_460800] = {
3448 .flags = FL_BASE2,
3449 .num_ports = 4,
3450 .base_baud = 460800,
3451 .uart_offset = 8,
3452 },
3453 [pbn_b2_8_460800] = {
3454 .flags = FL_BASE2,
3455 .num_ports = 8,
3456 .base_baud = 460800,
3457 .uart_offset = 8,
3458 },
3459 [pbn_b2_16_460800] = {
3460 .flags = FL_BASE2,
3461 .num_ports = 16,
3462 .base_baud = 460800,
3463 .uart_offset = 8,
3464 },
3465
3466 [pbn_b2_1_921600] = {
3467 .flags = FL_BASE2,
3468 .num_ports = 1,
3469 .base_baud = 921600,
3470 .uart_offset = 8,
3471 },
3472 [pbn_b2_4_921600] = {
3473 .flags = FL_BASE2,
3474 .num_ports = 4,
3475 .base_baud = 921600,
3476 .uart_offset = 8,
3477 },
3478 [pbn_b2_8_921600] = {
3479 .flags = FL_BASE2,
3480 .num_ports = 8,
3481 .base_baud = 921600,
3482 .uart_offset = 8,
3483 },
3484
3485 [pbn_b2_8_1152000] = {
3486 .flags = FL_BASE2,
3487 .num_ports = 8,
3488 .base_baud = 1152000,
3489 .uart_offset = 8,
3490 },
3491
3492 [pbn_b2_bt_1_115200] = {
3493 .flags = FL_BASE2|FL_BASE_BARS,
3494 .num_ports = 1,
3495 .base_baud = 115200,
3496 .uart_offset = 8,
3497 },
3498 [pbn_b2_bt_2_115200] = {
3499 .flags = FL_BASE2|FL_BASE_BARS,
3500 .num_ports = 2,
3501 .base_baud = 115200,
3502 .uart_offset = 8,
3503 },
3504 [pbn_b2_bt_4_115200] = {
3505 .flags = FL_BASE2|FL_BASE_BARS,
3506 .num_ports = 4,
3507 .base_baud = 115200,
3508 .uart_offset = 8,
3509 },
3510
3511 [pbn_b2_bt_2_921600] = {
3512 .flags = FL_BASE2|FL_BASE_BARS,
3513 .num_ports = 2,
3514 .base_baud = 921600,
3515 .uart_offset = 8,
3516 },
3517 [pbn_b2_bt_4_921600] = {
3518 .flags = FL_BASE2|FL_BASE_BARS,
3519 .num_ports = 4,
3520 .base_baud = 921600,
3521 .uart_offset = 8,
3522 },
3523
3524 [pbn_b3_2_115200] = {
3525 .flags = FL_BASE3,
3526 .num_ports = 2,
3527 .base_baud = 115200,
3528 .uart_offset = 8,
3529 },
3530 [pbn_b3_4_115200] = {
3531 .flags = FL_BASE3,
3532 .num_ports = 4,
3533 .base_baud = 115200,
3534 .uart_offset = 8,
3535 },
3536 [pbn_b3_8_115200] = {
3537 .flags = FL_BASE3,
3538 .num_ports = 8,
3539 .base_baud = 115200,
3540 .uart_offset = 8,
3541 },
3542
3543 [pbn_b4_bt_2_921600] = {
3544 .flags = FL_BASE4,
3545 .num_ports = 2,
3546 .base_baud = 921600,
3547 .uart_offset = 8,
3548 },
3549 [pbn_b4_bt_4_921600] = {
3550 .flags = FL_BASE4,
3551 .num_ports = 4,
3552 .base_baud = 921600,
3553 .uart_offset = 8,
3554 },
3555 [pbn_b4_bt_8_921600] = {
3556 .flags = FL_BASE4,
3557 .num_ports = 8,
3558 .base_baud = 921600,
3559 .uart_offset = 8,
3560 },
3561
3562 /*
3563 * Entries following this are board-specific.
3564 */
3565
3566 /*
3567 * Panacom - IOMEM
3568 */
3569 [pbn_panacom] = {
3570 .flags = FL_BASE2,
3571 .num_ports = 2,
3572 .base_baud = 921600,
3573 .uart_offset = 0x400,
3574 .reg_shift = 7,
3575 },
3576 [pbn_panacom2] = {
3577 .flags = FL_BASE2|FL_BASE_BARS,
3578 .num_ports = 2,
3579 .base_baud = 921600,
3580 .uart_offset = 0x400,
3581 .reg_shift = 7,
3582 },
3583 [pbn_panacom4] = {
3584 .flags = FL_BASE2|FL_BASE_BARS,
3585 .num_ports = 4,
3586 .base_baud = 921600,
3587 .uart_offset = 0x400,
3588 .reg_shift = 7,
3589 },
3590
3591 /* I think this entry is broken - the first_offset looks wrong --rmk */
3592 [pbn_plx_romulus] = {
3593 .flags = FL_BASE2,
3594 .num_ports = 4,
3595 .base_baud = 921600,
3596 .uart_offset = 8 << 2,
3597 .reg_shift = 2,
3598 .first_offset = 0x03,
3599 },
3600
3601 /*
3602 * This board uses the size of PCI Base region 0 to
3603 * signal now many ports are available
3604 */
3605 [pbn_oxsemi] = {
3606 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3607 .num_ports = 32,
3608 .base_baud = 115200,
3609 .uart_offset = 8,
3610 },
3611 [pbn_oxsemi_1_15625000] = {
3612 .flags = FL_BASE0,
3613 .num_ports = 1,
3614 .base_baud = 15625000,
3615 .uart_offset = 0x200,
3616 .first_offset = 0x1000,
3617 },
3618 [pbn_oxsemi_2_15625000] = {
3619 .flags = FL_BASE0,
3620 .num_ports = 2,
3621 .base_baud = 15625000,
3622 .uart_offset = 0x200,
3623 .first_offset = 0x1000,
3624 },
3625 [pbn_oxsemi_4_15625000] = {
3626 .flags = FL_BASE0,
3627 .num_ports = 4,
3628 .base_baud = 15625000,
3629 .uart_offset = 0x200,
3630 .first_offset = 0x1000,
3631 },
3632 [pbn_oxsemi_8_15625000] = {
3633 .flags = FL_BASE0,
3634 .num_ports = 8,
3635 .base_baud = 15625000,
3636 .uart_offset = 0x200,
3637 .first_offset = 0x1000,
3638 },
3639
3640
3641 /*
3642 * EKF addition for i960 Boards form EKF with serial port.
3643 * Max 256 ports.
3644 */
3645 [pbn_intel_i960] = {
3646 .flags = FL_BASE0,
3647 .num_ports = 32,
3648 .base_baud = 921600,
3649 .uart_offset = 8 << 2,
3650 .reg_shift = 2,
3651 .first_offset = 0x10000,
3652 },
3653 [pbn_sgi_ioc3] = {
3654 .flags = FL_BASE0|FL_NOIRQ,
3655 .num_ports = 1,
3656 .base_baud = 458333,
3657 .uart_offset = 8,
3658 .reg_shift = 0,
3659 .first_offset = 0x20178,
3660 },
3661
3662 /*
3663 * Computone - uses IOMEM.
3664 */
3665 [pbn_computone_4] = {
3666 .flags = FL_BASE0,
3667 .num_ports = 4,
3668 .base_baud = 921600,
3669 .uart_offset = 0x40,
3670 .reg_shift = 2,
3671 .first_offset = 0x200,
3672 },
3673 [pbn_computone_6] = {
3674 .flags = FL_BASE0,
3675 .num_ports = 6,
3676 .base_baud = 921600,
3677 .uart_offset = 0x40,
3678 .reg_shift = 2,
3679 .first_offset = 0x200,
3680 },
3681 [pbn_computone_8] = {
3682 .flags = FL_BASE0,
3683 .num_ports = 8,
3684 .base_baud = 921600,
3685 .uart_offset = 0x40,
3686 .reg_shift = 2,
3687 .first_offset = 0x200,
3688 },
3689 [pbn_sbsxrsio] = {
3690 .flags = FL_BASE0,
3691 .num_ports = 8,
3692 .base_baud = 460800,
3693 .uart_offset = 256,
3694 .reg_shift = 4,
3695 },
3696 /*
3697 * PA Semi PWRficient PA6T-1682M on-chip UART
3698 */
3699 [pbn_pasemi_1682M] = {
3700 .flags = FL_BASE0,
3701 .num_ports = 1,
3702 .base_baud = 8333333,
3703 },
3704 /*
3705 * National Instruments 843x
3706 */
3707 [pbn_ni8430_16] = {
3708 .flags = FL_BASE0,
3709 .num_ports = 16,
3710 .base_baud = 3686400,
3711 .uart_offset = 0x10,
3712 .first_offset = 0x800,
3713 },
3714 [pbn_ni8430_8] = {
3715 .flags = FL_BASE0,
3716 .num_ports = 8,
3717 .base_baud = 3686400,
3718 .uart_offset = 0x10,
3719 .first_offset = 0x800,
3720 },
3721 [pbn_ni8430_4] = {
3722 .flags = FL_BASE0,
3723 .num_ports = 4,
3724 .base_baud = 3686400,
3725 .uart_offset = 0x10,
3726 .first_offset = 0x800,
3727 },
3728 [pbn_ni8430_2] = {
3729 .flags = FL_BASE0,
3730 .num_ports = 2,
3731 .base_baud = 3686400,
3732 .uart_offset = 0x10,
3733 .first_offset = 0x800,
3734 },
3735 /*
3736 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3737 */
3738 [pbn_ADDIDATA_PCIe_1_3906250] = {
3739 .flags = FL_BASE0,
3740 .num_ports = 1,
3741 .base_baud = 3906250,
3742 .uart_offset = 0x200,
3743 .first_offset = 0x1000,
3744 },
3745 [pbn_ADDIDATA_PCIe_2_3906250] = {
3746 .flags = FL_BASE0,
3747 .num_ports = 2,
3748 .base_baud = 3906250,
3749 .uart_offset = 0x200,
3750 .first_offset = 0x1000,
3751 },
3752 [pbn_ADDIDATA_PCIe_4_3906250] = {
3753 .flags = FL_BASE0,
3754 .num_ports = 4,
3755 .base_baud = 3906250,
3756 .uart_offset = 0x200,
3757 .first_offset = 0x1000,
3758 },
3759 [pbn_ADDIDATA_PCIe_8_3906250] = {
3760 .flags = FL_BASE0,
3761 .num_ports = 8,
3762 .base_baud = 3906250,
3763 .uart_offset = 0x200,
3764 .first_offset = 0x1000,
3765 },
3766 [pbn_ce4100_1_115200] = {
3767 .flags = FL_BASE_BARS,
3768 .num_ports = 2,
3769 .base_baud = 921600,
3770 .reg_shift = 2,
3771 },
3772 [pbn_omegapci] = {
3773 .flags = FL_BASE0,
3774 .num_ports = 8,
3775 .base_baud = 115200,
3776 .uart_offset = 0x200,
3777 },
3778 [pbn_NETMOS9900_2s_115200] = {
3779 .flags = FL_BASE0,
3780 .num_ports = 2,
3781 .base_baud = 115200,
3782 },
3783 [pbn_brcm_trumanage] = {
3784 .flags = FL_BASE0,
3785 .num_ports = 1,
3786 .reg_shift = 2,
3787 .base_baud = 115200,
3788 },
3789 [pbn_fintek_4] = {
3790 .num_ports = 4,
3791 .uart_offset = 8,
3792 .base_baud = 115200,
3793 .first_offset = 0x40,
3794 },
3795 [pbn_fintek_8] = {
3796 .num_ports = 8,
3797 .uart_offset = 8,
3798 .base_baud = 115200,
3799 .first_offset = 0x40,
3800 },
3801 [pbn_fintek_12] = {
3802 .num_ports = 12,
3803 .uart_offset = 8,
3804 .base_baud = 115200,
3805 .first_offset = 0x40,
3806 },
3807 [pbn_fintek_F81504A] = {
3808 .num_ports = 4,
3809 .uart_offset = 8,
3810 .base_baud = 115200,
3811 },
3812 [pbn_fintek_F81508A] = {
3813 .num_ports = 8,
3814 .uart_offset = 8,
3815 .base_baud = 115200,
3816 },
3817 [pbn_fintek_F81512A] = {
3818 .num_ports = 12,
3819 .uart_offset = 8,
3820 .base_baud = 115200,
3821 },
3822 [pbn_wch382_2] = {
3823 .flags = FL_BASE0,
3824 .num_ports = 2,
3825 .base_baud = 115200,
3826 .uart_offset = 8,
3827 .first_offset = 0xC0,
3828 },
3829 [pbn_wch384_4] = {
3830 .flags = FL_BASE0,
3831 .num_ports = 4,
3832 .base_baud = 115200,
3833 .uart_offset = 8,
3834 .first_offset = 0xC0,
3835 },
3836 [pbn_wch384_8] = {
3837 .flags = FL_BASE0,
3838 .num_ports = 8,
3839 .base_baud = 115200,
3840 .uart_offset = 8,
3841 .first_offset = 0x00,
3842 },
3843 [pbn_sunix_pci_1s] = {
3844 .num_ports = 1,
3845 .base_baud = 921600,
3846 .uart_offset = 0x8,
3847 },
3848 [pbn_sunix_pci_2s] = {
3849 .num_ports = 2,
3850 .base_baud = 921600,
3851 .uart_offset = 0x8,
3852 },
3853 [pbn_sunix_pci_4s] = {
3854 .num_ports = 4,
3855 .base_baud = 921600,
3856 .uart_offset = 0x8,
3857 },
3858 [pbn_sunix_pci_8s] = {
3859 .num_ports = 8,
3860 .base_baud = 921600,
3861 .uart_offset = 0x8,
3862 },
3863 [pbn_sunix_pci_16s] = {
3864 .num_ports = 16,
3865 .base_baud = 921600,
3866 .uart_offset = 0x8,
3867 },
3868 [pbn_titan_1_4000000] = {
3869 .flags = FL_BASE0,
3870 .num_ports = 1,
3871 .base_baud = 4000000,
3872 .uart_offset = 0x200,
3873 .first_offset = 0x1000,
3874 },
3875 [pbn_titan_2_4000000] = {
3876 .flags = FL_BASE0,
3877 .num_ports = 2,
3878 .base_baud = 4000000,
3879 .uart_offset = 0x200,
3880 .first_offset = 0x1000,
3881 },
3882 [pbn_titan_4_4000000] = {
3883 .flags = FL_BASE0,
3884 .num_ports = 4,
3885 .base_baud = 4000000,
3886 .uart_offset = 0x200,
3887 .first_offset = 0x1000,
3888 },
3889 [pbn_titan_8_4000000] = {
3890 .flags = FL_BASE0,
3891 .num_ports = 8,
3892 .base_baud = 4000000,
3893 .uart_offset = 0x200,
3894 .first_offset = 0x1000,
3895 },
3896 [pbn_moxa_2] = {
3897 .flags = FL_BASE1,
3898 .num_ports = 2,
3899 .base_baud = 921600,
3900 .uart_offset = 0x200,
3901 },
3902 [pbn_moxa_4] = {
3903 .flags = FL_BASE1,
3904 .num_ports = 4,
3905 .base_baud = 921600,
3906 .uart_offset = 0x200,
3907 },
3908 [pbn_moxa_8] = {
3909 .flags = FL_BASE1,
3910 .num_ports = 8,
3911 .base_baud = 921600,
3912 .uart_offset = 0x200,
3913 },
3914 };
3915
3916 #define REPORT_CONFIG(option) \
3917 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3918 #define REPORT_8250_CONFIG(option) \
3919 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3920 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3921
3922 static const struct pci_device_id blacklist[] = {
3923 /* softmodems */
3924 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3925 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3926 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3927
3928 /* multi-io cards handled by parport_serial */
3929 /* WCH CH353 2S1P */
3930 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3931 /* WCH CH353 1S1P */
3932 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3933 /* WCH CH382 2S1P */
3934 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3935
3936 /* Intel platforms with MID UART */
3937 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3938 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3939 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3940 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3941 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3942 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3943
3944 /* Intel platforms with DesignWare UART */
3945 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3946 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3947 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3948 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3949 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3950 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3951 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3952 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3953 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3954 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3955 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3956 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3957 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
3958
3959 /* Exar devices */
3960 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3961 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3962
3963 /* Pericom devices */
3964 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3965 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3966
3967 /* End of the black list */
3968 { }
3969 };
3970
serial_pci_is_class_communication(struct pci_dev * dev)3971 static int serial_pci_is_class_communication(struct pci_dev *dev)
3972 {
3973 /*
3974 * If it is not a communications device or the programming
3975 * interface is greater than 6, give up.
3976 */
3977 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3978 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3979 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3980 (dev->class & 0xff) > 6)
3981 return -ENODEV;
3982
3983 return 0;
3984 }
3985
3986 /*
3987 * Given a complete unknown PCI device, try to use some heuristics to
3988 * guess what the configuration might be, based on the pitiful PCI
3989 * serial specs. Returns 0 on success, -ENODEV on failure.
3990 */
3991 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3992 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3993 {
3994 int num_iomem, num_port, first_port = -1, i;
3995 int rc;
3996
3997 rc = serial_pci_is_class_communication(dev);
3998 if (rc)
3999 return rc;
4000
4001 /*
4002 * Should we try to make guesses for multiport serial devices later?
4003 */
4004 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4005 return -ENODEV;
4006
4007 num_iomem = num_port = 0;
4008 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4009 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4010 num_port++;
4011 if (first_port == -1)
4012 first_port = i;
4013 }
4014 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4015 num_iomem++;
4016 }
4017
4018 /*
4019 * If there is 1 or 0 iomem regions, and exactly one port,
4020 * use it. We guess the number of ports based on the IO
4021 * region size.
4022 */
4023 if (num_iomem <= 1 && num_port == 1) {
4024 board->flags = first_port;
4025 board->num_ports = pci_resource_len(dev, first_port) / 8;
4026 return 0;
4027 }
4028
4029 /*
4030 * Now guess if we've got a board which indexes by BARs.
4031 * Each IO BAR should be 8 bytes, and they should follow
4032 * consecutively.
4033 */
4034 first_port = -1;
4035 num_port = 0;
4036 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4037 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4038 pci_resource_len(dev, i) == 8 &&
4039 (first_port == -1 || (first_port + num_port) == i)) {
4040 num_port++;
4041 if (first_port == -1)
4042 first_port = i;
4043 }
4044 }
4045
4046 if (num_port > 1) {
4047 board->flags = first_port | FL_BASE_BARS;
4048 board->num_ports = num_port;
4049 return 0;
4050 }
4051
4052 return -ENODEV;
4053 }
4054
4055 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4056 serial_pci_matches(const struct pciserial_board *board,
4057 const struct pciserial_board *guessed)
4058 {
4059 return
4060 board->num_ports == guessed->num_ports &&
4061 board->base_baud == guessed->base_baud &&
4062 board->uart_offset == guessed->uart_offset &&
4063 board->reg_shift == guessed->reg_shift &&
4064 board->first_offset == guessed->first_offset;
4065 }
4066
4067 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4068 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4069 {
4070 struct uart_8250_port uart;
4071 struct serial_private *priv;
4072 struct pci_serial_quirk *quirk;
4073 int rc, nr_ports, i;
4074
4075 nr_ports = board->num_ports;
4076
4077 /*
4078 * Find an init and setup quirks.
4079 */
4080 quirk = find_quirk(dev);
4081
4082 /*
4083 * Run the new-style initialization function.
4084 * The initialization function returns:
4085 * <0 - error
4086 * 0 - use board->num_ports
4087 * >0 - number of ports
4088 */
4089 if (quirk->init) {
4090 rc = quirk->init(dev);
4091 if (rc < 0) {
4092 priv = ERR_PTR(rc);
4093 goto err_out;
4094 }
4095 if (rc)
4096 nr_ports = rc;
4097 }
4098
4099 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
4100 if (!priv) {
4101 priv = ERR_PTR(-ENOMEM);
4102 goto err_deinit;
4103 }
4104
4105 priv->dev = dev;
4106 priv->quirk = quirk;
4107
4108 memset(&uart, 0, sizeof(uart));
4109 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4110 uart.port.uartclk = board->base_baud * 16;
4111
4112 if (board->flags & FL_NOIRQ) {
4113 uart.port.irq = 0;
4114 } else {
4115 if (pci_match_id(pci_use_msi, dev)) {
4116 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4117 pci_set_master(dev);
4118 uart.port.flags &= ~UPF_SHARE_IRQ;
4119 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4120 } else {
4121 pci_dbg(dev, "Using legacy interrupts\n");
4122 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4123 }
4124 if (rc < 0) {
4125 kfree(priv);
4126 priv = ERR_PTR(rc);
4127 goto err_deinit;
4128 }
4129
4130 uart.port.irq = pci_irq_vector(dev, 0);
4131 }
4132
4133 uart.port.dev = &dev->dev;
4134
4135 for (i = 0; i < nr_ports; i++) {
4136 if (quirk->setup(priv, board, &uart, i))
4137 break;
4138
4139 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4140 uart.port.iobase, uart.port.irq, uart.port.iotype);
4141
4142 priv->line[i] = serial8250_register_8250_port(&uart);
4143 if (priv->line[i] < 0) {
4144 pci_err(dev,
4145 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4146 uart.port.iobase, uart.port.irq,
4147 uart.port.iotype, priv->line[i]);
4148 break;
4149 }
4150 }
4151 priv->nr = i;
4152 priv->board = board;
4153 return priv;
4154
4155 err_deinit:
4156 if (quirk->exit)
4157 quirk->exit(dev);
4158 err_out:
4159 return priv;
4160 }
4161 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4162
pciserial_detach_ports(struct serial_private * priv)4163 static void pciserial_detach_ports(struct serial_private *priv)
4164 {
4165 struct pci_serial_quirk *quirk;
4166 int i;
4167
4168 for (i = 0; i < priv->nr; i++)
4169 serial8250_unregister_port(priv->line[i]);
4170
4171 /*
4172 * Find the exit quirks.
4173 */
4174 quirk = find_quirk(priv->dev);
4175 if (quirk->exit)
4176 quirk->exit(priv->dev);
4177 }
4178
pciserial_remove_ports(struct serial_private * priv)4179 void pciserial_remove_ports(struct serial_private *priv)
4180 {
4181 pciserial_detach_ports(priv);
4182 kfree(priv);
4183 }
4184 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4185
pciserial_suspend_ports(struct serial_private * priv)4186 void pciserial_suspend_ports(struct serial_private *priv)
4187 {
4188 int i;
4189
4190 for (i = 0; i < priv->nr; i++)
4191 if (priv->line[i] >= 0)
4192 serial8250_suspend_port(priv->line[i]);
4193
4194 /*
4195 * Ensure that every init quirk is properly torn down
4196 */
4197 if (priv->quirk->exit)
4198 priv->quirk->exit(priv->dev);
4199 }
4200 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4201
pciserial_resume_ports(struct serial_private * priv)4202 void pciserial_resume_ports(struct serial_private *priv)
4203 {
4204 int i;
4205
4206 /*
4207 * Ensure that the board is correctly configured.
4208 */
4209 if (priv->quirk->init)
4210 priv->quirk->init(priv->dev);
4211
4212 for (i = 0; i < priv->nr; i++)
4213 if (priv->line[i] >= 0)
4214 serial8250_resume_port(priv->line[i]);
4215 }
4216 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4217
4218 /*
4219 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4220 * to the arrangement of serial ports on a PCI card.
4221 */
4222 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4223 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4224 {
4225 struct pci_serial_quirk *quirk;
4226 struct serial_private *priv;
4227 const struct pciserial_board *board;
4228 const struct pci_device_id *exclude;
4229 struct pciserial_board tmp;
4230 int rc;
4231
4232 quirk = find_quirk(dev);
4233 if (quirk->probe) {
4234 rc = quirk->probe(dev);
4235 if (rc)
4236 return rc;
4237 }
4238
4239 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4240 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4241 return -EINVAL;
4242 }
4243
4244 board = &pci_boards[ent->driver_data];
4245
4246 exclude = pci_match_id(blacklist, dev);
4247 if (exclude) {
4248 if (exclude->driver_data)
4249 pci_warn(dev, "ignoring port, enable %s to handle\n",
4250 (const char *)exclude->driver_data);
4251 return -ENODEV;
4252 }
4253
4254 rc = pcim_enable_device(dev);
4255 pci_save_state(dev);
4256 if (rc)
4257 return rc;
4258
4259 if (ent->driver_data == pbn_default) {
4260 /*
4261 * Use a copy of the pci_board entry for this;
4262 * avoid changing entries in the table.
4263 */
4264 memcpy(&tmp, board, sizeof(struct pciserial_board));
4265 board = &tmp;
4266
4267 /*
4268 * We matched one of our class entries. Try to
4269 * determine the parameters of this board.
4270 */
4271 rc = serial_pci_guess_board(dev, &tmp);
4272 if (rc)
4273 return rc;
4274 } else {
4275 /*
4276 * We matched an explicit entry. If we are able to
4277 * detect this boards settings with our heuristic,
4278 * then we no longer need this entry.
4279 */
4280 memcpy(&tmp, &pci_boards[pbn_default],
4281 sizeof(struct pciserial_board));
4282 rc = serial_pci_guess_board(dev, &tmp);
4283 if (rc == 0 && serial_pci_matches(board, &tmp))
4284 moan_device("Redundant entry in serial pci_table.",
4285 dev);
4286 }
4287
4288 priv = pciserial_init_ports(dev, board);
4289 if (IS_ERR(priv))
4290 return PTR_ERR(priv);
4291
4292 pci_set_drvdata(dev, priv);
4293 return 0;
4294 }
4295
pciserial_remove_one(struct pci_dev * dev)4296 static void pciserial_remove_one(struct pci_dev *dev)
4297 {
4298 struct serial_private *priv = pci_get_drvdata(dev);
4299
4300 pciserial_remove_ports(priv);
4301 }
4302
4303 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4304 static int pciserial_suspend_one(struct device *dev)
4305 {
4306 struct serial_private *priv = dev_get_drvdata(dev);
4307
4308 if (priv)
4309 pciserial_suspend_ports(priv);
4310
4311 return 0;
4312 }
4313
pciserial_resume_one(struct device * dev)4314 static int pciserial_resume_one(struct device *dev)
4315 {
4316 struct pci_dev *pdev = to_pci_dev(dev);
4317 struct serial_private *priv = pci_get_drvdata(pdev);
4318 int err;
4319
4320 if (priv) {
4321 /*
4322 * The device may have been disabled. Re-enable it.
4323 */
4324 err = pci_enable_device(pdev);
4325 /* FIXME: We cannot simply error out here */
4326 if (err)
4327 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4328 pciserial_resume_ports(priv);
4329 }
4330 return 0;
4331 }
4332 #endif
4333
4334 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4335 pciserial_resume_one);
4336
4337 static const struct pci_device_id serial_pci_tbl[] = {
4338 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4339 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4340 pbn_b0_4_921600 },
4341 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4342 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4343 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4344 pbn_b2_8_921600 },
4345 /* Advantech also use 0x3618 and 0xf618 */
4346 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4347 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4348 pbn_b0_4_921600 },
4349 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4350 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4351 pbn_b0_4_921600 },
4352 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4353 PCI_SUBVENDOR_ID_CONNECT_TECH,
4354 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4355 pbn_b1_8_1382400 },
4356 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4357 PCI_SUBVENDOR_ID_CONNECT_TECH,
4358 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4359 pbn_b1_4_1382400 },
4360 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4361 PCI_SUBVENDOR_ID_CONNECT_TECH,
4362 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4363 pbn_b1_2_1382400 },
4364 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4365 PCI_SUBVENDOR_ID_CONNECT_TECH,
4366 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4367 pbn_b1_8_1382400 },
4368 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4369 PCI_SUBVENDOR_ID_CONNECT_TECH,
4370 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4371 pbn_b1_4_1382400 },
4372 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4373 PCI_SUBVENDOR_ID_CONNECT_TECH,
4374 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4375 pbn_b1_2_1382400 },
4376 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4377 PCI_SUBVENDOR_ID_CONNECT_TECH,
4378 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4379 pbn_b1_8_921600 },
4380 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4381 PCI_SUBVENDOR_ID_CONNECT_TECH,
4382 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4383 pbn_b1_8_921600 },
4384 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4385 PCI_SUBVENDOR_ID_CONNECT_TECH,
4386 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4387 pbn_b1_4_921600 },
4388 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4389 PCI_SUBVENDOR_ID_CONNECT_TECH,
4390 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4391 pbn_b1_4_921600 },
4392 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4393 PCI_SUBVENDOR_ID_CONNECT_TECH,
4394 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4395 pbn_b1_2_921600 },
4396 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4397 PCI_SUBVENDOR_ID_CONNECT_TECH,
4398 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4399 pbn_b1_8_921600 },
4400 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4401 PCI_SUBVENDOR_ID_CONNECT_TECH,
4402 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4403 pbn_b1_8_921600 },
4404 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4405 PCI_SUBVENDOR_ID_CONNECT_TECH,
4406 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4407 pbn_b1_4_921600 },
4408 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4409 PCI_SUBVENDOR_ID_CONNECT_TECH,
4410 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4411 pbn_b1_2_1250000 },
4412 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4413 PCI_SUBVENDOR_ID_CONNECT_TECH,
4414 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4415 pbn_b0_2_1843200 },
4416 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4417 PCI_SUBVENDOR_ID_CONNECT_TECH,
4418 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4419 pbn_b0_4_1843200 },
4420 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4421 PCI_VENDOR_ID_AFAVLAB,
4422 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4423 pbn_b0_4_1152000 },
4424 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_b2_bt_1_115200 },
4427 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_b2_bt_2_115200 },
4430 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b2_bt_4_115200 },
4433 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b2_bt_2_115200 },
4436 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_b2_bt_4_115200 },
4439 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b2_8_115200 },
4442 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b2_8_460800 },
4445 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b2_8_115200 },
4448
4449 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b2_bt_2_115200 },
4452 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b2_bt_2_921600 },
4455 /*
4456 * VScom SPCOM800, from sl@s.pl
4457 */
4458 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_b2_8_921600 },
4461 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_b2_4_921600 },
4464 /* Unknown card - subdevice 0x1584 */
4465 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4466 PCI_VENDOR_ID_PLX,
4467 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4468 pbn_b2_4_115200 },
4469 /* Unknown card - subdevice 0x1588 */
4470 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4471 PCI_VENDOR_ID_PLX,
4472 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4473 pbn_b2_8_115200 },
4474 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4475 PCI_SUBVENDOR_ID_KEYSPAN,
4476 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4477 pbn_panacom },
4478 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_panacom4 },
4481 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_panacom2 },
4484 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4485 PCI_VENDOR_ID_ESDGMBH,
4486 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4487 pbn_b2_4_115200 },
4488 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4489 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4490 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4491 pbn_b2_4_460800 },
4492 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4493 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4494 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4495 pbn_b2_8_460800 },
4496 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4497 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4498 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4499 pbn_b2_16_460800 },
4500 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4501 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4502 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4503 pbn_b2_16_460800 },
4504 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4505 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4506 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4507 pbn_b2_4_460800 },
4508 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4509 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4510 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4511 pbn_b2_8_460800 },
4512 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4513 PCI_SUBVENDOR_ID_EXSYS,
4514 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4515 pbn_b2_4_115200 },
4516 /*
4517 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4518 * (Exoray@isys.ca)
4519 */
4520 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4521 0x10b5, 0x106a, 0, 0,
4522 pbn_plx_romulus },
4523 /*
4524 * Quatech cards. These actually have configurable clocks but for
4525 * now we just use the default.
4526 *
4527 * 100 series are RS232, 200 series RS422,
4528 */
4529 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_b1_4_115200 },
4532 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_b1_2_115200 },
4535 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 pbn_b2_2_115200 },
4538 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 pbn_b1_2_115200 },
4541 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543 pbn_b2_2_115200 },
4544 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 pbn_b1_4_115200 },
4547 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_b1_8_115200 },
4550 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 pbn_b1_8_115200 },
4553 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 pbn_b1_4_115200 },
4556 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558 pbn_b1_2_115200 },
4559 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561 pbn_b1_4_115200 },
4562 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564 pbn_b1_2_115200 },
4565 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567 pbn_b2_4_115200 },
4568 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_b2_2_115200 },
4571 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573 pbn_b2_1_115200 },
4574 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576 pbn_b2_4_115200 },
4577 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579 pbn_b2_2_115200 },
4580 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_b2_1_115200 },
4583 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585 pbn_b0_8_115200 },
4586
4587 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4588 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4589 0, 0,
4590 pbn_b0_4_921600 },
4591 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4592 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4593 0, 0,
4594 pbn_b0_4_1152000 },
4595 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_b0_bt_2_921600 },
4598
4599 /*
4600 * The below card is a little controversial since it is the
4601 * subject of a PCI vendor/device ID clash. (See
4602 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4603 * For now just used the hex ID 0x950a.
4604 */
4605 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4606 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4607 0, 0, pbn_b0_2_115200 },
4608 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4609 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4610 0, 0, pbn_b0_2_115200 },
4611 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b0_2_1130000 },
4614 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4615 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4616 pbn_b0_1_921600 },
4617 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b0_4_115200 },
4620 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b0_bt_2_921600 },
4623 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_b2_8_1152000 },
4626
4627 /*
4628 * Oxford Semiconductor Inc. Tornado PCI express device range.
4629 */
4630 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b0_1_15625000 },
4633 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b0_1_15625000 },
4636 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_oxsemi_1_15625000 },
4639 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_oxsemi_1_15625000 },
4642 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_b0_1_15625000 },
4645 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b0_1_15625000 },
4648 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_oxsemi_1_15625000 },
4651 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_oxsemi_1_15625000 },
4654 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b0_1_15625000 },
4657 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_b0_1_15625000 },
4660 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b0_1_15625000 },
4663 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_b0_1_15625000 },
4666 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668 pbn_oxsemi_2_15625000 },
4669 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_oxsemi_2_15625000 },
4672 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_oxsemi_4_15625000 },
4675 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_oxsemi_4_15625000 },
4678 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_oxsemi_8_15625000 },
4681 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_oxsemi_8_15625000 },
4684 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_oxsemi_1_15625000 },
4687 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_oxsemi_1_15625000 },
4690 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_oxsemi_1_15625000 },
4693 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_oxsemi_1_15625000 },
4696 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_oxsemi_1_15625000 },
4699 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_oxsemi_1_15625000 },
4702 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_oxsemi_1_15625000 },
4705 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_oxsemi_1_15625000 },
4708 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_oxsemi_1_15625000 },
4711 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_oxsemi_1_15625000 },
4714 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_oxsemi_1_15625000 },
4717 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_oxsemi_1_15625000 },
4720 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_oxsemi_1_15625000 },
4723 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_oxsemi_1_15625000 },
4726 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_oxsemi_1_15625000 },
4729 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_oxsemi_1_15625000 },
4732 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_oxsemi_1_15625000 },
4735 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_oxsemi_1_15625000 },
4738 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_oxsemi_1_15625000 },
4741 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_oxsemi_1_15625000 },
4744 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_oxsemi_1_15625000 },
4747 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_oxsemi_1_15625000 },
4750 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_oxsemi_1_15625000 },
4753 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_oxsemi_1_15625000 },
4756 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_oxsemi_1_15625000 },
4759 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_oxsemi_1_15625000 },
4762 /*
4763 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4764 */
4765 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4766 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4767 pbn_oxsemi_1_15625000 },
4768 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4769 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4770 pbn_oxsemi_2_15625000 },
4771 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4772 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4773 pbn_oxsemi_4_15625000 },
4774 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4775 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4776 pbn_oxsemi_8_15625000 },
4777
4778 /*
4779 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4780 */
4781 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4782 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4783 pbn_oxsemi_2_15625000 },
4784 /*
4785 * EndRun Technologies. PCI express device range.
4786 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4787 */
4788 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_oxsemi_2_15625000 },
4791
4792 /*
4793 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4794 * from skokodyn@yahoo.com
4795 */
4796 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4797 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4798 pbn_sbsxrsio },
4799 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4800 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4801 pbn_sbsxrsio },
4802 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4803 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4804 pbn_sbsxrsio },
4805 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4806 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4807 pbn_sbsxrsio },
4808
4809 /*
4810 * Digitan DS560-558, from jimd@esoft.com
4811 */
4812 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_b1_1_115200 },
4815
4816 /*
4817 * Titan Electronic cards
4818 * The 400L and 800L have a custom setup quirk.
4819 */
4820 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 pbn_b0_1_921600 },
4823 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 pbn_b0_2_921600 },
4826 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 pbn_b0_4_921600 },
4829 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831 pbn_b0_4_921600 },
4832 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834 pbn_b1_1_921600 },
4835 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 pbn_b1_bt_2_921600 },
4838 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 pbn_b0_bt_4_921600 },
4841 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 pbn_b0_bt_8_921600 },
4844 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 pbn_b4_bt_2_921600 },
4847 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 pbn_b4_bt_4_921600 },
4850 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852 pbn_b4_bt_8_921600 },
4853 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855 pbn_b0_4_921600 },
4856 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858 pbn_b0_4_921600 },
4859 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 pbn_b0_4_921600 },
4862 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_titan_1_4000000 },
4865 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_titan_2_4000000 },
4868 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_titan_4_4000000 },
4871 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_titan_8_4000000 },
4874 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_titan_2_4000000 },
4877 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_titan_2_4000000 },
4880 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b0_bt_2_921600 },
4883 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_4_921600 },
4886 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_4_921600 },
4889 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_4_921600 },
4892 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_4_921600 },
4895
4896 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b2_1_460800 },
4899 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b2_1_460800 },
4902 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b2_1_460800 },
4905 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b2_bt_2_921600 },
4908 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_b2_bt_2_921600 },
4911 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_b2_bt_2_921600 },
4914 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_b2_bt_4_921600 },
4917 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919 pbn_b2_bt_4_921600 },
4920 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922 pbn_b2_bt_4_921600 },
4923 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 pbn_b0_1_921600 },
4926 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 pbn_b0_1_921600 },
4929 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_b0_1_921600 },
4932 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 pbn_b0_bt_2_921600 },
4935 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 pbn_b0_bt_2_921600 },
4938 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 pbn_b0_bt_2_921600 },
4941 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 pbn_b0_bt_4_921600 },
4944 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 pbn_b0_bt_4_921600 },
4947 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949 pbn_b0_bt_4_921600 },
4950 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4952 pbn_b0_bt_8_921600 },
4953 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955 pbn_b0_bt_8_921600 },
4956 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958 pbn_b0_bt_8_921600 },
4959
4960 /*
4961 * Computone devices submitted by Doug McNash dmcnash@computone.com
4962 */
4963 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4964 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4965 0, 0, pbn_computone_4 },
4966 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4967 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4968 0, 0, pbn_computone_8 },
4969 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4970 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4971 0, 0, pbn_computone_6 },
4972
4973 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_oxsemi },
4976 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4977 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4978 pbn_b0_bt_1_921600 },
4979
4980 /*
4981 * Sunix PCI serial boards
4982 */
4983 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4984 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4985 pbn_sunix_pci_1s },
4986 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4987 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4988 pbn_sunix_pci_2s },
4989 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4990 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4991 pbn_sunix_pci_4s },
4992 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4993 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4994 pbn_sunix_pci_4s },
4995 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4996 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4997 pbn_sunix_pci_8s },
4998 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4999 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5000 pbn_sunix_pci_8s },
5001 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5002 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5003 pbn_sunix_pci_16s },
5004
5005 /*
5006 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5007 */
5008 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 pbn_b0_bt_8_115200 },
5011 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013 pbn_b0_bt_8_115200 },
5014
5015 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 pbn_b0_bt_2_115200 },
5018 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_b0_bt_2_115200 },
5021 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_b0_bt_2_115200 },
5024 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026 pbn_b0_bt_4_460800 },
5027 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5029 pbn_b0_bt_4_460800 },
5030 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032 pbn_b0_bt_2_460800 },
5033 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 pbn_b0_bt_2_460800 },
5036 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_b0_bt_2_460800 },
5039 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_b0_bt_1_115200 },
5042 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_b0_bt_1_460800 },
5045
5046 /*
5047 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5048 * Cards are identified by their subsystem vendor IDs, which
5049 * (in hex) match the model number.
5050 *
5051 * Note that JC140x are RS422/485 cards which require ox950
5052 * ACR = 0x10, and as such are not currently fully supported.
5053 */
5054 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5055 0x1204, 0x0004, 0, 0,
5056 pbn_b0_4_921600 },
5057 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5058 0x1208, 0x0004, 0, 0,
5059 pbn_b0_4_921600 },
5060 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5061 0x1402, 0x0002, 0, 0,
5062 pbn_b0_2_921600 }, */
5063 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5064 0x1404, 0x0004, 0, 0,
5065 pbn_b0_4_921600 }, */
5066 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5067 0x1208, 0x0004, 0, 0,
5068 pbn_b0_4_921600 },
5069
5070 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5071 0x1204, 0x0004, 0, 0,
5072 pbn_b0_4_921600 },
5073 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5074 0x1208, 0x0004, 0, 0,
5075 pbn_b0_4_921600 },
5076 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5077 0x1208, 0x0004, 0, 0,
5078 pbn_b0_4_921600 },
5079 /*
5080 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5081 */
5082 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 pbn_b1_1_1382400 },
5085
5086 /*
5087 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5088 */
5089 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 pbn_b1_1_1382400 },
5092
5093 /*
5094 * RAStel 2 port modem, gerg@moreton.com.au
5095 */
5096 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 pbn_b2_bt_2_115200 },
5099
5100 /*
5101 * EKF addition for i960 Boards form EKF with serial port
5102 */
5103 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5104 0xE4BF, PCI_ANY_ID, 0, 0,
5105 pbn_intel_i960 },
5106
5107 /*
5108 * Xircom Cardbus/Ethernet combos
5109 */
5110 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112 pbn_b0_1_115200 },
5113 /*
5114 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5115 */
5116 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_b0_1_115200 },
5119
5120 /*
5121 * Untested PCI modems, sent in from various folks...
5122 */
5123
5124 /*
5125 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5126 */
5127 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5128 0x1048, 0x1500, 0, 0,
5129 pbn_b1_1_115200 },
5130
5131 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5132 0xFF00, 0, 0, 0,
5133 pbn_sgi_ioc3 },
5134
5135 /*
5136 * HP Diva card
5137 */
5138 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5139 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5140 pbn_b1_1_115200 },
5141 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5143 pbn_b0_5_115200 },
5144 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5146 pbn_b2_1_115200 },
5147 /* HPE PCI serial device */
5148 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5150 pbn_b1_1_115200 },
5151
5152 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 pbn_b3_2_115200 },
5155 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157 pbn_b3_4_115200 },
5158 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 pbn_b3_8_115200 },
5161 /*
5162 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5163 */
5164 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166 pbn_b0_1_115200 },
5167 /*
5168 * ITE
5169 */
5170 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5171 PCI_ANY_ID, PCI_ANY_ID,
5172 0, 0,
5173 pbn_b1_bt_1_115200 },
5174
5175 /*
5176 * IntaShield IS-100
5177 */
5178 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5180 pbn_b2_1_115200 },
5181 /*
5182 * IntaShield IS-200
5183 */
5184 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5186 pbn_b2_2_115200 },
5187 /*
5188 * IntaShield IS-400
5189 */
5190 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5192 pbn_b2_4_115200 },
5193 /*
5194 * IntaShield IX-100
5195 */
5196 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5197 PCI_ANY_ID, PCI_ANY_ID,
5198 0, 0,
5199 pbn_oxsemi_1_15625000 },
5200 /*
5201 * IntaShield IX-200
5202 */
5203 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5204 PCI_ANY_ID, PCI_ANY_ID,
5205 0, 0,
5206 pbn_oxsemi_2_15625000 },
5207 /*
5208 * IntaShield IX-400
5209 */
5210 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5211 PCI_ANY_ID, PCI_ANY_ID,
5212 0, 0,
5213 pbn_oxsemi_4_15625000 },
5214 /* Brainboxes Devices */
5215 /*
5216 * Brainboxes UC-101
5217 */
5218 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5219 PCI_ANY_ID, PCI_ANY_ID,
5220 0, 0,
5221 pbn_b2_2_115200 },
5222 /*
5223 * Brainboxes UC-235/246
5224 */
5225 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5226 PCI_ANY_ID, PCI_ANY_ID,
5227 0, 0,
5228 pbn_b2_1_115200 },
5229 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5230 PCI_ANY_ID, PCI_ANY_ID,
5231 0, 0,
5232 pbn_b2_1_115200 },
5233 /*
5234 * Brainboxes UC-253/UC-734
5235 */
5236 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5237 PCI_ANY_ID, PCI_ANY_ID,
5238 0, 0,
5239 pbn_b2_2_115200 },
5240 /*
5241 * Brainboxes UC-260/271/701/756
5242 */
5243 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5244 PCI_ANY_ID, PCI_ANY_ID,
5245 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5246 pbn_b2_4_115200 },
5247 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5248 PCI_ANY_ID, PCI_ANY_ID,
5249 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5250 pbn_b2_4_115200 },
5251 /*
5252 * Brainboxes UC-268
5253 */
5254 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5255 PCI_ANY_ID, PCI_ANY_ID,
5256 0, 0,
5257 pbn_b2_4_115200 },
5258 /*
5259 * Brainboxes UC-275/279
5260 */
5261 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5262 PCI_ANY_ID, PCI_ANY_ID,
5263 0, 0,
5264 pbn_b2_8_115200 },
5265 /*
5266 * Brainboxes UC-302
5267 */
5268 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5269 PCI_ANY_ID, PCI_ANY_ID,
5270 0, 0,
5271 pbn_b2_2_115200 },
5272 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5273 PCI_ANY_ID, PCI_ANY_ID,
5274 0, 0,
5275 pbn_b2_2_115200 },
5276 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5277 PCI_ANY_ID, PCI_ANY_ID,
5278 0, 0,
5279 pbn_b2_2_115200 },
5280 /*
5281 * Brainboxes UC-310
5282 */
5283 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 0, 0,
5286 pbn_b2_2_115200 },
5287 /*
5288 * Brainboxes UC-313
5289 */
5290 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5291 PCI_ANY_ID, PCI_ANY_ID,
5292 0, 0,
5293 pbn_b2_2_115200 },
5294 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5295 PCI_ANY_ID, PCI_ANY_ID,
5296 0, 0,
5297 pbn_b2_2_115200 },
5298 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5299 PCI_ANY_ID, PCI_ANY_ID,
5300 0, 0,
5301 pbn_b2_2_115200 },
5302 /*
5303 * Brainboxes UC-320/324
5304 */
5305 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5306 PCI_ANY_ID, PCI_ANY_ID,
5307 0, 0,
5308 pbn_b2_1_115200 },
5309 /*
5310 * Brainboxes UC-346
5311 */
5312 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5313 PCI_ANY_ID, PCI_ANY_ID,
5314 0, 0,
5315 pbn_b2_4_115200 },
5316 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5317 PCI_ANY_ID, PCI_ANY_ID,
5318 0, 0,
5319 pbn_b2_4_115200 },
5320 /*
5321 * Brainboxes UC-357
5322 */
5323 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5324 PCI_ANY_ID, PCI_ANY_ID,
5325 0, 0,
5326 pbn_b2_2_115200 },
5327 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5328 PCI_ANY_ID, PCI_ANY_ID,
5329 0, 0,
5330 pbn_b2_2_115200 },
5331 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5332 PCI_ANY_ID, PCI_ANY_ID,
5333 0, 0,
5334 pbn_b2_2_115200 },
5335 /*
5336 * Brainboxes UC-368
5337 */
5338 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5339 PCI_ANY_ID, PCI_ANY_ID,
5340 0, 0,
5341 pbn_b2_4_115200 },
5342 /*
5343 * Brainboxes UC-420
5344 */
5345 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5346 PCI_ANY_ID, PCI_ANY_ID,
5347 0, 0,
5348 pbn_b2_4_115200 },
5349 /*
5350 * Brainboxes UC-607
5351 */
5352 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5353 PCI_ANY_ID, PCI_ANY_ID,
5354 0, 0,
5355 pbn_b2_2_115200 },
5356 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 0, 0,
5359 pbn_b2_2_115200 },
5360 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5361 PCI_ANY_ID, PCI_ANY_ID,
5362 0, 0,
5363 pbn_b2_2_115200 },
5364 /*
5365 * Brainboxes UC-836
5366 */
5367 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5368 PCI_ANY_ID, PCI_ANY_ID,
5369 0, 0,
5370 pbn_b2_4_115200 },
5371 /*
5372 * Brainboxes UP-189
5373 */
5374 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5375 PCI_ANY_ID, PCI_ANY_ID,
5376 0, 0,
5377 pbn_b2_2_115200 },
5378 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5379 PCI_ANY_ID, PCI_ANY_ID,
5380 0, 0,
5381 pbn_b2_2_115200 },
5382 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5383 PCI_ANY_ID, PCI_ANY_ID,
5384 0, 0,
5385 pbn_b2_2_115200 },
5386 /*
5387 * Brainboxes UP-200
5388 */
5389 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5390 PCI_ANY_ID, PCI_ANY_ID,
5391 0, 0,
5392 pbn_b2_2_115200 },
5393 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5394 PCI_ANY_ID, PCI_ANY_ID,
5395 0, 0,
5396 pbn_b2_2_115200 },
5397 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5398 PCI_ANY_ID, PCI_ANY_ID,
5399 0, 0,
5400 pbn_b2_2_115200 },
5401 /*
5402 * Brainboxes UP-869
5403 */
5404 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5405 PCI_ANY_ID, PCI_ANY_ID,
5406 0, 0,
5407 pbn_b2_2_115200 },
5408 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5409 PCI_ANY_ID, PCI_ANY_ID,
5410 0, 0,
5411 pbn_b2_2_115200 },
5412 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5413 PCI_ANY_ID, PCI_ANY_ID,
5414 0, 0,
5415 pbn_b2_2_115200 },
5416 /*
5417 * Brainboxes UP-880
5418 */
5419 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5420 PCI_ANY_ID, PCI_ANY_ID,
5421 0, 0,
5422 pbn_b2_2_115200 },
5423 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5424 PCI_ANY_ID, PCI_ANY_ID,
5425 0, 0,
5426 pbn_b2_2_115200 },
5427 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5428 PCI_ANY_ID, PCI_ANY_ID,
5429 0, 0,
5430 pbn_b2_2_115200 },
5431 /*
5432 * Brainboxes PX-101
5433 */
5434 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5435 PCI_ANY_ID, PCI_ANY_ID,
5436 0, 0,
5437 pbn_b0_2_115200 },
5438 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5439 PCI_ANY_ID, PCI_ANY_ID,
5440 0, 0,
5441 pbn_oxsemi_2_15625000 },
5442 /*
5443 * Brainboxes PX-235/246
5444 */
5445 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5446 PCI_ANY_ID, PCI_ANY_ID,
5447 0, 0,
5448 pbn_b0_1_115200 },
5449 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5450 PCI_ANY_ID, PCI_ANY_ID,
5451 0, 0,
5452 pbn_oxsemi_1_15625000 },
5453 /*
5454 * Brainboxes PX-203/PX-257
5455 */
5456 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5457 PCI_ANY_ID, PCI_ANY_ID,
5458 0, 0,
5459 pbn_b0_2_115200 },
5460 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5461 PCI_ANY_ID, PCI_ANY_ID,
5462 0, 0,
5463 pbn_oxsemi_2_15625000 },
5464 /*
5465 * Brainboxes PX-260/PX-701
5466 */
5467 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5468 PCI_ANY_ID, PCI_ANY_ID,
5469 0, 0,
5470 pbn_oxsemi_4_15625000 },
5471 /*
5472 * Brainboxes PX-275/279
5473 */
5474 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5475 PCI_ANY_ID, PCI_ANY_ID,
5476 0, 0,
5477 pbn_b2_8_115200 },
5478 /*
5479 * Brainboxes PX-310
5480 */
5481 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5482 PCI_ANY_ID, PCI_ANY_ID,
5483 0, 0,
5484 pbn_oxsemi_2_15625000 },
5485 /*
5486 * Brainboxes PX-313
5487 */
5488 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5489 PCI_ANY_ID, PCI_ANY_ID,
5490 0, 0,
5491 pbn_oxsemi_2_15625000 },
5492 /*
5493 * Brainboxes PX-320/324/PX-376/PX-387
5494 */
5495 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5496 PCI_ANY_ID, PCI_ANY_ID,
5497 0, 0,
5498 pbn_oxsemi_1_15625000 },
5499 /*
5500 * Brainboxes PX-335/346
5501 */
5502 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5503 PCI_ANY_ID, PCI_ANY_ID,
5504 0, 0,
5505 pbn_oxsemi_4_15625000 },
5506 /*
5507 * Brainboxes PX-368
5508 */
5509 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5510 PCI_ANY_ID, PCI_ANY_ID,
5511 0, 0,
5512 pbn_oxsemi_4_15625000 },
5513 /*
5514 * Brainboxes PX-420
5515 */
5516 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5517 PCI_ANY_ID, PCI_ANY_ID,
5518 0, 0,
5519 pbn_b0_4_115200 },
5520 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5521 PCI_ANY_ID, PCI_ANY_ID,
5522 0, 0,
5523 pbn_oxsemi_4_15625000 },
5524 /*
5525 * Brainboxes PX-475
5526 */
5527 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5528 PCI_ANY_ID, PCI_ANY_ID,
5529 0, 0,
5530 pbn_oxsemi_1_15625000 },
5531 /*
5532 * Brainboxes PX-803/PX-857
5533 */
5534 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5535 PCI_ANY_ID, PCI_ANY_ID,
5536 0, 0,
5537 pbn_b0_2_115200 },
5538 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5539 PCI_ANY_ID, PCI_ANY_ID,
5540 0, 0,
5541 pbn_oxsemi_2_15625000 },
5542 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5543 PCI_ANY_ID, PCI_ANY_ID,
5544 0, 0,
5545 pbn_oxsemi_2_15625000 },
5546 /*
5547 * Brainboxes PX-820
5548 */
5549 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5550 PCI_ANY_ID, PCI_ANY_ID,
5551 0, 0,
5552 pbn_b0_4_115200 },
5553 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5554 PCI_ANY_ID, PCI_ANY_ID,
5555 0, 0,
5556 pbn_oxsemi_4_15625000 },
5557 /*
5558 * Brainboxes PX-835/PX-846
5559 */
5560 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5561 PCI_ANY_ID, PCI_ANY_ID,
5562 0, 0,
5563 pbn_b0_1_115200 },
5564 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5565 PCI_ANY_ID, PCI_ANY_ID,
5566 0, 0,
5567 pbn_oxsemi_1_15625000 },
5568
5569 /*
5570 * Perle PCI-RAS cards
5571 */
5572 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5573 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5574 0, 0, pbn_b2_4_921600 },
5575 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5576 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5577 0, 0, pbn_b2_8_921600 },
5578
5579 /*
5580 * Mainpine series cards: Fairly standard layout but fools
5581 * parts of the autodetect in some cases and uses otherwise
5582 * unmatched communications subclasses in the PCI Express case
5583 */
5584
5585 { /* RockForceDUO */
5586 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5587 PCI_VENDOR_ID_MAINPINE, 0x0200,
5588 0, 0, pbn_b0_2_115200 },
5589 { /* RockForceQUATRO */
5590 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5591 PCI_VENDOR_ID_MAINPINE, 0x0300,
5592 0, 0, pbn_b0_4_115200 },
5593 { /* RockForceDUO+ */
5594 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5595 PCI_VENDOR_ID_MAINPINE, 0x0400,
5596 0, 0, pbn_b0_2_115200 },
5597 { /* RockForceQUATRO+ */
5598 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5599 PCI_VENDOR_ID_MAINPINE, 0x0500,
5600 0, 0, pbn_b0_4_115200 },
5601 { /* RockForce+ */
5602 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5603 PCI_VENDOR_ID_MAINPINE, 0x0600,
5604 0, 0, pbn_b0_2_115200 },
5605 { /* RockForce+ */
5606 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5607 PCI_VENDOR_ID_MAINPINE, 0x0700,
5608 0, 0, pbn_b0_4_115200 },
5609 { /* RockForceOCTO+ */
5610 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5611 PCI_VENDOR_ID_MAINPINE, 0x0800,
5612 0, 0, pbn_b0_8_115200 },
5613 { /* RockForceDUO+ */
5614 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5615 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5616 0, 0, pbn_b0_2_115200 },
5617 { /* RockForceQUARTRO+ */
5618 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5619 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5620 0, 0, pbn_b0_4_115200 },
5621 { /* RockForceOCTO+ */
5622 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5623 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5624 0, 0, pbn_b0_8_115200 },
5625 { /* RockForceD1 */
5626 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5627 PCI_VENDOR_ID_MAINPINE, 0x2000,
5628 0, 0, pbn_b0_1_115200 },
5629 { /* RockForceF1 */
5630 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5631 PCI_VENDOR_ID_MAINPINE, 0x2100,
5632 0, 0, pbn_b0_1_115200 },
5633 { /* RockForceD2 */
5634 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5635 PCI_VENDOR_ID_MAINPINE, 0x2200,
5636 0, 0, pbn_b0_2_115200 },
5637 { /* RockForceF2 */
5638 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5639 PCI_VENDOR_ID_MAINPINE, 0x2300,
5640 0, 0, pbn_b0_2_115200 },
5641 { /* RockForceD4 */
5642 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5643 PCI_VENDOR_ID_MAINPINE, 0x2400,
5644 0, 0, pbn_b0_4_115200 },
5645 { /* RockForceF4 */
5646 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5647 PCI_VENDOR_ID_MAINPINE, 0x2500,
5648 0, 0, pbn_b0_4_115200 },
5649 { /* RockForceD8 */
5650 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5651 PCI_VENDOR_ID_MAINPINE, 0x2600,
5652 0, 0, pbn_b0_8_115200 },
5653 { /* RockForceF8 */
5654 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5655 PCI_VENDOR_ID_MAINPINE, 0x2700,
5656 0, 0, pbn_b0_8_115200 },
5657 { /* IQ Express D1 */
5658 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5659 PCI_VENDOR_ID_MAINPINE, 0x3000,
5660 0, 0, pbn_b0_1_115200 },
5661 { /* IQ Express F1 */
5662 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5663 PCI_VENDOR_ID_MAINPINE, 0x3100,
5664 0, 0, pbn_b0_1_115200 },
5665 { /* IQ Express D2 */
5666 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5667 PCI_VENDOR_ID_MAINPINE, 0x3200,
5668 0, 0, pbn_b0_2_115200 },
5669 { /* IQ Express F2 */
5670 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5671 PCI_VENDOR_ID_MAINPINE, 0x3300,
5672 0, 0, pbn_b0_2_115200 },
5673 { /* IQ Express D4 */
5674 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5675 PCI_VENDOR_ID_MAINPINE, 0x3400,
5676 0, 0, pbn_b0_4_115200 },
5677 { /* IQ Express F4 */
5678 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5679 PCI_VENDOR_ID_MAINPINE, 0x3500,
5680 0, 0, pbn_b0_4_115200 },
5681 { /* IQ Express D8 */
5682 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5683 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5684 0, 0, pbn_b0_8_115200 },
5685 { /* IQ Express F8 */
5686 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5687 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5688 0, 0, pbn_b0_8_115200 },
5689
5690
5691 /*
5692 * PA Semi PA6T-1682M on-chip UART
5693 */
5694 { PCI_VENDOR_ID_PASEMI, 0xa004,
5695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5696 pbn_pasemi_1682M },
5697
5698 /*
5699 * National Instruments
5700 */
5701 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5703 pbn_b1_16_115200 },
5704 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5706 pbn_b1_8_115200 },
5707 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5709 pbn_b1_bt_4_115200 },
5710 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5712 pbn_b1_bt_2_115200 },
5713 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5715 pbn_b1_bt_4_115200 },
5716 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5718 pbn_b1_bt_2_115200 },
5719 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5721 pbn_b1_16_115200 },
5722 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5724 pbn_b1_8_115200 },
5725 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5727 pbn_b1_bt_4_115200 },
5728 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5730 pbn_b1_bt_2_115200 },
5731 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5733 pbn_b1_bt_4_115200 },
5734 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5736 pbn_b1_bt_2_115200 },
5737 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5739 pbn_ni8430_2 },
5740 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5742 pbn_ni8430_2 },
5743 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5745 pbn_ni8430_4 },
5746 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5748 pbn_ni8430_4 },
5749 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5751 pbn_ni8430_8 },
5752 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5754 pbn_ni8430_8 },
5755 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5757 pbn_ni8430_16 },
5758 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5760 pbn_ni8430_16 },
5761 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5763 pbn_ni8430_2 },
5764 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5766 pbn_ni8430_2 },
5767 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5769 pbn_ni8430_4 },
5770 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5772 pbn_ni8430_4 },
5773
5774 /*
5775 * MOXA
5776 */
5777 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5778 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5779 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5780 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5781 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5782 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5783 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5784 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5785 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5786 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5787 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5788 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5789 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5790 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5791 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5792 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5793 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5794 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5795
5796 /*
5797 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5798 */
5799 { PCI_VENDOR_ID_ADDIDATA,
5800 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5801 PCI_ANY_ID,
5802 PCI_ANY_ID,
5803 0,
5804 0,
5805 pbn_b0_4_115200 },
5806
5807 { PCI_VENDOR_ID_ADDIDATA,
5808 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5809 PCI_ANY_ID,
5810 PCI_ANY_ID,
5811 0,
5812 0,
5813 pbn_b0_2_115200 },
5814
5815 { PCI_VENDOR_ID_ADDIDATA,
5816 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5817 PCI_ANY_ID,
5818 PCI_ANY_ID,
5819 0,
5820 0,
5821 pbn_b0_1_115200 },
5822
5823 { PCI_VENDOR_ID_AMCC,
5824 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5825 PCI_ANY_ID,
5826 PCI_ANY_ID,
5827 0,
5828 0,
5829 pbn_b1_8_115200 },
5830
5831 { PCI_VENDOR_ID_ADDIDATA,
5832 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5833 PCI_ANY_ID,
5834 PCI_ANY_ID,
5835 0,
5836 0,
5837 pbn_b0_4_115200 },
5838
5839 { PCI_VENDOR_ID_ADDIDATA,
5840 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5841 PCI_ANY_ID,
5842 PCI_ANY_ID,
5843 0,
5844 0,
5845 pbn_b0_2_115200 },
5846
5847 { PCI_VENDOR_ID_ADDIDATA,
5848 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5849 PCI_ANY_ID,
5850 PCI_ANY_ID,
5851 0,
5852 0,
5853 pbn_b0_1_115200 },
5854
5855 { PCI_VENDOR_ID_ADDIDATA,
5856 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5857 PCI_ANY_ID,
5858 PCI_ANY_ID,
5859 0,
5860 0,
5861 pbn_b0_4_115200 },
5862
5863 { PCI_VENDOR_ID_ADDIDATA,
5864 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5865 PCI_ANY_ID,
5866 PCI_ANY_ID,
5867 0,
5868 0,
5869 pbn_b0_2_115200 },
5870
5871 { PCI_VENDOR_ID_ADDIDATA,
5872 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5873 PCI_ANY_ID,
5874 PCI_ANY_ID,
5875 0,
5876 0,
5877 pbn_b0_1_115200 },
5878
5879 { PCI_VENDOR_ID_ADDIDATA,
5880 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5881 PCI_ANY_ID,
5882 PCI_ANY_ID,
5883 0,
5884 0,
5885 pbn_b0_8_115200 },
5886
5887 { PCI_VENDOR_ID_ADDIDATA,
5888 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5889 PCI_ANY_ID,
5890 PCI_ANY_ID,
5891 0,
5892 0,
5893 pbn_ADDIDATA_PCIe_4_3906250 },
5894
5895 { PCI_VENDOR_ID_ADDIDATA,
5896 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5897 PCI_ANY_ID,
5898 PCI_ANY_ID,
5899 0,
5900 0,
5901 pbn_ADDIDATA_PCIe_2_3906250 },
5902
5903 { PCI_VENDOR_ID_ADDIDATA,
5904 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5905 PCI_ANY_ID,
5906 PCI_ANY_ID,
5907 0,
5908 0,
5909 pbn_ADDIDATA_PCIe_1_3906250 },
5910
5911 { PCI_VENDOR_ID_ADDIDATA,
5912 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5913 PCI_ANY_ID,
5914 PCI_ANY_ID,
5915 0,
5916 0,
5917 pbn_ADDIDATA_PCIe_8_3906250 },
5918
5919 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5920 PCI_VENDOR_ID_IBM, 0x0299,
5921 0, 0, pbn_b0_bt_2_115200 },
5922
5923 /*
5924 * other NetMos 9835 devices are most likely handled by the
5925 * parport_serial driver, check drivers/parport/parport_serial.c
5926 * before adding them here.
5927 */
5928
5929 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5930 0xA000, 0x1000,
5931 0, 0, pbn_b0_1_115200 },
5932
5933 /* the 9901 is a rebranded 9912 */
5934 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5935 0xA000, 0x1000,
5936 0, 0, pbn_b0_1_115200 },
5937
5938 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5939 0xA000, 0x1000,
5940 0, 0, pbn_b0_1_115200 },
5941
5942 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5943 0xA000, 0x1000,
5944 0, 0, pbn_b0_1_115200 },
5945
5946 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5947 0xA000, 0x1000,
5948 0, 0, pbn_b0_1_115200 },
5949
5950 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5951 0xA000, 0x3002,
5952 0, 0, pbn_NETMOS9900_2s_115200 },
5953
5954 /*
5955 * Best Connectivity and Rosewill PCI Multi I/O cards
5956 */
5957
5958 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5959 0xA000, 0x1000,
5960 0, 0, pbn_b0_1_115200 },
5961
5962 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5963 0xA000, 0x3002,
5964 0, 0, pbn_b0_bt_2_115200 },
5965
5966 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5967 0xA000, 0x3004,
5968 0, 0, pbn_b0_bt_4_115200 },
5969
5970 /*
5971 * ASIX AX99100 PCIe to Multi I/O Controller
5972 */
5973 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
5974 0xA000, 0x1000,
5975 0, 0, pbn_b0_1_115200 },
5976
5977 /* Intel CE4100 */
5978 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5980 pbn_ce4100_1_115200 },
5981
5982 /*
5983 * Cronyx Omega PCI
5984 */
5985 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5987 pbn_omegapci },
5988
5989 /*
5990 * Broadcom TruManage
5991 */
5992 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5994 pbn_brcm_trumanage },
5995
5996 /*
5997 * AgeStar as-prs2-009
5998 */
5999 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6000 PCI_ANY_ID, PCI_ANY_ID,
6001 0, 0, pbn_b0_bt_2_115200 },
6002
6003 /*
6004 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6005 * so not listed here.
6006 */
6007 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
6008 PCI_ANY_ID, PCI_ANY_ID,
6009 0, 0, pbn_b0_bt_4_115200 },
6010
6011 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
6012 PCI_ANY_ID, PCI_ANY_ID,
6013 0, 0, pbn_b0_bt_2_115200 },
6014
6015 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
6016 PCI_ANY_ID, PCI_ANY_ID,
6017 0, 0, pbn_b0_bt_4_115200 },
6018
6019 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
6020 PCI_ANY_ID, PCI_ANY_ID,
6021 0, 0, pbn_wch382_2 },
6022
6023 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
6024 PCI_ANY_ID, PCI_ANY_ID,
6025 0, 0, pbn_wch384_4 },
6026
6027 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
6028 PCI_ANY_ID, PCI_ANY_ID,
6029 0, 0, pbn_wch384_8 },
6030 /*
6031 * Realtek RealManage
6032 */
6033 { PCI_VENDOR_ID_REALTEK, 0x816a,
6034 PCI_ANY_ID, PCI_ANY_ID,
6035 0, 0, pbn_b0_1_115200 },
6036
6037 { PCI_VENDOR_ID_REALTEK, 0x816b,
6038 PCI_ANY_ID, PCI_ANY_ID,
6039 0, 0, pbn_b0_1_115200 },
6040
6041 /* Fintek PCI serial cards */
6042 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6043 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6044 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6045 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6046 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6047 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6048
6049 /* MKS Tenta SCOM-080x serial cards */
6050 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6051 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6052
6053 /* Amazon PCI serial device */
6054 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6055
6056 /*
6057 * These entries match devices with class COMMUNICATION_SERIAL,
6058 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6059 */
6060 { PCI_ANY_ID, PCI_ANY_ID,
6061 PCI_ANY_ID, PCI_ANY_ID,
6062 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6063 0xffff00, pbn_default },
6064 { PCI_ANY_ID, PCI_ANY_ID,
6065 PCI_ANY_ID, PCI_ANY_ID,
6066 PCI_CLASS_COMMUNICATION_MODEM << 8,
6067 0xffff00, pbn_default },
6068 { PCI_ANY_ID, PCI_ANY_ID,
6069 PCI_ANY_ID, PCI_ANY_ID,
6070 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6071 0xffff00, pbn_default },
6072 { 0, }
6073 };
6074
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6075 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6076 pci_channel_state_t state)
6077 {
6078 struct serial_private *priv = pci_get_drvdata(dev);
6079
6080 if (state == pci_channel_io_perm_failure)
6081 return PCI_ERS_RESULT_DISCONNECT;
6082
6083 if (priv)
6084 pciserial_detach_ports(priv);
6085
6086 pci_disable_device(dev);
6087
6088 return PCI_ERS_RESULT_NEED_RESET;
6089 }
6090
serial8250_io_slot_reset(struct pci_dev * dev)6091 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6092 {
6093 int rc;
6094
6095 rc = pci_enable_device(dev);
6096
6097 if (rc)
6098 return PCI_ERS_RESULT_DISCONNECT;
6099
6100 pci_restore_state(dev);
6101 pci_save_state(dev);
6102
6103 return PCI_ERS_RESULT_RECOVERED;
6104 }
6105
serial8250_io_resume(struct pci_dev * dev)6106 static void serial8250_io_resume(struct pci_dev *dev)
6107 {
6108 struct serial_private *priv = pci_get_drvdata(dev);
6109 struct serial_private *new;
6110
6111 if (!priv)
6112 return;
6113
6114 new = pciserial_init_ports(dev, priv->board);
6115 if (!IS_ERR(new)) {
6116 pci_set_drvdata(dev, new);
6117 kfree(priv);
6118 }
6119 }
6120
6121 static const struct pci_error_handlers serial8250_err_handler = {
6122 .error_detected = serial8250_io_error_detected,
6123 .slot_reset = serial8250_io_slot_reset,
6124 .resume = serial8250_io_resume,
6125 };
6126
6127 static struct pci_driver serial_pci_driver = {
6128 .name = "serial",
6129 .probe = pciserial_init_one,
6130 .remove = pciserial_remove_one,
6131 .driver = {
6132 .pm = &pciserial_pm_ops,
6133 },
6134 .id_table = serial_pci_tbl,
6135 .err_handler = &serial8250_err_handler,
6136 };
6137
6138 module_pci_driver(serial_pci_driver);
6139
6140 MODULE_LICENSE("GPL");
6141 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6142 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6143 MODULE_IMPORT_NS(SERIAL_8250_PCI);
6144