1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49 }; 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[]; 57 }; 58 59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 60 61 static const struct pci_device_id pci_use_msi[] = { 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 69 PCI_ANY_ID, PCI_ANY_ID) }, 70 { } 71 }; 72 73 static int pci_default_setup(struct serial_private*, 74 const struct pciserial_board*, struct uart_8250_port *, int); 75 76 static void moan_device(const char *str, struct pci_dev *dev) 77 { 78 pci_err(dev, "%s\n" 79 "Please send the output of lspci -vv, this\n" 80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 81 "manufacturer and name of serial board or\n" 82 "modem board to <linux-serial@vger.kernel.org>.\n", 83 str, dev->vendor, dev->device, 84 dev->subsystem_vendor, dev->subsystem_device); 85 } 86 87 static int 88 setup_port(struct serial_private *priv, struct uart_8250_port *port, 89 u8 bar, unsigned int offset, int regshift) 90 { 91 struct pci_dev *dev = priv->dev; 92 93 if (bar >= PCI_STD_NUM_BARS) 94 return -EINVAL; 95 96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 98 return -ENOMEM; 99 100 port->port.iotype = UPIO_MEM; 101 port->port.iobase = 0; 102 port->port.mapbase = pci_resource_start(dev, bar) + offset; 103 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 104 port->port.regshift = regshift; 105 } else { 106 port->port.iotype = UPIO_PORT; 107 port->port.iobase = pci_resource_start(dev, bar) + offset; 108 port->port.mapbase = 0; 109 port->port.membase = NULL; 110 port->port.regshift = 0; 111 } 112 return 0; 113 } 114 115 /* 116 * ADDI-DATA GmbH communication cards <info@addi-data.com> 117 */ 118 static int addidata_apci7800_setup(struct serial_private *priv, 119 const struct pciserial_board *board, 120 struct uart_8250_port *port, int idx) 121 { 122 unsigned int bar = 0, offset = board->first_offset; 123 bar = FL_GET_BASE(board->flags); 124 125 if (idx < 2) { 126 offset += idx * board->uart_offset; 127 } else if ((idx >= 2) && (idx < 4)) { 128 bar += 1; 129 offset += ((idx - 2) * board->uart_offset); 130 } else if ((idx >= 4) && (idx < 6)) { 131 bar += 2; 132 offset += ((idx - 4) * board->uart_offset); 133 } else if (idx >= 6) { 134 bar += 3; 135 offset += ((idx - 6) * board->uart_offset); 136 } 137 138 return setup_port(priv, port, bar, offset, board->reg_shift); 139 } 140 141 /* 142 * AFAVLAB uses a different mixture of BARs and offsets 143 * Not that ugly ;) -- HW 144 */ 145 static int 146 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 147 struct uart_8250_port *port, int idx) 148 { 149 unsigned int bar, offset = board->first_offset; 150 151 bar = FL_GET_BASE(board->flags); 152 if (idx < 4) 153 bar += idx; 154 else { 155 bar = 4; 156 offset += (idx - 4) * board->uart_offset; 157 } 158 159 return setup_port(priv, port, bar, offset, board->reg_shift); 160 } 161 162 /* 163 * HP's Remote Management Console. The Diva chip came in several 164 * different versions. N-class, L2000 and A500 have two Diva chips, each 165 * with 3 UARTs (the third UART on the second chip is unused). Superdome 166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 167 * one Diva chip, but it has been expanded to 5 UARTs. 168 */ 169 static int pci_hp_diva_init(struct pci_dev *dev) 170 { 171 int rc = 0; 172 173 switch (dev->subsystem_device) { 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 177 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 178 rc = 3; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 181 rc = 2; 182 break; 183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 184 rc = 4; 185 break; 186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 188 rc = 1; 189 break; 190 } 191 192 return rc; 193 } 194 195 /* 196 * HP's Diva chip puts the 4th/5th serial port further out, and 197 * some serial ports are supposed to be hidden on certain models. 198 */ 199 static int 200 pci_hp_diva_setup(struct serial_private *priv, 201 const struct pciserial_board *board, 202 struct uart_8250_port *port, int idx) 203 { 204 unsigned int offset = board->first_offset; 205 unsigned int bar = FL_GET_BASE(board->flags); 206 207 switch (priv->dev->subsystem_device) { 208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 209 if (idx == 3) 210 idx++; 211 break; 212 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 213 if (idx > 0) 214 idx++; 215 if (idx > 2) 216 idx++; 217 break; 218 } 219 if (idx > 2) 220 offset = 0x18; 221 222 offset += idx * board->uart_offset; 223 224 return setup_port(priv, port, bar, offset, board->reg_shift); 225 } 226 227 /* 228 * Added for EKF Intel i960 serial boards 229 */ 230 static int pci_inteli960ni_init(struct pci_dev *dev) 231 { 232 u32 oldval; 233 234 if (!(dev->subsystem_device & 0x1000)) 235 return -ENODEV; 236 237 /* is firmware started? */ 238 pci_read_config_dword(dev, 0x44, &oldval); 239 if (oldval == 0x00001000L) { /* RESET value */ 240 pci_dbg(dev, "Local i960 firmware missing\n"); 241 return -ENODEV; 242 } 243 return 0; 244 } 245 246 /* 247 * Some PCI serial cards using the PLX 9050 PCI interface chip require 248 * that the card interrupt be explicitly enabled or disabled. This 249 * seems to be mainly needed on card using the PLX which also use I/O 250 * mapped memory. 251 */ 252 static int pci_plx9050_init(struct pci_dev *dev) 253 { 254 u8 irq_config; 255 void __iomem *p; 256 257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 258 moan_device("no memory in bar 0", dev); 259 return 0; 260 } 261 262 irq_config = 0x41; 263 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 265 irq_config = 0x43; 266 267 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 269 /* 270 * As the megawolf cards have the int pins active 271 * high, and have 2 UART chips, both ints must be 272 * enabled on the 9050. Also, the UARTS are set in 273 * 16450 mode by default, so we have to enable the 274 * 16C950 'enhanced' mode so that we can use the 275 * deep FIFOs 276 */ 277 irq_config = 0x5b; 278 /* 279 * enable/disable interrupts 280 */ 281 p = ioremap(pci_resource_start(dev, 0), 0x80); 282 if (p == NULL) 283 return -ENOMEM; 284 writel(irq_config, p + 0x4c); 285 286 /* 287 * Read the register back to ensure that it took effect. 288 */ 289 readl(p + 0x4c); 290 iounmap(p); 291 292 return 0; 293 } 294 295 static void pci_plx9050_exit(struct pci_dev *dev) 296 { 297 u8 __iomem *p; 298 299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 300 return; 301 302 /* 303 * disable interrupts 304 */ 305 p = ioremap(pci_resource_start(dev, 0), 0x80); 306 if (p != NULL) { 307 writel(0, p + 0x4c); 308 309 /* 310 * Read the register back to ensure that it took effect. 311 */ 312 readl(p + 0x4c); 313 iounmap(p); 314 } 315 } 316 317 #define NI8420_INT_ENABLE_REG 0x38 318 #define NI8420_INT_ENABLE_BIT 0x2000 319 320 static void pci_ni8420_exit(struct pci_dev *dev) 321 { 322 void __iomem *p; 323 unsigned int bar = 0; 324 325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 326 moan_device("no memory in bar", dev); 327 return; 328 } 329 330 p = pci_ioremap_bar(dev, bar); 331 if (p == NULL) 332 return; 333 334 /* Disable the CPU Interrupt */ 335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 336 p + NI8420_INT_ENABLE_REG); 337 iounmap(p); 338 } 339 340 341 /* MITE registers */ 342 #define MITE_IOWBSR1 0xc4 343 #define MITE_IOWCR1 0xf4 344 #define MITE_LCIMR1 0x08 345 #define MITE_LCIMR2 0x10 346 347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 348 349 static void pci_ni8430_exit(struct pci_dev *dev) 350 { 351 void __iomem *p; 352 unsigned int bar = 0; 353 354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 355 moan_device("no memory in bar", dev); 356 return; 357 } 358 359 p = pci_ioremap_bar(dev, bar); 360 if (p == NULL) 361 return; 362 363 /* Disable the CPU Interrupt */ 364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 365 iounmap(p); 366 } 367 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 369 static int 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 371 struct uart_8250_port *port, int idx) 372 { 373 unsigned int bar, offset = board->first_offset; 374 375 bar = 0; 376 377 if (idx < 4) { 378 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 379 offset += idx * board->uart_offset; 380 } else if (idx < 8) { 381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 382 offset += idx * board->uart_offset + 0xC00; 383 } else /* we have only 8 ports on PMC-OCTALPRO */ 384 return 1; 385 386 return setup_port(priv, port, bar, offset, board->reg_shift); 387 } 388 389 /* 390 * This does initialization for PMC OCTALPRO cards: 391 * maps the device memory, resets the UARTs (needed, bc 392 * if the module is removed and inserted again, the card 393 * is in the sleep mode) and enables global interrupt. 394 */ 395 396 /* global control register offset for SBS PMC-OctalPro */ 397 #define OCT_REG_CR_OFF 0x500 398 399 static int sbs_init(struct pci_dev *dev) 400 { 401 u8 __iomem *p; 402 403 p = pci_ioremap_bar(dev, 0); 404 405 if (p == NULL) 406 return -ENOMEM; 407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 408 writeb(0x10, p + OCT_REG_CR_OFF); 409 udelay(50); 410 writeb(0x0, p + OCT_REG_CR_OFF); 411 412 /* Set bit-2 (INTENABLE) of Control Register */ 413 writeb(0x4, p + OCT_REG_CR_OFF); 414 iounmap(p); 415 416 return 0; 417 } 418 419 /* 420 * Disables the global interrupt of PMC-OctalPro 421 */ 422 423 static void sbs_exit(struct pci_dev *dev) 424 { 425 u8 __iomem *p; 426 427 p = pci_ioremap_bar(dev, 0); 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 429 if (p != NULL) 430 writeb(0, p + OCT_REG_CR_OFF); 431 iounmap(p); 432 } 433 434 /* 435 * SIIG serial cards have an PCI interface chip which also controls 436 * the UART clocking frequency. Each UART can be clocked independently 437 * (except cards equipped with 4 UARTs) and initial clocking settings 438 * are stored in the EEPROM chip. It can cause problems because this 439 * version of serial driver doesn't support differently clocked UART's 440 * on single PCI card. To prevent this, initialization functions set 441 * high frequency clocking for all UART's on given card. It is safe (I 442 * hope) because it doesn't touch EEPROM settings to prevent conflicts 443 * with other OSes (like M$ DOS). 444 * 445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 446 * 447 * There is two family of SIIG serial cards with different PCI 448 * interface chip and different configuration methods: 449 * - 10x cards have control registers in IO and/or memory space; 450 * - 20x cards have control registers in standard PCI configuration space. 451 * 452 * Note: all 10x cards have PCI device ids 0x10.. 453 * all 20x cards have PCI device ids 0x20.. 454 * 455 * There are also Quartet Serial cards which use Oxford Semiconductor 456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 457 * 458 * Note: some SIIG cards are probed by the parport_serial object. 459 */ 460 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 463 464 static int pci_siig10x_init(struct pci_dev *dev) 465 { 466 u16 data; 467 void __iomem *p; 468 469 switch (dev->device & 0xfff8) { 470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 471 data = 0xffdf; 472 break; 473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 474 data = 0xf7ff; 475 break; 476 default: /* 1S1P, 4S */ 477 data = 0xfffb; 478 break; 479 } 480 481 p = ioremap(pci_resource_start(dev, 0), 0x80); 482 if (p == NULL) 483 return -ENOMEM; 484 485 writew(readw(p + 0x28) & data, p + 0x28); 486 readw(p + 0x28); 487 iounmap(p); 488 return 0; 489 } 490 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 493 494 static int pci_siig20x_init(struct pci_dev *dev) 495 { 496 u8 data; 497 498 /* Change clock frequency for the first UART. */ 499 pci_read_config_byte(dev, 0x6f, &data); 500 pci_write_config_byte(dev, 0x6f, data & 0xef); 501 502 /* If this card has 2 UART, we have to do the same with second UART. */ 503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 505 pci_read_config_byte(dev, 0x73, &data); 506 pci_write_config_byte(dev, 0x73, data & 0xef); 507 } 508 return 0; 509 } 510 511 static int pci_siig_init(struct pci_dev *dev) 512 { 513 unsigned int type = dev->device & 0xff00; 514 515 if (type == 0x1000) 516 return pci_siig10x_init(dev); 517 if (type == 0x2000) 518 return pci_siig20x_init(dev); 519 520 moan_device("Unknown SIIG card", dev); 521 return -ENODEV; 522 } 523 524 static int pci_siig_setup(struct serial_private *priv, 525 const struct pciserial_board *board, 526 struct uart_8250_port *port, int idx) 527 { 528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 529 530 if (idx > 3) { 531 bar = 4; 532 offset = (idx - 4) * 8; 533 } 534 535 return setup_port(priv, port, bar, offset, 0); 536 } 537 538 /* 539 * Timedia has an explosion of boards, and to avoid the PCI table from 540 * growing *huge*, we use this function to collapse some 70 entries 541 * in the PCI table into one, for sanity's and compactness's sake. 542 */ 543 static const unsigned short timedia_single_port[] = { 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 545 }; 546 547 static const unsigned short timedia_dual_port[] = { 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 552 0xD079, 0 553 }; 554 555 static const unsigned short timedia_quad_port[] = { 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 559 0xB157, 0 560 }; 561 562 static const unsigned short timedia_eight_port[] = { 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 565 }; 566 567 static const struct timedia_struct { 568 int num; 569 const unsigned short *ids; 570 } timedia_data[] = { 571 { 1, timedia_single_port }, 572 { 2, timedia_dual_port }, 573 { 4, timedia_quad_port }, 574 { 8, timedia_eight_port } 575 }; 576 577 /* 578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 579 * listing them individually, this driver merely grabs them all with 580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 581 * and should be left free to be claimed by parport_serial instead. 582 */ 583 static int pci_timedia_probe(struct pci_dev *dev) 584 { 585 /* 586 * Check the third digit of the subdevice ID 587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 588 */ 589 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 591 dev->subsystem_device); 592 return -ENODEV; 593 } 594 595 return 0; 596 } 597 598 static int pci_timedia_init(struct pci_dev *dev) 599 { 600 const unsigned short *ids; 601 int i, j; 602 603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 604 ids = timedia_data[i].ids; 605 for (j = 0; ids[j]; j++) 606 if (dev->subsystem_device == ids[j]) 607 return timedia_data[i].num; 608 } 609 return 0; 610 } 611 612 /* 613 * Timedia/SUNIX uses a mixture of BARs and offsets 614 * Ugh, this is ugly as all hell --- TYT 615 */ 616 static int 617 pci_timedia_setup(struct serial_private *priv, 618 const struct pciserial_board *board, 619 struct uart_8250_port *port, int idx) 620 { 621 unsigned int bar = 0, offset = board->first_offset; 622 623 switch (idx) { 624 case 0: 625 bar = 0; 626 break; 627 case 1: 628 offset = board->uart_offset; 629 bar = 0; 630 break; 631 case 2: 632 bar = 1; 633 break; 634 case 3: 635 offset = board->uart_offset; 636 fallthrough; 637 case 4: /* BAR 2 */ 638 case 5: /* BAR 3 */ 639 case 6: /* BAR 4 */ 640 case 7: /* BAR 5 */ 641 bar = idx - 2; 642 } 643 644 return setup_port(priv, port, bar, offset, board->reg_shift); 645 } 646 647 /* 648 * Some Titan cards are also a little weird 649 */ 650 static int 651 titan_400l_800l_setup(struct serial_private *priv, 652 const struct pciserial_board *board, 653 struct uart_8250_port *port, int idx) 654 { 655 unsigned int bar, offset = board->first_offset; 656 657 switch (idx) { 658 case 0: 659 bar = 1; 660 break; 661 case 1: 662 bar = 2; 663 break; 664 default: 665 bar = 4; 666 offset = (idx - 2) * board->uart_offset; 667 } 668 669 return setup_port(priv, port, bar, offset, board->reg_shift); 670 } 671 672 static int pci_xircom_init(struct pci_dev *dev) 673 { 674 msleep(100); 675 return 0; 676 } 677 678 static int pci_ni8420_init(struct pci_dev *dev) 679 { 680 void __iomem *p; 681 unsigned int bar = 0; 682 683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 684 moan_device("no memory in bar", dev); 685 return 0; 686 } 687 688 p = pci_ioremap_bar(dev, bar); 689 if (p == NULL) 690 return -ENOMEM; 691 692 /* Enable CPU Interrupt */ 693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 694 p + NI8420_INT_ENABLE_REG); 695 696 iounmap(p); 697 return 0; 698 } 699 700 #define MITE_IOWBSR1_WSIZE 0xa 701 #define MITE_IOWBSR1_WIN_OFFSET 0x800 702 #define MITE_IOWBSR1_WENAB (1 << 7) 703 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 706 707 static int pci_ni8430_init(struct pci_dev *dev) 708 { 709 void __iomem *p; 710 struct pci_bus_region region; 711 u32 device_window; 712 unsigned int bar = 0; 713 714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 715 moan_device("no memory in bar", dev); 716 return 0; 717 } 718 719 p = pci_ioremap_bar(dev, bar); 720 if (p == NULL) 721 return -ENOMEM; 722 723 /* 724 * Set device window address and size in BAR0, while acknowledging that 725 * the resource structure may contain a translated address that differs 726 * from the address the device responds to. 727 */ 728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 731 writel(device_window, p + MITE_IOWBSR1); 732 733 /* Set window access to go to RAMSEL IO address space */ 734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 735 p + MITE_IOWCR1); 736 737 /* Enable IO Bus Interrupt 0 */ 738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 739 740 /* Enable CPU Interrupt */ 741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 742 743 iounmap(p); 744 return 0; 745 } 746 747 /* UART Port Control Register */ 748 #define NI8430_PORTCON 0x0f 749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 750 751 static int 752 pci_ni8430_setup(struct serial_private *priv, 753 const struct pciserial_board *board, 754 struct uart_8250_port *port, int idx) 755 { 756 struct pci_dev *dev = priv->dev; 757 void __iomem *p; 758 unsigned int bar, offset = board->first_offset; 759 760 if (idx >= board->num_ports) 761 return 1; 762 763 bar = FL_GET_BASE(board->flags); 764 offset += idx * board->uart_offset; 765 766 p = pci_ioremap_bar(dev, bar); 767 if (!p) 768 return -ENOMEM; 769 770 /* enable the transceiver */ 771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 772 p + offset + NI8430_PORTCON); 773 774 iounmap(p); 775 776 return setup_port(priv, port, bar, offset, board->reg_shift); 777 } 778 779 static int pci_netmos_9900_setup(struct serial_private *priv, 780 const struct pciserial_board *board, 781 struct uart_8250_port *port, int idx) 782 { 783 unsigned int bar; 784 785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 786 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 787 /* netmos apparently orders BARs by datasheet layout, so serial 788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 789 */ 790 bar = 3 * idx; 791 792 return setup_port(priv, port, bar, 0, board->reg_shift); 793 } 794 795 return pci_default_setup(priv, board, port, idx); 796 } 797 798 /* the 99xx series comes with a range of device IDs and a variety 799 * of capabilities: 800 * 801 * 9900 has varying capabilities and can cascade to sub-controllers 802 * (cascading should be purely internal) 803 * 9904 is hardwired with 4 serial ports 804 * 9912 and 9922 are hardwired with 2 serial ports 805 */ 806 static int pci_netmos_9900_numports(struct pci_dev *dev) 807 { 808 unsigned int c = dev->class; 809 unsigned int pi; 810 unsigned short sub_serports; 811 812 pi = c & 0xff; 813 814 if (pi == 2) 815 return 1; 816 817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 818 /* two possibilities: 0x30ps encodes number of parallel and 819 * serial ports, or 0x1000 indicates *something*. This is not 820 * immediately obvious, since the 2s1p+4s configuration seems 821 * to offer all functionality on functions 0..2, while still 822 * advertising the same function 3 as the 4s+2s1p config. 823 */ 824 sub_serports = dev->subsystem_device & 0xf; 825 if (sub_serports > 0) 826 return sub_serports; 827 828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 829 return 0; 830 } 831 832 moan_device("unknown NetMos/Mostech program interface", dev); 833 return 0; 834 } 835 836 static int pci_netmos_init(struct pci_dev *dev) 837 { 838 /* subdevice 0x00PS means <P> parallel, <S> serial */ 839 unsigned int num_serial = dev->subsystem_device & 0xf; 840 841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 842 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 843 return 0; 844 845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 846 dev->subsystem_device == 0x0299) 847 return 0; 848 849 switch (dev->device) { /* FALLTHROUGH on all */ 850 case PCI_DEVICE_ID_NETMOS_9904: 851 case PCI_DEVICE_ID_NETMOS_9912: 852 case PCI_DEVICE_ID_NETMOS_9922: 853 case PCI_DEVICE_ID_NETMOS_9900: 854 num_serial = pci_netmos_9900_numports(dev); 855 break; 856 857 default: 858 break; 859 } 860 861 if (num_serial == 0) { 862 moan_device("unknown NetMos/Mostech device", dev); 863 return -ENODEV; 864 } 865 866 return num_serial; 867 } 868 869 /* 870 * These chips are available with optionally one parallel port and up to 871 * two serial ports. Unfortunately they all have the same product id. 872 * 873 * Basic configuration is done over a region of 32 I/O ports. The base 874 * ioport is called INTA or INTC, depending on docs/other drivers. 875 * 876 * The region of the 32 I/O ports is configured in POSIO0R... 877 */ 878 879 /* registers */ 880 #define ITE_887x_MISCR 0x9c 881 #define ITE_887x_INTCBAR 0x78 882 #define ITE_887x_UARTBAR 0x7c 883 #define ITE_887x_PS0BAR 0x10 884 #define ITE_887x_POSIO0 0x60 885 886 /* I/O space size */ 887 #define ITE_887x_IOSIZE 32 888 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 889 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 890 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 891 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 892 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 893 #define ITE_887x_POSIO_SPEED (3 << 29) 894 /* enable IO_Space bit */ 895 #define ITE_887x_POSIO_ENABLE (1 << 31) 896 897 /* inta_addr are the configuration addresses of the ITE */ 898 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 899 static int pci_ite887x_init(struct pci_dev *dev) 900 { 901 int ret, i, type; 902 struct resource *iobase = NULL; 903 u32 miscr, uartbar, ioport; 904 905 /* search for the base-ioport */ 906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 908 "ite887x"); 909 if (iobase != NULL) { 910 /* write POSIO0R - speed | size | ioport */ 911 pci_write_config_dword(dev, ITE_887x_POSIO0, 912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 914 /* write INTCBAR - ioport */ 915 pci_write_config_dword(dev, ITE_887x_INTCBAR, 916 inta_addr[i]); 917 ret = inb(inta_addr[i]); 918 if (ret != 0xff) { 919 /* ioport connected */ 920 break; 921 } 922 release_region(iobase->start, ITE_887x_IOSIZE); 923 } 924 } 925 926 if (i == ARRAY_SIZE(inta_addr)) { 927 pci_err(dev, "could not find iobase\n"); 928 return -ENODEV; 929 } 930 931 /* start of undocumented type checking (see parport_pc.c) */ 932 type = inb(iobase->start + 0x18) & 0x0f; 933 934 switch (type) { 935 case 0x2: /* ITE8871 (1P) */ 936 case 0xa: /* ITE8875 (1P) */ 937 ret = 0; 938 break; 939 case 0xe: /* ITE8872 (2S1P) */ 940 ret = 2; 941 break; 942 case 0x6: /* ITE8873 (1S) */ 943 ret = 1; 944 break; 945 case 0x8: /* ITE8874 (2S) */ 946 ret = 2; 947 break; 948 default: 949 moan_device("Unknown ITE887x", dev); 950 ret = -ENODEV; 951 } 952 953 /* configure all serial ports */ 954 for (i = 0; i < ret; i++) { 955 /* read the I/O port from the device */ 956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 957 &ioport); 958 ioport &= 0x0000FF00; /* the actual base address */ 959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 961 ITE_887x_POSIO_IOSIZE_8 | ioport); 962 963 /* write the ioport to the UARTBAR */ 964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 966 uartbar |= (ioport << (16 * i)); /* set the ioport */ 967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 968 969 /* get current config */ 970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 971 /* disable interrupts (UARTx_Routing[3:0]) */ 972 miscr &= ~(0xf << (12 - 4 * i)); 973 /* activate the UART (UARTx_En) */ 974 miscr |= 1 << (23 - i); 975 /* write new config with activated UART */ 976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 977 } 978 979 if (ret <= 0) { 980 /* the device has no UARTs if we get here */ 981 release_region(iobase->start, ITE_887x_IOSIZE); 982 } 983 984 return ret; 985 } 986 987 static void pci_ite887x_exit(struct pci_dev *dev) 988 { 989 u32 ioport; 990 /* the ioport is bit 0-15 in POSIO0R */ 991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 992 ioport &= 0xffff; 993 release_region(ioport, ITE_887x_IOSIZE); 994 } 995 996 /* 997 * EndRun Technologies. 998 * Determine the number of ports available on the device. 999 */ 1000 #define PCI_VENDOR_ID_ENDRUN 0x7401 1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1002 1003 static int pci_endrun_init(struct pci_dev *dev) 1004 { 1005 u8 __iomem *p; 1006 unsigned long deviceID; 1007 unsigned int number_uarts = 0; 1008 1009 /* EndRun device is all 0xexxx */ 1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1011 (dev->device & 0xf000) != 0xe000) 1012 return 0; 1013 1014 p = pci_iomap(dev, 0, 5); 1015 if (p == NULL) 1016 return -ENOMEM; 1017 1018 deviceID = ioread32(p); 1019 /* EndRun device */ 1020 if (deviceID == 0x07000200) { 1021 number_uarts = ioread8(p + 4); 1022 pci_dbg(dev, "%d ports detected on EndRun PCI Express device\n", number_uarts); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* 1029 * Oxford Semiconductor Inc. 1030 * Check that device is part of the Tornado range of devices, then determine 1031 * the number of ports available on the device. 1032 */ 1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1034 { 1035 u8 __iomem *p; 1036 unsigned long deviceID; 1037 unsigned int number_uarts = 0; 1038 1039 /* OxSemi Tornado devices are all 0xCxxx */ 1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1041 (dev->device & 0xF000) != 0xC000) 1042 return 0; 1043 1044 p = pci_iomap(dev, 0, 5); 1045 if (p == NULL) 1046 return -ENOMEM; 1047 1048 deviceID = ioread32(p); 1049 /* Tornado device */ 1050 if (deviceID == 0x07000200) { 1051 number_uarts = ioread8(p + 4); 1052 pci_dbg(dev, "%d ports detected on Oxford PCI Express device\n", number_uarts); 1053 } 1054 pci_iounmap(dev, p); 1055 return number_uarts; 1056 } 1057 1058 static int pci_asix_setup(struct serial_private *priv, 1059 const struct pciserial_board *board, 1060 struct uart_8250_port *port, int idx) 1061 { 1062 port->bugs |= UART_BUG_PARITY; 1063 return pci_default_setup(priv, board, port, idx); 1064 } 1065 1066 #define QPCR_TEST_FOR1 0x3F 1067 #define QPCR_TEST_GET1 0x00 1068 #define QPCR_TEST_FOR2 0x40 1069 #define QPCR_TEST_GET2 0x40 1070 #define QPCR_TEST_FOR3 0x80 1071 #define QPCR_TEST_GET3 0x40 1072 #define QPCR_TEST_FOR4 0xC0 1073 #define QPCR_TEST_GET4 0x80 1074 1075 #define QOPR_CLOCK_X1 0x0000 1076 #define QOPR_CLOCK_X2 0x0001 1077 #define QOPR_CLOCK_X4 0x0002 1078 #define QOPR_CLOCK_X8 0x0003 1079 #define QOPR_CLOCK_RATE_MASK 0x0003 1080 1081 /* Quatech devices have their own extra interface features */ 1082 static struct pci_device_id quatech_cards[] = { 1083 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1084 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1085 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1086 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1087 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1088 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1089 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1090 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1091 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1092 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1093 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1094 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1095 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1096 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1097 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1098 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1099 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1100 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1101 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1102 { 0, } 1103 }; 1104 1105 static int pci_quatech_rqopr(struct uart_8250_port *port) 1106 { 1107 unsigned long base = port->port.iobase; 1108 u8 LCR, val; 1109 1110 LCR = inb(base + UART_LCR); 1111 outb(0xBF, base + UART_LCR); 1112 val = inb(base + UART_SCR); 1113 outb(LCR, base + UART_LCR); 1114 return val; 1115 } 1116 1117 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1118 { 1119 unsigned long base = port->port.iobase; 1120 u8 LCR; 1121 1122 LCR = inb(base + UART_LCR); 1123 outb(0xBF, base + UART_LCR); 1124 inb(base + UART_SCR); 1125 outb(qopr, base + UART_SCR); 1126 outb(LCR, base + UART_LCR); 1127 } 1128 1129 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1130 { 1131 unsigned long base = port->port.iobase; 1132 u8 LCR, val, qmcr; 1133 1134 LCR = inb(base + UART_LCR); 1135 outb(0xBF, base + UART_LCR); 1136 val = inb(base + UART_SCR); 1137 outb(val | 0x10, base + UART_SCR); 1138 qmcr = inb(base + UART_MCR); 1139 outb(val, base + UART_SCR); 1140 outb(LCR, base + UART_LCR); 1141 1142 return qmcr; 1143 } 1144 1145 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1146 { 1147 unsigned long base = port->port.iobase; 1148 u8 LCR, val; 1149 1150 LCR = inb(base + UART_LCR); 1151 outb(0xBF, base + UART_LCR); 1152 val = inb(base + UART_SCR); 1153 outb(val | 0x10, base + UART_SCR); 1154 outb(qmcr, base + UART_MCR); 1155 outb(val, base + UART_SCR); 1156 outb(LCR, base + UART_LCR); 1157 } 1158 1159 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1160 { 1161 unsigned long base = port->port.iobase; 1162 u8 LCR, val; 1163 1164 LCR = inb(base + UART_LCR); 1165 outb(0xBF, base + UART_LCR); 1166 val = inb(base + UART_SCR); 1167 if (val & 0x20) { 1168 outb(0x80, UART_LCR); 1169 if (!(inb(UART_SCR) & 0x20)) { 1170 outb(LCR, base + UART_LCR); 1171 return 1; 1172 } 1173 } 1174 return 0; 1175 } 1176 1177 static int pci_quatech_test(struct uart_8250_port *port) 1178 { 1179 u8 reg, qopr; 1180 1181 qopr = pci_quatech_rqopr(port); 1182 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1183 reg = pci_quatech_rqopr(port) & 0xC0; 1184 if (reg != QPCR_TEST_GET1) 1185 return -EINVAL; 1186 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1187 reg = pci_quatech_rqopr(port) & 0xC0; 1188 if (reg != QPCR_TEST_GET2) 1189 return -EINVAL; 1190 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1191 reg = pci_quatech_rqopr(port) & 0xC0; 1192 if (reg != QPCR_TEST_GET3) 1193 return -EINVAL; 1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1195 reg = pci_quatech_rqopr(port) & 0xC0; 1196 if (reg != QPCR_TEST_GET4) 1197 return -EINVAL; 1198 1199 pci_quatech_wqopr(port, qopr); 1200 return 0; 1201 } 1202 1203 static int pci_quatech_clock(struct uart_8250_port *port) 1204 { 1205 u8 qopr, reg, set; 1206 unsigned long clock; 1207 1208 if (pci_quatech_test(port) < 0) 1209 return 1843200; 1210 1211 qopr = pci_quatech_rqopr(port); 1212 1213 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1214 reg = pci_quatech_rqopr(port); 1215 if (reg & QOPR_CLOCK_X8) { 1216 clock = 1843200; 1217 goto out; 1218 } 1219 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1220 reg = pci_quatech_rqopr(port); 1221 if (!(reg & QOPR_CLOCK_X8)) { 1222 clock = 1843200; 1223 goto out; 1224 } 1225 reg &= QOPR_CLOCK_X8; 1226 if (reg == QOPR_CLOCK_X2) { 1227 clock = 3685400; 1228 set = QOPR_CLOCK_X2; 1229 } else if (reg == QOPR_CLOCK_X4) { 1230 clock = 7372800; 1231 set = QOPR_CLOCK_X4; 1232 } else if (reg == QOPR_CLOCK_X8) { 1233 clock = 14745600; 1234 set = QOPR_CLOCK_X8; 1235 } else { 1236 clock = 1843200; 1237 set = QOPR_CLOCK_X1; 1238 } 1239 qopr &= ~QOPR_CLOCK_RATE_MASK; 1240 qopr |= set; 1241 1242 out: 1243 pci_quatech_wqopr(port, qopr); 1244 return clock; 1245 } 1246 1247 static int pci_quatech_rs422(struct uart_8250_port *port) 1248 { 1249 u8 qmcr; 1250 int rs422 = 0; 1251 1252 if (!pci_quatech_has_qmcr(port)) 1253 return 0; 1254 qmcr = pci_quatech_rqmcr(port); 1255 pci_quatech_wqmcr(port, 0xFF); 1256 if (pci_quatech_rqmcr(port)) 1257 rs422 = 1; 1258 pci_quatech_wqmcr(port, qmcr); 1259 return rs422; 1260 } 1261 1262 static int pci_quatech_init(struct pci_dev *dev) 1263 { 1264 const struct pci_device_id *match; 1265 bool amcc = false; 1266 1267 match = pci_match_id(quatech_cards, dev); 1268 if (match) 1269 amcc = match->driver_data; 1270 else 1271 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1272 1273 if (amcc) { 1274 unsigned long base = pci_resource_start(dev, 0); 1275 if (base) { 1276 u32 tmp; 1277 1278 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1279 tmp = inl(base + 0x3c); 1280 outl(tmp | 0x01000000, base + 0x3c); 1281 outl(tmp & ~0x01000000, base + 0x3c); 1282 } 1283 } 1284 return 0; 1285 } 1286 1287 static int pci_quatech_setup(struct serial_private *priv, 1288 const struct pciserial_board *board, 1289 struct uart_8250_port *port, int idx) 1290 { 1291 /* Needed by pci_quatech calls below */ 1292 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1293 /* Set up the clocking */ 1294 port->port.uartclk = pci_quatech_clock(port); 1295 /* For now just warn about RS422 */ 1296 if (pci_quatech_rs422(port)) 1297 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1298 return pci_default_setup(priv, board, port, idx); 1299 } 1300 1301 static int pci_default_setup(struct serial_private *priv, 1302 const struct pciserial_board *board, 1303 struct uart_8250_port *port, int idx) 1304 { 1305 unsigned int bar, offset = board->first_offset, maxnr; 1306 1307 bar = FL_GET_BASE(board->flags); 1308 if (board->flags & FL_BASE_BARS) 1309 bar += idx; 1310 else 1311 offset += idx * board->uart_offset; 1312 1313 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1314 (board->reg_shift + 3); 1315 1316 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1317 return 1; 1318 1319 return setup_port(priv, port, bar, offset, board->reg_shift); 1320 } 1321 1322 static int 1323 ce4100_serial_setup(struct serial_private *priv, 1324 const struct pciserial_board *board, 1325 struct uart_8250_port *port, int idx) 1326 { 1327 int ret; 1328 1329 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1330 port->port.iotype = UPIO_MEM32; 1331 port->port.type = PORT_XSCALE; 1332 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1333 port->port.regshift = 2; 1334 1335 return ret; 1336 } 1337 1338 static int 1339 pci_omegapci_setup(struct serial_private *priv, 1340 const struct pciserial_board *board, 1341 struct uart_8250_port *port, int idx) 1342 { 1343 return setup_port(priv, port, 2, idx * 8, 0); 1344 } 1345 1346 static int 1347 pci_brcm_trumanage_setup(struct serial_private *priv, 1348 const struct pciserial_board *board, 1349 struct uart_8250_port *port, int idx) 1350 { 1351 int ret = pci_default_setup(priv, board, port, idx); 1352 1353 port->port.type = PORT_BRCM_TRUMANAGE; 1354 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1355 return ret; 1356 } 1357 1358 /* RTS will control by MCR if this bit is 0 */ 1359 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1360 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1361 #define FINTEK_RTS_INVERT BIT(5) 1362 1363 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1364 static int pci_fintek_rs485_config(struct uart_port *port, 1365 struct serial_rs485 *rs485) 1366 { 1367 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1368 u8 setting; 1369 u8 *index = (u8 *) port->private_data; 1370 1371 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1372 1373 if (!rs485) 1374 rs485 = &port->rs485; 1375 else if (rs485->flags & SER_RS485_ENABLED) 1376 memset(rs485->padding, 0, sizeof(rs485->padding)); 1377 else 1378 memset(rs485, 0, sizeof(*rs485)); 1379 1380 /* F81504/508/512 not support RTS delay before or after send */ 1381 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1382 1383 if (rs485->flags & SER_RS485_ENABLED) { 1384 /* Enable RTS H/W control mode */ 1385 setting |= FINTEK_RTS_CONTROL_BY_HW; 1386 1387 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1388 /* RTS driving high on TX */ 1389 setting &= ~FINTEK_RTS_INVERT; 1390 } else { 1391 /* RTS driving low on TX */ 1392 setting |= FINTEK_RTS_INVERT; 1393 } 1394 1395 rs485->delay_rts_after_send = 0; 1396 rs485->delay_rts_before_send = 0; 1397 } else { 1398 /* Disable RTS H/W control mode */ 1399 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1400 } 1401 1402 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1403 1404 if (rs485 != &port->rs485) 1405 port->rs485 = *rs485; 1406 1407 return 0; 1408 } 1409 1410 static int pci_fintek_setup(struct serial_private *priv, 1411 const struct pciserial_board *board, 1412 struct uart_8250_port *port, int idx) 1413 { 1414 struct pci_dev *pdev = priv->dev; 1415 u8 *data; 1416 u8 config_base; 1417 u16 iobase; 1418 1419 config_base = 0x40 + 0x08 * idx; 1420 1421 /* Get the io address from configuration space */ 1422 pci_read_config_word(pdev, config_base + 4, &iobase); 1423 1424 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1425 1426 port->port.iotype = UPIO_PORT; 1427 port->port.iobase = iobase; 1428 port->port.rs485_config = pci_fintek_rs485_config; 1429 1430 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1431 if (!data) 1432 return -ENOMEM; 1433 1434 /* preserve index in PCI configuration space */ 1435 *data = idx; 1436 port->port.private_data = data; 1437 1438 return 0; 1439 } 1440 1441 static int pci_fintek_init(struct pci_dev *dev) 1442 { 1443 unsigned long iobase; 1444 u32 max_port, i; 1445 resource_size_t bar_data[3]; 1446 u8 config_base; 1447 struct serial_private *priv = pci_get_drvdata(dev); 1448 struct uart_8250_port *port; 1449 1450 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1451 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1452 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1453 return -ENODEV; 1454 1455 switch (dev->device) { 1456 case 0x1104: /* 4 ports */ 1457 case 0x1108: /* 8 ports */ 1458 max_port = dev->device & 0xff; 1459 break; 1460 case 0x1112: /* 12 ports */ 1461 max_port = 12; 1462 break; 1463 default: 1464 return -EINVAL; 1465 } 1466 1467 /* Get the io address dispatch from the BIOS */ 1468 bar_data[0] = pci_resource_start(dev, 5); 1469 bar_data[1] = pci_resource_start(dev, 4); 1470 bar_data[2] = pci_resource_start(dev, 3); 1471 1472 for (i = 0; i < max_port; ++i) { 1473 /* UART0 configuration offset start from 0x40 */ 1474 config_base = 0x40 + 0x08 * i; 1475 1476 /* Calculate Real IO Port */ 1477 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1478 1479 /* Enable UART I/O port */ 1480 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1481 1482 /* Select 128-byte FIFO and 8x FIFO threshold */ 1483 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1484 1485 /* LSB UART */ 1486 pci_write_config_byte(dev, config_base + 0x04, 1487 (u8)(iobase & 0xff)); 1488 1489 /* MSB UART */ 1490 pci_write_config_byte(dev, config_base + 0x05, 1491 (u8)((iobase & 0xff00) >> 8)); 1492 1493 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1494 1495 if (priv) { 1496 /* re-apply RS232/485 mode when 1497 * pciserial_resume_ports() 1498 */ 1499 port = serial8250_get_port(priv->line[i]); 1500 pci_fintek_rs485_config(&port->port, NULL); 1501 } else { 1502 /* First init without port data 1503 * force init to RS232 Mode 1504 */ 1505 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1506 } 1507 } 1508 1509 return max_port; 1510 } 1511 1512 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1513 { 1514 struct f815xxa_data *data = p->private_data; 1515 unsigned long flags; 1516 1517 spin_lock_irqsave(&data->lock, flags); 1518 writeb(value, p->membase + offset); 1519 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1520 spin_unlock_irqrestore(&data->lock, flags); 1521 } 1522 1523 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1524 const struct pciserial_board *board, 1525 struct uart_8250_port *port, int idx) 1526 { 1527 struct pci_dev *pdev = priv->dev; 1528 struct f815xxa_data *data; 1529 1530 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1531 if (!data) 1532 return -ENOMEM; 1533 1534 data->idx = idx; 1535 spin_lock_init(&data->lock); 1536 1537 port->port.private_data = data; 1538 port->port.iotype = UPIO_MEM; 1539 port->port.flags |= UPF_IOREMAP; 1540 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1541 port->port.serial_out = f815xxa_mem_serial_out; 1542 1543 return 0; 1544 } 1545 1546 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1547 { 1548 u32 max_port, i; 1549 int config_base; 1550 1551 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1552 return -ENODEV; 1553 1554 switch (dev->device) { 1555 case 0x1204: /* 4 ports */ 1556 case 0x1208: /* 8 ports */ 1557 max_port = dev->device & 0xff; 1558 break; 1559 case 0x1212: /* 12 ports */ 1560 max_port = 12; 1561 break; 1562 default: 1563 return -EINVAL; 1564 } 1565 1566 /* Set to mmio decode */ 1567 pci_write_config_byte(dev, 0x209, 0x40); 1568 1569 for (i = 0; i < max_port; ++i) { 1570 /* UART0 configuration offset start from 0x2A0 */ 1571 config_base = 0x2A0 + 0x08 * i; 1572 1573 /* Select 128-byte FIFO and 8x FIFO threshold */ 1574 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1575 1576 /* Enable UART I/O port */ 1577 pci_write_config_byte(dev, config_base + 0, 0x01); 1578 } 1579 1580 return max_port; 1581 } 1582 1583 static int skip_tx_en_setup(struct serial_private *priv, 1584 const struct pciserial_board *board, 1585 struct uart_8250_port *port, int idx) 1586 { 1587 port->port.quirks |= UPQ_NO_TXEN_TEST; 1588 pci_dbg(priv->dev, 1589 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1590 priv->dev->vendor, priv->dev->device, 1591 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1592 1593 return pci_default_setup(priv, board, port, idx); 1594 } 1595 1596 static void kt_handle_break(struct uart_port *p) 1597 { 1598 struct uart_8250_port *up = up_to_u8250p(p); 1599 /* 1600 * On receipt of a BI, serial device in Intel ME (Intel 1601 * management engine) needs to have its fifos cleared for sane 1602 * SOL (Serial Over Lan) output. 1603 */ 1604 serial8250_clear_and_reinit_fifos(up); 1605 } 1606 1607 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1608 { 1609 struct uart_8250_port *up = up_to_u8250p(p); 1610 unsigned int val; 1611 1612 /* 1613 * When the Intel ME (management engine) gets reset its serial 1614 * port registers could return 0 momentarily. Functions like 1615 * serial8250_console_write, read and save the IER, perform 1616 * some operation and then restore it. In order to avoid 1617 * setting IER register inadvertently to 0, if the value read 1618 * is 0, double check with ier value in uart_8250_port and use 1619 * that instead. up->ier should be the same value as what is 1620 * currently configured. 1621 */ 1622 val = inb(p->iobase + offset); 1623 if (offset == UART_IER) { 1624 if (val == 0) 1625 val = up->ier; 1626 } 1627 return val; 1628 } 1629 1630 static int kt_serial_setup(struct serial_private *priv, 1631 const struct pciserial_board *board, 1632 struct uart_8250_port *port, int idx) 1633 { 1634 port->port.flags |= UPF_BUG_THRE; 1635 port->port.serial_in = kt_serial_in; 1636 port->port.handle_break = kt_handle_break; 1637 return skip_tx_en_setup(priv, board, port, idx); 1638 } 1639 1640 static int pci_eg20t_init(struct pci_dev *dev) 1641 { 1642 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1643 return -ENODEV; 1644 #else 1645 return 0; 1646 #endif 1647 } 1648 1649 static int 1650 pci_wch_ch353_setup(struct serial_private *priv, 1651 const struct pciserial_board *board, 1652 struct uart_8250_port *port, int idx) 1653 { 1654 port->port.flags |= UPF_FIXED_TYPE; 1655 port->port.type = PORT_16550A; 1656 return pci_default_setup(priv, board, port, idx); 1657 } 1658 1659 static int 1660 pci_wch_ch355_setup(struct serial_private *priv, 1661 const struct pciserial_board *board, 1662 struct uart_8250_port *port, int idx) 1663 { 1664 port->port.flags |= UPF_FIXED_TYPE; 1665 port->port.type = PORT_16550A; 1666 return pci_default_setup(priv, board, port, idx); 1667 } 1668 1669 static int 1670 pci_wch_ch38x_setup(struct serial_private *priv, 1671 const struct pciserial_board *board, 1672 struct uart_8250_port *port, int idx) 1673 { 1674 port->port.flags |= UPF_FIXED_TYPE; 1675 port->port.type = PORT_16850; 1676 return pci_default_setup(priv, board, port, idx); 1677 } 1678 1679 1680 #define CH384_XINT_ENABLE_REG 0xEB 1681 #define CH384_XINT_ENABLE_BIT 0x02 1682 1683 static int pci_wch_ch38x_init(struct pci_dev *dev) 1684 { 1685 int max_port; 1686 unsigned long iobase; 1687 1688 1689 switch (dev->device) { 1690 case 0x3853: /* 8 ports */ 1691 max_port = 8; 1692 break; 1693 default: 1694 return -EINVAL; 1695 } 1696 1697 iobase = pci_resource_start(dev, 0); 1698 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1699 1700 return max_port; 1701 } 1702 1703 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1704 { 1705 unsigned long iobase; 1706 1707 iobase = pci_resource_start(dev, 0); 1708 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1709 } 1710 1711 1712 static int 1713 pci_sunix_setup(struct serial_private *priv, 1714 const struct pciserial_board *board, 1715 struct uart_8250_port *port, int idx) 1716 { 1717 int bar; 1718 int offset; 1719 1720 port->port.flags |= UPF_FIXED_TYPE; 1721 port->port.type = PORT_SUNIX; 1722 1723 if (idx < 4) { 1724 bar = 0; 1725 offset = idx * board->uart_offset; 1726 } else { 1727 bar = 1; 1728 idx -= 4; 1729 idx = div_s64_rem(idx, 4, &offset); 1730 offset = idx * 64 + offset * board->uart_offset; 1731 } 1732 1733 return setup_port(priv, port, bar, offset, 0); 1734 } 1735 1736 static int 1737 pci_moxa_setup(struct serial_private *priv, 1738 const struct pciserial_board *board, 1739 struct uart_8250_port *port, int idx) 1740 { 1741 unsigned int bar = FL_GET_BASE(board->flags); 1742 int offset; 1743 1744 if (board->num_ports == 4 && idx == 3) 1745 offset = 7 * board->uart_offset; 1746 else 1747 offset = idx * board->uart_offset; 1748 1749 return setup_port(priv, port, bar, offset, 0); 1750 } 1751 1752 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1753 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1754 #define PCI_DEVICE_ID_OCTPRO 0x0001 1755 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1756 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1757 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1758 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1759 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1760 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1761 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1762 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1763 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1764 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1765 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1766 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1767 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1768 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1769 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1770 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1771 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1772 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1773 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1774 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1775 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1776 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1777 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1778 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1779 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1780 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1781 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1782 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1783 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1784 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1785 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1786 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1787 #define PCI_VENDOR_ID_WCH 0x4348 1788 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1789 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1790 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1791 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1792 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1793 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1794 #define PCI_VENDOR_ID_AGESTAR 0x5372 1795 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1796 #define PCI_VENDOR_ID_ASIX 0x9710 1797 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1798 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1799 1800 #define PCIE_VENDOR_ID_WCH 0x1c00 1801 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1802 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1803 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1804 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1805 1806 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1807 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1808 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1809 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1810 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1811 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1812 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1813 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1814 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1815 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1816 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1817 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1818 1819 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1820 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1821 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1822 1823 /* 1824 * Master list of serial port init/setup/exit quirks. 1825 * This does not describe the general nature of the port. 1826 * (ie, baud base, number and location of ports, etc) 1827 * 1828 * This list is ordered alphabetically by vendor then device. 1829 * Specific entries must come before more generic entries. 1830 */ 1831 static struct pci_serial_quirk pci_serial_quirks[] = { 1832 /* 1833 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1834 */ 1835 { 1836 .vendor = PCI_VENDOR_ID_AMCC, 1837 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1838 .subvendor = PCI_ANY_ID, 1839 .subdevice = PCI_ANY_ID, 1840 .setup = addidata_apci7800_setup, 1841 }, 1842 /* 1843 * AFAVLAB cards - these may be called via parport_serial 1844 * It is not clear whether this applies to all products. 1845 */ 1846 { 1847 .vendor = PCI_VENDOR_ID_AFAVLAB, 1848 .device = PCI_ANY_ID, 1849 .subvendor = PCI_ANY_ID, 1850 .subdevice = PCI_ANY_ID, 1851 .setup = afavlab_setup, 1852 }, 1853 /* 1854 * HP Diva 1855 */ 1856 { 1857 .vendor = PCI_VENDOR_ID_HP, 1858 .device = PCI_DEVICE_ID_HP_DIVA, 1859 .subvendor = PCI_ANY_ID, 1860 .subdevice = PCI_ANY_ID, 1861 .init = pci_hp_diva_init, 1862 .setup = pci_hp_diva_setup, 1863 }, 1864 /* 1865 * HPE PCI serial device 1866 */ 1867 { 1868 .vendor = PCI_VENDOR_ID_HP_3PAR, 1869 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 1870 .subvendor = PCI_ANY_ID, 1871 .subdevice = PCI_ANY_ID, 1872 .setup = pci_hp_diva_setup, 1873 }, 1874 /* 1875 * Intel 1876 */ 1877 { 1878 .vendor = PCI_VENDOR_ID_INTEL, 1879 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1880 .subvendor = 0xe4bf, 1881 .subdevice = PCI_ANY_ID, 1882 .init = pci_inteli960ni_init, 1883 .setup = pci_default_setup, 1884 }, 1885 { 1886 .vendor = PCI_VENDOR_ID_INTEL, 1887 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1888 .subvendor = PCI_ANY_ID, 1889 .subdevice = PCI_ANY_ID, 1890 .setup = skip_tx_en_setup, 1891 }, 1892 { 1893 .vendor = PCI_VENDOR_ID_INTEL, 1894 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1895 .subvendor = PCI_ANY_ID, 1896 .subdevice = PCI_ANY_ID, 1897 .setup = skip_tx_en_setup, 1898 }, 1899 { 1900 .vendor = PCI_VENDOR_ID_INTEL, 1901 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1902 .subvendor = PCI_ANY_ID, 1903 .subdevice = PCI_ANY_ID, 1904 .setup = skip_tx_en_setup, 1905 }, 1906 { 1907 .vendor = PCI_VENDOR_ID_INTEL, 1908 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1909 .subvendor = PCI_ANY_ID, 1910 .subdevice = PCI_ANY_ID, 1911 .setup = ce4100_serial_setup, 1912 }, 1913 { 1914 .vendor = PCI_VENDOR_ID_INTEL, 1915 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1916 .subvendor = PCI_ANY_ID, 1917 .subdevice = PCI_ANY_ID, 1918 .setup = kt_serial_setup, 1919 }, 1920 /* 1921 * ITE 1922 */ 1923 { 1924 .vendor = PCI_VENDOR_ID_ITE, 1925 .device = PCI_DEVICE_ID_ITE_8872, 1926 .subvendor = PCI_ANY_ID, 1927 .subdevice = PCI_ANY_ID, 1928 .init = pci_ite887x_init, 1929 .setup = pci_default_setup, 1930 .exit = pci_ite887x_exit, 1931 }, 1932 /* 1933 * National Instruments 1934 */ 1935 { 1936 .vendor = PCI_VENDOR_ID_NI, 1937 .device = PCI_DEVICE_ID_NI_PCI23216, 1938 .subvendor = PCI_ANY_ID, 1939 .subdevice = PCI_ANY_ID, 1940 .init = pci_ni8420_init, 1941 .setup = pci_default_setup, 1942 .exit = pci_ni8420_exit, 1943 }, 1944 { 1945 .vendor = PCI_VENDOR_ID_NI, 1946 .device = PCI_DEVICE_ID_NI_PCI2328, 1947 .subvendor = PCI_ANY_ID, 1948 .subdevice = PCI_ANY_ID, 1949 .init = pci_ni8420_init, 1950 .setup = pci_default_setup, 1951 .exit = pci_ni8420_exit, 1952 }, 1953 { 1954 .vendor = PCI_VENDOR_ID_NI, 1955 .device = PCI_DEVICE_ID_NI_PCI2324, 1956 .subvendor = PCI_ANY_ID, 1957 .subdevice = PCI_ANY_ID, 1958 .init = pci_ni8420_init, 1959 .setup = pci_default_setup, 1960 .exit = pci_ni8420_exit, 1961 }, 1962 { 1963 .vendor = PCI_VENDOR_ID_NI, 1964 .device = PCI_DEVICE_ID_NI_PCI2322, 1965 .subvendor = PCI_ANY_ID, 1966 .subdevice = PCI_ANY_ID, 1967 .init = pci_ni8420_init, 1968 .setup = pci_default_setup, 1969 .exit = pci_ni8420_exit, 1970 }, 1971 { 1972 .vendor = PCI_VENDOR_ID_NI, 1973 .device = PCI_DEVICE_ID_NI_PCI2324I, 1974 .subvendor = PCI_ANY_ID, 1975 .subdevice = PCI_ANY_ID, 1976 .init = pci_ni8420_init, 1977 .setup = pci_default_setup, 1978 .exit = pci_ni8420_exit, 1979 }, 1980 { 1981 .vendor = PCI_VENDOR_ID_NI, 1982 .device = PCI_DEVICE_ID_NI_PCI2322I, 1983 .subvendor = PCI_ANY_ID, 1984 .subdevice = PCI_ANY_ID, 1985 .init = pci_ni8420_init, 1986 .setup = pci_default_setup, 1987 .exit = pci_ni8420_exit, 1988 }, 1989 { 1990 .vendor = PCI_VENDOR_ID_NI, 1991 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 1992 .subvendor = PCI_ANY_ID, 1993 .subdevice = PCI_ANY_ID, 1994 .init = pci_ni8420_init, 1995 .setup = pci_default_setup, 1996 .exit = pci_ni8420_exit, 1997 }, 1998 { 1999 .vendor = PCI_VENDOR_ID_NI, 2000 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2001 .subvendor = PCI_ANY_ID, 2002 .subdevice = PCI_ANY_ID, 2003 .init = pci_ni8420_init, 2004 .setup = pci_default_setup, 2005 .exit = pci_ni8420_exit, 2006 }, 2007 { 2008 .vendor = PCI_VENDOR_ID_NI, 2009 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2010 .subvendor = PCI_ANY_ID, 2011 .subdevice = PCI_ANY_ID, 2012 .init = pci_ni8420_init, 2013 .setup = pci_default_setup, 2014 .exit = pci_ni8420_exit, 2015 }, 2016 { 2017 .vendor = PCI_VENDOR_ID_NI, 2018 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2019 .subvendor = PCI_ANY_ID, 2020 .subdevice = PCI_ANY_ID, 2021 .init = pci_ni8420_init, 2022 .setup = pci_default_setup, 2023 .exit = pci_ni8420_exit, 2024 }, 2025 { 2026 .vendor = PCI_VENDOR_ID_NI, 2027 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2028 .subvendor = PCI_ANY_ID, 2029 .subdevice = PCI_ANY_ID, 2030 .init = pci_ni8420_init, 2031 .setup = pci_default_setup, 2032 .exit = pci_ni8420_exit, 2033 }, 2034 { 2035 .vendor = PCI_VENDOR_ID_NI, 2036 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2037 .subvendor = PCI_ANY_ID, 2038 .subdevice = PCI_ANY_ID, 2039 .init = pci_ni8420_init, 2040 .setup = pci_default_setup, 2041 .exit = pci_ni8420_exit, 2042 }, 2043 { 2044 .vendor = PCI_VENDOR_ID_NI, 2045 .device = PCI_ANY_ID, 2046 .subvendor = PCI_ANY_ID, 2047 .subdevice = PCI_ANY_ID, 2048 .init = pci_ni8430_init, 2049 .setup = pci_ni8430_setup, 2050 .exit = pci_ni8430_exit, 2051 }, 2052 /* Quatech */ 2053 { 2054 .vendor = PCI_VENDOR_ID_QUATECH, 2055 .device = PCI_ANY_ID, 2056 .subvendor = PCI_ANY_ID, 2057 .subdevice = PCI_ANY_ID, 2058 .init = pci_quatech_init, 2059 .setup = pci_quatech_setup, 2060 }, 2061 /* 2062 * Panacom 2063 */ 2064 { 2065 .vendor = PCI_VENDOR_ID_PANACOM, 2066 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2067 .subvendor = PCI_ANY_ID, 2068 .subdevice = PCI_ANY_ID, 2069 .init = pci_plx9050_init, 2070 .setup = pci_default_setup, 2071 .exit = pci_plx9050_exit, 2072 }, 2073 { 2074 .vendor = PCI_VENDOR_ID_PANACOM, 2075 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2076 .subvendor = PCI_ANY_ID, 2077 .subdevice = PCI_ANY_ID, 2078 .init = pci_plx9050_init, 2079 .setup = pci_default_setup, 2080 .exit = pci_plx9050_exit, 2081 }, 2082 /* 2083 * PLX 2084 */ 2085 { 2086 .vendor = PCI_VENDOR_ID_PLX, 2087 .device = PCI_DEVICE_ID_PLX_9050, 2088 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2089 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2090 .init = pci_plx9050_init, 2091 .setup = pci_default_setup, 2092 .exit = pci_plx9050_exit, 2093 }, 2094 { 2095 .vendor = PCI_VENDOR_ID_PLX, 2096 .device = PCI_DEVICE_ID_PLX_9050, 2097 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2098 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2099 .init = pci_plx9050_init, 2100 .setup = pci_default_setup, 2101 .exit = pci_plx9050_exit, 2102 }, 2103 { 2104 .vendor = PCI_VENDOR_ID_PLX, 2105 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2106 .subvendor = PCI_VENDOR_ID_PLX, 2107 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2108 .init = pci_plx9050_init, 2109 .setup = pci_default_setup, 2110 .exit = pci_plx9050_exit, 2111 }, 2112 /* 2113 * SBS Technologies, Inc., PMC-OCTALPRO 232 2114 */ 2115 { 2116 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2117 .device = PCI_DEVICE_ID_OCTPRO, 2118 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2119 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2120 .init = sbs_init, 2121 .setup = sbs_setup, 2122 .exit = sbs_exit, 2123 }, 2124 /* 2125 * SBS Technologies, Inc., PMC-OCTALPRO 422 2126 */ 2127 { 2128 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2129 .device = PCI_DEVICE_ID_OCTPRO, 2130 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2131 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2132 .init = sbs_init, 2133 .setup = sbs_setup, 2134 .exit = sbs_exit, 2135 }, 2136 /* 2137 * SBS Technologies, Inc., P-Octal 232 2138 */ 2139 { 2140 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2141 .device = PCI_DEVICE_ID_OCTPRO, 2142 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2143 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2144 .init = sbs_init, 2145 .setup = sbs_setup, 2146 .exit = sbs_exit, 2147 }, 2148 /* 2149 * SBS Technologies, Inc., P-Octal 422 2150 */ 2151 { 2152 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2153 .device = PCI_DEVICE_ID_OCTPRO, 2154 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2155 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2156 .init = sbs_init, 2157 .setup = sbs_setup, 2158 .exit = sbs_exit, 2159 }, 2160 /* 2161 * SIIG cards - these may be called via parport_serial 2162 */ 2163 { 2164 .vendor = PCI_VENDOR_ID_SIIG, 2165 .device = PCI_ANY_ID, 2166 .subvendor = PCI_ANY_ID, 2167 .subdevice = PCI_ANY_ID, 2168 .init = pci_siig_init, 2169 .setup = pci_siig_setup, 2170 }, 2171 /* 2172 * Titan cards 2173 */ 2174 { 2175 .vendor = PCI_VENDOR_ID_TITAN, 2176 .device = PCI_DEVICE_ID_TITAN_400L, 2177 .subvendor = PCI_ANY_ID, 2178 .subdevice = PCI_ANY_ID, 2179 .setup = titan_400l_800l_setup, 2180 }, 2181 { 2182 .vendor = PCI_VENDOR_ID_TITAN, 2183 .device = PCI_DEVICE_ID_TITAN_800L, 2184 .subvendor = PCI_ANY_ID, 2185 .subdevice = PCI_ANY_ID, 2186 .setup = titan_400l_800l_setup, 2187 }, 2188 /* 2189 * Timedia cards 2190 */ 2191 { 2192 .vendor = PCI_VENDOR_ID_TIMEDIA, 2193 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2194 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2195 .subdevice = PCI_ANY_ID, 2196 .probe = pci_timedia_probe, 2197 .init = pci_timedia_init, 2198 .setup = pci_timedia_setup, 2199 }, 2200 { 2201 .vendor = PCI_VENDOR_ID_TIMEDIA, 2202 .device = PCI_ANY_ID, 2203 .subvendor = PCI_ANY_ID, 2204 .subdevice = PCI_ANY_ID, 2205 .setup = pci_timedia_setup, 2206 }, 2207 /* 2208 * Sunix PCI serial boards 2209 */ 2210 { 2211 .vendor = PCI_VENDOR_ID_SUNIX, 2212 .device = PCI_DEVICE_ID_SUNIX_1999, 2213 .subvendor = PCI_VENDOR_ID_SUNIX, 2214 .subdevice = PCI_ANY_ID, 2215 .setup = pci_sunix_setup, 2216 }, 2217 /* 2218 * Xircom cards 2219 */ 2220 { 2221 .vendor = PCI_VENDOR_ID_XIRCOM, 2222 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2223 .subvendor = PCI_ANY_ID, 2224 .subdevice = PCI_ANY_ID, 2225 .init = pci_xircom_init, 2226 .setup = pci_default_setup, 2227 }, 2228 /* 2229 * Netmos cards - these may be called via parport_serial 2230 */ 2231 { 2232 .vendor = PCI_VENDOR_ID_NETMOS, 2233 .device = PCI_ANY_ID, 2234 .subvendor = PCI_ANY_ID, 2235 .subdevice = PCI_ANY_ID, 2236 .init = pci_netmos_init, 2237 .setup = pci_netmos_9900_setup, 2238 }, 2239 /* 2240 * EndRun Technologies 2241 */ 2242 { 2243 .vendor = PCI_VENDOR_ID_ENDRUN, 2244 .device = PCI_ANY_ID, 2245 .subvendor = PCI_ANY_ID, 2246 .subdevice = PCI_ANY_ID, 2247 .init = pci_endrun_init, 2248 .setup = pci_default_setup, 2249 }, 2250 /* 2251 * For Oxford Semiconductor Tornado based devices 2252 */ 2253 { 2254 .vendor = PCI_VENDOR_ID_OXSEMI, 2255 .device = PCI_ANY_ID, 2256 .subvendor = PCI_ANY_ID, 2257 .subdevice = PCI_ANY_ID, 2258 .init = pci_oxsemi_tornado_init, 2259 .setup = pci_default_setup, 2260 }, 2261 { 2262 .vendor = PCI_VENDOR_ID_MAINPINE, 2263 .device = PCI_ANY_ID, 2264 .subvendor = PCI_ANY_ID, 2265 .subdevice = PCI_ANY_ID, 2266 .init = pci_oxsemi_tornado_init, 2267 .setup = pci_default_setup, 2268 }, 2269 { 2270 .vendor = PCI_VENDOR_ID_DIGI, 2271 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2272 .subvendor = PCI_SUBVENDOR_ID_IBM, 2273 .subdevice = PCI_ANY_ID, 2274 .init = pci_oxsemi_tornado_init, 2275 .setup = pci_default_setup, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_INTEL, 2279 .device = 0x8811, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .init = pci_eg20t_init, 2283 .setup = pci_default_setup, 2284 }, 2285 { 2286 .vendor = PCI_VENDOR_ID_INTEL, 2287 .device = 0x8812, 2288 .subvendor = PCI_ANY_ID, 2289 .subdevice = PCI_ANY_ID, 2290 .init = pci_eg20t_init, 2291 .setup = pci_default_setup, 2292 }, 2293 { 2294 .vendor = PCI_VENDOR_ID_INTEL, 2295 .device = 0x8813, 2296 .subvendor = PCI_ANY_ID, 2297 .subdevice = PCI_ANY_ID, 2298 .init = pci_eg20t_init, 2299 .setup = pci_default_setup, 2300 }, 2301 { 2302 .vendor = PCI_VENDOR_ID_INTEL, 2303 .device = 0x8814, 2304 .subvendor = PCI_ANY_ID, 2305 .subdevice = PCI_ANY_ID, 2306 .init = pci_eg20t_init, 2307 .setup = pci_default_setup, 2308 }, 2309 { 2310 .vendor = 0x10DB, 2311 .device = 0x8027, 2312 .subvendor = PCI_ANY_ID, 2313 .subdevice = PCI_ANY_ID, 2314 .init = pci_eg20t_init, 2315 .setup = pci_default_setup, 2316 }, 2317 { 2318 .vendor = 0x10DB, 2319 .device = 0x8028, 2320 .subvendor = PCI_ANY_ID, 2321 .subdevice = PCI_ANY_ID, 2322 .init = pci_eg20t_init, 2323 .setup = pci_default_setup, 2324 }, 2325 { 2326 .vendor = 0x10DB, 2327 .device = 0x8029, 2328 .subvendor = PCI_ANY_ID, 2329 .subdevice = PCI_ANY_ID, 2330 .init = pci_eg20t_init, 2331 .setup = pci_default_setup, 2332 }, 2333 { 2334 .vendor = 0x10DB, 2335 .device = 0x800C, 2336 .subvendor = PCI_ANY_ID, 2337 .subdevice = PCI_ANY_ID, 2338 .init = pci_eg20t_init, 2339 .setup = pci_default_setup, 2340 }, 2341 { 2342 .vendor = 0x10DB, 2343 .device = 0x800D, 2344 .subvendor = PCI_ANY_ID, 2345 .subdevice = PCI_ANY_ID, 2346 .init = pci_eg20t_init, 2347 .setup = pci_default_setup, 2348 }, 2349 /* 2350 * Cronyx Omega PCI (PLX-chip based) 2351 */ 2352 { 2353 .vendor = PCI_VENDOR_ID_PLX, 2354 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2355 .subvendor = PCI_ANY_ID, 2356 .subdevice = PCI_ANY_ID, 2357 .setup = pci_omegapci_setup, 2358 }, 2359 /* WCH CH353 1S1P card (16550 clone) */ 2360 { 2361 .vendor = PCI_VENDOR_ID_WCH, 2362 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2363 .subvendor = PCI_ANY_ID, 2364 .subdevice = PCI_ANY_ID, 2365 .setup = pci_wch_ch353_setup, 2366 }, 2367 /* WCH CH353 2S1P card (16550 clone) */ 2368 { 2369 .vendor = PCI_VENDOR_ID_WCH, 2370 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2371 .subvendor = PCI_ANY_ID, 2372 .subdevice = PCI_ANY_ID, 2373 .setup = pci_wch_ch353_setup, 2374 }, 2375 /* WCH CH353 4S card (16550 clone) */ 2376 { 2377 .vendor = PCI_VENDOR_ID_WCH, 2378 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2379 .subvendor = PCI_ANY_ID, 2380 .subdevice = PCI_ANY_ID, 2381 .setup = pci_wch_ch353_setup, 2382 }, 2383 /* WCH CH353 2S1PF card (16550 clone) */ 2384 { 2385 .vendor = PCI_VENDOR_ID_WCH, 2386 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2387 .subvendor = PCI_ANY_ID, 2388 .subdevice = PCI_ANY_ID, 2389 .setup = pci_wch_ch353_setup, 2390 }, 2391 /* WCH CH352 2S card (16550 clone) */ 2392 { 2393 .vendor = PCI_VENDOR_ID_WCH, 2394 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2395 .subvendor = PCI_ANY_ID, 2396 .subdevice = PCI_ANY_ID, 2397 .setup = pci_wch_ch353_setup, 2398 }, 2399 /* WCH CH355 4S card (16550 clone) */ 2400 { 2401 .vendor = PCI_VENDOR_ID_WCH, 2402 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2403 .subvendor = PCI_ANY_ID, 2404 .subdevice = PCI_ANY_ID, 2405 .setup = pci_wch_ch355_setup, 2406 }, 2407 /* WCH CH382 2S card (16850 clone) */ 2408 { 2409 .vendor = PCIE_VENDOR_ID_WCH, 2410 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2411 .subvendor = PCI_ANY_ID, 2412 .subdevice = PCI_ANY_ID, 2413 .setup = pci_wch_ch38x_setup, 2414 }, 2415 /* WCH CH382 2S1P card (16850 clone) */ 2416 { 2417 .vendor = PCIE_VENDOR_ID_WCH, 2418 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2419 .subvendor = PCI_ANY_ID, 2420 .subdevice = PCI_ANY_ID, 2421 .setup = pci_wch_ch38x_setup, 2422 }, 2423 /* WCH CH384 4S card (16850 clone) */ 2424 { 2425 .vendor = PCIE_VENDOR_ID_WCH, 2426 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2427 .subvendor = PCI_ANY_ID, 2428 .subdevice = PCI_ANY_ID, 2429 .setup = pci_wch_ch38x_setup, 2430 }, 2431 /* WCH CH384 8S card (16850 clone) */ 2432 { 2433 .vendor = PCIE_VENDOR_ID_WCH, 2434 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2435 .subvendor = PCI_ANY_ID, 2436 .subdevice = PCI_ANY_ID, 2437 .init = pci_wch_ch38x_init, 2438 .exit = pci_wch_ch38x_exit, 2439 .setup = pci_wch_ch38x_setup, 2440 }, 2441 /* 2442 * ASIX devices with FIFO bug 2443 */ 2444 { 2445 .vendor = PCI_VENDOR_ID_ASIX, 2446 .device = PCI_ANY_ID, 2447 .subvendor = PCI_ANY_ID, 2448 .subdevice = PCI_ANY_ID, 2449 .setup = pci_asix_setup, 2450 }, 2451 /* 2452 * Broadcom TruManage (NetXtreme) 2453 */ 2454 { 2455 .vendor = PCI_VENDOR_ID_BROADCOM, 2456 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2457 .subvendor = PCI_ANY_ID, 2458 .subdevice = PCI_ANY_ID, 2459 .setup = pci_brcm_trumanage_setup, 2460 }, 2461 { 2462 .vendor = 0x1c29, 2463 .device = 0x1104, 2464 .subvendor = PCI_ANY_ID, 2465 .subdevice = PCI_ANY_ID, 2466 .setup = pci_fintek_setup, 2467 .init = pci_fintek_init, 2468 }, 2469 { 2470 .vendor = 0x1c29, 2471 .device = 0x1108, 2472 .subvendor = PCI_ANY_ID, 2473 .subdevice = PCI_ANY_ID, 2474 .setup = pci_fintek_setup, 2475 .init = pci_fintek_init, 2476 }, 2477 { 2478 .vendor = 0x1c29, 2479 .device = 0x1112, 2480 .subvendor = PCI_ANY_ID, 2481 .subdevice = PCI_ANY_ID, 2482 .setup = pci_fintek_setup, 2483 .init = pci_fintek_init, 2484 }, 2485 /* 2486 * MOXA 2487 */ 2488 { 2489 .vendor = PCI_VENDOR_ID_MOXA, 2490 .device = PCI_ANY_ID, 2491 .subvendor = PCI_ANY_ID, 2492 .subdevice = PCI_ANY_ID, 2493 .setup = pci_moxa_setup, 2494 }, 2495 { 2496 .vendor = 0x1c29, 2497 .device = 0x1204, 2498 .subvendor = PCI_ANY_ID, 2499 .subdevice = PCI_ANY_ID, 2500 .setup = pci_fintek_f815xxa_setup, 2501 .init = pci_fintek_f815xxa_init, 2502 }, 2503 { 2504 .vendor = 0x1c29, 2505 .device = 0x1208, 2506 .subvendor = PCI_ANY_ID, 2507 .subdevice = PCI_ANY_ID, 2508 .setup = pci_fintek_f815xxa_setup, 2509 .init = pci_fintek_f815xxa_init, 2510 }, 2511 { 2512 .vendor = 0x1c29, 2513 .device = 0x1212, 2514 .subvendor = PCI_ANY_ID, 2515 .subdevice = PCI_ANY_ID, 2516 .setup = pci_fintek_f815xxa_setup, 2517 .init = pci_fintek_f815xxa_init, 2518 }, 2519 2520 /* 2521 * Default "match everything" terminator entry 2522 */ 2523 { 2524 .vendor = PCI_ANY_ID, 2525 .device = PCI_ANY_ID, 2526 .subvendor = PCI_ANY_ID, 2527 .subdevice = PCI_ANY_ID, 2528 .setup = pci_default_setup, 2529 } 2530 }; 2531 2532 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2533 { 2534 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2535 } 2536 2537 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2538 { 2539 struct pci_serial_quirk *quirk; 2540 2541 for (quirk = pci_serial_quirks; ; quirk++) 2542 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2543 quirk_id_matches(quirk->device, dev->device) && 2544 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2545 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2546 break; 2547 return quirk; 2548 } 2549 2550 /* 2551 * This is the configuration table for all of the PCI serial boards 2552 * which we support. It is directly indexed by the pci_board_num_t enum 2553 * value, which is encoded in the pci_device_id PCI probe table's 2554 * driver_data member. 2555 * 2556 * The makeup of these names are: 2557 * pbn_bn{_bt}_n_baud{_offsetinhex} 2558 * 2559 * bn = PCI BAR number 2560 * bt = Index using PCI BARs 2561 * n = number of serial ports 2562 * baud = baud rate 2563 * offsetinhex = offset for each sequential port (in hex) 2564 * 2565 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2566 * 2567 * Please note: in theory if n = 1, _bt infix should make no difference. 2568 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2569 */ 2570 enum pci_board_num_t { 2571 pbn_default = 0, 2572 2573 pbn_b0_1_115200, 2574 pbn_b0_2_115200, 2575 pbn_b0_4_115200, 2576 pbn_b0_5_115200, 2577 pbn_b0_8_115200, 2578 2579 pbn_b0_1_921600, 2580 pbn_b0_2_921600, 2581 pbn_b0_4_921600, 2582 2583 pbn_b0_2_1130000, 2584 2585 pbn_b0_4_1152000, 2586 2587 pbn_b0_4_1250000, 2588 2589 pbn_b0_2_1843200, 2590 pbn_b0_4_1843200, 2591 2592 pbn_b0_1_3906250, 2593 2594 pbn_b0_bt_1_115200, 2595 pbn_b0_bt_2_115200, 2596 pbn_b0_bt_4_115200, 2597 pbn_b0_bt_8_115200, 2598 2599 pbn_b0_bt_1_460800, 2600 pbn_b0_bt_2_460800, 2601 pbn_b0_bt_4_460800, 2602 2603 pbn_b0_bt_1_921600, 2604 pbn_b0_bt_2_921600, 2605 pbn_b0_bt_4_921600, 2606 pbn_b0_bt_8_921600, 2607 2608 pbn_b1_1_115200, 2609 pbn_b1_2_115200, 2610 pbn_b1_4_115200, 2611 pbn_b1_8_115200, 2612 pbn_b1_16_115200, 2613 2614 pbn_b1_1_921600, 2615 pbn_b1_2_921600, 2616 pbn_b1_4_921600, 2617 pbn_b1_8_921600, 2618 2619 pbn_b1_2_1250000, 2620 2621 pbn_b1_bt_1_115200, 2622 pbn_b1_bt_2_115200, 2623 pbn_b1_bt_4_115200, 2624 2625 pbn_b1_bt_2_921600, 2626 2627 pbn_b1_1_1382400, 2628 pbn_b1_2_1382400, 2629 pbn_b1_4_1382400, 2630 pbn_b1_8_1382400, 2631 2632 pbn_b2_1_115200, 2633 pbn_b2_2_115200, 2634 pbn_b2_4_115200, 2635 pbn_b2_8_115200, 2636 2637 pbn_b2_1_460800, 2638 pbn_b2_4_460800, 2639 pbn_b2_8_460800, 2640 pbn_b2_16_460800, 2641 2642 pbn_b2_1_921600, 2643 pbn_b2_4_921600, 2644 pbn_b2_8_921600, 2645 2646 pbn_b2_8_1152000, 2647 2648 pbn_b2_bt_1_115200, 2649 pbn_b2_bt_2_115200, 2650 pbn_b2_bt_4_115200, 2651 2652 pbn_b2_bt_2_921600, 2653 pbn_b2_bt_4_921600, 2654 2655 pbn_b3_2_115200, 2656 pbn_b3_4_115200, 2657 pbn_b3_8_115200, 2658 2659 pbn_b4_bt_2_921600, 2660 pbn_b4_bt_4_921600, 2661 pbn_b4_bt_8_921600, 2662 2663 /* 2664 * Board-specific versions. 2665 */ 2666 pbn_panacom, 2667 pbn_panacom2, 2668 pbn_panacom4, 2669 pbn_plx_romulus, 2670 pbn_endrun_2_3906250, 2671 pbn_oxsemi, 2672 pbn_oxsemi_1_3906250, 2673 pbn_oxsemi_2_3906250, 2674 pbn_oxsemi_4_3906250, 2675 pbn_oxsemi_8_3906250, 2676 pbn_intel_i960, 2677 pbn_sgi_ioc3, 2678 pbn_computone_4, 2679 pbn_computone_6, 2680 pbn_computone_8, 2681 pbn_sbsxrsio, 2682 pbn_pasemi_1682M, 2683 pbn_ni8430_2, 2684 pbn_ni8430_4, 2685 pbn_ni8430_8, 2686 pbn_ni8430_16, 2687 pbn_ADDIDATA_PCIe_1_3906250, 2688 pbn_ADDIDATA_PCIe_2_3906250, 2689 pbn_ADDIDATA_PCIe_4_3906250, 2690 pbn_ADDIDATA_PCIe_8_3906250, 2691 pbn_ce4100_1_115200, 2692 pbn_omegapci, 2693 pbn_NETMOS9900_2s_115200, 2694 pbn_brcm_trumanage, 2695 pbn_fintek_4, 2696 pbn_fintek_8, 2697 pbn_fintek_12, 2698 pbn_fintek_F81504A, 2699 pbn_fintek_F81508A, 2700 pbn_fintek_F81512A, 2701 pbn_wch382_2, 2702 pbn_wch384_4, 2703 pbn_wch384_8, 2704 pbn_sunix_pci_1s, 2705 pbn_sunix_pci_2s, 2706 pbn_sunix_pci_4s, 2707 pbn_sunix_pci_8s, 2708 pbn_sunix_pci_16s, 2709 pbn_titan_1_4000000, 2710 pbn_titan_2_4000000, 2711 pbn_titan_4_4000000, 2712 pbn_titan_8_4000000, 2713 pbn_moxa8250_2p, 2714 pbn_moxa8250_4p, 2715 pbn_moxa8250_8p, 2716 }; 2717 2718 /* 2719 * uart_offset - the space between channels 2720 * reg_shift - describes how the UART registers are mapped 2721 * to PCI memory by the card. 2722 * For example IER register on SBS, Inc. PMC-OctPro is located at 2723 * offset 0x10 from the UART base, while UART_IER is defined as 1 2724 * in include/linux/serial_reg.h, 2725 * see first lines of serial_in() and serial_out() in 8250.c 2726 */ 2727 2728 static struct pciserial_board pci_boards[] = { 2729 [pbn_default] = { 2730 .flags = FL_BASE0, 2731 .num_ports = 1, 2732 .base_baud = 115200, 2733 .uart_offset = 8, 2734 }, 2735 [pbn_b0_1_115200] = { 2736 .flags = FL_BASE0, 2737 .num_ports = 1, 2738 .base_baud = 115200, 2739 .uart_offset = 8, 2740 }, 2741 [pbn_b0_2_115200] = { 2742 .flags = FL_BASE0, 2743 .num_ports = 2, 2744 .base_baud = 115200, 2745 .uart_offset = 8, 2746 }, 2747 [pbn_b0_4_115200] = { 2748 .flags = FL_BASE0, 2749 .num_ports = 4, 2750 .base_baud = 115200, 2751 .uart_offset = 8, 2752 }, 2753 [pbn_b0_5_115200] = { 2754 .flags = FL_BASE0, 2755 .num_ports = 5, 2756 .base_baud = 115200, 2757 .uart_offset = 8, 2758 }, 2759 [pbn_b0_8_115200] = { 2760 .flags = FL_BASE0, 2761 .num_ports = 8, 2762 .base_baud = 115200, 2763 .uart_offset = 8, 2764 }, 2765 [pbn_b0_1_921600] = { 2766 .flags = FL_BASE0, 2767 .num_ports = 1, 2768 .base_baud = 921600, 2769 .uart_offset = 8, 2770 }, 2771 [pbn_b0_2_921600] = { 2772 .flags = FL_BASE0, 2773 .num_ports = 2, 2774 .base_baud = 921600, 2775 .uart_offset = 8, 2776 }, 2777 [pbn_b0_4_921600] = { 2778 .flags = FL_BASE0, 2779 .num_ports = 4, 2780 .base_baud = 921600, 2781 .uart_offset = 8, 2782 }, 2783 2784 [pbn_b0_2_1130000] = { 2785 .flags = FL_BASE0, 2786 .num_ports = 2, 2787 .base_baud = 1130000, 2788 .uart_offset = 8, 2789 }, 2790 2791 [pbn_b0_4_1152000] = { 2792 .flags = FL_BASE0, 2793 .num_ports = 4, 2794 .base_baud = 1152000, 2795 .uart_offset = 8, 2796 }, 2797 2798 [pbn_b0_4_1250000] = { 2799 .flags = FL_BASE0, 2800 .num_ports = 4, 2801 .base_baud = 1250000, 2802 .uart_offset = 8, 2803 }, 2804 2805 [pbn_b0_2_1843200] = { 2806 .flags = FL_BASE0, 2807 .num_ports = 2, 2808 .base_baud = 1843200, 2809 .uart_offset = 8, 2810 }, 2811 [pbn_b0_4_1843200] = { 2812 .flags = FL_BASE0, 2813 .num_ports = 4, 2814 .base_baud = 1843200, 2815 .uart_offset = 8, 2816 }, 2817 2818 [pbn_b0_1_3906250] = { 2819 .flags = FL_BASE0, 2820 .num_ports = 1, 2821 .base_baud = 3906250, 2822 .uart_offset = 8, 2823 }, 2824 2825 [pbn_b0_bt_1_115200] = { 2826 .flags = FL_BASE0|FL_BASE_BARS, 2827 .num_ports = 1, 2828 .base_baud = 115200, 2829 .uart_offset = 8, 2830 }, 2831 [pbn_b0_bt_2_115200] = { 2832 .flags = FL_BASE0|FL_BASE_BARS, 2833 .num_ports = 2, 2834 .base_baud = 115200, 2835 .uart_offset = 8, 2836 }, 2837 [pbn_b0_bt_4_115200] = { 2838 .flags = FL_BASE0|FL_BASE_BARS, 2839 .num_ports = 4, 2840 .base_baud = 115200, 2841 .uart_offset = 8, 2842 }, 2843 [pbn_b0_bt_8_115200] = { 2844 .flags = FL_BASE0|FL_BASE_BARS, 2845 .num_ports = 8, 2846 .base_baud = 115200, 2847 .uart_offset = 8, 2848 }, 2849 2850 [pbn_b0_bt_1_460800] = { 2851 .flags = FL_BASE0|FL_BASE_BARS, 2852 .num_ports = 1, 2853 .base_baud = 460800, 2854 .uart_offset = 8, 2855 }, 2856 [pbn_b0_bt_2_460800] = { 2857 .flags = FL_BASE0|FL_BASE_BARS, 2858 .num_ports = 2, 2859 .base_baud = 460800, 2860 .uart_offset = 8, 2861 }, 2862 [pbn_b0_bt_4_460800] = { 2863 .flags = FL_BASE0|FL_BASE_BARS, 2864 .num_ports = 4, 2865 .base_baud = 460800, 2866 .uart_offset = 8, 2867 }, 2868 2869 [pbn_b0_bt_1_921600] = { 2870 .flags = FL_BASE0|FL_BASE_BARS, 2871 .num_ports = 1, 2872 .base_baud = 921600, 2873 .uart_offset = 8, 2874 }, 2875 [pbn_b0_bt_2_921600] = { 2876 .flags = FL_BASE0|FL_BASE_BARS, 2877 .num_ports = 2, 2878 .base_baud = 921600, 2879 .uart_offset = 8, 2880 }, 2881 [pbn_b0_bt_4_921600] = { 2882 .flags = FL_BASE0|FL_BASE_BARS, 2883 .num_ports = 4, 2884 .base_baud = 921600, 2885 .uart_offset = 8, 2886 }, 2887 [pbn_b0_bt_8_921600] = { 2888 .flags = FL_BASE0|FL_BASE_BARS, 2889 .num_ports = 8, 2890 .base_baud = 921600, 2891 .uart_offset = 8, 2892 }, 2893 2894 [pbn_b1_1_115200] = { 2895 .flags = FL_BASE1, 2896 .num_ports = 1, 2897 .base_baud = 115200, 2898 .uart_offset = 8, 2899 }, 2900 [pbn_b1_2_115200] = { 2901 .flags = FL_BASE1, 2902 .num_ports = 2, 2903 .base_baud = 115200, 2904 .uart_offset = 8, 2905 }, 2906 [pbn_b1_4_115200] = { 2907 .flags = FL_BASE1, 2908 .num_ports = 4, 2909 .base_baud = 115200, 2910 .uart_offset = 8, 2911 }, 2912 [pbn_b1_8_115200] = { 2913 .flags = FL_BASE1, 2914 .num_ports = 8, 2915 .base_baud = 115200, 2916 .uart_offset = 8, 2917 }, 2918 [pbn_b1_16_115200] = { 2919 .flags = FL_BASE1, 2920 .num_ports = 16, 2921 .base_baud = 115200, 2922 .uart_offset = 8, 2923 }, 2924 2925 [pbn_b1_1_921600] = { 2926 .flags = FL_BASE1, 2927 .num_ports = 1, 2928 .base_baud = 921600, 2929 .uart_offset = 8, 2930 }, 2931 [pbn_b1_2_921600] = { 2932 .flags = FL_BASE1, 2933 .num_ports = 2, 2934 .base_baud = 921600, 2935 .uart_offset = 8, 2936 }, 2937 [pbn_b1_4_921600] = { 2938 .flags = FL_BASE1, 2939 .num_ports = 4, 2940 .base_baud = 921600, 2941 .uart_offset = 8, 2942 }, 2943 [pbn_b1_8_921600] = { 2944 .flags = FL_BASE1, 2945 .num_ports = 8, 2946 .base_baud = 921600, 2947 .uart_offset = 8, 2948 }, 2949 [pbn_b1_2_1250000] = { 2950 .flags = FL_BASE1, 2951 .num_ports = 2, 2952 .base_baud = 1250000, 2953 .uart_offset = 8, 2954 }, 2955 2956 [pbn_b1_bt_1_115200] = { 2957 .flags = FL_BASE1|FL_BASE_BARS, 2958 .num_ports = 1, 2959 .base_baud = 115200, 2960 .uart_offset = 8, 2961 }, 2962 [pbn_b1_bt_2_115200] = { 2963 .flags = FL_BASE1|FL_BASE_BARS, 2964 .num_ports = 2, 2965 .base_baud = 115200, 2966 .uart_offset = 8, 2967 }, 2968 [pbn_b1_bt_4_115200] = { 2969 .flags = FL_BASE1|FL_BASE_BARS, 2970 .num_ports = 4, 2971 .base_baud = 115200, 2972 .uart_offset = 8, 2973 }, 2974 2975 [pbn_b1_bt_2_921600] = { 2976 .flags = FL_BASE1|FL_BASE_BARS, 2977 .num_ports = 2, 2978 .base_baud = 921600, 2979 .uart_offset = 8, 2980 }, 2981 2982 [pbn_b1_1_1382400] = { 2983 .flags = FL_BASE1, 2984 .num_ports = 1, 2985 .base_baud = 1382400, 2986 .uart_offset = 8, 2987 }, 2988 [pbn_b1_2_1382400] = { 2989 .flags = FL_BASE1, 2990 .num_ports = 2, 2991 .base_baud = 1382400, 2992 .uart_offset = 8, 2993 }, 2994 [pbn_b1_4_1382400] = { 2995 .flags = FL_BASE1, 2996 .num_ports = 4, 2997 .base_baud = 1382400, 2998 .uart_offset = 8, 2999 }, 3000 [pbn_b1_8_1382400] = { 3001 .flags = FL_BASE1, 3002 .num_ports = 8, 3003 .base_baud = 1382400, 3004 .uart_offset = 8, 3005 }, 3006 3007 [pbn_b2_1_115200] = { 3008 .flags = FL_BASE2, 3009 .num_ports = 1, 3010 .base_baud = 115200, 3011 .uart_offset = 8, 3012 }, 3013 [pbn_b2_2_115200] = { 3014 .flags = FL_BASE2, 3015 .num_ports = 2, 3016 .base_baud = 115200, 3017 .uart_offset = 8, 3018 }, 3019 [pbn_b2_4_115200] = { 3020 .flags = FL_BASE2, 3021 .num_ports = 4, 3022 .base_baud = 115200, 3023 .uart_offset = 8, 3024 }, 3025 [pbn_b2_8_115200] = { 3026 .flags = FL_BASE2, 3027 .num_ports = 8, 3028 .base_baud = 115200, 3029 .uart_offset = 8, 3030 }, 3031 3032 [pbn_b2_1_460800] = { 3033 .flags = FL_BASE2, 3034 .num_ports = 1, 3035 .base_baud = 460800, 3036 .uart_offset = 8, 3037 }, 3038 [pbn_b2_4_460800] = { 3039 .flags = FL_BASE2, 3040 .num_ports = 4, 3041 .base_baud = 460800, 3042 .uart_offset = 8, 3043 }, 3044 [pbn_b2_8_460800] = { 3045 .flags = FL_BASE2, 3046 .num_ports = 8, 3047 .base_baud = 460800, 3048 .uart_offset = 8, 3049 }, 3050 [pbn_b2_16_460800] = { 3051 .flags = FL_BASE2, 3052 .num_ports = 16, 3053 .base_baud = 460800, 3054 .uart_offset = 8, 3055 }, 3056 3057 [pbn_b2_1_921600] = { 3058 .flags = FL_BASE2, 3059 .num_ports = 1, 3060 .base_baud = 921600, 3061 .uart_offset = 8, 3062 }, 3063 [pbn_b2_4_921600] = { 3064 .flags = FL_BASE2, 3065 .num_ports = 4, 3066 .base_baud = 921600, 3067 .uart_offset = 8, 3068 }, 3069 [pbn_b2_8_921600] = { 3070 .flags = FL_BASE2, 3071 .num_ports = 8, 3072 .base_baud = 921600, 3073 .uart_offset = 8, 3074 }, 3075 3076 [pbn_b2_8_1152000] = { 3077 .flags = FL_BASE2, 3078 .num_ports = 8, 3079 .base_baud = 1152000, 3080 .uart_offset = 8, 3081 }, 3082 3083 [pbn_b2_bt_1_115200] = { 3084 .flags = FL_BASE2|FL_BASE_BARS, 3085 .num_ports = 1, 3086 .base_baud = 115200, 3087 .uart_offset = 8, 3088 }, 3089 [pbn_b2_bt_2_115200] = { 3090 .flags = FL_BASE2|FL_BASE_BARS, 3091 .num_ports = 2, 3092 .base_baud = 115200, 3093 .uart_offset = 8, 3094 }, 3095 [pbn_b2_bt_4_115200] = { 3096 .flags = FL_BASE2|FL_BASE_BARS, 3097 .num_ports = 4, 3098 .base_baud = 115200, 3099 .uart_offset = 8, 3100 }, 3101 3102 [pbn_b2_bt_2_921600] = { 3103 .flags = FL_BASE2|FL_BASE_BARS, 3104 .num_ports = 2, 3105 .base_baud = 921600, 3106 .uart_offset = 8, 3107 }, 3108 [pbn_b2_bt_4_921600] = { 3109 .flags = FL_BASE2|FL_BASE_BARS, 3110 .num_ports = 4, 3111 .base_baud = 921600, 3112 .uart_offset = 8, 3113 }, 3114 3115 [pbn_b3_2_115200] = { 3116 .flags = FL_BASE3, 3117 .num_ports = 2, 3118 .base_baud = 115200, 3119 .uart_offset = 8, 3120 }, 3121 [pbn_b3_4_115200] = { 3122 .flags = FL_BASE3, 3123 .num_ports = 4, 3124 .base_baud = 115200, 3125 .uart_offset = 8, 3126 }, 3127 [pbn_b3_8_115200] = { 3128 .flags = FL_BASE3, 3129 .num_ports = 8, 3130 .base_baud = 115200, 3131 .uart_offset = 8, 3132 }, 3133 3134 [pbn_b4_bt_2_921600] = { 3135 .flags = FL_BASE4, 3136 .num_ports = 2, 3137 .base_baud = 921600, 3138 .uart_offset = 8, 3139 }, 3140 [pbn_b4_bt_4_921600] = { 3141 .flags = FL_BASE4, 3142 .num_ports = 4, 3143 .base_baud = 921600, 3144 .uart_offset = 8, 3145 }, 3146 [pbn_b4_bt_8_921600] = { 3147 .flags = FL_BASE4, 3148 .num_ports = 8, 3149 .base_baud = 921600, 3150 .uart_offset = 8, 3151 }, 3152 3153 /* 3154 * Entries following this are board-specific. 3155 */ 3156 3157 /* 3158 * Panacom - IOMEM 3159 */ 3160 [pbn_panacom] = { 3161 .flags = FL_BASE2, 3162 .num_ports = 2, 3163 .base_baud = 921600, 3164 .uart_offset = 0x400, 3165 .reg_shift = 7, 3166 }, 3167 [pbn_panacom2] = { 3168 .flags = FL_BASE2|FL_BASE_BARS, 3169 .num_ports = 2, 3170 .base_baud = 921600, 3171 .uart_offset = 0x400, 3172 .reg_shift = 7, 3173 }, 3174 [pbn_panacom4] = { 3175 .flags = FL_BASE2|FL_BASE_BARS, 3176 .num_ports = 4, 3177 .base_baud = 921600, 3178 .uart_offset = 0x400, 3179 .reg_shift = 7, 3180 }, 3181 3182 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3183 [pbn_plx_romulus] = { 3184 .flags = FL_BASE2, 3185 .num_ports = 4, 3186 .base_baud = 921600, 3187 .uart_offset = 8 << 2, 3188 .reg_shift = 2, 3189 .first_offset = 0x03, 3190 }, 3191 3192 /* 3193 * EndRun Technologies 3194 * Uses the size of PCI Base region 0 to 3195 * signal now many ports are available 3196 * 2 port 952 Uart support 3197 */ 3198 [pbn_endrun_2_3906250] = { 3199 .flags = FL_BASE0, 3200 .num_ports = 2, 3201 .base_baud = 3906250, 3202 .uart_offset = 0x200, 3203 .first_offset = 0x1000, 3204 }, 3205 3206 /* 3207 * This board uses the size of PCI Base region 0 to 3208 * signal now many ports are available 3209 */ 3210 [pbn_oxsemi] = { 3211 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3212 .num_ports = 32, 3213 .base_baud = 115200, 3214 .uart_offset = 8, 3215 }, 3216 [pbn_oxsemi_1_3906250] = { 3217 .flags = FL_BASE0, 3218 .num_ports = 1, 3219 .base_baud = 3906250, 3220 .uart_offset = 0x200, 3221 .first_offset = 0x1000, 3222 }, 3223 [pbn_oxsemi_2_3906250] = { 3224 .flags = FL_BASE0, 3225 .num_ports = 2, 3226 .base_baud = 3906250, 3227 .uart_offset = 0x200, 3228 .first_offset = 0x1000, 3229 }, 3230 [pbn_oxsemi_4_3906250] = { 3231 .flags = FL_BASE0, 3232 .num_ports = 4, 3233 .base_baud = 3906250, 3234 .uart_offset = 0x200, 3235 .first_offset = 0x1000, 3236 }, 3237 [pbn_oxsemi_8_3906250] = { 3238 .flags = FL_BASE0, 3239 .num_ports = 8, 3240 .base_baud = 3906250, 3241 .uart_offset = 0x200, 3242 .first_offset = 0x1000, 3243 }, 3244 3245 3246 /* 3247 * EKF addition for i960 Boards form EKF with serial port. 3248 * Max 256 ports. 3249 */ 3250 [pbn_intel_i960] = { 3251 .flags = FL_BASE0, 3252 .num_ports = 32, 3253 .base_baud = 921600, 3254 .uart_offset = 8 << 2, 3255 .reg_shift = 2, 3256 .first_offset = 0x10000, 3257 }, 3258 [pbn_sgi_ioc3] = { 3259 .flags = FL_BASE0|FL_NOIRQ, 3260 .num_ports = 1, 3261 .base_baud = 458333, 3262 .uart_offset = 8, 3263 .reg_shift = 0, 3264 .first_offset = 0x20178, 3265 }, 3266 3267 /* 3268 * Computone - uses IOMEM. 3269 */ 3270 [pbn_computone_4] = { 3271 .flags = FL_BASE0, 3272 .num_ports = 4, 3273 .base_baud = 921600, 3274 .uart_offset = 0x40, 3275 .reg_shift = 2, 3276 .first_offset = 0x200, 3277 }, 3278 [pbn_computone_6] = { 3279 .flags = FL_BASE0, 3280 .num_ports = 6, 3281 .base_baud = 921600, 3282 .uart_offset = 0x40, 3283 .reg_shift = 2, 3284 .first_offset = 0x200, 3285 }, 3286 [pbn_computone_8] = { 3287 .flags = FL_BASE0, 3288 .num_ports = 8, 3289 .base_baud = 921600, 3290 .uart_offset = 0x40, 3291 .reg_shift = 2, 3292 .first_offset = 0x200, 3293 }, 3294 [pbn_sbsxrsio] = { 3295 .flags = FL_BASE0, 3296 .num_ports = 8, 3297 .base_baud = 460800, 3298 .uart_offset = 256, 3299 .reg_shift = 4, 3300 }, 3301 /* 3302 * PA Semi PWRficient PA6T-1682M on-chip UART 3303 */ 3304 [pbn_pasemi_1682M] = { 3305 .flags = FL_BASE0, 3306 .num_ports = 1, 3307 .base_baud = 8333333, 3308 }, 3309 /* 3310 * National Instruments 843x 3311 */ 3312 [pbn_ni8430_16] = { 3313 .flags = FL_BASE0, 3314 .num_ports = 16, 3315 .base_baud = 3686400, 3316 .uart_offset = 0x10, 3317 .first_offset = 0x800, 3318 }, 3319 [pbn_ni8430_8] = { 3320 .flags = FL_BASE0, 3321 .num_ports = 8, 3322 .base_baud = 3686400, 3323 .uart_offset = 0x10, 3324 .first_offset = 0x800, 3325 }, 3326 [pbn_ni8430_4] = { 3327 .flags = FL_BASE0, 3328 .num_ports = 4, 3329 .base_baud = 3686400, 3330 .uart_offset = 0x10, 3331 .first_offset = 0x800, 3332 }, 3333 [pbn_ni8430_2] = { 3334 .flags = FL_BASE0, 3335 .num_ports = 2, 3336 .base_baud = 3686400, 3337 .uart_offset = 0x10, 3338 .first_offset = 0x800, 3339 }, 3340 /* 3341 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3342 */ 3343 [pbn_ADDIDATA_PCIe_1_3906250] = { 3344 .flags = FL_BASE0, 3345 .num_ports = 1, 3346 .base_baud = 3906250, 3347 .uart_offset = 0x200, 3348 .first_offset = 0x1000, 3349 }, 3350 [pbn_ADDIDATA_PCIe_2_3906250] = { 3351 .flags = FL_BASE0, 3352 .num_ports = 2, 3353 .base_baud = 3906250, 3354 .uart_offset = 0x200, 3355 .first_offset = 0x1000, 3356 }, 3357 [pbn_ADDIDATA_PCIe_4_3906250] = { 3358 .flags = FL_BASE0, 3359 .num_ports = 4, 3360 .base_baud = 3906250, 3361 .uart_offset = 0x200, 3362 .first_offset = 0x1000, 3363 }, 3364 [pbn_ADDIDATA_PCIe_8_3906250] = { 3365 .flags = FL_BASE0, 3366 .num_ports = 8, 3367 .base_baud = 3906250, 3368 .uart_offset = 0x200, 3369 .first_offset = 0x1000, 3370 }, 3371 [pbn_ce4100_1_115200] = { 3372 .flags = FL_BASE_BARS, 3373 .num_ports = 2, 3374 .base_baud = 921600, 3375 .reg_shift = 2, 3376 }, 3377 [pbn_omegapci] = { 3378 .flags = FL_BASE0, 3379 .num_ports = 8, 3380 .base_baud = 115200, 3381 .uart_offset = 0x200, 3382 }, 3383 [pbn_NETMOS9900_2s_115200] = { 3384 .flags = FL_BASE0, 3385 .num_ports = 2, 3386 .base_baud = 115200, 3387 }, 3388 [pbn_brcm_trumanage] = { 3389 .flags = FL_BASE0, 3390 .num_ports = 1, 3391 .reg_shift = 2, 3392 .base_baud = 115200, 3393 }, 3394 [pbn_fintek_4] = { 3395 .num_ports = 4, 3396 .uart_offset = 8, 3397 .base_baud = 115200, 3398 .first_offset = 0x40, 3399 }, 3400 [pbn_fintek_8] = { 3401 .num_ports = 8, 3402 .uart_offset = 8, 3403 .base_baud = 115200, 3404 .first_offset = 0x40, 3405 }, 3406 [pbn_fintek_12] = { 3407 .num_ports = 12, 3408 .uart_offset = 8, 3409 .base_baud = 115200, 3410 .first_offset = 0x40, 3411 }, 3412 [pbn_fintek_F81504A] = { 3413 .num_ports = 4, 3414 .uart_offset = 8, 3415 .base_baud = 115200, 3416 }, 3417 [pbn_fintek_F81508A] = { 3418 .num_ports = 8, 3419 .uart_offset = 8, 3420 .base_baud = 115200, 3421 }, 3422 [pbn_fintek_F81512A] = { 3423 .num_ports = 12, 3424 .uart_offset = 8, 3425 .base_baud = 115200, 3426 }, 3427 [pbn_wch382_2] = { 3428 .flags = FL_BASE0, 3429 .num_ports = 2, 3430 .base_baud = 115200, 3431 .uart_offset = 8, 3432 .first_offset = 0xC0, 3433 }, 3434 [pbn_wch384_4] = { 3435 .flags = FL_BASE0, 3436 .num_ports = 4, 3437 .base_baud = 115200, 3438 .uart_offset = 8, 3439 .first_offset = 0xC0, 3440 }, 3441 [pbn_wch384_8] = { 3442 .flags = FL_BASE0, 3443 .num_ports = 8, 3444 .base_baud = 115200, 3445 .uart_offset = 8, 3446 .first_offset = 0x00, 3447 }, 3448 [pbn_sunix_pci_1s] = { 3449 .num_ports = 1, 3450 .base_baud = 921600, 3451 .uart_offset = 0x8, 3452 }, 3453 [pbn_sunix_pci_2s] = { 3454 .num_ports = 2, 3455 .base_baud = 921600, 3456 .uart_offset = 0x8, 3457 }, 3458 [pbn_sunix_pci_4s] = { 3459 .num_ports = 4, 3460 .base_baud = 921600, 3461 .uart_offset = 0x8, 3462 }, 3463 [pbn_sunix_pci_8s] = { 3464 .num_ports = 8, 3465 .base_baud = 921600, 3466 .uart_offset = 0x8, 3467 }, 3468 [pbn_sunix_pci_16s] = { 3469 .num_ports = 16, 3470 .base_baud = 921600, 3471 .uart_offset = 0x8, 3472 }, 3473 [pbn_titan_1_4000000] = { 3474 .flags = FL_BASE0, 3475 .num_ports = 1, 3476 .base_baud = 4000000, 3477 .uart_offset = 0x200, 3478 .first_offset = 0x1000, 3479 }, 3480 [pbn_titan_2_4000000] = { 3481 .flags = FL_BASE0, 3482 .num_ports = 2, 3483 .base_baud = 4000000, 3484 .uart_offset = 0x200, 3485 .first_offset = 0x1000, 3486 }, 3487 [pbn_titan_4_4000000] = { 3488 .flags = FL_BASE0, 3489 .num_ports = 4, 3490 .base_baud = 4000000, 3491 .uart_offset = 0x200, 3492 .first_offset = 0x1000, 3493 }, 3494 [pbn_titan_8_4000000] = { 3495 .flags = FL_BASE0, 3496 .num_ports = 8, 3497 .base_baud = 4000000, 3498 .uart_offset = 0x200, 3499 .first_offset = 0x1000, 3500 }, 3501 [pbn_moxa8250_2p] = { 3502 .flags = FL_BASE1, 3503 .num_ports = 2, 3504 .base_baud = 921600, 3505 .uart_offset = 0x200, 3506 }, 3507 [pbn_moxa8250_4p] = { 3508 .flags = FL_BASE1, 3509 .num_ports = 4, 3510 .base_baud = 921600, 3511 .uart_offset = 0x200, 3512 }, 3513 [pbn_moxa8250_8p] = { 3514 .flags = FL_BASE1, 3515 .num_ports = 8, 3516 .base_baud = 921600, 3517 .uart_offset = 0x200, 3518 }, 3519 }; 3520 3521 static const struct pci_device_id blacklist[] = { 3522 /* softmodems */ 3523 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3524 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3525 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3526 3527 /* multi-io cards handled by parport_serial */ 3528 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3529 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3530 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3531 3532 /* Intel platforms with MID UART */ 3533 { PCI_VDEVICE(INTEL, 0x081b), }, 3534 { PCI_VDEVICE(INTEL, 0x081c), }, 3535 { PCI_VDEVICE(INTEL, 0x081d), }, 3536 { PCI_VDEVICE(INTEL, 0x1191), }, 3537 { PCI_VDEVICE(INTEL, 0x18d8), }, 3538 { PCI_VDEVICE(INTEL, 0x19d8), }, 3539 3540 /* Intel platforms with DesignWare UART */ 3541 { PCI_VDEVICE(INTEL, 0x0936), }, 3542 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3543 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3544 { PCI_VDEVICE(INTEL, 0x228a), }, 3545 { PCI_VDEVICE(INTEL, 0x228c), }, 3546 { PCI_VDEVICE(INTEL, 0x4b96), }, 3547 { PCI_VDEVICE(INTEL, 0x4b97), }, 3548 { PCI_VDEVICE(INTEL, 0x4b98), }, 3549 { PCI_VDEVICE(INTEL, 0x4b99), }, 3550 { PCI_VDEVICE(INTEL, 0x4b9a), }, 3551 { PCI_VDEVICE(INTEL, 0x4b9b), }, 3552 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3553 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3554 3555 /* Exar devices */ 3556 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3557 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3558 3559 /* Pericom devices */ 3560 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), }, 3561 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), }, 3562 3563 /* End of the black list */ 3564 { } 3565 }; 3566 3567 static int serial_pci_is_class_communication(struct pci_dev *dev) 3568 { 3569 /* 3570 * If it is not a communications device or the programming 3571 * interface is greater than 6, give up. 3572 */ 3573 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3574 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3575 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3576 (dev->class & 0xff) > 6) 3577 return -ENODEV; 3578 3579 return 0; 3580 } 3581 3582 /* 3583 * Given a complete unknown PCI device, try to use some heuristics to 3584 * guess what the configuration might be, based on the pitiful PCI 3585 * serial specs. Returns 0 on success, -ENODEV on failure. 3586 */ 3587 static int 3588 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3589 { 3590 int num_iomem, num_port, first_port = -1, i; 3591 int rc; 3592 3593 rc = serial_pci_is_class_communication(dev); 3594 if (rc) 3595 return rc; 3596 3597 /* 3598 * Should we try to make guesses for multiport serial devices later? 3599 */ 3600 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3601 return -ENODEV; 3602 3603 num_iomem = num_port = 0; 3604 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3605 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3606 num_port++; 3607 if (first_port == -1) 3608 first_port = i; 3609 } 3610 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3611 num_iomem++; 3612 } 3613 3614 /* 3615 * If there is 1 or 0 iomem regions, and exactly one port, 3616 * use it. We guess the number of ports based on the IO 3617 * region size. 3618 */ 3619 if (num_iomem <= 1 && num_port == 1) { 3620 board->flags = first_port; 3621 board->num_ports = pci_resource_len(dev, first_port) / 8; 3622 return 0; 3623 } 3624 3625 /* 3626 * Now guess if we've got a board which indexes by BARs. 3627 * Each IO BAR should be 8 bytes, and they should follow 3628 * consecutively. 3629 */ 3630 first_port = -1; 3631 num_port = 0; 3632 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3633 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3634 pci_resource_len(dev, i) == 8 && 3635 (first_port == -1 || (first_port + num_port) == i)) { 3636 num_port++; 3637 if (first_port == -1) 3638 first_port = i; 3639 } 3640 } 3641 3642 if (num_port > 1) { 3643 board->flags = first_port | FL_BASE_BARS; 3644 board->num_ports = num_port; 3645 return 0; 3646 } 3647 3648 return -ENODEV; 3649 } 3650 3651 static inline int 3652 serial_pci_matches(const struct pciserial_board *board, 3653 const struct pciserial_board *guessed) 3654 { 3655 return 3656 board->num_ports == guessed->num_ports && 3657 board->base_baud == guessed->base_baud && 3658 board->uart_offset == guessed->uart_offset && 3659 board->reg_shift == guessed->reg_shift && 3660 board->first_offset == guessed->first_offset; 3661 } 3662 3663 struct serial_private * 3664 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3665 { 3666 struct uart_8250_port uart; 3667 struct serial_private *priv; 3668 struct pci_serial_quirk *quirk; 3669 int rc, nr_ports, i; 3670 3671 nr_ports = board->num_ports; 3672 3673 /* 3674 * Find an init and setup quirks. 3675 */ 3676 quirk = find_quirk(dev); 3677 3678 /* 3679 * Run the new-style initialization function. 3680 * The initialization function returns: 3681 * <0 - error 3682 * 0 - use board->num_ports 3683 * >0 - number of ports 3684 */ 3685 if (quirk->init) { 3686 rc = quirk->init(dev); 3687 if (rc < 0) { 3688 priv = ERR_PTR(rc); 3689 goto err_out; 3690 } 3691 if (rc) 3692 nr_ports = rc; 3693 } 3694 3695 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3696 if (!priv) { 3697 priv = ERR_PTR(-ENOMEM); 3698 goto err_deinit; 3699 } 3700 3701 priv->dev = dev; 3702 priv->quirk = quirk; 3703 3704 memset(&uart, 0, sizeof(uart)); 3705 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3706 uart.port.uartclk = board->base_baud * 16; 3707 3708 if (board->flags & FL_NOIRQ) { 3709 uart.port.irq = 0; 3710 } else { 3711 if (pci_match_id(pci_use_msi, dev)) { 3712 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3713 pci_set_master(dev); 3714 uart.port.flags &= ~UPF_SHARE_IRQ; 3715 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3716 } else { 3717 pci_dbg(dev, "Using legacy interrupts\n"); 3718 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3719 } 3720 if (rc < 0) { 3721 kfree(priv); 3722 priv = ERR_PTR(rc); 3723 goto err_deinit; 3724 } 3725 3726 uart.port.irq = pci_irq_vector(dev, 0); 3727 } 3728 3729 uart.port.dev = &dev->dev; 3730 3731 for (i = 0; i < nr_ports; i++) { 3732 if (quirk->setup(priv, board, &uart, i)) 3733 break; 3734 3735 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3736 uart.port.iobase, uart.port.irq, uart.port.iotype); 3737 3738 priv->line[i] = serial8250_register_8250_port(&uart); 3739 if (priv->line[i] < 0) { 3740 pci_err(dev, 3741 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3742 uart.port.iobase, uart.port.irq, 3743 uart.port.iotype, priv->line[i]); 3744 break; 3745 } 3746 } 3747 priv->nr = i; 3748 priv->board = board; 3749 return priv; 3750 3751 err_deinit: 3752 if (quirk->exit) 3753 quirk->exit(dev); 3754 err_out: 3755 return priv; 3756 } 3757 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3758 3759 static void pciserial_detach_ports(struct serial_private *priv) 3760 { 3761 struct pci_serial_quirk *quirk; 3762 int i; 3763 3764 for (i = 0; i < priv->nr; i++) 3765 serial8250_unregister_port(priv->line[i]); 3766 3767 /* 3768 * Find the exit quirks. 3769 */ 3770 quirk = find_quirk(priv->dev); 3771 if (quirk->exit) 3772 quirk->exit(priv->dev); 3773 } 3774 3775 void pciserial_remove_ports(struct serial_private *priv) 3776 { 3777 pciserial_detach_ports(priv); 3778 kfree(priv); 3779 } 3780 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3781 3782 void pciserial_suspend_ports(struct serial_private *priv) 3783 { 3784 int i; 3785 3786 for (i = 0; i < priv->nr; i++) 3787 if (priv->line[i] >= 0) 3788 serial8250_suspend_port(priv->line[i]); 3789 3790 /* 3791 * Ensure that every init quirk is properly torn down 3792 */ 3793 if (priv->quirk->exit) 3794 priv->quirk->exit(priv->dev); 3795 } 3796 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3797 3798 void pciserial_resume_ports(struct serial_private *priv) 3799 { 3800 int i; 3801 3802 /* 3803 * Ensure that the board is correctly configured. 3804 */ 3805 if (priv->quirk->init) 3806 priv->quirk->init(priv->dev); 3807 3808 for (i = 0; i < priv->nr; i++) 3809 if (priv->line[i] >= 0) 3810 serial8250_resume_port(priv->line[i]); 3811 } 3812 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3813 3814 /* 3815 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3816 * to the arrangement of serial ports on a PCI card. 3817 */ 3818 static int 3819 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3820 { 3821 struct pci_serial_quirk *quirk; 3822 struct serial_private *priv; 3823 const struct pciserial_board *board; 3824 const struct pci_device_id *exclude; 3825 struct pciserial_board tmp; 3826 int rc; 3827 3828 quirk = find_quirk(dev); 3829 if (quirk->probe) { 3830 rc = quirk->probe(dev); 3831 if (rc) 3832 return rc; 3833 } 3834 3835 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3836 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 3837 return -EINVAL; 3838 } 3839 3840 board = &pci_boards[ent->driver_data]; 3841 3842 exclude = pci_match_id(blacklist, dev); 3843 if (exclude) 3844 return -ENODEV; 3845 3846 rc = pcim_enable_device(dev); 3847 pci_save_state(dev); 3848 if (rc) 3849 return rc; 3850 3851 if (ent->driver_data == pbn_default) { 3852 /* 3853 * Use a copy of the pci_board entry for this; 3854 * avoid changing entries in the table. 3855 */ 3856 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3857 board = &tmp; 3858 3859 /* 3860 * We matched one of our class entries. Try to 3861 * determine the parameters of this board. 3862 */ 3863 rc = serial_pci_guess_board(dev, &tmp); 3864 if (rc) 3865 return rc; 3866 } else { 3867 /* 3868 * We matched an explicit entry. If we are able to 3869 * detect this boards settings with our heuristic, 3870 * then we no longer need this entry. 3871 */ 3872 memcpy(&tmp, &pci_boards[pbn_default], 3873 sizeof(struct pciserial_board)); 3874 rc = serial_pci_guess_board(dev, &tmp); 3875 if (rc == 0 && serial_pci_matches(board, &tmp)) 3876 moan_device("Redundant entry in serial pci_table.", 3877 dev); 3878 } 3879 3880 priv = pciserial_init_ports(dev, board); 3881 if (IS_ERR(priv)) 3882 return PTR_ERR(priv); 3883 3884 pci_set_drvdata(dev, priv); 3885 return 0; 3886 } 3887 3888 static void pciserial_remove_one(struct pci_dev *dev) 3889 { 3890 struct serial_private *priv = pci_get_drvdata(dev); 3891 3892 pciserial_remove_ports(priv); 3893 } 3894 3895 #ifdef CONFIG_PM_SLEEP 3896 static int pciserial_suspend_one(struct device *dev) 3897 { 3898 struct serial_private *priv = dev_get_drvdata(dev); 3899 3900 if (priv) 3901 pciserial_suspend_ports(priv); 3902 3903 return 0; 3904 } 3905 3906 static int pciserial_resume_one(struct device *dev) 3907 { 3908 struct pci_dev *pdev = to_pci_dev(dev); 3909 struct serial_private *priv = pci_get_drvdata(pdev); 3910 int err; 3911 3912 if (priv) { 3913 /* 3914 * The device may have been disabled. Re-enable it. 3915 */ 3916 err = pci_enable_device(pdev); 3917 /* FIXME: We cannot simply error out here */ 3918 if (err) 3919 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 3920 pciserial_resume_ports(priv); 3921 } 3922 return 0; 3923 } 3924 #endif 3925 3926 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 3927 pciserial_resume_one); 3928 3929 static const struct pci_device_id serial_pci_tbl[] = { 3930 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 3931 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 3932 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 3933 pbn_b2_8_921600 }, 3934 /* Advantech also use 0x3618 and 0xf618 */ 3935 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 3936 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3937 pbn_b0_4_921600 }, 3938 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 3939 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3940 pbn_b0_4_921600 }, 3941 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3942 PCI_SUBVENDOR_ID_CONNECT_TECH, 3943 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3944 pbn_b1_8_1382400 }, 3945 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3946 PCI_SUBVENDOR_ID_CONNECT_TECH, 3947 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3948 pbn_b1_4_1382400 }, 3949 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3950 PCI_SUBVENDOR_ID_CONNECT_TECH, 3951 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3952 pbn_b1_2_1382400 }, 3953 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3954 PCI_SUBVENDOR_ID_CONNECT_TECH, 3955 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3956 pbn_b1_8_1382400 }, 3957 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3958 PCI_SUBVENDOR_ID_CONNECT_TECH, 3959 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3960 pbn_b1_4_1382400 }, 3961 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3962 PCI_SUBVENDOR_ID_CONNECT_TECH, 3963 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3964 pbn_b1_2_1382400 }, 3965 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3966 PCI_SUBVENDOR_ID_CONNECT_TECH, 3967 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 3968 pbn_b1_8_921600 }, 3969 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3970 PCI_SUBVENDOR_ID_CONNECT_TECH, 3971 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 3972 pbn_b1_8_921600 }, 3973 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3974 PCI_SUBVENDOR_ID_CONNECT_TECH, 3975 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 3976 pbn_b1_4_921600 }, 3977 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3978 PCI_SUBVENDOR_ID_CONNECT_TECH, 3979 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 3980 pbn_b1_4_921600 }, 3981 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3982 PCI_SUBVENDOR_ID_CONNECT_TECH, 3983 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 3984 pbn_b1_2_921600 }, 3985 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3986 PCI_SUBVENDOR_ID_CONNECT_TECH, 3987 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 3988 pbn_b1_8_921600 }, 3989 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3990 PCI_SUBVENDOR_ID_CONNECT_TECH, 3991 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 3992 pbn_b1_8_921600 }, 3993 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3994 PCI_SUBVENDOR_ID_CONNECT_TECH, 3995 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 3996 pbn_b1_4_921600 }, 3997 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3998 PCI_SUBVENDOR_ID_CONNECT_TECH, 3999 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4000 pbn_b1_2_1250000 }, 4001 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4002 PCI_SUBVENDOR_ID_CONNECT_TECH, 4003 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4004 pbn_b0_2_1843200 }, 4005 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4006 PCI_SUBVENDOR_ID_CONNECT_TECH, 4007 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4008 pbn_b0_4_1843200 }, 4009 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4010 PCI_VENDOR_ID_AFAVLAB, 4011 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4012 pbn_b0_4_1152000 }, 4013 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4015 pbn_b2_bt_1_115200 }, 4016 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4018 pbn_b2_bt_2_115200 }, 4019 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4021 pbn_b2_bt_4_115200 }, 4022 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4024 pbn_b2_bt_2_115200 }, 4025 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4027 pbn_b2_bt_4_115200 }, 4028 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4030 pbn_b2_8_115200 }, 4031 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4033 pbn_b2_8_460800 }, 4034 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4036 pbn_b2_8_115200 }, 4037 4038 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4040 pbn_b2_bt_2_115200 }, 4041 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4043 pbn_b2_bt_2_921600 }, 4044 /* 4045 * VScom SPCOM800, from sl@s.pl 4046 */ 4047 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4049 pbn_b2_8_921600 }, 4050 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4052 pbn_b2_4_921600 }, 4053 /* Unknown card - subdevice 0x1584 */ 4054 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4055 PCI_VENDOR_ID_PLX, 4056 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4057 pbn_b2_4_115200 }, 4058 /* Unknown card - subdevice 0x1588 */ 4059 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4060 PCI_VENDOR_ID_PLX, 4061 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4062 pbn_b2_8_115200 }, 4063 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4064 PCI_SUBVENDOR_ID_KEYSPAN, 4065 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4066 pbn_panacom }, 4067 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4068 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4069 pbn_panacom4 }, 4070 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4071 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4072 pbn_panacom2 }, 4073 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4074 PCI_VENDOR_ID_ESDGMBH, 4075 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4076 pbn_b2_4_115200 }, 4077 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4078 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4079 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4080 pbn_b2_4_460800 }, 4081 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4082 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4083 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4084 pbn_b2_8_460800 }, 4085 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4086 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4087 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4088 pbn_b2_16_460800 }, 4089 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4090 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4091 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4092 pbn_b2_16_460800 }, 4093 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4094 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4095 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4096 pbn_b2_4_460800 }, 4097 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4098 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4099 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4100 pbn_b2_8_460800 }, 4101 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4102 PCI_SUBVENDOR_ID_EXSYS, 4103 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4104 pbn_b2_4_115200 }, 4105 /* 4106 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4107 * (Exoray@isys.ca) 4108 */ 4109 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4110 0x10b5, 0x106a, 0, 0, 4111 pbn_plx_romulus }, 4112 /* 4113 * EndRun Technologies. PCI express device range. 4114 * EndRun PTP/1588 has 2 Native UARTs. 4115 */ 4116 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4118 pbn_endrun_2_3906250 }, 4119 /* 4120 * Quatech cards. These actually have configurable clocks but for 4121 * now we just use the default. 4122 * 4123 * 100 series are RS232, 200 series RS422, 4124 */ 4125 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4127 pbn_b1_4_115200 }, 4128 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4130 pbn_b1_2_115200 }, 4131 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4133 pbn_b2_2_115200 }, 4134 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4136 pbn_b1_2_115200 }, 4137 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4139 pbn_b2_2_115200 }, 4140 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4142 pbn_b1_4_115200 }, 4143 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4145 pbn_b1_8_115200 }, 4146 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4148 pbn_b1_8_115200 }, 4149 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4151 pbn_b1_4_115200 }, 4152 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4154 pbn_b1_2_115200 }, 4155 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4157 pbn_b1_4_115200 }, 4158 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4160 pbn_b1_2_115200 }, 4161 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4163 pbn_b2_4_115200 }, 4164 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4166 pbn_b2_2_115200 }, 4167 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4169 pbn_b2_1_115200 }, 4170 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4172 pbn_b2_4_115200 }, 4173 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4175 pbn_b2_2_115200 }, 4176 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4178 pbn_b2_1_115200 }, 4179 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4181 pbn_b0_8_115200 }, 4182 4183 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4184 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4185 0, 0, 4186 pbn_b0_4_921600 }, 4187 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4188 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4189 0, 0, 4190 pbn_b0_4_1152000 }, 4191 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4193 pbn_b0_bt_2_921600 }, 4194 4195 /* 4196 * The below card is a little controversial since it is the 4197 * subject of a PCI vendor/device ID clash. (See 4198 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4199 * For now just used the hex ID 0x950a. 4200 */ 4201 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4202 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4203 0, 0, pbn_b0_2_115200 }, 4204 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4205 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4206 0, 0, pbn_b0_2_115200 }, 4207 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4209 pbn_b0_2_1130000 }, 4210 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4211 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4212 pbn_b0_1_921600 }, 4213 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4215 pbn_b0_4_115200 }, 4216 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4218 pbn_b0_bt_2_921600 }, 4219 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4221 pbn_b2_8_1152000 }, 4222 4223 /* 4224 * Oxford Semiconductor Inc. Tornado PCI express device range. 4225 */ 4226 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4228 pbn_b0_1_3906250 }, 4229 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4231 pbn_b0_1_3906250 }, 4232 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4234 pbn_oxsemi_1_3906250 }, 4235 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4237 pbn_oxsemi_1_3906250 }, 4238 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4240 pbn_b0_1_3906250 }, 4241 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4243 pbn_b0_1_3906250 }, 4244 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4246 pbn_oxsemi_1_3906250 }, 4247 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4249 pbn_oxsemi_1_3906250 }, 4250 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4252 pbn_b0_1_3906250 }, 4253 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4255 pbn_b0_1_3906250 }, 4256 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4258 pbn_b0_1_3906250 }, 4259 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4261 pbn_b0_1_3906250 }, 4262 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4264 pbn_oxsemi_2_3906250 }, 4265 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4267 pbn_oxsemi_2_3906250 }, 4268 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4270 pbn_oxsemi_4_3906250 }, 4271 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4273 pbn_oxsemi_4_3906250 }, 4274 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4276 pbn_oxsemi_8_3906250 }, 4277 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4279 pbn_oxsemi_8_3906250 }, 4280 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4282 pbn_oxsemi_1_3906250 }, 4283 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4285 pbn_oxsemi_1_3906250 }, 4286 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4288 pbn_oxsemi_1_3906250 }, 4289 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4291 pbn_oxsemi_1_3906250 }, 4292 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4294 pbn_oxsemi_1_3906250 }, 4295 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4297 pbn_oxsemi_1_3906250 }, 4298 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4300 pbn_oxsemi_1_3906250 }, 4301 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4303 pbn_oxsemi_1_3906250 }, 4304 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4306 pbn_oxsemi_1_3906250 }, 4307 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4309 pbn_oxsemi_1_3906250 }, 4310 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4312 pbn_oxsemi_1_3906250 }, 4313 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_oxsemi_1_3906250 }, 4316 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4318 pbn_oxsemi_1_3906250 }, 4319 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4321 pbn_oxsemi_1_3906250 }, 4322 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4324 pbn_oxsemi_1_3906250 }, 4325 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4327 pbn_oxsemi_1_3906250 }, 4328 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4330 pbn_oxsemi_1_3906250 }, 4331 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4333 pbn_oxsemi_1_3906250 }, 4334 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4336 pbn_oxsemi_1_3906250 }, 4337 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4339 pbn_oxsemi_1_3906250 }, 4340 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4342 pbn_oxsemi_1_3906250 }, 4343 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4345 pbn_oxsemi_1_3906250 }, 4346 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4348 pbn_oxsemi_1_3906250 }, 4349 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4351 pbn_oxsemi_1_3906250 }, 4352 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4354 pbn_oxsemi_1_3906250 }, 4355 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4357 pbn_oxsemi_1_3906250 }, 4358 /* 4359 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4360 */ 4361 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4362 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4363 pbn_oxsemi_1_3906250 }, 4364 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4365 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4366 pbn_oxsemi_2_3906250 }, 4367 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4368 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4369 pbn_oxsemi_4_3906250 }, 4370 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4371 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4372 pbn_oxsemi_8_3906250 }, 4373 4374 /* 4375 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4376 */ 4377 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4378 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4379 pbn_oxsemi_2_3906250 }, 4380 4381 /* 4382 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4383 * from skokodyn@yahoo.com 4384 */ 4385 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4386 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4387 pbn_sbsxrsio }, 4388 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4389 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4390 pbn_sbsxrsio }, 4391 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4392 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4393 pbn_sbsxrsio }, 4394 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4395 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4396 pbn_sbsxrsio }, 4397 4398 /* 4399 * Digitan DS560-558, from jimd@esoft.com 4400 */ 4401 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4403 pbn_b1_1_115200 }, 4404 4405 /* 4406 * Titan Electronic cards 4407 * The 400L and 800L have a custom setup quirk. 4408 */ 4409 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4411 pbn_b0_1_921600 }, 4412 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4414 pbn_b0_2_921600 }, 4415 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4417 pbn_b0_4_921600 }, 4418 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4420 pbn_b0_4_921600 }, 4421 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_b1_1_921600 }, 4424 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_b1_bt_2_921600 }, 4427 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_b0_bt_4_921600 }, 4430 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_b0_bt_8_921600 }, 4433 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_b4_bt_2_921600 }, 4436 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_b4_bt_4_921600 }, 4439 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_b4_bt_8_921600 }, 4442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_b0_4_921600 }, 4445 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4447 pbn_b0_4_921600 }, 4448 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4450 pbn_b0_4_921600 }, 4451 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4453 pbn_titan_1_4000000 }, 4454 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_titan_2_4000000 }, 4457 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4459 pbn_titan_4_4000000 }, 4460 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_titan_8_4000000 }, 4463 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_titan_2_4000000 }, 4466 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_titan_2_4000000 }, 4469 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_b0_bt_2_921600 }, 4472 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_b0_4_921600 }, 4475 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_b0_4_921600 }, 4478 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_b0_4_921600 }, 4481 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_b0_4_921600 }, 4484 4485 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_b2_1_460800 }, 4488 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_b2_1_460800 }, 4491 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_b2_1_460800 }, 4494 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4496 pbn_b2_bt_2_921600 }, 4497 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4499 pbn_b2_bt_2_921600 }, 4500 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_b2_bt_2_921600 }, 4503 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_b2_bt_4_921600 }, 4506 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_b2_bt_4_921600 }, 4509 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4511 pbn_b2_bt_4_921600 }, 4512 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_b0_1_921600 }, 4515 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_b0_1_921600 }, 4518 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4520 pbn_b0_1_921600 }, 4521 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_b0_bt_2_921600 }, 4524 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4526 pbn_b0_bt_2_921600 }, 4527 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_b0_bt_2_921600 }, 4530 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4532 pbn_b0_bt_4_921600 }, 4533 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4535 pbn_b0_bt_4_921600 }, 4536 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4538 pbn_b0_bt_4_921600 }, 4539 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4541 pbn_b0_bt_8_921600 }, 4542 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4544 pbn_b0_bt_8_921600 }, 4545 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4547 pbn_b0_bt_8_921600 }, 4548 4549 /* 4550 * Computone devices submitted by Doug McNash dmcnash@computone.com 4551 */ 4552 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4553 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4554 0, 0, pbn_computone_4 }, 4555 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4556 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4557 0, 0, pbn_computone_8 }, 4558 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4559 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4560 0, 0, pbn_computone_6 }, 4561 4562 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_oxsemi }, 4565 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4566 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4567 pbn_b0_bt_1_921600 }, 4568 4569 /* 4570 * Sunix PCI serial boards 4571 */ 4572 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4573 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4574 pbn_sunix_pci_1s }, 4575 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4576 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4577 pbn_sunix_pci_2s }, 4578 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4579 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4580 pbn_sunix_pci_4s }, 4581 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4582 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4583 pbn_sunix_pci_4s }, 4584 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4585 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4586 pbn_sunix_pci_8s }, 4587 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4588 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4589 pbn_sunix_pci_8s }, 4590 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4591 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4592 pbn_sunix_pci_16s }, 4593 4594 /* 4595 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4596 */ 4597 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_b0_bt_8_115200 }, 4600 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_b0_bt_8_115200 }, 4603 4604 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_b0_bt_2_115200 }, 4607 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_b0_bt_2_115200 }, 4610 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_b0_bt_2_115200 }, 4613 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_b0_bt_2_115200 }, 4616 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_b0_bt_2_115200 }, 4619 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_b0_bt_4_460800 }, 4622 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_b0_bt_4_460800 }, 4625 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_b0_bt_2_460800 }, 4628 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_b0_bt_2_460800 }, 4631 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_b0_bt_2_460800 }, 4634 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_b0_bt_1_115200 }, 4637 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_b0_bt_1_460800 }, 4640 4641 /* 4642 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4643 * Cards are identified by their subsystem vendor IDs, which 4644 * (in hex) match the model number. 4645 * 4646 * Note that JC140x are RS422/485 cards which require ox950 4647 * ACR = 0x10, and as such are not currently fully supported. 4648 */ 4649 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4650 0x1204, 0x0004, 0, 0, 4651 pbn_b0_4_921600 }, 4652 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4653 0x1208, 0x0004, 0, 0, 4654 pbn_b0_4_921600 }, 4655 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4656 0x1402, 0x0002, 0, 0, 4657 pbn_b0_2_921600 }, */ 4658 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4659 0x1404, 0x0004, 0, 0, 4660 pbn_b0_4_921600 }, */ 4661 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4662 0x1208, 0x0004, 0, 0, 4663 pbn_b0_4_921600 }, 4664 4665 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4666 0x1204, 0x0004, 0, 0, 4667 pbn_b0_4_921600 }, 4668 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4669 0x1208, 0x0004, 0, 0, 4670 pbn_b0_4_921600 }, 4671 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4672 0x1208, 0x0004, 0, 0, 4673 pbn_b0_4_921600 }, 4674 /* 4675 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4676 */ 4677 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b1_1_1382400 }, 4680 4681 /* 4682 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4683 */ 4684 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_b1_1_1382400 }, 4687 4688 /* 4689 * RAStel 2 port modem, gerg@moreton.com.au 4690 */ 4691 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_b2_bt_2_115200 }, 4694 4695 /* 4696 * EKF addition for i960 Boards form EKF with serial port 4697 */ 4698 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4699 0xE4BF, PCI_ANY_ID, 0, 0, 4700 pbn_intel_i960 }, 4701 4702 /* 4703 * Xircom Cardbus/Ethernet combos 4704 */ 4705 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_b0_1_115200 }, 4708 /* 4709 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4710 */ 4711 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_b0_1_115200 }, 4714 4715 /* 4716 * Untested PCI modems, sent in from various folks... 4717 */ 4718 4719 /* 4720 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4721 */ 4722 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4723 0x1048, 0x1500, 0, 0, 4724 pbn_b1_1_115200 }, 4725 4726 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4727 0xFF00, 0, 0, 0, 4728 pbn_sgi_ioc3 }, 4729 4730 /* 4731 * HP Diva card 4732 */ 4733 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4734 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4735 pbn_b1_1_115200 }, 4736 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_b0_5_115200 }, 4739 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_b2_1_115200 }, 4742 /* HPE PCI serial device */ 4743 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4745 pbn_b1_1_115200 }, 4746 4747 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4749 pbn_b3_2_115200 }, 4750 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4752 pbn_b3_4_115200 }, 4753 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4755 pbn_b3_8_115200 }, 4756 /* 4757 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4758 */ 4759 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_b0_1_115200 }, 4762 /* 4763 * ITE 4764 */ 4765 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4766 PCI_ANY_ID, PCI_ANY_ID, 4767 0, 0, 4768 pbn_b1_bt_1_115200 }, 4769 4770 /* 4771 * IntaShield IS-200 4772 */ 4773 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4775 pbn_b2_2_115200 }, 4776 /* 4777 * IntaShield IS-400 4778 */ 4779 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4781 pbn_b2_4_115200 }, 4782 /* Brainboxes Devices */ 4783 /* 4784 * Brainboxes UC-101 4785 */ 4786 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4787 PCI_ANY_ID, PCI_ANY_ID, 4788 0, 0, 4789 pbn_b2_2_115200 }, 4790 /* 4791 * Brainboxes UC-235/246 4792 */ 4793 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4794 PCI_ANY_ID, PCI_ANY_ID, 4795 0, 0, 4796 pbn_b2_1_115200 }, 4797 /* 4798 * Brainboxes UC-257 4799 */ 4800 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4801 PCI_ANY_ID, PCI_ANY_ID, 4802 0, 0, 4803 pbn_b2_2_115200 }, 4804 /* 4805 * Brainboxes UC-260/271/701/756 4806 */ 4807 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4808 PCI_ANY_ID, PCI_ANY_ID, 4809 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4810 pbn_b2_4_115200 }, 4811 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4812 PCI_ANY_ID, PCI_ANY_ID, 4813 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4814 pbn_b2_4_115200 }, 4815 /* 4816 * Brainboxes UC-268 4817 */ 4818 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 4819 PCI_ANY_ID, PCI_ANY_ID, 4820 0, 0, 4821 pbn_b2_4_115200 }, 4822 /* 4823 * Brainboxes UC-275/279 4824 */ 4825 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 4826 PCI_ANY_ID, PCI_ANY_ID, 4827 0, 0, 4828 pbn_b2_8_115200 }, 4829 /* 4830 * Brainboxes UC-302 4831 */ 4832 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 4833 PCI_ANY_ID, PCI_ANY_ID, 4834 0, 0, 4835 pbn_b2_2_115200 }, 4836 /* 4837 * Brainboxes UC-310 4838 */ 4839 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 4840 PCI_ANY_ID, PCI_ANY_ID, 4841 0, 0, 4842 pbn_b2_2_115200 }, 4843 /* 4844 * Brainboxes UC-313 4845 */ 4846 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 4847 PCI_ANY_ID, PCI_ANY_ID, 4848 0, 0, 4849 pbn_b2_2_115200 }, 4850 /* 4851 * Brainboxes UC-320/324 4852 */ 4853 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 4854 PCI_ANY_ID, PCI_ANY_ID, 4855 0, 0, 4856 pbn_b2_1_115200 }, 4857 /* 4858 * Brainboxes UC-346 4859 */ 4860 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 4861 PCI_ANY_ID, PCI_ANY_ID, 4862 0, 0, 4863 pbn_b2_4_115200 }, 4864 /* 4865 * Brainboxes UC-357 4866 */ 4867 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 4868 PCI_ANY_ID, PCI_ANY_ID, 4869 0, 0, 4870 pbn_b2_2_115200 }, 4871 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 4872 PCI_ANY_ID, PCI_ANY_ID, 4873 0, 0, 4874 pbn_b2_2_115200 }, 4875 /* 4876 * Brainboxes UC-368 4877 */ 4878 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 4879 PCI_ANY_ID, PCI_ANY_ID, 4880 0, 0, 4881 pbn_b2_4_115200 }, 4882 /* 4883 * Brainboxes UC-420/431 4884 */ 4885 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 4886 PCI_ANY_ID, PCI_ANY_ID, 4887 0, 0, 4888 pbn_b2_4_115200 }, 4889 /* 4890 * Perle PCI-RAS cards 4891 */ 4892 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4893 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4894 0, 0, pbn_b2_4_921600 }, 4895 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4896 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4897 0, 0, pbn_b2_8_921600 }, 4898 4899 /* 4900 * Mainpine series cards: Fairly standard layout but fools 4901 * parts of the autodetect in some cases and uses otherwise 4902 * unmatched communications subclasses in the PCI Express case 4903 */ 4904 4905 { /* RockForceDUO */ 4906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4907 PCI_VENDOR_ID_MAINPINE, 0x0200, 4908 0, 0, pbn_b0_2_115200 }, 4909 { /* RockForceQUATRO */ 4910 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4911 PCI_VENDOR_ID_MAINPINE, 0x0300, 4912 0, 0, pbn_b0_4_115200 }, 4913 { /* RockForceDUO+ */ 4914 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4915 PCI_VENDOR_ID_MAINPINE, 0x0400, 4916 0, 0, pbn_b0_2_115200 }, 4917 { /* RockForceQUATRO+ */ 4918 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4919 PCI_VENDOR_ID_MAINPINE, 0x0500, 4920 0, 0, pbn_b0_4_115200 }, 4921 { /* RockForce+ */ 4922 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4923 PCI_VENDOR_ID_MAINPINE, 0x0600, 4924 0, 0, pbn_b0_2_115200 }, 4925 { /* RockForce+ */ 4926 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4927 PCI_VENDOR_ID_MAINPINE, 0x0700, 4928 0, 0, pbn_b0_4_115200 }, 4929 { /* RockForceOCTO+ */ 4930 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4931 PCI_VENDOR_ID_MAINPINE, 0x0800, 4932 0, 0, pbn_b0_8_115200 }, 4933 { /* RockForceDUO+ */ 4934 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4935 PCI_VENDOR_ID_MAINPINE, 0x0C00, 4936 0, 0, pbn_b0_2_115200 }, 4937 { /* RockForceQUARTRO+ */ 4938 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4939 PCI_VENDOR_ID_MAINPINE, 0x0D00, 4940 0, 0, pbn_b0_4_115200 }, 4941 { /* RockForceOCTO+ */ 4942 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4943 PCI_VENDOR_ID_MAINPINE, 0x1D00, 4944 0, 0, pbn_b0_8_115200 }, 4945 { /* RockForceD1 */ 4946 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4947 PCI_VENDOR_ID_MAINPINE, 0x2000, 4948 0, 0, pbn_b0_1_115200 }, 4949 { /* RockForceF1 */ 4950 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4951 PCI_VENDOR_ID_MAINPINE, 0x2100, 4952 0, 0, pbn_b0_1_115200 }, 4953 { /* RockForceD2 */ 4954 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4955 PCI_VENDOR_ID_MAINPINE, 0x2200, 4956 0, 0, pbn_b0_2_115200 }, 4957 { /* RockForceF2 */ 4958 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4959 PCI_VENDOR_ID_MAINPINE, 0x2300, 4960 0, 0, pbn_b0_2_115200 }, 4961 { /* RockForceD4 */ 4962 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4963 PCI_VENDOR_ID_MAINPINE, 0x2400, 4964 0, 0, pbn_b0_4_115200 }, 4965 { /* RockForceF4 */ 4966 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4967 PCI_VENDOR_ID_MAINPINE, 0x2500, 4968 0, 0, pbn_b0_4_115200 }, 4969 { /* RockForceD8 */ 4970 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4971 PCI_VENDOR_ID_MAINPINE, 0x2600, 4972 0, 0, pbn_b0_8_115200 }, 4973 { /* RockForceF8 */ 4974 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4975 PCI_VENDOR_ID_MAINPINE, 0x2700, 4976 0, 0, pbn_b0_8_115200 }, 4977 { /* IQ Express D1 */ 4978 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4979 PCI_VENDOR_ID_MAINPINE, 0x3000, 4980 0, 0, pbn_b0_1_115200 }, 4981 { /* IQ Express F1 */ 4982 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4983 PCI_VENDOR_ID_MAINPINE, 0x3100, 4984 0, 0, pbn_b0_1_115200 }, 4985 { /* IQ Express D2 */ 4986 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4987 PCI_VENDOR_ID_MAINPINE, 0x3200, 4988 0, 0, pbn_b0_2_115200 }, 4989 { /* IQ Express F2 */ 4990 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4991 PCI_VENDOR_ID_MAINPINE, 0x3300, 4992 0, 0, pbn_b0_2_115200 }, 4993 { /* IQ Express D4 */ 4994 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4995 PCI_VENDOR_ID_MAINPINE, 0x3400, 4996 0, 0, pbn_b0_4_115200 }, 4997 { /* IQ Express F4 */ 4998 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4999 PCI_VENDOR_ID_MAINPINE, 0x3500, 5000 0, 0, pbn_b0_4_115200 }, 5001 { /* IQ Express D8 */ 5002 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5003 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5004 0, 0, pbn_b0_8_115200 }, 5005 { /* IQ Express F8 */ 5006 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5007 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5008 0, 0, pbn_b0_8_115200 }, 5009 5010 5011 /* 5012 * PA Semi PA6T-1682M on-chip UART 5013 */ 5014 { PCI_VENDOR_ID_PASEMI, 0xa004, 5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5016 pbn_pasemi_1682M }, 5017 5018 /* 5019 * National Instruments 5020 */ 5021 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5023 pbn_b1_16_115200 }, 5024 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5026 pbn_b1_8_115200 }, 5027 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5029 pbn_b1_bt_4_115200 }, 5030 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5031 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5032 pbn_b1_bt_2_115200 }, 5033 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5035 pbn_b1_bt_4_115200 }, 5036 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5038 pbn_b1_bt_2_115200 }, 5039 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5041 pbn_b1_16_115200 }, 5042 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5044 pbn_b1_8_115200 }, 5045 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5047 pbn_b1_bt_4_115200 }, 5048 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5050 pbn_b1_bt_2_115200 }, 5051 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5053 pbn_b1_bt_4_115200 }, 5054 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5056 pbn_b1_bt_2_115200 }, 5057 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5058 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5059 pbn_ni8430_2 }, 5060 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5062 pbn_ni8430_2 }, 5063 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5065 pbn_ni8430_4 }, 5066 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5067 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5068 pbn_ni8430_4 }, 5069 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5070 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5071 pbn_ni8430_8 }, 5072 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5073 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5074 pbn_ni8430_8 }, 5075 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5076 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5077 pbn_ni8430_16 }, 5078 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5080 pbn_ni8430_16 }, 5081 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5082 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5083 pbn_ni8430_2 }, 5084 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5086 pbn_ni8430_2 }, 5087 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5089 pbn_ni8430_4 }, 5090 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5092 pbn_ni8430_4 }, 5093 5094 /* 5095 * MOXA 5096 */ 5097 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5099 pbn_moxa8250_2p }, 5100 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5102 pbn_moxa8250_2p }, 5103 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5105 pbn_moxa8250_4p }, 5106 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5108 pbn_moxa8250_4p }, 5109 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5111 pbn_moxa8250_8p }, 5112 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5114 pbn_moxa8250_8p }, 5115 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5117 pbn_moxa8250_8p }, 5118 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5120 pbn_moxa8250_8p }, 5121 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5123 pbn_moxa8250_2p }, 5124 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5126 pbn_moxa8250_4p }, 5127 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5129 pbn_moxa8250_8p }, 5130 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5132 pbn_moxa8250_8p }, 5133 5134 /* 5135 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5136 */ 5137 { PCI_VENDOR_ID_ADDIDATA, 5138 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5139 PCI_ANY_ID, 5140 PCI_ANY_ID, 5141 0, 5142 0, 5143 pbn_b0_4_115200 }, 5144 5145 { PCI_VENDOR_ID_ADDIDATA, 5146 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5147 PCI_ANY_ID, 5148 PCI_ANY_ID, 5149 0, 5150 0, 5151 pbn_b0_2_115200 }, 5152 5153 { PCI_VENDOR_ID_ADDIDATA, 5154 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5155 PCI_ANY_ID, 5156 PCI_ANY_ID, 5157 0, 5158 0, 5159 pbn_b0_1_115200 }, 5160 5161 { PCI_VENDOR_ID_AMCC, 5162 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5163 PCI_ANY_ID, 5164 PCI_ANY_ID, 5165 0, 5166 0, 5167 pbn_b1_8_115200 }, 5168 5169 { PCI_VENDOR_ID_ADDIDATA, 5170 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5171 PCI_ANY_ID, 5172 PCI_ANY_ID, 5173 0, 5174 0, 5175 pbn_b0_4_115200 }, 5176 5177 { PCI_VENDOR_ID_ADDIDATA, 5178 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5179 PCI_ANY_ID, 5180 PCI_ANY_ID, 5181 0, 5182 0, 5183 pbn_b0_2_115200 }, 5184 5185 { PCI_VENDOR_ID_ADDIDATA, 5186 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5187 PCI_ANY_ID, 5188 PCI_ANY_ID, 5189 0, 5190 0, 5191 pbn_b0_1_115200 }, 5192 5193 { PCI_VENDOR_ID_ADDIDATA, 5194 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5195 PCI_ANY_ID, 5196 PCI_ANY_ID, 5197 0, 5198 0, 5199 pbn_b0_4_115200 }, 5200 5201 { PCI_VENDOR_ID_ADDIDATA, 5202 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5203 PCI_ANY_ID, 5204 PCI_ANY_ID, 5205 0, 5206 0, 5207 pbn_b0_2_115200 }, 5208 5209 { PCI_VENDOR_ID_ADDIDATA, 5210 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5211 PCI_ANY_ID, 5212 PCI_ANY_ID, 5213 0, 5214 0, 5215 pbn_b0_1_115200 }, 5216 5217 { PCI_VENDOR_ID_ADDIDATA, 5218 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5219 PCI_ANY_ID, 5220 PCI_ANY_ID, 5221 0, 5222 0, 5223 pbn_b0_8_115200 }, 5224 5225 { PCI_VENDOR_ID_ADDIDATA, 5226 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5227 PCI_ANY_ID, 5228 PCI_ANY_ID, 5229 0, 5230 0, 5231 pbn_ADDIDATA_PCIe_4_3906250 }, 5232 5233 { PCI_VENDOR_ID_ADDIDATA, 5234 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5235 PCI_ANY_ID, 5236 PCI_ANY_ID, 5237 0, 5238 0, 5239 pbn_ADDIDATA_PCIe_2_3906250 }, 5240 5241 { PCI_VENDOR_ID_ADDIDATA, 5242 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5243 PCI_ANY_ID, 5244 PCI_ANY_ID, 5245 0, 5246 0, 5247 pbn_ADDIDATA_PCIe_1_3906250 }, 5248 5249 { PCI_VENDOR_ID_ADDIDATA, 5250 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5251 PCI_ANY_ID, 5252 PCI_ANY_ID, 5253 0, 5254 0, 5255 pbn_ADDIDATA_PCIe_8_3906250 }, 5256 5257 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5258 PCI_VENDOR_ID_IBM, 0x0299, 5259 0, 0, pbn_b0_bt_2_115200 }, 5260 5261 /* 5262 * other NetMos 9835 devices are most likely handled by the 5263 * parport_serial driver, check drivers/parport/parport_serial.c 5264 * before adding them here. 5265 */ 5266 5267 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5268 0xA000, 0x1000, 5269 0, 0, pbn_b0_1_115200 }, 5270 5271 /* the 9901 is a rebranded 9912 */ 5272 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5273 0xA000, 0x1000, 5274 0, 0, pbn_b0_1_115200 }, 5275 5276 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5277 0xA000, 0x1000, 5278 0, 0, pbn_b0_1_115200 }, 5279 5280 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5281 0xA000, 0x1000, 5282 0, 0, pbn_b0_1_115200 }, 5283 5284 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5285 0xA000, 0x1000, 5286 0, 0, pbn_b0_1_115200 }, 5287 5288 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5289 0xA000, 0x3002, 5290 0, 0, pbn_NETMOS9900_2s_115200 }, 5291 5292 /* 5293 * Best Connectivity and Rosewill PCI Multi I/O cards 5294 */ 5295 5296 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5297 0xA000, 0x1000, 5298 0, 0, pbn_b0_1_115200 }, 5299 5300 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5301 0xA000, 0x3002, 5302 0, 0, pbn_b0_bt_2_115200 }, 5303 5304 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5305 0xA000, 0x3004, 5306 0, 0, pbn_b0_bt_4_115200 }, 5307 /* Intel CE4100 */ 5308 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5310 pbn_ce4100_1_115200 }, 5311 5312 /* 5313 * Cronyx Omega PCI 5314 */ 5315 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5317 pbn_omegapci }, 5318 5319 /* 5320 * Broadcom TruManage 5321 */ 5322 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5324 pbn_brcm_trumanage }, 5325 5326 /* 5327 * AgeStar as-prs2-009 5328 */ 5329 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5330 PCI_ANY_ID, PCI_ANY_ID, 5331 0, 0, pbn_b0_bt_2_115200 }, 5332 5333 /* 5334 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5335 * so not listed here. 5336 */ 5337 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5338 PCI_ANY_ID, PCI_ANY_ID, 5339 0, 0, pbn_b0_bt_4_115200 }, 5340 5341 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5342 PCI_ANY_ID, PCI_ANY_ID, 5343 0, 0, pbn_b0_bt_2_115200 }, 5344 5345 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5346 PCI_ANY_ID, PCI_ANY_ID, 5347 0, 0, pbn_b0_bt_4_115200 }, 5348 5349 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5350 PCI_ANY_ID, PCI_ANY_ID, 5351 0, 0, pbn_wch382_2 }, 5352 5353 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5354 PCI_ANY_ID, PCI_ANY_ID, 5355 0, 0, pbn_wch384_4 }, 5356 5357 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5358 PCI_ANY_ID, PCI_ANY_ID, 5359 0, 0, pbn_wch384_8 }, 5360 /* 5361 * Realtek RealManage 5362 */ 5363 { PCI_VENDOR_ID_REALTEK, 0x816a, 5364 PCI_ANY_ID, PCI_ANY_ID, 5365 0, 0, pbn_b0_1_115200 }, 5366 5367 { PCI_VENDOR_ID_REALTEK, 0x816b, 5368 PCI_ANY_ID, PCI_ANY_ID, 5369 0, 0, pbn_b0_1_115200 }, 5370 5371 /* Fintek PCI serial cards */ 5372 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5373 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5374 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5375 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5376 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5377 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5378 5379 /* MKS Tenta SCOM-080x serial cards */ 5380 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5381 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5382 5383 /* Amazon PCI serial device */ 5384 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5385 5386 /* 5387 * These entries match devices with class COMMUNICATION_SERIAL, 5388 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5389 */ 5390 { PCI_ANY_ID, PCI_ANY_ID, 5391 PCI_ANY_ID, PCI_ANY_ID, 5392 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5393 0xffff00, pbn_default }, 5394 { PCI_ANY_ID, PCI_ANY_ID, 5395 PCI_ANY_ID, PCI_ANY_ID, 5396 PCI_CLASS_COMMUNICATION_MODEM << 8, 5397 0xffff00, pbn_default }, 5398 { PCI_ANY_ID, PCI_ANY_ID, 5399 PCI_ANY_ID, PCI_ANY_ID, 5400 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5401 0xffff00, pbn_default }, 5402 { 0, } 5403 }; 5404 5405 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5406 pci_channel_state_t state) 5407 { 5408 struct serial_private *priv = pci_get_drvdata(dev); 5409 5410 if (state == pci_channel_io_perm_failure) 5411 return PCI_ERS_RESULT_DISCONNECT; 5412 5413 if (priv) 5414 pciserial_detach_ports(priv); 5415 5416 pci_disable_device(dev); 5417 5418 return PCI_ERS_RESULT_NEED_RESET; 5419 } 5420 5421 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5422 { 5423 int rc; 5424 5425 rc = pci_enable_device(dev); 5426 5427 if (rc) 5428 return PCI_ERS_RESULT_DISCONNECT; 5429 5430 pci_restore_state(dev); 5431 pci_save_state(dev); 5432 5433 return PCI_ERS_RESULT_RECOVERED; 5434 } 5435 5436 static void serial8250_io_resume(struct pci_dev *dev) 5437 { 5438 struct serial_private *priv = pci_get_drvdata(dev); 5439 struct serial_private *new; 5440 5441 if (!priv) 5442 return; 5443 5444 new = pciserial_init_ports(dev, priv->board); 5445 if (!IS_ERR(new)) { 5446 pci_set_drvdata(dev, new); 5447 kfree(priv); 5448 } 5449 } 5450 5451 static const struct pci_error_handlers serial8250_err_handler = { 5452 .error_detected = serial8250_io_error_detected, 5453 .slot_reset = serial8250_io_slot_reset, 5454 .resume = serial8250_io_resume, 5455 }; 5456 5457 static struct pci_driver serial_pci_driver = { 5458 .name = "serial", 5459 .probe = pciserial_init_one, 5460 .remove = pciserial_remove_one, 5461 .driver = { 5462 .pm = &pciserial_pm_ops, 5463 }, 5464 .id_table = serial_pci_tbl, 5465 .err_handler = &serial8250_err_handler, 5466 }; 5467 5468 module_pci_driver(serial_pci_driver); 5469 5470 MODULE_LICENSE("GPL"); 5471 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5472 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5473