1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/circ_buf.h>
12 #include <linux/module.h>
13 #include <linux/ioport.h>
14 #include <linux/init.h>
15 #include <linux/console.h>
16 #include <linux/sysrq.h>
17 #include <linux/platform_device.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/ktime.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/rational.h>
27 #include <linux/slab.h>
28 #include <linux/of.h>
29 #include <linux/io.h>
30 #include <linux/iopoll.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/irq.h>
34 #include <linux/dma/imx-dma.h>
35
36 #include "serial_mctrl_gpio.h"
37
38 /* Register definitions */
39 #define URXD0 0x0 /* Receiver Register */
40 #define URTX0 0x40 /* Transmitter Register */
41 #define UCR1 0x80 /* Control Register 1 */
42 #define UCR2 0x84 /* Control Register 2 */
43 #define UCR3 0x88 /* Control Register 3 */
44 #define UCR4 0x8c /* Control Register 4 */
45 #define UFCR 0x90 /* FIFO Control Register */
46 #define USR1 0x94 /* Status Register 1 */
47 #define USR2 0x98 /* Status Register 2 */
48 #define UESC 0x9c /* Escape Character Register */
49 #define UTIM 0xa0 /* Escape Timer Register */
50 #define UBIR 0xa4 /* BRM Incremental Register */
51 #define UBMR 0xa8 /* BRM Modulator Register */
52 #define UBRC 0xac /* Baud Rate Count Register */
53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57 /* UART Control Register Bit Fields.*/
58 #define URXD_DUMMY_READ (1<<16)
59 #define URXD_CHARRDY (1<<15)
60 #define URXD_ERR (1<<14)
61 #define URXD_OVRRUN (1<<13)
62 #define URXD_FRMERR (1<<12)
63 #define URXD_BRK (1<<11)
64 #define URXD_PRERR (1<<10)
65 #define URXD_RX_DATA (0xFF<<0)
66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73 #define UCR1_IREN (1<<7) /* Infrared interface enable */
74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76 #define UCR1_SNDBRK (1<<4) /* Send break */
77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80 #define UCR1_DOZE (1<<1) /* Doze */
81 #define UCR1_UARTEN (1<<0) /* UART enabled */
82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84 #define UCR2_CTSC (1<<13) /* CTS pin control */
85 #define UCR2_CTS (1<<12) /* Clear to send */
86 #define UCR2_ESCEN (1<<11) /* Escape enable */
87 #define UCR2_PREN (1<<8) /* Parity enable */
88 #define UCR2_PROE (1<<7) /* Parity odd/even */
89 #define UCR2_STPB (1<<6) /* Stop */
90 #define UCR2_WS (1<<5) /* Word size */
91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
94 #define UCR2_RXEN (1<<1) /* Receiver enabled */
95 #define UCR2_SRST (1<<0) /* SW reset */
96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97 #define UCR3_PARERREN (1<<12) /* Parity enable */
98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99 #define UCR3_DSR (1<<10) /* Data set ready */
100 #define UCR3_DCD (1<<9) /* Data carrier detect */
101 #define UCR3_RI (1<<8) /* Ring indicator */
102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR3_BPEN (1<<0) /* Preset registers enable */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117 #define UCR4_IRSC (1<<5) /* IR special case */
118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
124 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
127 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
128 #define USR1_RTSS (1<<14) /* RTS pin status */
129 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
130 #define USR1_RTSD (1<<12) /* RTS delta */
131 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
132 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
133 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
134 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
135 #define USR1_DTRD (1<<7) /* DTR Delta */
136 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
137 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
138 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
139 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
140 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
141 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
142 #define USR2_IDLE (1<<12) /* Idle condition */
143 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
144 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
145 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
146 #define USR2_WAKE (1<<7) /* Wake */
147 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
148 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
149 #define USR2_TXDC (1<<3) /* Transmitter complete */
150 #define USR2_BRCD (1<<2) /* Break condition */
151 #define USR2_ORE (1<<1) /* Overrun error */
152 #define USR2_RDR (1<<0) /* Recv data ready */
153 #define UTS_FRCPERR (1<<13) /* Force parity error */
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
155 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
156 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
157 #define UTS_TXFULL (1<<4) /* TxFIFO full */
158 #define UTS_RXFULL (1<<3) /* RxFIFO full */
159 #define UTS_SOFTRST (1<<0) /* Software reset */
160
161 /* We've been assigned a range on the "Low-density serial ports" major */
162 #define SERIAL_IMX_MAJOR 207
163 #define MINOR_START 16
164 #define DEV_NAME "ttymxc"
165
166 /*
167 * This determines how often we check the modem status signals
168 * for any change. They generally aren't connected to an IRQ
169 * so we have to poll them. We also check immediately before
170 * filling the TX fifo incase CTS has been dropped.
171 */
172 #define MCTRL_TIMEOUT (250*HZ/1000)
173
174 #define DRIVER_NAME "IMX-uart"
175
176 #define UART_NR 8
177
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
179 enum imx_uart_type {
180 IMX1_UART,
181 IMX21_UART,
182 };
183
184 /* device type dependent stuff */
185 struct imx_uart_data {
186 unsigned uts_reg;
187 enum imx_uart_type devtype;
188 };
189
190 enum imx_tx_state {
191 OFF,
192 WAIT_AFTER_RTS,
193 SEND,
194 WAIT_AFTER_SEND,
195 };
196
197 struct imx_port {
198 struct uart_port port;
199 struct timer_list timer;
200 unsigned int old_status;
201 unsigned int have_rtscts:1;
202 unsigned int have_rtsgpio:1;
203 unsigned int dte_mode:1;
204 unsigned int inverted_tx:1;
205 unsigned int inverted_rx:1;
206 struct clk *clk_ipg;
207 struct clk *clk_per;
208 const struct imx_uart_data *devdata;
209
210 struct mctrl_gpios *gpios;
211
212 /* counter to stop 0xff flood */
213 int idle_counter;
214
215 /* DMA fields */
216 unsigned int dma_is_enabled:1;
217 unsigned int dma_is_rxing:1;
218 unsigned int dma_is_txing:1;
219 struct dma_chan *dma_chan_rx, *dma_chan_tx;
220 struct scatterlist rx_sgl, tx_sgl[2];
221 void *rx_buf;
222 struct circ_buf rx_ring;
223 unsigned int rx_buf_size;
224 unsigned int rx_period_length;
225 unsigned int rx_periods;
226 dma_cookie_t rx_cookie;
227 unsigned int tx_bytes;
228 unsigned int dma_tx_nents;
229 unsigned int saved_reg[10];
230 bool context_saved;
231
232 enum imx_tx_state tx_state;
233 struct hrtimer trigger_start_tx;
234 struct hrtimer trigger_stop_tx;
235 };
236
237 struct imx_port_ucrs {
238 unsigned int ucr1;
239 unsigned int ucr2;
240 unsigned int ucr3;
241 };
242
243 static const struct imx_uart_data imx_uart_imx1_devdata = {
244 .uts_reg = IMX1_UTS,
245 .devtype = IMX1_UART,
246 };
247
248 static const struct imx_uart_data imx_uart_imx21_devdata = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 };
252
253 static const struct of_device_id imx_uart_dt_ids[] = {
254 /*
255 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
256 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
257 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
258 * doesn't make any distinction between these two variants.
259 */
260 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
261 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
262 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
263 { /* sentinel */ }
264 };
265 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
266
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)267 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
268 {
269 writel(val, sport->port.membase + offset);
270 }
271
imx_uart_readl(struct imx_port * sport,u32 offset)272 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
273 {
274 return readl(sport->port.membase + offset);
275 }
276
imx_uart_uts_reg(struct imx_port * sport)277 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
278 {
279 return sport->devdata->uts_reg;
280 }
281
imx_uart_is_imx1(struct imx_port * sport)282 static inline int imx_uart_is_imx1(struct imx_port *sport)
283 {
284 return sport->devdata->devtype == IMX1_UART;
285 }
286
287 /*
288 * Save and restore functions for UCR1, UCR2 and UCR3 registers
289 */
290 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)291 static void imx_uart_ucrs_save(struct imx_port *sport,
292 struct imx_port_ucrs *ucr)
293 {
294 /* save control registers */
295 ucr->ucr1 = imx_uart_readl(sport, UCR1);
296 ucr->ucr2 = imx_uart_readl(sport, UCR2);
297 ucr->ucr3 = imx_uart_readl(sport, UCR3);
298 }
299
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)300 static void imx_uart_ucrs_restore(struct imx_port *sport,
301 struct imx_port_ucrs *ucr)
302 {
303 /* restore control registers */
304 imx_uart_writel(sport, ucr->ucr1, UCR1);
305 imx_uart_writel(sport, ucr->ucr2, UCR2);
306 imx_uart_writel(sport, ucr->ucr3, UCR3);
307 }
308 #endif
309
310 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)311 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
312 {
313 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
314
315 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
316 }
317
318 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)319 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
320 {
321 *ucr2 &= ~UCR2_CTSC;
322 *ucr2 |= UCR2_CTS;
323
324 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
325 }
326
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)327 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
328 {
329 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
330 }
331
332 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)333 static void imx_uart_soft_reset(struct imx_port *sport)
334 {
335 int i = 10;
336 u32 ucr2, ubir, ubmr, uts;
337
338 /*
339 * According to the Reference Manual description of the UART SRST bit:
340 *
341 * "Reset the transmit and receive state machines,
342 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
343 * and UTS[6-3]".
344 *
345 * We don't need to restore the old values from USR1, USR2, URXD and
346 * UTXD. UBRC is read only, so only save/restore the other three
347 * registers.
348 */
349 ubir = imx_uart_readl(sport, UBIR);
350 ubmr = imx_uart_readl(sport, UBMR);
351 uts = imx_uart_readl(sport, IMX21_UTS);
352
353 ucr2 = imx_uart_readl(sport, UCR2);
354 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
355
356 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
357 udelay(1);
358
359 /* Restore the registers */
360 imx_uart_writel(sport, ubir, UBIR);
361 imx_uart_writel(sport, ubmr, UBMR);
362 imx_uart_writel(sport, uts, IMX21_UTS);
363
364 sport->idle_counter = 0;
365 }
366
imx_uart_disable_loopback_rs485(struct imx_port * sport)367 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
368 {
369 unsigned int uts;
370
371 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
372 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
373 uts &= ~UTS_LOOP;
374 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
375 }
376
377 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)378 static void imx_uart_start_rx(struct uart_port *port)
379 {
380 struct imx_port *sport = (struct imx_port *)port;
381 unsigned int ucr1, ucr2;
382
383 ucr1 = imx_uart_readl(sport, UCR1);
384 ucr2 = imx_uart_readl(sport, UCR2);
385
386 ucr2 |= UCR2_RXEN;
387
388 if (sport->dma_is_enabled) {
389 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
390 } else {
391 ucr1 |= UCR1_RRDYEN;
392 ucr2 |= UCR2_ATEN;
393 }
394
395 /* Write UCR2 first as it includes RXEN */
396 imx_uart_writel(sport, ucr2, UCR2);
397 imx_uart_writel(sport, ucr1, UCR1);
398 imx_uart_disable_loopback_rs485(sport);
399 }
400
401 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)402 static void imx_uart_stop_tx(struct uart_port *port)
403 {
404 struct imx_port *sport = (struct imx_port *)port;
405 u32 ucr1, ucr4, usr2;
406
407 if (sport->tx_state == OFF)
408 return;
409
410 /*
411 * We are maybe in the SMP context, so if the DMA TX thread is running
412 * on other cpu, we have to wait for it to finish.
413 */
414 if (sport->dma_is_txing)
415 return;
416
417 ucr1 = imx_uart_readl(sport, UCR1);
418 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
419
420 ucr4 = imx_uart_readl(sport, UCR4);
421 usr2 = imx_uart_readl(sport, USR2);
422 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
423 /* The shifter is still busy, so retry once TC triggers */
424 return;
425 }
426
427 ucr4 &= ~UCR4_TCEN;
428 imx_uart_writel(sport, ucr4, UCR4);
429
430 /* in rs485 mode disable transmitter */
431 if (port->rs485.flags & SER_RS485_ENABLED) {
432 if (sport->tx_state == SEND) {
433 sport->tx_state = WAIT_AFTER_SEND;
434
435 if (port->rs485.delay_rts_after_send > 0) {
436 start_hrtimer_ms(&sport->trigger_stop_tx,
437 port->rs485.delay_rts_after_send);
438 return;
439 }
440
441 /* continue without any delay */
442 }
443
444 if (sport->tx_state == WAIT_AFTER_RTS ||
445 sport->tx_state == WAIT_AFTER_SEND) {
446 u32 ucr2;
447
448 hrtimer_try_to_cancel(&sport->trigger_start_tx);
449
450 ucr2 = imx_uart_readl(sport, UCR2);
451 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
452 imx_uart_rts_active(sport, &ucr2);
453 else
454 imx_uart_rts_inactive(sport, &ucr2);
455 imx_uart_writel(sport, ucr2, UCR2);
456
457 if (!port->rs485_rx_during_tx_gpio)
458 imx_uart_start_rx(port);
459
460 sport->tx_state = OFF;
461 }
462 } else {
463 sport->tx_state = OFF;
464 }
465 }
466
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)467 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
468 {
469 struct imx_port *sport = (struct imx_port *)port;
470 u32 ucr1, ucr2, ucr4, uts;
471
472 ucr1 = imx_uart_readl(sport, UCR1);
473 ucr2 = imx_uart_readl(sport, UCR2);
474 ucr4 = imx_uart_readl(sport, UCR4);
475
476 if (sport->dma_is_enabled) {
477 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
478 } else {
479 ucr1 &= ~UCR1_RRDYEN;
480 ucr2 &= ~UCR2_ATEN;
481 ucr4 &= ~UCR4_OREN;
482 }
483 imx_uart_writel(sport, ucr1, UCR1);
484 imx_uart_writel(sport, ucr4, UCR4);
485
486 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
487 if (port->rs485.flags & SER_RS485_ENABLED &&
488 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
489 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
490 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
491 uts |= UTS_LOOP;
492 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
493 ucr2 |= UCR2_RXEN;
494 } else {
495 ucr2 &= ~UCR2_RXEN;
496 }
497
498 imx_uart_writel(sport, ucr2, UCR2);
499 }
500
501 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)502 static void imx_uart_stop_rx(struct uart_port *port)
503 {
504 /*
505 * Stop RX and enable loopback in order to make sure RS485 bus
506 * is not blocked. Se comment in imx_uart_probe().
507 */
508 imx_uart_stop_rx_with_loopback_ctrl(port, true);
509 }
510
511 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)512 static void imx_uart_enable_ms(struct uart_port *port)
513 {
514 struct imx_port *sport = (struct imx_port *)port;
515
516 mod_timer(&sport->timer, jiffies);
517
518 mctrl_gpio_enable_ms(sport->gpios);
519 }
520
521 static void imx_uart_dma_tx(struct imx_port *sport);
522
523 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)524 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
525 {
526 struct tty_port *tport = &sport->port.state->port;
527 unsigned char c;
528
529 if (sport->port.x_char) {
530 /* Send next char */
531 imx_uart_writel(sport, sport->port.x_char, URTX0);
532 sport->port.icount.tx++;
533 sport->port.x_char = 0;
534 return;
535 }
536
537 if (kfifo_is_empty(&tport->xmit_fifo) ||
538 uart_tx_stopped(&sport->port)) {
539 imx_uart_stop_tx(&sport->port);
540 return;
541 }
542
543 if (sport->dma_is_enabled) {
544 u32 ucr1;
545 /*
546 * We've just sent a X-char Ensure the TX DMA is enabled
547 * and the TX IRQ is disabled.
548 **/
549 ucr1 = imx_uart_readl(sport, UCR1);
550 ucr1 &= ~UCR1_TRDYEN;
551 if (sport->dma_is_txing) {
552 ucr1 |= UCR1_TXDMAEN;
553 imx_uart_writel(sport, ucr1, UCR1);
554 } else {
555 imx_uart_writel(sport, ucr1, UCR1);
556 imx_uart_dma_tx(sport);
557 }
558
559 return;
560 }
561
562 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
563 uart_fifo_get(&sport->port, &c))
564 imx_uart_writel(sport, c, URTX0);
565
566 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
567 uart_write_wakeup(&sport->port);
568
569 if (kfifo_is_empty(&tport->xmit_fifo))
570 imx_uart_stop_tx(&sport->port);
571 }
572
imx_uart_dma_tx_callback(void * data)573 static void imx_uart_dma_tx_callback(void *data)
574 {
575 struct imx_port *sport = data;
576 struct tty_port *tport = &sport->port.state->port;
577 struct scatterlist *sgl = &sport->tx_sgl[0];
578 unsigned long flags;
579 u32 ucr1;
580
581 uart_port_lock_irqsave(&sport->port, &flags);
582
583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
584
585 ucr1 = imx_uart_readl(sport, UCR1);
586 ucr1 &= ~UCR1_TXDMAEN;
587 imx_uart_writel(sport, ucr1, UCR1);
588
589 uart_xmit_advance(&sport->port, sport->tx_bytes);
590
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
592
593 sport->dma_is_txing = 0;
594
595 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
596 uart_write_wakeup(&sport->port);
597
598 if (!kfifo_is_empty(&tport->xmit_fifo) &&
599 !uart_tx_stopped(&sport->port))
600 imx_uart_dma_tx(sport);
601 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
602 u32 ucr4 = imx_uart_readl(sport, UCR4);
603 ucr4 |= UCR4_TCEN;
604 imx_uart_writel(sport, ucr4, UCR4);
605 }
606
607 uart_port_unlock_irqrestore(&sport->port, flags);
608 }
609
610 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)611 static void imx_uart_dma_tx(struct imx_port *sport)
612 {
613 struct tty_port *tport = &sport->port.state->port;
614 struct scatterlist *sgl = sport->tx_sgl;
615 struct dma_async_tx_descriptor *desc;
616 struct dma_chan *chan = sport->dma_chan_tx;
617 struct device *dev = sport->port.dev;
618 u32 ucr1, ucr4;
619 int ret;
620
621 if (sport->dma_is_txing)
622 return;
623
624 ucr4 = imx_uart_readl(sport, UCR4);
625 ucr4 &= ~UCR4_TCEN;
626 imx_uart_writel(sport, ucr4, UCR4);
627
628 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
629 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
630 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
631 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
632
633 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
634 if (ret == 0) {
635 dev_err(dev, "DMA mapping error for TX.\n");
636 return;
637 }
638 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
639 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
640 if (!desc) {
641 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
642 DMA_TO_DEVICE);
643 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
644 return;
645 }
646 desc->callback = imx_uart_dma_tx_callback;
647 desc->callback_param = sport;
648
649 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
650
651 ucr1 = imx_uart_readl(sport, UCR1);
652 ucr1 |= UCR1_TXDMAEN;
653 imx_uart_writel(sport, ucr1, UCR1);
654
655 /* fire it */
656 sport->dma_is_txing = 1;
657 dmaengine_submit(desc);
658 dma_async_issue_pending(chan);
659 return;
660 }
661
662 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)663 static void imx_uart_start_tx(struct uart_port *port)
664 {
665 struct imx_port *sport = (struct imx_port *)port;
666 struct tty_port *tport = &sport->port.state->port;
667 u32 ucr1;
668
669 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
670 return;
671
672 /*
673 * We cannot simply do nothing here if sport->tx_state == SEND already
674 * because UCR1_TXMPTYEN might already have been cleared in
675 * imx_uart_stop_tx(), but tx_state is still SEND.
676 */
677
678 if (port->rs485.flags & SER_RS485_ENABLED) {
679 if (sport->tx_state == OFF) {
680 u32 ucr2 = imx_uart_readl(sport, UCR2);
681 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
682 imx_uart_rts_active(sport, &ucr2);
683 else
684 imx_uart_rts_inactive(sport, &ucr2);
685 imx_uart_writel(sport, ucr2, UCR2);
686
687 /*
688 * Since we are about to transmit we can not stop RX
689 * with loopback enabled because that will make our
690 * transmitted data being just looped to RX.
691 */
692 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
693 !port->rs485_rx_during_tx_gpio)
694 imx_uart_stop_rx_with_loopback_ctrl(port, false);
695
696 sport->tx_state = WAIT_AFTER_RTS;
697
698 if (port->rs485.delay_rts_before_send > 0) {
699 start_hrtimer_ms(&sport->trigger_start_tx,
700 port->rs485.delay_rts_before_send);
701 return;
702 }
703
704 /* continue without any delay */
705 }
706
707 if (sport->tx_state == WAIT_AFTER_SEND
708 || sport->tx_state == WAIT_AFTER_RTS) {
709
710 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
711
712 /*
713 * Enable transmitter and shifter empty irq only if DMA
714 * is off. In the DMA case this is done in the
715 * tx-callback.
716 */
717 if (!sport->dma_is_enabled) {
718 u32 ucr4 = imx_uart_readl(sport, UCR4);
719 ucr4 |= UCR4_TCEN;
720 imx_uart_writel(sport, ucr4, UCR4);
721 }
722
723 sport->tx_state = SEND;
724 }
725 } else {
726 sport->tx_state = SEND;
727 }
728
729 if (!sport->dma_is_enabled) {
730 ucr1 = imx_uart_readl(sport, UCR1);
731 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
732 }
733
734 if (sport->dma_is_enabled) {
735 if (sport->port.x_char) {
736 /* We have X-char to send, so enable TX IRQ and
737 * disable TX DMA to let TX interrupt to send X-char */
738 ucr1 = imx_uart_readl(sport, UCR1);
739 ucr1 &= ~UCR1_TXDMAEN;
740 ucr1 |= UCR1_TRDYEN;
741 imx_uart_writel(sport, ucr1, UCR1);
742 return;
743 }
744
745 if (!kfifo_is_empty(&tport->xmit_fifo) &&
746 !uart_tx_stopped(port))
747 imx_uart_dma_tx(sport);
748 return;
749 }
750 }
751
__imx_uart_rtsint(int irq,void * dev_id)752 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
753 {
754 struct imx_port *sport = dev_id;
755 u32 usr1;
756
757 imx_uart_writel(sport, USR1_RTSD, USR1);
758 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
759 uart_handle_cts_change(&sport->port, usr1);
760 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
761
762 return IRQ_HANDLED;
763 }
764
imx_uart_rtsint(int irq,void * dev_id)765 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
766 {
767 struct imx_port *sport = dev_id;
768 irqreturn_t ret;
769
770 uart_port_lock(&sport->port);
771
772 ret = __imx_uart_rtsint(irq, dev_id);
773
774 uart_port_unlock(&sport->port);
775
776 return ret;
777 }
778
imx_uart_txint(int irq,void * dev_id)779 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
780 {
781 struct imx_port *sport = dev_id;
782
783 uart_port_lock(&sport->port);
784 imx_uart_transmit_buffer(sport);
785 uart_port_unlock(&sport->port);
786 return IRQ_HANDLED;
787 }
788
789 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
790 * This is to be called from Rx ISRs only when some bytes were actually
791 * received.
792 *
793 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
794 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
795 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
796 * that is terminated by any activity on RxD line, or could be stopped by
797 * issuing soft reset to the UART (just stop/start of RX does not help). Note
798 * that what we do here is sending isolated start bit about 2.4 times shorter
799 * than it is to be on UART configured baud rate.
800 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)801 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
802 {
803 /* To detect hardware 0xff flood we monitor RxD line between RX
804 * interrupts to isolate "receiving" of char(s) with no activity
805 * on RxD line, that'd never happen on actual data transfers.
806 *
807 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
808 * race here if we clear USR2_WAKE when receiving of a char is in
809 * progress, so we might get RX interrupt later with USR2_WAKE bit
810 * cleared. Note though that as we don't try to clear USR2_WAKE when we
811 * detected no activity, this race may hide actual activity only once.
812 *
813 * Yet another case where receive interrupt may occur without RxD
814 * activity is expiration of aging timer, so we consider this as well.
815 *
816 * We use 'idle_counter' to ensure that we got at least so many RX
817 * interrupts without any detected activity on RxD line. 2 cases
818 * described plus 1 to be on the safe side gives us a margin of 3,
819 * below. In practice I was not able to produce a false positive to
820 * induce soft reset at regular data transfers even using 1 as the
821 * margin, so 3 is actually very strong.
822 *
823 * We count interrupts, not chars in 'idle-counter' for simplicity.
824 */
825
826 if (usr2 & USR2_WAKE) {
827 imx_uart_writel(sport, USR2_WAKE, USR2);
828 sport->idle_counter = 0;
829 } else if (++sport->idle_counter > 3) {
830 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
831 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
832 }
833 }
834
__imx_uart_rxint(int irq,void * dev_id)835 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
836 {
837 struct imx_port *sport = dev_id;
838 struct tty_port *port = &sport->port.state->port;
839 u32 usr2, rx;
840
841 /* If we received something, check for 0xff flood */
842 usr2 = imx_uart_readl(sport, USR2);
843 if (usr2 & USR2_RDR)
844 imx_uart_check_flood(sport, usr2);
845
846 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
847 unsigned int flg = TTY_NORMAL;
848 sport->port.icount.rx++;
849
850 if (unlikely(rx & URXD_ERR)) {
851 if (rx & URXD_BRK) {
852 sport->port.icount.brk++;
853 if (uart_handle_break(&sport->port))
854 continue;
855 }
856 else if (rx & URXD_PRERR)
857 sport->port.icount.parity++;
858 else if (rx & URXD_FRMERR)
859 sport->port.icount.frame++;
860 if (rx & URXD_OVRRUN)
861 sport->port.icount.overrun++;
862
863 if (rx & sport->port.ignore_status_mask)
864 continue;
865
866 rx &= (sport->port.read_status_mask | 0xFF);
867
868 if (rx & URXD_BRK)
869 flg = TTY_BREAK;
870 else if (rx & URXD_PRERR)
871 flg = TTY_PARITY;
872 else if (rx & URXD_FRMERR)
873 flg = TTY_FRAME;
874 if (rx & URXD_OVRRUN)
875 flg = TTY_OVERRUN;
876
877 sport->port.sysrq = 0;
878 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
879 continue;
880 }
881
882 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
883 continue;
884
885 if (tty_insert_flip_char(port, rx, flg) == 0)
886 sport->port.icount.buf_overrun++;
887 }
888
889 tty_flip_buffer_push(port);
890
891 return IRQ_HANDLED;
892 }
893
imx_uart_rxint(int irq,void * dev_id)894 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
895 {
896 struct imx_port *sport = dev_id;
897 irqreturn_t ret;
898
899 uart_port_lock(&sport->port);
900
901 ret = __imx_uart_rxint(irq, dev_id);
902
903 uart_port_unlock(&sport->port);
904
905 return ret;
906 }
907
908 static void imx_uart_clear_rx_errors(struct imx_port *sport);
909
910 /*
911 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
912 */
imx_uart_get_hwmctrl(struct imx_port * sport)913 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
914 {
915 unsigned int tmp = TIOCM_DSR;
916 unsigned usr1 = imx_uart_readl(sport, USR1);
917 unsigned usr2 = imx_uart_readl(sport, USR2);
918
919 if (usr1 & USR1_RTSS)
920 tmp |= TIOCM_CTS;
921
922 /* in DCE mode DCDIN is always 0 */
923 if (!(usr2 & USR2_DCDIN))
924 tmp |= TIOCM_CAR;
925
926 if (sport->dte_mode)
927 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
928 tmp |= TIOCM_RI;
929
930 return tmp;
931 }
932
933 /*
934 * Handle any change of modem status signal since we were last called.
935 */
imx_uart_mctrl_check(struct imx_port * sport)936 static void imx_uart_mctrl_check(struct imx_port *sport)
937 {
938 unsigned int status, changed;
939
940 status = imx_uart_get_hwmctrl(sport);
941 changed = status ^ sport->old_status;
942
943 if (changed == 0)
944 return;
945
946 sport->old_status = status;
947
948 if (changed & TIOCM_RI && status & TIOCM_RI)
949 sport->port.icount.rng++;
950 if (changed & TIOCM_DSR)
951 sport->port.icount.dsr++;
952 if (changed & TIOCM_CAR)
953 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
954 if (changed & TIOCM_CTS)
955 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
956
957 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
958 }
959
imx_uart_int(int irq,void * dev_id)960 static irqreturn_t imx_uart_int(int irq, void *dev_id)
961 {
962 struct imx_port *sport = dev_id;
963 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
964 irqreturn_t ret = IRQ_NONE;
965
966 uart_port_lock(&sport->port);
967
968 usr1 = imx_uart_readl(sport, USR1);
969 usr2 = imx_uart_readl(sport, USR2);
970 ucr1 = imx_uart_readl(sport, UCR1);
971 ucr2 = imx_uart_readl(sport, UCR2);
972 ucr3 = imx_uart_readl(sport, UCR3);
973 ucr4 = imx_uart_readl(sport, UCR4);
974
975 /*
976 * Even if a condition is true that can trigger an irq only handle it if
977 * the respective irq source is enabled. This prevents some undesired
978 * actions, for example if a character that sits in the RX FIFO and that
979 * should be fetched via DMA is tried to be fetched using PIO. Or the
980 * receiver is currently off and so reading from URXD0 results in an
981 * exception. So just mask the (raw) status bits for disabled irqs.
982 */
983 if ((ucr1 & UCR1_RRDYEN) == 0)
984 usr1 &= ~USR1_RRDY;
985 if ((ucr2 & UCR2_ATEN) == 0)
986 usr1 &= ~USR1_AGTIM;
987 if ((ucr1 & UCR1_TRDYEN) == 0)
988 usr1 &= ~USR1_TRDY;
989 if ((ucr4 & UCR4_TCEN) == 0)
990 usr2 &= ~USR2_TXDC;
991 if ((ucr3 & UCR3_DTRDEN) == 0)
992 usr1 &= ~USR1_DTRD;
993 if ((ucr1 & UCR1_RTSDEN) == 0)
994 usr1 &= ~USR1_RTSD;
995 if ((ucr3 & UCR3_AWAKEN) == 0)
996 usr1 &= ~USR1_AWAKE;
997 if ((ucr4 & UCR4_OREN) == 0)
998 usr2 &= ~USR2_ORE;
999
1000 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1001 imx_uart_writel(sport, USR1_AGTIM, USR1);
1002
1003 __imx_uart_rxint(irq, dev_id);
1004 ret = IRQ_HANDLED;
1005 }
1006
1007 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1008 imx_uart_transmit_buffer(sport);
1009 ret = IRQ_HANDLED;
1010 }
1011
1012 if (usr1 & USR1_DTRD) {
1013 imx_uart_writel(sport, USR1_DTRD, USR1);
1014
1015 imx_uart_mctrl_check(sport);
1016
1017 ret = IRQ_HANDLED;
1018 }
1019
1020 if (usr1 & USR1_RTSD) {
1021 __imx_uart_rtsint(irq, dev_id);
1022 ret = IRQ_HANDLED;
1023 }
1024
1025 if (usr1 & USR1_AWAKE) {
1026 imx_uart_writel(sport, USR1_AWAKE, USR1);
1027 ret = IRQ_HANDLED;
1028 }
1029
1030 if (usr2 & USR2_ORE) {
1031 sport->port.icount.overrun++;
1032 imx_uart_writel(sport, USR2_ORE, USR2);
1033 ret = IRQ_HANDLED;
1034 }
1035
1036 uart_port_unlock(&sport->port);
1037
1038 return ret;
1039 }
1040
1041 /*
1042 * Return TIOCSER_TEMT when transmitter is not busy.
1043 */
imx_uart_tx_empty(struct uart_port * port)1044 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1045 {
1046 struct imx_port *sport = (struct imx_port *)port;
1047 unsigned int ret;
1048
1049 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1050
1051 /* If the TX DMA is working, return 0. */
1052 if (sport->dma_is_txing)
1053 ret = 0;
1054
1055 return ret;
1056 }
1057
1058 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1059 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1060 {
1061 struct imx_port *sport = (struct imx_port *)port;
1062 unsigned int ret = imx_uart_get_hwmctrl(sport);
1063
1064 mctrl_gpio_get(sport->gpios, &ret);
1065
1066 return ret;
1067 }
1068
1069 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1070 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1071 {
1072 struct imx_port *sport = (struct imx_port *)port;
1073 u32 ucr3, uts;
1074
1075 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1076 u32 ucr2;
1077
1078 /*
1079 * Turn off autoRTS if RTS is lowered and restore autoRTS
1080 * setting if RTS is raised.
1081 */
1082 ucr2 = imx_uart_readl(sport, UCR2);
1083 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1084 if (mctrl & TIOCM_RTS) {
1085 ucr2 |= UCR2_CTS;
1086 /*
1087 * UCR2_IRTS is unset if and only if the port is
1088 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1089 * to get the state to restore to.
1090 */
1091 if (!(ucr2 & UCR2_IRTS))
1092 ucr2 |= UCR2_CTSC;
1093 }
1094 imx_uart_writel(sport, ucr2, UCR2);
1095 }
1096
1097 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1098 if (!(mctrl & TIOCM_DTR))
1099 ucr3 |= UCR3_DSR;
1100 imx_uart_writel(sport, ucr3, UCR3);
1101
1102 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1103 if (mctrl & TIOCM_LOOP)
1104 uts |= UTS_LOOP;
1105 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1106
1107 mctrl_gpio_set(sport->gpios, mctrl);
1108 }
1109
1110 /*
1111 * Interrupts always disabled.
1112 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1113 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1114 {
1115 struct imx_port *sport = (struct imx_port *)port;
1116 unsigned long flags;
1117 u32 ucr1;
1118
1119 uart_port_lock_irqsave(&sport->port, &flags);
1120
1121 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1122
1123 if (break_state != 0)
1124 ucr1 |= UCR1_SNDBRK;
1125
1126 imx_uart_writel(sport, ucr1, UCR1);
1127
1128 uart_port_unlock_irqrestore(&sport->port, flags);
1129 }
1130
1131 /*
1132 * This is our per-port timeout handler, for checking the
1133 * modem status signals.
1134 */
imx_uart_timeout(struct timer_list * t)1135 static void imx_uart_timeout(struct timer_list *t)
1136 {
1137 struct imx_port *sport = from_timer(sport, t, timer);
1138 unsigned long flags;
1139
1140 if (sport->port.state) {
1141 uart_port_lock_irqsave(&sport->port, &flags);
1142 imx_uart_mctrl_check(sport);
1143 uart_port_unlock_irqrestore(&sport->port, flags);
1144
1145 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1146 }
1147 }
1148
1149 /*
1150 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1151 * [1] the RX DMA buffer is full.
1152 * [2] the aging timer expires
1153 *
1154 * Condition [2] is triggered when a character has been sitting in the FIFO
1155 * for at least 8 byte durations.
1156 */
imx_uart_dma_rx_callback(void * data)1157 static void imx_uart_dma_rx_callback(void *data)
1158 {
1159 struct imx_port *sport = data;
1160 struct dma_chan *chan = sport->dma_chan_rx;
1161 struct scatterlist *sgl = &sport->rx_sgl;
1162 struct tty_port *port = &sport->port.state->port;
1163 struct dma_tx_state state;
1164 struct circ_buf *rx_ring = &sport->rx_ring;
1165 enum dma_status status;
1166 unsigned int w_bytes = 0;
1167 unsigned int r_bytes;
1168 unsigned int bd_size;
1169
1170 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1171
1172 if (status == DMA_ERROR) {
1173 uart_port_lock(&sport->port);
1174 imx_uart_clear_rx_errors(sport);
1175 uart_port_unlock(&sport->port);
1176 return;
1177 }
1178
1179 /*
1180 * The state-residue variable represents the empty space
1181 * relative to the entire buffer. Taking this in consideration
1182 * the head is always calculated base on the buffer total
1183 * length - DMA transaction residue. The UART script from the
1184 * SDMA firmware will jump to the next buffer descriptor,
1185 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1186 * Taking this in consideration the tail is always at the
1187 * beginning of the buffer descriptor that contains the head.
1188 */
1189
1190 /* Calculate the head */
1191 rx_ring->head = sg_dma_len(sgl) - state.residue;
1192
1193 /* Calculate the tail. */
1194 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1195 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1196
1197 if (rx_ring->head <= sg_dma_len(sgl) &&
1198 rx_ring->head > rx_ring->tail) {
1199
1200 /* Move data from tail to head */
1201 r_bytes = rx_ring->head - rx_ring->tail;
1202
1203 /* If we received something, check for 0xff flood */
1204 uart_port_lock(&sport->port);
1205 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1206 uart_port_unlock(&sport->port);
1207
1208 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1209
1210 /* CPU claims ownership of RX DMA buffer */
1211 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1212 DMA_FROM_DEVICE);
1213
1214 w_bytes = tty_insert_flip_string(port,
1215 sport->rx_buf + rx_ring->tail, r_bytes);
1216
1217 /* UART retrieves ownership of RX DMA buffer */
1218 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1219 DMA_FROM_DEVICE);
1220
1221 if (w_bytes != r_bytes)
1222 sport->port.icount.buf_overrun++;
1223
1224 sport->port.icount.rx += w_bytes;
1225 }
1226 } else {
1227 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1228 WARN_ON(rx_ring->head <= rx_ring->tail);
1229 }
1230
1231 if (w_bytes) {
1232 tty_flip_buffer_push(port);
1233 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1234 }
1235 }
1236
imx_uart_start_rx_dma(struct imx_port * sport)1237 static int imx_uart_start_rx_dma(struct imx_port *sport)
1238 {
1239 struct scatterlist *sgl = &sport->rx_sgl;
1240 struct dma_chan *chan = sport->dma_chan_rx;
1241 struct device *dev = sport->port.dev;
1242 struct dma_async_tx_descriptor *desc;
1243 int ret;
1244
1245 sport->rx_ring.head = 0;
1246 sport->rx_ring.tail = 0;
1247
1248 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1249 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1250 if (ret == 0) {
1251 dev_err(dev, "DMA mapping error for RX.\n");
1252 return -EINVAL;
1253 }
1254
1255 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1256 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1257 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1258
1259 if (!desc) {
1260 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1261 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1262 return -EINVAL;
1263 }
1264 desc->callback = imx_uart_dma_rx_callback;
1265 desc->callback_param = sport;
1266
1267 dev_dbg(dev, "RX: prepare for the DMA.\n");
1268 sport->dma_is_rxing = 1;
1269 sport->rx_cookie = dmaengine_submit(desc);
1270 dma_async_issue_pending(chan);
1271 return 0;
1272 }
1273
imx_uart_clear_rx_errors(struct imx_port * sport)1274 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1275 {
1276 struct tty_port *port = &sport->port.state->port;
1277 u32 usr1, usr2;
1278
1279 usr1 = imx_uart_readl(sport, USR1);
1280 usr2 = imx_uart_readl(sport, USR2);
1281
1282 if (usr2 & USR2_BRCD) {
1283 sport->port.icount.brk++;
1284 imx_uart_writel(sport, USR2_BRCD, USR2);
1285 uart_handle_break(&sport->port);
1286 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1287 sport->port.icount.buf_overrun++;
1288 tty_flip_buffer_push(port);
1289 } else {
1290 if (usr1 & USR1_FRAMERR) {
1291 sport->port.icount.frame++;
1292 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1293 } else if (usr1 & USR1_PARITYERR) {
1294 sport->port.icount.parity++;
1295 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1296 }
1297 }
1298
1299 if (usr2 & USR2_ORE) {
1300 sport->port.icount.overrun++;
1301 imx_uart_writel(sport, USR2_ORE, USR2);
1302 }
1303
1304 sport->idle_counter = 0;
1305
1306 }
1307
1308 #define TXTL_DEFAULT 8
1309 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1310 #define TXTL_DMA 8 /* DMA burst setting */
1311 #define RXTL_DMA 9 /* DMA burst setting */
1312
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1313 static void imx_uart_setup_ufcr(struct imx_port *sport,
1314 unsigned char txwl, unsigned char rxwl)
1315 {
1316 unsigned int val;
1317
1318 /* set receiver / transmitter trigger level */
1319 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1320 val |= txwl << UFCR_TXTL_SHF | rxwl;
1321 imx_uart_writel(sport, val, UFCR);
1322 }
1323
imx_uart_dma_exit(struct imx_port * sport)1324 static void imx_uart_dma_exit(struct imx_port *sport)
1325 {
1326 if (sport->dma_chan_rx) {
1327 dmaengine_terminate_sync(sport->dma_chan_rx);
1328 dma_release_channel(sport->dma_chan_rx);
1329 sport->dma_chan_rx = NULL;
1330 sport->rx_cookie = -EINVAL;
1331 kfree(sport->rx_buf);
1332 sport->rx_buf = NULL;
1333 }
1334
1335 if (sport->dma_chan_tx) {
1336 dmaengine_terminate_sync(sport->dma_chan_tx);
1337 dma_release_channel(sport->dma_chan_tx);
1338 sport->dma_chan_tx = NULL;
1339 }
1340 }
1341
imx_uart_dma_init(struct imx_port * sport)1342 static int imx_uart_dma_init(struct imx_port *sport)
1343 {
1344 struct dma_slave_config slave_config = {};
1345 struct device *dev = sport->port.dev;
1346 struct dma_chan *chan;
1347 int ret;
1348
1349 /* Prepare for RX : */
1350 chan = dma_request_chan(dev, "rx");
1351 if (IS_ERR(chan)) {
1352 dev_dbg(dev, "cannot get the DMA channel.\n");
1353 sport->dma_chan_rx = NULL;
1354 ret = PTR_ERR(chan);
1355 goto err;
1356 }
1357 sport->dma_chan_rx = chan;
1358
1359 slave_config.direction = DMA_DEV_TO_MEM;
1360 slave_config.src_addr = sport->port.mapbase + URXD0;
1361 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1362 /* one byte less than the watermark level to enable the aging timer */
1363 slave_config.src_maxburst = RXTL_DMA - 1;
1364 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1365 if (ret) {
1366 dev_err(dev, "error in RX dma configuration.\n");
1367 goto err;
1368 }
1369
1370 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1371 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1372 if (!sport->rx_buf) {
1373 ret = -ENOMEM;
1374 goto err;
1375 }
1376 sport->rx_ring.buf = sport->rx_buf;
1377
1378 /* Prepare for TX : */
1379 chan = dma_request_chan(dev, "tx");
1380 if (IS_ERR(chan)) {
1381 dev_err(dev, "cannot get the TX DMA channel!\n");
1382 sport->dma_chan_tx = NULL;
1383 ret = PTR_ERR(chan);
1384 goto err;
1385 }
1386 sport->dma_chan_tx = chan;
1387
1388 slave_config.direction = DMA_MEM_TO_DEV;
1389 slave_config.dst_addr = sport->port.mapbase + URTX0;
1390 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1391 slave_config.dst_maxburst = TXTL_DMA;
1392 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1393 if (ret) {
1394 dev_err(dev, "error in TX dma configuration.");
1395 goto err;
1396 }
1397
1398 return 0;
1399 err:
1400 imx_uart_dma_exit(sport);
1401 return ret;
1402 }
1403
imx_uart_enable_dma(struct imx_port * sport)1404 static void imx_uart_enable_dma(struct imx_port *sport)
1405 {
1406 u32 ucr1;
1407
1408 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1409
1410 /* set UCR1 */
1411 ucr1 = imx_uart_readl(sport, UCR1);
1412 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1413 imx_uart_writel(sport, ucr1, UCR1);
1414
1415 sport->dma_is_enabled = 1;
1416 }
1417
imx_uart_disable_dma(struct imx_port * sport)1418 static void imx_uart_disable_dma(struct imx_port *sport)
1419 {
1420 u32 ucr1;
1421
1422 /* clear UCR1 */
1423 ucr1 = imx_uart_readl(sport, UCR1);
1424 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1425 imx_uart_writel(sport, ucr1, UCR1);
1426
1427 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1428
1429 sport->dma_is_enabled = 0;
1430 }
1431
1432 /* half the RX buffer size */
1433 #define CTSTL 16
1434
imx_uart_startup(struct uart_port * port)1435 static int imx_uart_startup(struct uart_port *port)
1436 {
1437 struct imx_port *sport = (struct imx_port *)port;
1438 int retval;
1439 unsigned long flags;
1440 int dma_is_inited = 0;
1441 u32 ucr1, ucr2, ucr3, ucr4;
1442
1443 retval = clk_prepare_enable(sport->clk_per);
1444 if (retval)
1445 return retval;
1446 retval = clk_prepare_enable(sport->clk_ipg);
1447 if (retval) {
1448 clk_disable_unprepare(sport->clk_per);
1449 return retval;
1450 }
1451
1452 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1453
1454 /* disable the DREN bit (Data Ready interrupt enable) before
1455 * requesting IRQs
1456 */
1457 ucr4 = imx_uart_readl(sport, UCR4);
1458
1459 /* set the trigger level for CTS */
1460 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1461 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1462
1463 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1464
1465 /* Can we enable the DMA support? */
1466 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1467 lockdep_set_subclass(&port->lock, 1);
1468 dma_is_inited = 1;
1469 }
1470
1471 uart_port_lock_irqsave(&sport->port, &flags);
1472
1473 /* Reset fifo's and state machines */
1474 imx_uart_soft_reset(sport);
1475
1476 /*
1477 * Finally, clear and enable interrupts
1478 */
1479 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1480 imx_uart_writel(sport, USR2_ORE, USR2);
1481
1482 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1483 ucr1 |= UCR1_UARTEN;
1484 if (sport->have_rtscts)
1485 ucr1 |= UCR1_RTSDEN;
1486
1487 imx_uart_writel(sport, ucr1, UCR1);
1488
1489 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1490 if (!dma_is_inited)
1491 ucr4 |= UCR4_OREN;
1492 if (sport->inverted_rx)
1493 ucr4 |= UCR4_INVR;
1494 imx_uart_writel(sport, ucr4, UCR4);
1495
1496 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1497 /*
1498 * configure tx polarity before enabling tx
1499 */
1500 if (sport->inverted_tx)
1501 ucr3 |= UCR3_INVT;
1502
1503 if (!imx_uart_is_imx1(sport)) {
1504 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1505
1506 if (sport->dte_mode)
1507 /* disable broken interrupts */
1508 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1509 }
1510 imx_uart_writel(sport, ucr3, UCR3);
1511
1512 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1513 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1514 if (!sport->have_rtscts)
1515 ucr2 |= UCR2_IRTS;
1516 /*
1517 * make sure the edge sensitive RTS-irq is disabled,
1518 * we're using RTSD instead.
1519 */
1520 if (!imx_uart_is_imx1(sport))
1521 ucr2 &= ~UCR2_RTSEN;
1522 imx_uart_writel(sport, ucr2, UCR2);
1523
1524 /*
1525 * Enable modem status interrupts
1526 */
1527 imx_uart_enable_ms(&sport->port);
1528
1529 if (dma_is_inited) {
1530 imx_uart_enable_dma(sport);
1531 imx_uart_start_rx_dma(sport);
1532 } else {
1533 ucr1 = imx_uart_readl(sport, UCR1);
1534 ucr1 |= UCR1_RRDYEN;
1535 imx_uart_writel(sport, ucr1, UCR1);
1536
1537 ucr2 = imx_uart_readl(sport, UCR2);
1538 ucr2 |= UCR2_ATEN;
1539 imx_uart_writel(sport, ucr2, UCR2);
1540 }
1541
1542 imx_uart_disable_loopback_rs485(sport);
1543
1544 uart_port_unlock_irqrestore(&sport->port, flags);
1545
1546 return 0;
1547 }
1548
imx_uart_shutdown(struct uart_port * port)1549 static void imx_uart_shutdown(struct uart_port *port)
1550 {
1551 struct imx_port *sport = (struct imx_port *)port;
1552 unsigned long flags;
1553 u32 ucr1, ucr2, ucr4, uts;
1554
1555 if (sport->dma_is_enabled) {
1556 dmaengine_terminate_sync(sport->dma_chan_tx);
1557 if (sport->dma_is_txing) {
1558 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1559 sport->dma_tx_nents, DMA_TO_DEVICE);
1560 sport->dma_is_txing = 0;
1561 }
1562 dmaengine_terminate_sync(sport->dma_chan_rx);
1563 if (sport->dma_is_rxing) {
1564 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1565 1, DMA_FROM_DEVICE);
1566 sport->dma_is_rxing = 0;
1567 }
1568
1569 uart_port_lock_irqsave(&sport->port, &flags);
1570 imx_uart_stop_tx(port);
1571 imx_uart_stop_rx(port);
1572 imx_uart_disable_dma(sport);
1573 uart_port_unlock_irqrestore(&sport->port, flags);
1574 imx_uart_dma_exit(sport);
1575 }
1576
1577 mctrl_gpio_disable_ms(sport->gpios);
1578
1579 uart_port_lock_irqsave(&sport->port, &flags);
1580 ucr2 = imx_uart_readl(sport, UCR2);
1581 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1582 imx_uart_writel(sport, ucr2, UCR2);
1583 uart_port_unlock_irqrestore(&sport->port, flags);
1584
1585 /*
1586 * Stop our timer.
1587 */
1588 del_timer_sync(&sport->timer);
1589
1590 /*
1591 * Disable all interrupts, port and break condition.
1592 */
1593
1594 uart_port_lock_irqsave(&sport->port, &flags);
1595
1596 ucr1 = imx_uart_readl(sport, UCR1);
1597 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1598 UCR1_ATDMAEN | UCR1_SNDBRK);
1599 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1600 if (port->rs485.flags & SER_RS485_ENABLED &&
1601 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1602 sport->have_rtscts && !sport->have_rtsgpio) {
1603 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1604 uts |= UTS_LOOP;
1605 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1606 ucr1 |= UCR1_UARTEN;
1607 } else {
1608 ucr1 &= ~UCR1_UARTEN;
1609 }
1610 imx_uart_writel(sport, ucr1, UCR1);
1611
1612 ucr4 = imx_uart_readl(sport, UCR4);
1613 ucr4 &= ~UCR4_TCEN;
1614 imx_uart_writel(sport, ucr4, UCR4);
1615
1616 uart_port_unlock_irqrestore(&sport->port, flags);
1617
1618 clk_disable_unprepare(sport->clk_per);
1619 clk_disable_unprepare(sport->clk_ipg);
1620 }
1621
1622 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1623 static void imx_uart_flush_buffer(struct uart_port *port)
1624 {
1625 struct imx_port *sport = (struct imx_port *)port;
1626 struct scatterlist *sgl = &sport->tx_sgl[0];
1627
1628 if (!sport->dma_chan_tx)
1629 return;
1630
1631 sport->tx_bytes = 0;
1632 dmaengine_terminate_all(sport->dma_chan_tx);
1633 if (sport->dma_is_txing) {
1634 u32 ucr1;
1635
1636 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1637 DMA_TO_DEVICE);
1638 ucr1 = imx_uart_readl(sport, UCR1);
1639 ucr1 &= ~UCR1_TXDMAEN;
1640 imx_uart_writel(sport, ucr1, UCR1);
1641 sport->dma_is_txing = 0;
1642 }
1643
1644 imx_uart_soft_reset(sport);
1645
1646 }
1647
1648 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1649 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1650 const struct ktermios *old)
1651 {
1652 struct imx_port *sport = (struct imx_port *)port;
1653 unsigned long flags;
1654 u32 ucr2, old_ucr2, ufcr;
1655 unsigned int baud, quot;
1656 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1657 unsigned long div;
1658 unsigned long num, denom, old_ubir, old_ubmr;
1659 uint64_t tdiv64;
1660
1661 /*
1662 * We only support CS7 and CS8.
1663 */
1664 while ((termios->c_cflag & CSIZE) != CS7 &&
1665 (termios->c_cflag & CSIZE) != CS8) {
1666 termios->c_cflag &= ~CSIZE;
1667 termios->c_cflag |= old_csize;
1668 old_csize = CS8;
1669 }
1670
1671 del_timer_sync(&sport->timer);
1672
1673 /*
1674 * Ask the core to calculate the divisor for us.
1675 */
1676 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1677 quot = uart_get_divisor(port, baud);
1678
1679 uart_port_lock_irqsave(&sport->port, &flags);
1680
1681 /*
1682 * Read current UCR2 and save it for future use, then clear all the bits
1683 * except those we will or may need to preserve.
1684 */
1685 old_ucr2 = imx_uart_readl(sport, UCR2);
1686 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1687
1688 ucr2 |= UCR2_SRST | UCR2_IRTS;
1689 if ((termios->c_cflag & CSIZE) == CS8)
1690 ucr2 |= UCR2_WS;
1691
1692 if (!sport->have_rtscts)
1693 termios->c_cflag &= ~CRTSCTS;
1694
1695 if (port->rs485.flags & SER_RS485_ENABLED) {
1696 /*
1697 * RTS is mandatory for rs485 operation, so keep
1698 * it under manual control and keep transmitter
1699 * disabled.
1700 */
1701 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1702 imx_uart_rts_active(sport, &ucr2);
1703 else
1704 imx_uart_rts_inactive(sport, &ucr2);
1705
1706 } else if (termios->c_cflag & CRTSCTS) {
1707 /*
1708 * Only let receiver control RTS output if we were not requested
1709 * to have RTS inactive (which then should take precedence).
1710 */
1711 if (ucr2 & UCR2_CTS)
1712 ucr2 |= UCR2_CTSC;
1713 }
1714
1715 if (termios->c_cflag & CRTSCTS)
1716 ucr2 &= ~UCR2_IRTS;
1717 if (termios->c_cflag & CSTOPB)
1718 ucr2 |= UCR2_STPB;
1719 if (termios->c_cflag & PARENB) {
1720 ucr2 |= UCR2_PREN;
1721 if (termios->c_cflag & PARODD)
1722 ucr2 |= UCR2_PROE;
1723 }
1724
1725 sport->port.read_status_mask = 0;
1726 if (termios->c_iflag & INPCK)
1727 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1728 if (termios->c_iflag & (BRKINT | PARMRK))
1729 sport->port.read_status_mask |= URXD_BRK;
1730
1731 /*
1732 * Characters to ignore
1733 */
1734 sport->port.ignore_status_mask = 0;
1735 if (termios->c_iflag & IGNPAR)
1736 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1737 if (termios->c_iflag & IGNBRK) {
1738 sport->port.ignore_status_mask |= URXD_BRK;
1739 /*
1740 * If we're ignoring parity and break indicators,
1741 * ignore overruns too (for real raw support).
1742 */
1743 if (termios->c_iflag & IGNPAR)
1744 sport->port.ignore_status_mask |= URXD_OVRRUN;
1745 }
1746
1747 if ((termios->c_cflag & CREAD) == 0)
1748 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1749
1750 /*
1751 * Update the per-port timeout.
1752 */
1753 uart_update_timeout(port, termios->c_cflag, baud);
1754
1755 /* custom-baudrate handling */
1756 div = sport->port.uartclk / (baud * 16);
1757 if (baud == 38400 && quot != div)
1758 baud = sport->port.uartclk / (quot * 16);
1759
1760 div = sport->port.uartclk / (baud * 16);
1761 if (div > 7)
1762 div = 7;
1763 if (!div)
1764 div = 1;
1765
1766 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1767 1 << 16, 1 << 16, &num, &denom);
1768
1769 tdiv64 = sport->port.uartclk;
1770 tdiv64 *= num;
1771 do_div(tdiv64, denom * 16 * div);
1772 tty_termios_encode_baud_rate(termios,
1773 (speed_t)tdiv64, (speed_t)tdiv64);
1774
1775 num -= 1;
1776 denom -= 1;
1777
1778 ufcr = imx_uart_readl(sport, UFCR);
1779 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1780 imx_uart_writel(sport, ufcr, UFCR);
1781
1782 /*
1783 * Two registers below should always be written both and in this
1784 * particular order. One consequence is that we need to check if any of
1785 * them changes and then update both. We do need the check for change
1786 * as even writing the same values seem to "restart"
1787 * transmission/receiving logic in the hardware, that leads to data
1788 * breakage even when rate doesn't in fact change. E.g., user switches
1789 * RTS/CTS handshake and suddenly gets broken bytes.
1790 */
1791 old_ubir = imx_uart_readl(sport, UBIR);
1792 old_ubmr = imx_uart_readl(sport, UBMR);
1793 if (old_ubir != num || old_ubmr != denom) {
1794 imx_uart_writel(sport, num, UBIR);
1795 imx_uart_writel(sport, denom, UBMR);
1796 }
1797
1798 if (!imx_uart_is_imx1(sport))
1799 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1800 IMX21_ONEMS);
1801
1802 imx_uart_writel(sport, ucr2, UCR2);
1803
1804 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1805 imx_uart_enable_ms(&sport->port);
1806
1807 uart_port_unlock_irqrestore(&sport->port, flags);
1808 }
1809
imx_uart_type(struct uart_port * port)1810 static const char *imx_uart_type(struct uart_port *port)
1811 {
1812 return port->type == PORT_IMX ? "IMX" : NULL;
1813 }
1814
1815 /*
1816 * Configure/autoconfigure the port.
1817 */
imx_uart_config_port(struct uart_port * port,int flags)1818 static void imx_uart_config_port(struct uart_port *port, int flags)
1819 {
1820 if (flags & UART_CONFIG_TYPE)
1821 port->type = PORT_IMX;
1822 }
1823
1824 /*
1825 * Verify the new serial_struct (for TIOCSSERIAL).
1826 * The only change we allow are to the flags and type, and
1827 * even then only between PORT_IMX and PORT_UNKNOWN
1828 */
1829 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1830 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1831 {
1832 int ret = 0;
1833
1834 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1835 ret = -EINVAL;
1836 if (port->irq != ser->irq)
1837 ret = -EINVAL;
1838 if (ser->io_type != UPIO_MEM)
1839 ret = -EINVAL;
1840 if (port->uartclk / 16 != ser->baud_base)
1841 ret = -EINVAL;
1842 if (port->mapbase != (unsigned long)ser->iomem_base)
1843 ret = -EINVAL;
1844 if (port->iobase != ser->port)
1845 ret = -EINVAL;
1846 if (ser->hub6 != 0)
1847 ret = -EINVAL;
1848 return ret;
1849 }
1850
1851 #if defined(CONFIG_CONSOLE_POLL)
1852
imx_uart_poll_init(struct uart_port * port)1853 static int imx_uart_poll_init(struct uart_port *port)
1854 {
1855 struct imx_port *sport = (struct imx_port *)port;
1856 unsigned long flags;
1857 u32 ucr1, ucr2;
1858 int retval;
1859
1860 retval = clk_prepare_enable(sport->clk_ipg);
1861 if (retval)
1862 return retval;
1863 retval = clk_prepare_enable(sport->clk_per);
1864 if (retval)
1865 clk_disable_unprepare(sport->clk_ipg);
1866
1867 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1868
1869 uart_port_lock_irqsave(&sport->port, &flags);
1870
1871 /*
1872 * Be careful about the order of enabling bits here. First enable the
1873 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1874 * This prevents that a character that already sits in the RX fifo is
1875 * triggering an irq but the try to fetch it from there results in an
1876 * exception because UARTEN or RXEN is still off.
1877 */
1878 ucr1 = imx_uart_readl(sport, UCR1);
1879 ucr2 = imx_uart_readl(sport, UCR2);
1880
1881 if (imx_uart_is_imx1(sport))
1882 ucr1 |= IMX1_UCR1_UARTCLKEN;
1883
1884 ucr1 |= UCR1_UARTEN;
1885 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1886
1887 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1888 ucr2 &= ~UCR2_ATEN;
1889
1890 imx_uart_writel(sport, ucr1, UCR1);
1891 imx_uart_writel(sport, ucr2, UCR2);
1892
1893 /* now enable irqs */
1894 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1895 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1896
1897 uart_port_unlock_irqrestore(&sport->port, flags);
1898
1899 return 0;
1900 }
1901
imx_uart_poll_get_char(struct uart_port * port)1902 static int imx_uart_poll_get_char(struct uart_port *port)
1903 {
1904 struct imx_port *sport = (struct imx_port *)port;
1905 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1906 return NO_POLL_CHAR;
1907
1908 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1909 }
1910
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1911 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1912 {
1913 struct imx_port *sport = (struct imx_port *)port;
1914 unsigned int status;
1915
1916 /* drain */
1917 do {
1918 status = imx_uart_readl(sport, USR1);
1919 } while (~status & USR1_TRDY);
1920
1921 /* write */
1922 imx_uart_writel(sport, c, URTX0);
1923
1924 /* flush */
1925 do {
1926 status = imx_uart_readl(sport, USR2);
1927 } while (~status & USR2_TXDC);
1928 }
1929 #endif
1930
1931 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1932 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1933 struct serial_rs485 *rs485conf)
1934 {
1935 struct imx_port *sport = (struct imx_port *)port;
1936 u32 ucr2;
1937
1938 if (rs485conf->flags & SER_RS485_ENABLED) {
1939 /* Enable receiver if low-active RTS signal is requested */
1940 if (sport->have_rtscts && !sport->have_rtsgpio &&
1941 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1942 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1943
1944 /* disable transmitter */
1945 ucr2 = imx_uart_readl(sport, UCR2);
1946 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1947 imx_uart_rts_active(sport, &ucr2);
1948 else
1949 imx_uart_rts_inactive(sport, &ucr2);
1950 imx_uart_writel(sport, ucr2, UCR2);
1951 }
1952
1953 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1954 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1955 rs485conf->flags & SER_RS485_RX_DURING_TX)
1956 imx_uart_start_rx(port);
1957
1958 return 0;
1959 }
1960
1961 static const struct uart_ops imx_uart_pops = {
1962 .tx_empty = imx_uart_tx_empty,
1963 .set_mctrl = imx_uart_set_mctrl,
1964 .get_mctrl = imx_uart_get_mctrl,
1965 .stop_tx = imx_uart_stop_tx,
1966 .start_tx = imx_uart_start_tx,
1967 .stop_rx = imx_uart_stop_rx,
1968 .enable_ms = imx_uart_enable_ms,
1969 .break_ctl = imx_uart_break_ctl,
1970 .startup = imx_uart_startup,
1971 .shutdown = imx_uart_shutdown,
1972 .flush_buffer = imx_uart_flush_buffer,
1973 .set_termios = imx_uart_set_termios,
1974 .type = imx_uart_type,
1975 .config_port = imx_uart_config_port,
1976 .verify_port = imx_uart_verify_port,
1977 #if defined(CONFIG_CONSOLE_POLL)
1978 .poll_init = imx_uart_poll_init,
1979 .poll_get_char = imx_uart_poll_get_char,
1980 .poll_put_char = imx_uart_poll_put_char,
1981 #endif
1982 };
1983
1984 static struct imx_port *imx_uart_ports[UART_NR];
1985
1986 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)1987 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1988 {
1989 struct imx_port *sport = (struct imx_port *)port;
1990
1991 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1992 barrier();
1993
1994 imx_uart_writel(sport, ch, URTX0);
1995 }
1996
1997 /*
1998 * Interrupts are disabled on entering
1999 */
2000 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2001 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2002 {
2003 struct imx_port *sport = imx_uart_ports[co->index];
2004 struct imx_port_ucrs old_ucr;
2005 unsigned long flags;
2006 unsigned int ucr1, usr2;
2007 int locked = 1;
2008
2009 if (sport->port.sysrq)
2010 locked = 0;
2011 else if (oops_in_progress)
2012 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2013 else
2014 uart_port_lock_irqsave(&sport->port, &flags);
2015
2016 /*
2017 * First, save UCR1/2/3 and then disable interrupts
2018 */
2019 imx_uart_ucrs_save(sport, &old_ucr);
2020 ucr1 = old_ucr.ucr1;
2021
2022 if (imx_uart_is_imx1(sport))
2023 ucr1 |= IMX1_UCR1_UARTCLKEN;
2024 ucr1 |= UCR1_UARTEN;
2025 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2026
2027 imx_uart_writel(sport, ucr1, UCR1);
2028
2029 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2030
2031 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2032
2033 /*
2034 * Finally, wait for transmitter to become empty
2035 * and restore UCR1/2/3
2036 */
2037 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2038 0, USEC_PER_SEC, false, sport, USR2);
2039 imx_uart_ucrs_restore(sport, &old_ucr);
2040
2041 if (locked)
2042 uart_port_unlock_irqrestore(&sport->port, flags);
2043 }
2044
2045 /*
2046 * If the port was already initialised (eg, by a boot loader),
2047 * try to determine the current setup.
2048 */
2049 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2050 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2051 int *parity, int *bits)
2052 {
2053
2054 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2055 /* ok, the port was enabled */
2056 unsigned int ucr2, ubir, ubmr, uartclk;
2057 unsigned int baud_raw;
2058 unsigned int ucfr_rfdiv;
2059
2060 ucr2 = imx_uart_readl(sport, UCR2);
2061
2062 *parity = 'n';
2063 if (ucr2 & UCR2_PREN) {
2064 if (ucr2 & UCR2_PROE)
2065 *parity = 'o';
2066 else
2067 *parity = 'e';
2068 }
2069
2070 if (ucr2 & UCR2_WS)
2071 *bits = 8;
2072 else
2073 *bits = 7;
2074
2075 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2076 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2077
2078 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2079 if (ucfr_rfdiv == 6)
2080 ucfr_rfdiv = 7;
2081 else
2082 ucfr_rfdiv = 6 - ucfr_rfdiv;
2083
2084 uartclk = clk_get_rate(sport->clk_per);
2085 uartclk /= ucfr_rfdiv;
2086
2087 { /*
2088 * The next code provides exact computation of
2089 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2090 * without need of float support or long long division,
2091 * which would be required to prevent 32bit arithmetic overflow
2092 */
2093 unsigned int mul = ubir + 1;
2094 unsigned int div = 16 * (ubmr + 1);
2095 unsigned int rem = uartclk % div;
2096
2097 baud_raw = (uartclk / div) * mul;
2098 baud_raw += (rem * mul + div / 2) / div;
2099 *baud = (baud_raw + 50) / 100 * 100;
2100 }
2101
2102 if (*baud != baud_raw)
2103 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2104 baud_raw, *baud);
2105 }
2106 }
2107
2108 static int
imx_uart_console_setup(struct console * co,char * options)2109 imx_uart_console_setup(struct console *co, char *options)
2110 {
2111 struct imx_port *sport;
2112 int baud = 9600;
2113 int bits = 8;
2114 int parity = 'n';
2115 int flow = 'n';
2116 int retval;
2117
2118 /*
2119 * Check whether an invalid uart number has been specified, and
2120 * if so, search for the first available port that does have
2121 * console support.
2122 */
2123 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2124 co->index = 0;
2125 sport = imx_uart_ports[co->index];
2126 if (sport == NULL)
2127 return -ENODEV;
2128
2129 /* For setting the registers, we only need to enable the ipg clock. */
2130 retval = clk_prepare_enable(sport->clk_ipg);
2131 if (retval)
2132 goto error_console;
2133
2134 if (options)
2135 uart_parse_options(options, &baud, &parity, &bits, &flow);
2136 else
2137 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2138
2139 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2140
2141 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2142
2143 if (retval) {
2144 clk_disable_unprepare(sport->clk_ipg);
2145 goto error_console;
2146 }
2147
2148 retval = clk_prepare_enable(sport->clk_per);
2149 if (retval)
2150 clk_disable_unprepare(sport->clk_ipg);
2151
2152 error_console:
2153 return retval;
2154 }
2155
2156 static int
imx_uart_console_exit(struct console * co)2157 imx_uart_console_exit(struct console *co)
2158 {
2159 struct imx_port *sport = imx_uart_ports[co->index];
2160
2161 clk_disable_unprepare(sport->clk_per);
2162 clk_disable_unprepare(sport->clk_ipg);
2163
2164 return 0;
2165 }
2166
2167 static struct uart_driver imx_uart_uart_driver;
2168 static struct console imx_uart_console = {
2169 .name = DEV_NAME,
2170 .write = imx_uart_console_write,
2171 .device = uart_console_device,
2172 .setup = imx_uart_console_setup,
2173 .exit = imx_uart_console_exit,
2174 .flags = CON_PRINTBUFFER,
2175 .index = -1,
2176 .data = &imx_uart_uart_driver,
2177 };
2178
2179 #define IMX_CONSOLE &imx_uart_console
2180
2181 #else
2182 #define IMX_CONSOLE NULL
2183 #endif
2184
2185 static struct uart_driver imx_uart_uart_driver = {
2186 .owner = THIS_MODULE,
2187 .driver_name = DRIVER_NAME,
2188 .dev_name = DEV_NAME,
2189 .major = SERIAL_IMX_MAJOR,
2190 .minor = MINOR_START,
2191 .nr = ARRAY_SIZE(imx_uart_ports),
2192 .cons = IMX_CONSOLE,
2193 };
2194
imx_trigger_start_tx(struct hrtimer * t)2195 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2196 {
2197 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2198 unsigned long flags;
2199
2200 uart_port_lock_irqsave(&sport->port, &flags);
2201 if (sport->tx_state == WAIT_AFTER_RTS)
2202 imx_uart_start_tx(&sport->port);
2203 uart_port_unlock_irqrestore(&sport->port, flags);
2204
2205 return HRTIMER_NORESTART;
2206 }
2207
imx_trigger_stop_tx(struct hrtimer * t)2208 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2209 {
2210 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2211 unsigned long flags;
2212
2213 uart_port_lock_irqsave(&sport->port, &flags);
2214 if (sport->tx_state == WAIT_AFTER_SEND)
2215 imx_uart_stop_tx(&sport->port);
2216 uart_port_unlock_irqrestore(&sport->port, flags);
2217
2218 return HRTIMER_NORESTART;
2219 }
2220
2221 static const struct serial_rs485 imx_rs485_supported = {
2222 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2223 SER_RS485_RX_DURING_TX,
2224 .delay_rts_before_send = 1,
2225 .delay_rts_after_send = 1,
2226 };
2227
2228 /* Default RX DMA buffer configuration */
2229 #define RX_DMA_PERIODS 16
2230 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2231
imx_uart_probe(struct platform_device * pdev)2232 static int imx_uart_probe(struct platform_device *pdev)
2233 {
2234 struct device_node *np = pdev->dev.of_node;
2235 struct imx_port *sport;
2236 void __iomem *base;
2237 u32 dma_buf_conf[2];
2238 int ret = 0;
2239 u32 ucr1, ucr2, uts;
2240 struct resource *res;
2241 int txirq, rxirq, rtsirq;
2242
2243 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2244 if (!sport)
2245 return -ENOMEM;
2246
2247 sport->devdata = of_device_get_match_data(&pdev->dev);
2248
2249 ret = of_alias_get_id(np, "serial");
2250 if (ret < 0) {
2251 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2252 return ret;
2253 }
2254 sport->port.line = ret;
2255
2256 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2257 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2258
2259 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2260
2261 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2262
2263 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2264
2265 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2266
2267 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2268 sport->rx_period_length = dma_buf_conf[0];
2269 sport->rx_periods = dma_buf_conf[1];
2270 } else {
2271 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2272 sport->rx_periods = RX_DMA_PERIODS;
2273 }
2274
2275 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2276 dev_err(&pdev->dev, "serial%d out of range\n",
2277 sport->port.line);
2278 return -EINVAL;
2279 }
2280
2281 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2282 if (IS_ERR(base))
2283 return PTR_ERR(base);
2284
2285 rxirq = platform_get_irq(pdev, 0);
2286 if (rxirq < 0)
2287 return rxirq;
2288 txirq = platform_get_irq_optional(pdev, 1);
2289 rtsirq = platform_get_irq_optional(pdev, 2);
2290
2291 sport->port.dev = &pdev->dev;
2292 sport->port.mapbase = res->start;
2293 sport->port.membase = base;
2294 sport->port.type = PORT_IMX;
2295 sport->port.iotype = UPIO_MEM;
2296 sport->port.irq = rxirq;
2297 sport->port.fifosize = 32;
2298 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2299 sport->port.ops = &imx_uart_pops;
2300 sport->port.rs485_config = imx_uart_rs485_config;
2301 /* RTS is required to control the RS485 transmitter */
2302 if (sport->have_rtscts || sport->have_rtsgpio)
2303 sport->port.rs485_supported = imx_rs485_supported;
2304 sport->port.flags = UPF_BOOT_AUTOCONF;
2305 timer_setup(&sport->timer, imx_uart_timeout, 0);
2306
2307 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2308 if (IS_ERR(sport->gpios))
2309 return PTR_ERR(sport->gpios);
2310
2311 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2312 if (IS_ERR(sport->clk_ipg)) {
2313 ret = PTR_ERR(sport->clk_ipg);
2314 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2315 return ret;
2316 }
2317
2318 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2319 if (IS_ERR(sport->clk_per)) {
2320 ret = PTR_ERR(sport->clk_per);
2321 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2322 return ret;
2323 }
2324
2325 sport->port.uartclk = clk_get_rate(sport->clk_per);
2326
2327 /* For register access, we only need to enable the ipg clock. */
2328 ret = clk_prepare_enable(sport->clk_ipg);
2329 if (ret) {
2330 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2331 return ret;
2332 }
2333
2334 ret = uart_get_rs485_mode(&sport->port);
2335 if (ret)
2336 goto err_clk;
2337
2338 /*
2339 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2340 * signal cannot be set low during transmission in case the
2341 * receiver is off (limitation of the i.MX UART IP).
2342 */
2343 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2344 sport->have_rtscts && !sport->have_rtsgpio &&
2345 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2346 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2347 dev_err(&pdev->dev,
2348 "low-active RTS not possible when receiver is off, enabling receiver\n");
2349
2350 /* Disable interrupts before requesting them */
2351 ucr1 = imx_uart_readl(sport, UCR1);
2352 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2353 imx_uart_writel(sport, ucr1, UCR1);
2354
2355 /* Disable Ageing Timer interrupt */
2356 ucr2 = imx_uart_readl(sport, UCR2);
2357 ucr2 &= ~UCR2_ATEN;
2358 imx_uart_writel(sport, ucr2, UCR2);
2359
2360 /*
2361 * In case RS485 is enabled without GPIO RTS control, the UART IP
2362 * is used to control CTS signal. Keep both the UART and Receiver
2363 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2364 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2365 * data from being fed into the RX FIFO, enable loopback mode in
2366 * UTS register, which disconnects the RX path from external RXD
2367 * pin and connects it to the Transceiver, which is disabled, so
2368 * no data can be fed to the RX FIFO that way.
2369 */
2370 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2371 sport->have_rtscts && !sport->have_rtsgpio) {
2372 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2373 uts |= UTS_LOOP;
2374 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2375
2376 ucr1 = imx_uart_readl(sport, UCR1);
2377 ucr1 |= UCR1_UARTEN;
2378 imx_uart_writel(sport, ucr1, UCR1);
2379
2380 ucr2 = imx_uart_readl(sport, UCR2);
2381 ucr2 |= UCR2_RXEN;
2382 imx_uart_writel(sport, ucr2, UCR2);
2383 }
2384
2385 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2386 /*
2387 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2388 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2389 * and DCD (when they are outputs) or enables the respective
2390 * irqs. So set this bit early, i.e. before requesting irqs.
2391 */
2392 u32 ufcr = imx_uart_readl(sport, UFCR);
2393 if (!(ufcr & UFCR_DCEDTE))
2394 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2395
2396 /*
2397 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2398 * enabled later because they cannot be cleared
2399 * (confirmed on i.MX25) which makes them unusable.
2400 */
2401 imx_uart_writel(sport,
2402 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2403 UCR3);
2404
2405 } else {
2406 u32 ucr3 = UCR3_DSR;
2407 u32 ufcr = imx_uart_readl(sport, UFCR);
2408 if (ufcr & UFCR_DCEDTE)
2409 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2410
2411 if (!imx_uart_is_imx1(sport))
2412 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2413 imx_uart_writel(sport, ucr3, UCR3);
2414 }
2415
2416 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2417 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2418 sport->trigger_start_tx.function = imx_trigger_start_tx;
2419 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2420
2421 /*
2422 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2423 * chips only have one interrupt.
2424 */
2425 if (txirq > 0) {
2426 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2427 dev_name(&pdev->dev), sport);
2428 if (ret) {
2429 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2430 ret);
2431 goto err_clk;
2432 }
2433
2434 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2435 dev_name(&pdev->dev), sport);
2436 if (ret) {
2437 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2438 ret);
2439 goto err_clk;
2440 }
2441
2442 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2443 dev_name(&pdev->dev), sport);
2444 if (ret) {
2445 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2446 ret);
2447 goto err_clk;
2448 }
2449 } else {
2450 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2451 dev_name(&pdev->dev), sport);
2452 if (ret) {
2453 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2454 goto err_clk;
2455 }
2456 }
2457
2458 imx_uart_ports[sport->port.line] = sport;
2459
2460 platform_set_drvdata(pdev, sport);
2461
2462 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2463
2464 err_clk:
2465 clk_disable_unprepare(sport->clk_ipg);
2466
2467 return ret;
2468 }
2469
imx_uart_remove(struct platform_device * pdev)2470 static void imx_uart_remove(struct platform_device *pdev)
2471 {
2472 struct imx_port *sport = platform_get_drvdata(pdev);
2473
2474 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2475 }
2476
imx_uart_restore_context(struct imx_port * sport)2477 static void imx_uart_restore_context(struct imx_port *sport)
2478 {
2479 unsigned long flags;
2480
2481 uart_port_lock_irqsave(&sport->port, &flags);
2482 if (!sport->context_saved) {
2483 uart_port_unlock_irqrestore(&sport->port, flags);
2484 return;
2485 }
2486
2487 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2488 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2489 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2490 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2491 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2492 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2493 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2494 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2495 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2496 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2497 sport->context_saved = false;
2498 uart_port_unlock_irqrestore(&sport->port, flags);
2499 }
2500
imx_uart_save_context(struct imx_port * sport)2501 static void imx_uart_save_context(struct imx_port *sport)
2502 {
2503 unsigned long flags;
2504
2505 /* Save necessary regs */
2506 uart_port_lock_irqsave(&sport->port, &flags);
2507 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2508 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2509 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2510 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2511 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2512 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2513 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2514 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2515 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2516 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2517 sport->context_saved = true;
2518 uart_port_unlock_irqrestore(&sport->port, flags);
2519 }
2520
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2521 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2522 {
2523 u32 ucr3;
2524
2525 ucr3 = imx_uart_readl(sport, UCR3);
2526 if (on) {
2527 imx_uart_writel(sport, USR1_AWAKE, USR1);
2528 ucr3 |= UCR3_AWAKEN;
2529 } else {
2530 ucr3 &= ~UCR3_AWAKEN;
2531 }
2532 imx_uart_writel(sport, ucr3, UCR3);
2533
2534 if (sport->have_rtscts) {
2535 u32 ucr1 = imx_uart_readl(sport, UCR1);
2536 if (on) {
2537 imx_uart_writel(sport, USR1_RTSD, USR1);
2538 ucr1 |= UCR1_RTSDEN;
2539 } else {
2540 ucr1 &= ~UCR1_RTSDEN;
2541 }
2542 imx_uart_writel(sport, ucr1, UCR1);
2543 }
2544 }
2545
imx_uart_suspend_noirq(struct device * dev)2546 static int imx_uart_suspend_noirq(struct device *dev)
2547 {
2548 struct imx_port *sport = dev_get_drvdata(dev);
2549
2550 imx_uart_save_context(sport);
2551
2552 clk_disable(sport->clk_ipg);
2553
2554 pinctrl_pm_select_sleep_state(dev);
2555
2556 return 0;
2557 }
2558
imx_uart_resume_noirq(struct device * dev)2559 static int imx_uart_resume_noirq(struct device *dev)
2560 {
2561 struct imx_port *sport = dev_get_drvdata(dev);
2562 int ret;
2563
2564 pinctrl_pm_select_default_state(dev);
2565
2566 ret = clk_enable(sport->clk_ipg);
2567 if (ret)
2568 return ret;
2569
2570 imx_uart_restore_context(sport);
2571
2572 return 0;
2573 }
2574
imx_uart_suspend(struct device * dev)2575 static int imx_uart_suspend(struct device *dev)
2576 {
2577 struct imx_port *sport = dev_get_drvdata(dev);
2578 int ret;
2579
2580 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2581 disable_irq(sport->port.irq);
2582
2583 ret = clk_prepare_enable(sport->clk_ipg);
2584 if (ret)
2585 return ret;
2586
2587 /* enable wakeup from i.MX UART */
2588 imx_uart_enable_wakeup(sport, true);
2589
2590 return 0;
2591 }
2592
imx_uart_resume(struct device * dev)2593 static int imx_uart_resume(struct device *dev)
2594 {
2595 struct imx_port *sport = dev_get_drvdata(dev);
2596
2597 /* disable wakeup from i.MX UART */
2598 imx_uart_enable_wakeup(sport, false);
2599
2600 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2601 enable_irq(sport->port.irq);
2602
2603 clk_disable_unprepare(sport->clk_ipg);
2604
2605 return 0;
2606 }
2607
imx_uart_freeze(struct device * dev)2608 static int imx_uart_freeze(struct device *dev)
2609 {
2610 struct imx_port *sport = dev_get_drvdata(dev);
2611
2612 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2613
2614 return clk_prepare_enable(sport->clk_ipg);
2615 }
2616
imx_uart_thaw(struct device * dev)2617 static int imx_uart_thaw(struct device *dev)
2618 {
2619 struct imx_port *sport = dev_get_drvdata(dev);
2620
2621 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2622
2623 clk_disable_unprepare(sport->clk_ipg);
2624
2625 return 0;
2626 }
2627
2628 static const struct dev_pm_ops imx_uart_pm_ops = {
2629 .suspend_noirq = imx_uart_suspend_noirq,
2630 .resume_noirq = imx_uart_resume_noirq,
2631 .freeze_noirq = imx_uart_suspend_noirq,
2632 .thaw_noirq = imx_uart_resume_noirq,
2633 .restore_noirq = imx_uart_resume_noirq,
2634 .suspend = imx_uart_suspend,
2635 .resume = imx_uart_resume,
2636 .freeze = imx_uart_freeze,
2637 .thaw = imx_uart_thaw,
2638 .restore = imx_uart_thaw,
2639 };
2640
2641 static struct platform_driver imx_uart_platform_driver = {
2642 .probe = imx_uart_probe,
2643 .remove_new = imx_uart_remove,
2644
2645 .driver = {
2646 .name = "imx-uart",
2647 .of_match_table = imx_uart_dt_ids,
2648 .pm = &imx_uart_pm_ops,
2649 },
2650 };
2651
imx_uart_init(void)2652 static int __init imx_uart_init(void)
2653 {
2654 int ret = uart_register_driver(&imx_uart_uart_driver);
2655
2656 if (ret)
2657 return ret;
2658
2659 ret = platform_driver_register(&imx_uart_platform_driver);
2660 if (ret != 0)
2661 uart_unregister_driver(&imx_uart_uart_driver);
2662
2663 return ret;
2664 }
2665
imx_uart_exit(void)2666 static void __exit imx_uart_exit(void)
2667 {
2668 platform_driver_unregister(&imx_uart_platform_driver);
2669 uart_unregister_driver(&imx_uart_uart_driver);
2670 }
2671
2672 module_init(imx_uart_init);
2673 module_exit(imx_uart_exit);
2674
2675 MODULE_AUTHOR("Sascha Hauer");
2676 MODULE_DESCRIPTION("IMX generic serial port driver");
2677 MODULE_LICENSE("GPL");
2678 MODULE_ALIAS("platform:imx-uart");
2679